TI1 CDCEL913PWG4 Programmable 1-pll vcxo clock synthesizer with 1.8-v, 2.5-v, and 3.3-v output Datasheet

CDCE913
CDCEL913
www.ti.com
SCAS849E – JUNE 2007 – REVISED MARCH 2010
Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs
Check for Samples: CDCE913, CDCEL913
FEATURES
1
• Member of Programmable Clock Generator
Family
– CDCE913/CDCEL913: 1-PLL, 3 Outputs
– CDCE925/CDCEL925: 2-PLL, 5 Outputs
– CDCE937/CDCEL937: 3-PLL, 7 Outputs
– CDCE949/CDCEL949: 4-PLL, 9 Outputs
• In-System Programmability and EEPROM
– Serial Programmable Volatile Register
– Nonvolatile EEPROM to Store Customer
Setting
• Flexible Input Clocking Concept
– External Crystal: 8 MHz to 32 MHz
– On-Chip VCXO: Pull Range ±150 ppm
– Single-Ended LVCMOS up to 160 MHz
• Free Selectable Output Frequency up to
230 MHz
• Low-Noise PLL Core
– PLL Loop Filter Components Integrated
– Low Period Jitter (Typical 50 ps)
• Separate Output Supply Pins
– CDCE913: 3.3 V and 2.5 V
2345
VDD
•
•
•
•
•
– CDCEL913: 1.8 V
Flexible Clock Driver
– Three User-Definable Control Inputs
[S0/S1/S2], for example., SSC Selection,
Frequency Switching, Output Enable, or
Power Down
– Generates Highly Accurate Clocks for
Video, Audio, USB, IEEE1394, RFID,
Bluetooth™, WLAN, Ethernet™, and GPS
– Generates Common Clock Frequencies
Used With TI- DaVinci™, OMAP™, DSPs
– Programmable SSC Modulation
– Enables 0-PPM Clock Generation
1.8-V Device Power Supply
Wide Temperature Range –40° C to 85° C
Packaged in TSSOP
Development and Programming Kit for Easy
PLL Design and Programming (TI Pro-Clock™)
APPLICATIONS
•
D-TV, STB, IP-STB, DVD-Player, DVD-Recorder,
Printer
VDDOUT
GND
Crystal or
Clock Input
Vctr
S2/S1/S0 or
SDA/SCL
VCXO
XO
LVCMOS
3
EEPROM
Programming
and
Control Register
PLL
with SSC
Divider
and
Output
Control
LV
CMOS
Y1
LV
CMOS
Y2
LV
CMOS
Y3
Xin/CLK
S0
VDD
Vctr
GND
VDDOUT
VDDOUT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Xout
S1/SDA
S2/SCL
Y1
GND
Y2
Y3
1
2
3
4
5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DaVinci, OMAP, Pro-Clock are trademarks of Texas Instruments.
Bluetooth is a trademark of Bluetooth SIG.
I2C is a trademark of Philips Electronics.
Ethernet is a trademark of Xerox Corporattion.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2010, Texas Instruments Incorporated
CDCE913
CDCEL913
SCAS849E – JUNE 2007 – REVISED MARCH 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION
The CDCE913 and CDCEL913 are modular PLL-based low-cost, high-performance, programmable clock
synthesizers, multipliers, and dividers. They generate up to 3 output clocks from a single input frequency. Each
output can be programmed in-system for any clock frequency up to 230 MHz, using the integrated configurable
PLL.
The CDCx913 has separate output supply pins, VDDOUT, which is 1.8 V for CDCEL913 and 2.5 V to 3.3 V for
CDCE913.
The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load
capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF.
Additionally, an on-chip VCXO is selectable which allows synchronization of the output frequency to an external
control signal, that is, PWM signal.
The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, BlueTooth,
Ethernet, GPS) or interface (USB, IEEE1394, Memory Stick) clocks from e.g., a 27 MHz reference input
frequency.
The PLL supports SSC (spread-spectrum clocking). SSC can be center-spread or down-spread clocking which is
a common technique to reduce electro-magnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop filter components are automatically
adjusted to achieve high stability and optimized jitter transfer characteristic.
The device supports non-volatile EEPROM programming for ease customization of the device to the application.
It is preset to a factory default configuration (see the DEFAULT DEVICE CONFIGURATION section). It can be
re-programmed to a different application configuration before PCB assembly, or re-programmed by in-system
programming. All device settings are programmable through SDA/SCL bus, a 2-wire serial interface.
Three programmable control inputs, S0, S1 and S2, can be used to select different frequencies, or change SSC
setting for lowering EMI, or other control features like, outputs disable to low, outputs 3-state, power down, PLL
bypass etc).
The CDCx913 operates in a 1.8 V environment. It operates in a temperature range of –40° C to 85° C.
Terminal Functions for CDCE913, CDCEL913
TERMINAL
NAME
Y1–Y3
I/O
PIN TSSOP14
DESCRIPTION
11, 9, 8
O
LVCMOS outputs
Xin/CLK
1
I
Crystal oscillator input or LVCMOS clock Input (selectable via SDA/SCL bus)
Xout
14
O
Crystal oscillator output (leave open or pullup when not used)
VCtrl
4
I
VCXO control voltage (leave open or pullup when not used)
VDD
3
Power
VDDOUT
6, 7
Power
GND
5, 10
Ground
S0
2
I
SDA/S1
13
I/O or I
SCL/S2
12
I
2
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1.8-V power supply for the device
CDCEL913: 1.8-V supply for all outputs
CDCE913: 3.3-V or 2.5-V supply for all outputs
Ground
User-programmable control input S0; LVCMOS inputs; internal pullup 500k
SDA: bidirectional serial data input/output (default configuration), LVCMOS internal
pullup; or
S1: user-programmable control input; LVCMOS inputs; internal pullup 500k
SCL: serial clock input LVCMOS (default configuration), internal pullup 500k or
S2: user-programmable control input; LVCMOS inputs; internal pullup 500k
Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE913 CDCEL913
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CDCEL913
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SCAS849E – JUNE 2007 – REVISED MARCH 2010
VDD
VDDOUT
GND
LV
CMOS
Y1
M2
LV
CMOS
Y2
LV
CMOS
Y3
Pdiv1
10-Bit
M1
Xin/CLK
M3
Input Clock
Vctr
VCXO
XO
with SSC
Xout
MUX1
PLL 1
LVCMOS
PLL Bypass
EEPROM
Pdiv2
7-Bit
Pdiv3
7-Bit
Programming
and
SDA/SCL
Register
S0
S1/SDA
S2/SCL
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VDD
Supply voltage range
VI
Input voltage range (2)
(3)
(2)
VALUE
UNIT
–0.5 to 2.5
V
–0.5 to VDD + 0.5
V
VO
Output voltage range
–0.5 to VDD + 0.5
V
II
Input current (VI < 0, VI > VDD)
20
mA
IO
Continuous output current
50
mA
Tstg
Storage temperature range
–65 to 150
°C
TJ
Maximum junction temperature
125
°C
(1)
(2)
(3)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
SDA and SCL can go up to 3.6V as stated in the Recommended Operating Conditions table.
PACKAGE THERMAL RESISTANCE for TSSOP (PW) PACKAGE (1)
(2)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TJA
Thermal Resistance Junction to Ambient
AIRFLOW
(lfm)
TSSOP14
°C/W
0
106
150
93
200
92
250
90
500
85
43
TJC
Thermal Resistance Junction to Case
—
TJB
Thermal Resistance Junction to Board
—
66
RqJT
Thermal Resistance Junction to Top
—
1.4
RqJB
Thermal Resistance Junction to Bottom
—
62
(1)
(2)
The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE913 CDCEL913
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CDCEL913
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www.ti.com
RECOMMENDED OPERATING CONDITIONS
VDD
VO
MIN
NOM
MAX
Device supply voltage
1.7
1.8
1.9
Output Yx supply voltage for CDCE913, VDDOUT
2.3
3.6
Output Yx supply voltage for CDCEL913, VDDOUT
1.7
1.9
VIL
Low-level input voltage LVCMOS
VIH
High-level input voltage LVCMOS
VI
Input voltage threshold LVCMOS
(thresh)
VI(S)
VI(CLK)
IOH /IOL
0.3 VDD
0.7 VDD
0.5 VDD
1.9
Input voltage range S1, S2, SDA, SCL; VI(thresh) = 0.5 VDD
0
3.6
Input voltage range CLK
0
1.9
Output current (VDDOUT = 3.3 V)
±12
Output current (VDDOUT = 2.5 V)
±10
Output current (VDDOUT = 1.8 V)
±8
Output load LVCMOS
Operating free-air temperature
V
V
V
0
TA
V
V
Input voltage range S0
CL
UNIT
–40
V
V
mA
15
pF
85
°C
RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS (1)
fXtal
Crystal input frequency range (fundamental mode)
ESR
Effective series resistance
fPR
Pulling range (0 V ≤ VCtrl ≤ 1.8 V) (2)
NOM
MAX
UNIT
8
27
32
MHz
±120
±150
100
Frequency control voltage, VCtrl
0
C0/C1
Pullability ratio
CL
On-chip load capacitance at Xin and Xout
(1)
(2)
MIN
Ω
ppm
VDD
V
220
0
20
pF
For more information about VCXO configuration, and crystal recommendation, see application report (SCAA085).
Pulling range depends on crystal-type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm
applies for crystal listed in the application report (SCAA085).
EEPROM SPECIFICATION
EEcyc
Programming cycles of EEPROM
EEret
Data retention
4
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MIN
TYP
100
1000
10
MAX
UNIT
cycles
years
Copyright © 2007–2010, Texas Instruments Incorporated
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CDCEL913
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SCAS849E – JUNE 2007 – REVISED MARCH 2010
TIMING REQUIREMENTS
over recommended ranges of supply voltage, load, and operating free-air temperature
MIN
NOM
MAX
UNIT
CLK_IN REQUIREMENTS
PLL bypass mode
0
160
PLL mode
8
160
40%
60%
fCLK
LVCMOS clock input frequency
tr / tf
Rise and fall time CLK signal (20% to 80%)
MHz
3
Duty cycle CLK at VDD/2
STANDARD
MODE
FAST
MODE
ns
UNIT
MIN
MAX
MIN
MAX
0
100
0
400
SDA/SCL TIMING REQUIREMENTS (see Figure 12)
fSCL
SCL clock frequency
tsu(START)
START setup time (SCL high before SDA low)
th(START)
START hold time (SCL low after SDA low)
tw(SCLL)
SCL low-pulse duration
tw(SCLH)
SCL high-pulse duration
4
th(SDA)
SDA hold time (SDA valid after SCL low)
0
tsu(SDA)
SDA setup time
tr
SCL/SDA input rise time
1000
300
tf
SCL/SDA input fall time
300
300
tsu(STOP)
STOP setup time
tBUS
Bus free time between a STOP and START condition
4.7
0.6
ms
4
0.6
ms
4.7
1.3
ms
0.6
3.45
250
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kHz
0
ms
0.9
100
ms
ns
ns
ns
4
0.6
ms
4.7
1.3
ms
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CDCE913
CDCEL913
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DEVICE CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
OVERALL PARAMETER
Supply current (see Figure 3)
All outputs off, fCLK = 27 MHz,
fVCO = 135 MHz;
fOUT = 27 MHz
All PLLS on
IDD
IDD(OUT)
Supply current (see Figure 4 and Figure 5)
No load, all outputs on,
fOUT = 27 MHz
VDDOUT = 3.3 V
1.3
VDDOUT = 1.8 V
0.7
IDD(PD)
Power-down current. Every circuit powered
down except SDA/SCL
fIN = 0 MHz,
VDD = 1.9 V
30
V(PUC)
Supply voltage Vdd threshold for power-up
control circuit
fVCO
VCO frequency range of PLL
fOUT
LVCMOS output frequency
11
mA
9
Per PLL
mA
mA
0.85
1.45
V
80
230
MHz
VDDOUT = 3.3 V
230
VDDOUT = 1.8 V
230
–1.2
V
±5
mA
MHz
LVCMOS PARAMETER
VIK
LVCMOS input voltage
VDD = 1.7 V; II = –18 mA
II
LVCMOS Input current
VI = 0 V or VDD; VDD = 1.9 V
IIH
LVCMOS Input current for S0/S1/S2
VI = VDD; VDD = 1.9 V
5
mA
IIL
LVCMOS Input current for S0/S1/S2
VI = 0 V; VDD = 1.9 V
–4
mA
Input capacitance at Xin/Clk
VIClk = 0 V or VDD
6
Input capacitance at Xout
VIXout = 0 V or VDD
2
Input capacitance at S0/S1/S2
VIS = 0 V or VDD
3
CI
pF
CDCE913 - LVCMOS PARAMETER FOR VDDOUT = 3.3 V – MODE
VOH
LVCMOS high-level output voltage
VOL
LVCMOS low-level output voltage
VDDOUT = 3 V, IOH = –0.1 mA
2.9
VDDOUT = 3 V, IOH = –8 mA
2.4
VDDOUT = 3 V, IOH = –12 mA
2.2
V
VDDOUT = 3 V, IOL = 0.1 mA
0.1
VDDOUT = 3 V, IOL = 8 mA
0.5
VDDOUT = 3 V, IOL = 12 mA
0.8
V
tPLH, tPHL
Propagation delay
PLL bypass
3.2
tr/tf
Rise and fall time
VDDOUT = 3.3 V (20%–80%)
0.6
tjit(cc)
Cycle-to-cycle jitter (2)
1 PLL switching, Y2-to-Y3
50
70
ps
tjit(per)
Peak-to-peak period jitter (3)
1 PLL switching, Y2-to-Y3
60
100
ps
tsk(o)
Output skew
60
ps
odc
Output duty cycle
(4)
(3)
, See Table 2
(5)
fOUT = 50 MHz; Y1-to-Y3
fVCO = 100 MHz; Pdiv = 1
45%
ns
ns
55%
CDCE913 – LVCMOS PARAMETER for VDDOUT = 2.5 V – Mode
VOH
LVCMOS high-level output voltage
VOL
LVCMOS low-level output voltage
VDDOUT = 2.3 V, IOH = –0.1 mA
2.2
VDDOUT = 2.3 V, IOH = –6 mA
1.7
VDDOUT = 2.3 V, IOH = –10 mA
1.6
V
VDDOUT = 2.3 V, IOL = 0.1 mA
0.1
VDDOUT = 2.3 V, IOL = 6 mA
0.5
VDDOUT = 2.3 V, IOL = 10 mA
0.7
V
tPLH, tPHL
Propagation delay
PLL bypass
3.6
tr/tf
Rise and fall time
VDDOUT = 2.5 V (20%–80%)
0.8
tjit(cc)
Cycle-to-cycle jitter (2)
1 PLL switching, Y2-to-Y3
50
70
ps
tjit(per)
Peak-to-peak period jitter (3)
1 PLL switching, Y2-to-Y3
60
100
ps
tsk(o)
Output skew (4) , See Table 2
fOUT = 50 MHz; Y1-to-Y3
60
ps
odc
Output duty cycle (5)
fVCO = 100 MHz; Pdiv = 1
(1)
(2)
(3)
(4)
(5)
6
(3)
45%
ns
ns
55%
All typical values are at respective nominal VDD.
10000 cycles.
Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz (measured at Y2).
The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider.
odc depends on output rise and fall time (tr/tf); data sampled on rising edge (tr)
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CDCEL913
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SCAS849E – JUNE 2007 – REVISED MARCH 2010
DEVICE CHARACTERISTICS (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
CDCEL913 — LVCMOS PARAMETER for VDDOUT = 1.8 V – Mode
VOH
LVCMOS high-level output voltage
VOL
LVCMOS low-level output voltage
VDDOUT = 1.7 V, IOH = –0.1 mA
1.6
VDDOUT = 1.7 V, IOH = –4 mA
1.4
VDDOUT = 1.7 V, IOH = –8 mA
1.1
V
VDDOUT = 1.7 V, IOL = 0.1 mA
0.1
VDDOUT = 1.7 V, IOL = 4 mA
0.3
VDDOUT = 1.7 V, IOL = 8 mA
0.6
V
tPLH, tPHL
Propagation delay
PLL bypass
2.6
tr/tf
Rise and fall time
VDDOUT = 1.8 V (20%–80%)
0.7
tjit(cc)
Cycle-to-cycle jitter
1 PLL switching, Y2-to-Y3
80
110
ps
1 PLL switching, Y2-to-Y3
100
130
ps
50
ps
(6) (7)
(7)
tjit(per)
Peak-to-peak period jitter
tsk(o)
Output skew (8) , See Table 2
fOUT = 50 MHz; Y1-to-Y3
odc
Output duty cycle (9)
fVCO = 100 MHz; Pdiv = 1
45%
ns
ns
55%
SDA/SCL PARAMETER
VIK
SCL and SDA input clamp voltage
VDD = 1.7 V; II = –18 mA
–1.2
V
IIH
SCL and SDA input current
VI = VDD; VDD = 1.9 V
±10
mA
VIH
SDA/SCL input high voltage (10)
VIL
SDA/SCL input low voltage (10)
VOL
SDA low-level output voltage
IOL = 3 mA, VDD = 1.7 V
CI
SCL/SDA Input capacitance
VI = 0 V or VDD
(6)
(7)
(8)
(9)
(10)
0.7 VDD
V
0.3 VDD
3
V
0.2 VDD
V
10
pF
10000 cycles.
Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz (measured at Y2).
The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider.
odc depends on output rise and fall time (tr/tf); data sampled on rising edge (tr)
SDA and SCL pins are 3.3 V tolerant.
PARAMETER MEASUREMENT INFORMATION
CDCE913
CDCEL913
1 kW
LVCMOS
1 kW
10 pF
Figure 1. Test Load
CDCE913
CDCEL913
LVCMOS
LVCMOS
Typical Driver
Impedance
~ 32 W
Series
Termination
~ 18 W
Line Impedance
Zo = 50 W
Figure 2. Test Load for 50-Ω Board Environment
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CDCEL913
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TYPICAL CHARACTERISTICS
CDCE913, CDCEL913
SUPPLY CURRENT
vs
PLL FREQUENCY
CDCE913
OUTPUT CURRENT
vs
OUTPUT FREQUENCY
16
30
VDD = 1.8 V
14
3 Outputs on
12
20
IDDOUT - mA
IDD - Supply Current - mA
25
VDD = 1.8 V,
VDDOUT = 3.3 V,
no load
1 PLL on
15
10
1 Output on
8
6
10
4
all PLL off
5
2
0
10
60
110
160
fVCO - Frequency - MHz
0
10
210
all Outputs off
30
50 70 90 110 130 150 170 190 210 230
fOUT - Output Frequency - MHz
Figure 3.
Figure 4.
CDCEL913
OUTPUT CURRENT
vs
OUTPUT FREQUENCY
4.5
4
VDD = 1.8 V,
VDDOUT = 1.8 V,
no load
3 Outputs on
IDDOUT - mA
3.5
3
2.5
2
1 Output on
1.5
1
all Outputs off
0.5
0
10 30 50
70
90 110 130 150 170 190 210 230
fOUT - Output Frequency - MHz
Figure 5.
8
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APPLICATION INFORMATION
CONTROL TERMINAL CONFIGURATION
The CDCE913/CDCEL913 has three user-definable control terminals (S0, S1, and S2) which allow external
control of device settings. They can be programmed to any of the following functions:
• Spread spectrum clocking selection → spread type and spread amount selection
• Frequency selection → switching between any of two user-defined frequencies
• Output state selection → output configuration and power down control
The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.
Table 1. Control Terminal Definition
External Control Bits
PLL1 Setting
PLL Frequency
Selection
Control Function
SSC Selection
Y1Setting
Output Y2/Y3 Selection
Output Y1 and Power-Down Selection
Table 2. PLLx Setting (can be selected for each PLL individual) (1)
SSC Selection (Center/Down)
SSCx [3-bits]
Center
Down
0
0
0
0% (off)
0% (off)
0
0
1
±0.25%
–0.25%
0
1
0
±0.5%
–0.5%
0
1
1
±0.75%
–0.75%
1
0
0
±1.0%
–1.0%
1
0
1
±1.25%
–1.25%
1
1
0
±1.5%
–1.5%
1
1
1
±2.0%
–2.0%
FREQUENCY SELECTION (2)
FSx
FUNCTION
0
Frequency0
1
Frequency1
OUTPUT SELECTION (3) (Y2 ... Y3)
(1)
(2)
(3)
YxYx
FUNCTION
0
State0
1
State1
Center/Down-Spread, Frequency0/1 and State0/1 are user-definable in PLLx Configuration Register;
Frequency0 and Frequency1 can be any frequency within the specified fVCO range.
State0/1 selection is valid for both outputs of the corresponding PLL module and can be power down,
3-state, low or active
Table 3. Y1 Setting (1)
Y1 SELECTION
(1)
Y1
FUNCTION
0
State 0
1
State 1
State0 and State1 are user definable in Generic Configuration
Register and can be power down, 3-state, low, or active.
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S1/SDA and S2/SCL pins of the CDCE913/CDCEL913 are dual function pins. In default configuration they are
defined as SDA/SCL for the serial programming interface. They can be programmed as control-pins (S1/S2) by
setting the appropriate bits in the EEPROM. Note that the changes to the Control Register (Bit [6] of Byte 02h)
have no effect until they are written into the EEPROM.
Once they are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is
forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL).
S0 is not a multi use pin; it is a control pin only.
DEFAULT DEVICE CONFIGURATION
The internal EEPROM of CDCE913/CDCEL913 is pre-configured with a factory default configuration as shown in
Figure 6 (The input frequency is passed through the output as a default).This allows the device to operate in
default mode without the extra production step of programming it. The default setting appears after power is
supplied or after power-down/up sequence until it is reprogrammed by the user to a different application
configuration. A new register setting is programmed via the serial SDA/SCL Interface.
VDD
VDDOUT
GND
1 = Output Enabled
0 = Output 3-State
EEPROM
Programming
and
SDA/SCL
Register
S0
Programming Bus
SDA
SCL
Pdiv2 = 1
Y2 = 27 MHz
LV
CMOS
Y3 = 27 MHz
MUX1
Xout
LV
CMOS
Pdiv1 =1
X-tal
PLL 1
power down
Y1 = 27 MHz
M2
27 MHz
Crystal
LV
CMOS
M3
M1
Input Clock
Xin
Pdiv3 = 1
PLL Bypass
Figure 6. Default Configuration
Table 4 shows the factory default setting for the Control Terminal Register. Note that even though 8 different
register settings are possible, in default configuration, only the first two settings (0 and 1) can be selected with
S0, as S1 and S2 are configured as programming pins in default mode.
Table 4. Factory Default Setting for Control Terminal Register (1)
Y1
External Control Pins
PLL1 Settings
Output Selection
Frequency Selection
SSC Selection
Output Selection
Y1
FS1
SSC1
Y2Y3
S2
S1
S0
SCL (I2C)
SDA (I2C)
0
3-state
fVCO1_0
off
3-state
SCL (I2C)
SDA (I2C)
1
enabled
fVCO1_0
off
enabled
(1)
In default mode or when programmed respectively, S1 and S2 act as serial programming interface, SDA/SCL. They do not have any
control-pin function but they are internally interpreted as if S1=0 and S2=0. S0, however, is a control-pin which in the default mode
switches all outputs ON or OFF (as previously predefined).
SDA/SCL SERIAL INTERFACE
The CDCE913/CDCEL913 operates as a slave device of the 2-wire serial SDA/SCL bus, compatible with the
popular SMBus or I2C specification. It operates in the standard-mode transfer (up to 100kbit/s) and fast-mode
transfer (up to 400kbit/s) and supports 7-bit addressing.
The S1/SDA and S2/SCL pins of the CDCE913/CDCEL913 are dual function pins. In the default configuration
they are used as SDA/SCL serial programming interface. They can be re-programmed as general purpose
control pins, S1 and S2, by changing the corresponding EEPROM setting, Byte 02h, Bit [6].
10
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DATA PROTOCOL
The device supports Byte Write and Byte Read and Block Write and Block Read operations.
For Byte Write/Read operations, the system controller can individually access addressed bytes.
For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with
most significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of
Bytes read-out are defined by Byte Count in the Generic Configuration Register. At Block Read instruction, all
bytes defined in the Byte Count must be readout to correctly finish the read cycle.
Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to
each transferred byte regardless of whether this is a Byte Write or a Block Write sequence.
If the EEPROM Write Cycle is initiated, the internal SDA registers are written into the EEPROM. During this Write
Cycle, data is not accepted at the SDA/SCL bus until the write cycle is completed. However, data can be read
out during the programming sequence (Byte Read or Block Read). The programming status can be monitored by
EEPIP, byte 01h–bit 6.
The offset of the indexed byte is encoded in the command code, as described in Table 5.
Table 5. Slave Receiver Address (7 Bits)
A6
A5
A4
A3
A2
A1 (1)
A0 (1)
R/W
CDCE913/CDCEL913
1
1
0
0
1
0
1
1/0
CDCE925/CDCEL925
1
1
0
0
1
0
0
1/0
CDCE937/CDCEL937
1
1
0
1
1
0
1
1/0
CDCE949/CDCEL949
1
1
0
1
1
0
0
1/0
DEVICE
(1)
Address bits A0 and A1 are programmable via the SDA/SCL bus (byte 01, bit [1:0]. This allows addressing up to 4 devices connected to
the same SDA/SCL bus. The least-significant bit of the address byte designates a write or read operation.
COMMAND CODE DEFINITION
Table 6. Command Code Definition
BIT
7
(6:0)
DESCRIPTION
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
Byte Offset for Byte Read, Block Read, Byte Write and Block Write operation.
Generic Programming Sequence
1
S
7
Slave Address
MSB
LSB
S
Start Condition
Sr
Repeated Start Condition
R/W
1
R/W
1
A
8
Data Byte
MSB
1
A
1
P
LSB
1 = Read (Rd) From CDCE9xx Device; 0 = Write (Wr) to CDCE9xxx
A
Acknowledge (ACK = 0 and NACK =1)
P
Stop Condition
Master-to-Slave Transmission
Slave-to-Master Transmission
Figure 7. Generic Programming Sequence
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Byte Write Programming Sequence
1
S
7
Slave Address
1
Wr
1
A
8
CommandCode
1
A
8
Data Byte
1
A
1
P
7
Slave Address
1
Rd
1
A
1
A
1
P
Figure 8. Byte Write Protocol
Byte Read Programming Sequence
1
S
7
Slave Address
1
Wr
1
A
8
Data Byte
1
A
1
P
8
CommandCode
1
A
1
S
Figure 9. Byte Read Protocol
Block Write Programming Sequence
1
S
(1)
7
Slave Address
1
Wr
8
Data Byte 0
1
A
1
A
8
CommandCode
8
Data Byte 1
1
A
1
A
8
Byte Count = N
1
A
8
Data Byte N-1
…
Data byte 0 bits [7:0] is reserved for Revision Code and Vendor Identification. Also, it is used for internal test purpose
and should not be overwritten.
Figure 10. Block Write Protocol
Block Read Programming Sequence
1
S
7
Slave Address
1
Wr
8
Byte Count N
1
A
1
A
8
CommandCode
8
Data Byte 0
1
A
1
A
1
Sr
…
7
Slave Address
1
Rd
1
A
8
Data Byte N-1
1
A
1
P
Figure 11. Block Read Protocol
Timing Diagram for the SDA/SCL Serial Control Interface
P
S
tw(SCLL)
Bit 7 (MSB)
tw(SCLH)
Bit 6
tr
Bit 0 (LSB)
A
P
tf
VIH
SCL
VIL
tsu(START)
th(START)
tsu(SDA)
th(SDA)
t(BUS)
tr
tsu(STOP)
tf
VIH
SDA
VIL
Figure 12. Timing Diagram for SDA/SCL Serial Control Interface
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SDA/SCL HARDWARE INTERFACE
Figure 13 shows how the CDCE913/CDCEL913 clock synthesizer is connected to the SDA/SCL serial interface
bus. Multiple devices can be connected to the bus but the speed may need to be reduced (400 kHz is the
maximum) if many devices are connected.
Note that the pullup resistors (RP) depends on the supply voltage, bus capacitance, and number of connected
devices. The recommended pullup value is 4.7 kΩ. It must meet the minimum sink current of 3 mA at
VOLmax = 0.4 V for the output stages (for more details see the SMBus or I2C™ Bus specification).
CDCE913
CDCEL913
RP
RP
Master
Slave
SDA
SCL
CBUS
CBUS
Figure 13. SDA / SCL Hardware Interface
SDA/SCL CONFIGURATION REGISTERS
The clock input, control pins, PLLs, and output stages are user configurable. The following tables and
explanations describe the programmable functions of the CDCE913/CDCEL913. All settings can be manually
written into the device via the SDA/SCL bus or easily programmed by using the TI Pro-Clock™ software. TI
Pro-Clock™ software allows the user to quickly make all settings and automatically calculates the values for
optimized performance at lowest jitter.
Table 7. SDA/SCL Registers
Address Offset
Register Description
Table
00h
Generic Configuration Register
Table 9
10h
PLL1 Configuration Register
Table 10
The grey-highlighted bits, described in the Configuration Registers tables in the following pages, belong to the
Control Terminal Register. The user can predefine up to eight different control settings. These settings then can
be selected by the external control pins, S0, S1, and S2. See the Control Terminal Configuration section.
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Table 8. Configuration Register,
External Control Terminals
Y1
External Control
Pins
Output Selection
14
Frequency Selection
SSC Selection
Output Selection
S2
S1
S0
Y1
FS1
SSC1
Y2Y3
0
0
0
0
Y1_0
FS1_0
SSC1_0
Y2Y3_0
1
0
0
1
Y1_1
FS1_1
SSC1_1
Y2Y3_1
2
0
1
0
Y1_2
FS1_2
SSC1_2
Y2Y3_2
3
0
1
1
Y1_3
FS1_3
SSC1_3
Y2Y3_3
4
1
0
0
Y1_4
FS1_4
SSC1_4
Y2Y3_4
5
1
0
1
Y1_5
FS1_5
SSC1_5
Y2Y3_5
6
1
1
0
Y1_6
FS1_6
SSC1_6
Y2Y3_6
7
1
1
1
Y1_7
FS1_7
SSC1_7
Y2Y3_7
04h
13h
10h–12h
15h
Address Offset (1)
(1)
PLL1 Settings
Address Offset refers to the byte address in the Configuration Register in Table 9 and Table 10.
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Table 9. Generic Configuration Register
Offset
00h
(1)
Bit
(2)
Acronym
Default
(3)
Description
7
E_EL
Xb
Device identification (read-only): 1 is CDCE913 (3.3 V out), 0 is CDCEL913 (1.8 V out)
6:4
RID
Xb
Revision Identification Number (read only)
3:0
VID
1h
Vendor Identification Number (read only)
7
–
0b
Reserved – always write 0
6
EEPIP
0b
EEPROM Programming Status4: (4) (read only)
0 – EEPROM programming is completed
1 – EEPROM is in programming mode
5
EELOCK
0b
Permanently Lock EEPROM Data (5)
0 – EEPROM is not locked
1 – EEPROM will be permanently locked
4
PWDN
0b
Device Power Down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)
Note: PWDN cannot be set to 1 in the EEPROM.
01h
0 – device active (PLL1 and all outputs are enabled)
1 – device power down (PLL1 in power down and all outputs in 3-state)
3:2
INCLK
00b
00 – Xtal
10 – LVCMOS
01 – VCXO
11 – reserved
Input clock selection:
1:0
SLAVE_ADR
01b
Address Bits A0 and A1 of the Slave Receiver Address
7
M1
1b
Clock source selection for output Y1:
0 – input clock
1 – PLL1 clock
Operation mode selection for pin 12/13 (6)
02h
6
SPICON
0b
5:4
Y1_ST1
11b
3:2
Y1_ST0
01b
1:0
Pdiv1 [9:8]
7:0
Pdiv1 [7:0]
7
Y1_7
0b
6
Y1_6
0b
5
Y1_5
0b
4
Y1_4
0b
3
Y1_3
0b
2
Y1_2
0b
1
Y1_1
1b
0
Y1_0
0b
001h
03h
04h
0 – serial programming interface SDA (pin 13) and SCL (pin 12)
1 – control pins S1 (pin 13) and S2 (pin 12)
Y1-State0/1 Definition
00 – device power down (all PLLs in power down and all
outputs in 3-State)
01 – Y1 disabled to 3-state
10-Bit Y1-Output-Divider Pdiv1:
0 – divider reset and stand-by
1-to-1023 – divider value
Y1_x State Selection (7)
0 – State0 (predefined by Y1_ST0)
1 – State1 (predefined by Y1_ST1)
Crystal Load Capacitor Selection (8)
7:3
XCSEL
10 – Y1 disabled to low
11 – Y1 enabled
0Ah
05h
00h → 0 pF
01h → 1 pF
02h → 2 pF
:14h-to-1Fh → 20 pF
Vctr
Xin
20pF
i.e.
XCSEL = 10pF
XO
Xout
2:0
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
0b
VCXO
20pF
Reserved – do not write other than 0
Writing data beyond ‘20h’ may affect device function.
All data transferred with the MSB first.
Unless customer-specific setting.
During EEPROM programming, no data is allowed to be sent to the device via the SDA/SCL bus until the programming sequence is
completed. Data, however, can be read out during the programming sequence (Byte Read or Block Read).
If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. No further programming is possible.
Data, however can still be written via SDA/SCL bus to the internal register to change device function on the fly. But new data can no
longer be saved to the EEPROM. EELOCK is effective only, if written into the EEPROM.
Selection of “control pins” is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are
no longer available. However, if VDDOUT is forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins
(SDA/SCL), and the two slave receiver address bits are reset to A0=”0” and A1=“0”.
These are the bits of the Control Terminal Register (see Table 8). The user can predefine up to eight different control settings. These
settings then can be selected by the external control pins, S0, S1, and S2.
The internal load capacitor (C1, C2) has to be used to achieve the best clock performance. External capacitors should be used only to
finely adjust CL by a few picofarads. The value of CL can be programmed with a resolution of 1 pF for a crystal load range of 0 pF to 20
pF. For CL > 20 pF, use additional external capacitors. Also, the value of the device input capacitance has to be considered which
always adds 1.5 pF (6 pF//2 pF) to the selected CL. For more information about VCXO configuration and crystal recommendation, see
application report SCAA085.
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Table 9. Generic Configuration Register (continued)
Offset (1)
Bit (2)
Acronym
Default (3)
Description
7:1
BCOUNT
20h
7-Bit Byte Count (defines the number of bytes which will be sent from this device at the next Block Read transfer); all bytes
have to be read out to correctly finish the read cycle.
0
EEWRITE
0b
Initiate EEPROM Write Cycle
—
0h
Unused address range
06h
07h-0Fh
(9)
(4) (9)
0– no EEPROM write cycle
1 – start EEPROM write cycle (internal register are saved to the EEPROM)
The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The
EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level high does not trigger an EEPROM WRITE cycle. The
EEWRITE bit has to be reset to low after the programming is completed. The programming status can be monitored by reading out
EEPIP. If EELOCK is set to high, no EEPROM programming is possible.
Table 10. PLL1 Configuration Register
OFFSET (1)
10h
11h
12h
13h
14h
15h
(1)
(2)
(3)
(4)
16
Bit (2)
Acronym
Default (3)
7:5
SSC1_7 [2:0]
000b
4:2
SSC1_6 [2:0]
000b
1:0
SSC1_5 [2:1]
7
SSC1_5 [0]
6:4
SSC1_4 [2:0]
000b
3:1
SSC1_3 [2:0]
000b
0
SSC1_2 [2]
7:6
SSC1_2 [1:0]
5:3
SSC1_1 [2:0]
000b
2:0
SSC1_0 [2:0]
000b
7
FS1_7
0b
6
FS1_6
0b
5
FS1_5
0b
4
FS1_4
0b
3
FS1_3
0b
2
FS1_2
0b
1
FS1_1
0b
0
FS1_0
0b
7
MUX1
1b
PLL1 Multiplexer:
0 – PLL1
1 – PLL1 Bypass (PLL1 is in power down)
6
M2
1b
Output Y2 Multiplexer:
0 – Pdiv1
1 – Pdiv2
5:4
M3
10b
Output Y3 Multiplexer:
00 –
01 –
10 –
11 –
3:2
Y2Y3_ST1
11b
Y2, Y3-State0/1definition:
00 – Y2/Y3 disabled to 3-State (PLL1 is in power down)
01 – Y2/Y3 disabled to 3-State
10–Y2/Y3 disabled to low
11 – Y2/Y3 enabled
000b
000b
1:0
Y2Y3_ST0
01b
7
Y2Y3_7
0b
6
Y2Y3_6
0b
5
Y2Y3_5
0b
4
Y2Y3_4
0b
3
Y2Y3_3
0b
2
Y2Y3_2
0b
1
Y2Y3_1
1b
0
Y2Y3_0
0b
DESCRIPTION
SSC1: PLL1 SSC Selection (Modulation Amount) (4)
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
FS1_x: PLL1 Frequency Selection (4)
0 – fVCO1_0 (predefined by PLL1_0 – Multiplier/Divider value)
1 – fVCO1_1 (predefined by PLL1_1 – Multiplier/Divider value)
Y2Y3_x Output State Selection
Pdiv1-Divider
Pdiv2-Divider
Pdiv3-Divider
reserved
(4)
0 – state0 (predefined by Y2Y3_ST0)
1 – state1 (predefined by Y2Y3_ST1)
Writing data beyond 20h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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Table 10. PLL1 Configuration Register (continued)
OFFSET (1)
Bit (2)
Acronym
Default (3)
DESCRIPTION
7
SSC1DC
0b
PLL1 SSC down/center selection:
0 – down
1 – center
6:0
Pdiv2
01h
7-Bit Y2-Output-Divider Pdiv2:
0 – reset and stand-by
1-to-127 is divider value
7
—
0b
Reserved – do not write others than 0
6:0
Pdiv3
01h
7-Bit Y3-Output-Divider Pdiv3:
7:0
PLL1_0N [11:4]
7:4
PLL1_0N [3:0]
3:0
PLL1_0R [8:5]
7:3
PLL1_0R[4:0]
2:0
PLL1_0Q [5:3]
7:5
PLL1_0Q [2:0]
4:2
PLL1_0P [2:0]
010b
1:0
VCO1_0_RANGE
00b
7:0
PLL1_1N [11:4]
7:4
PLL1_1N [3:0]
3:0
PLL1_1R [8:5]
7:3
PLL1_1R[4:0]
2:0
PLL1_1Q [5:3]
7:5
PLL1_1Q [2:0]
4:2
PLL1_1P [2:0]
010b
1:0
VCO1_1_RANGE
00b
16h
17h
18h
19h
1Ah
004h
000h
PLL1_0 (5): 30-Bit Multiplier/Divider value for frequency fVCO1_0
(for more information, see paragraph PLL Multiplier/Divider Definition).
10h
1Bh
1Ch
1Dh
1Eh
1Fh
(5)
0 – reset and stand-by
1-to-127 is divider value
fVCO1_0 range selection:
00 –
01 –
10 –
11 –
fVCO1_0 < 125 MHz
125 MHz ≤ fVCO1_0 < 150 MHz
150 MHz ≤ fVCO1_0 < 175 MHz
fVCO1_0 ≥ 175 MHz
004h
000h
PLL1_1 (5): 30-Bit Multiplier/Divider value for frequency fVCO1_1
(for more information see paragraph PLL Multiplier/Divider Definition)
10h
fVCO1_1 range selection:
00 –
01 –
10 –
11 –
fVCO1_1 < 125 MHz
125 MHz ≤ fVCO1_1 < 150 MHz
150 MHz ≤ fVCO1_1 < 175 MHz
fVCO1_1 ≥ 175 MHz
PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096
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PLL Multiplier/Divider Definition
At a given input frequency (ƒIN), the output frequency (ƒOUT) of the CDCE913/CDCEL913 can be calculated:
ƒ
N
ƒ OUT + IN
Pdiv M
(1)
where
M (1 to 511) and N (1 to 4095) are the multiplier/divide values of the PLL; Pdiv (1 to 127) is the output
divider.
The target VCO frequency (ƒVCO) of each PLL can be calculated:
N
ƒ VCO + ƒIN
M
(2)
The PLL internally operates as fractional divider and needs the following multiplier/divider settings:
• N
•
•
•
ǒ
log N Ǔ [if P t 0 then P + 0]
M
P = 4 – int
NȀǓ
ǒ
Q = int M
2
R = N′ – M × Q
where
N′ = N × 2P;
N ≥ M;
100 MHz < ƒVCO > 200 MHz;
16 ≤ q ≤ 63
0≤p≤7
0 ≤ r ≤ 51
Example:
for ƒIN = 27 MHz; M = 1; N = 4; Pdiv = 2;
for ƒIN = 27 MHz; M = 2; N = 11; Pdiv = 2;
→ fOUT = 54 MHz
→ fOUT = 74.25 MHz
→ fVCO = 108 MHz
→ fVCO = 148.50 MHz
→ P = 4 – int(log24) = 4 – 2 = 2
→ P = 4 – int(log25.5) = 4 – 2 = 2
2
→ N′’ = 4 × 2 = 16
→ N′’ = 11 × 22 = 44
→ Q = int(16) = 16
→ Q = int(22) = 22
→ R = 16 – 16 = 0
→ R = 44 – 44 = 0
The values for P, Q, R, and N’ are automatically calculated when using TI Pro-Clock™ software.
18
Submit Documentation Feedback
Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE913 CDCEL913
CDCE913
CDCEL913
www.ti.com
SCAS849E – JUNE 2007 – REVISED MARCH 2010
REVISION HISTORY
Changes from Revision B (December 2007) to Revision C
Page
•
Added SDA and SCL can go up to 3.6V as stated in the Recommended Operating Conditions table ............................... 3
•
Deleted 230 value, moved to Max ........................................................................................................................................ 6
•
Deleted 230 value, moved to Max ........................................................................................................................................ 6
Changes from Revision C (September) to Revision D
•
Page
Deleted sentence - A different default setting can be programmed upon customer request. Contact Texas
Instruments sales or marketing representative for more information. ................................................................................ 10
Changes from Revision D (October 2009) to Revision E
Page
•
Added PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096 foot to PLL1 Configure Register Table ....................... 17
•
Added PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511 to PLL Multiplier/Divider Definition Section .................................... 18
Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE913 CDCEL913
Submit Documentation Feedback
19
PACKAGE OPTION ADDENDUM
www.ti.com
26-Apr-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
CDCE913PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Add to cart
CDCE913PWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Add to cart
CDCE913PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Add to cart
CDCE913PWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Add to cart
CDCEL913PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Add to cart
CDCEL913PWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Add to cart
CDCEL913PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Add to cart
CDCEL913PWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Add to cart
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Apr-2012
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CDCEL913 :
• Automotive: CDCEL913-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CDCE913PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CDCEL913PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCE913PWR
TSSOP
PW
14
2000
367.0
367.0
35.0
CDCEL913PWR
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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