ALSC AS80SSTVF16857-48VT Ddr 14-bit registered buffer Datasheet

July 2003
Advance Information
PulseC re AS80SSTVF16857
Š
DDR 14-Bit Registered Buffer
Features
Recommended Applications
•
•
•
•
•
•
•
•
Block Diagram
CLK
CLKB
RESETB
D1
VREF
Pin Configuration
38
39
34
48
35
•
DDR memory modules
Provides complete DDR DIMM logic solution
with PCV857
SSTL_2-compatible data registers
R
CLK
D1
To 13 other channels
Q1
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AS80SSTVF16857
•
Differential clock signals
Meets SSTL_2 class II specifications on outputs
Supports SSTL_2 Class I and II specifications
Low voltage operation – VDD = 2.3V to 2.7V
Available in 48-pin TSSOP and TVSOP package
Operates at 2.3V to 2.7V for PC1600, PC2100, and
PC2700; 2.5V to 2.7V for PC3200
Pinout and Functionality Compatible with JEDEC
Standard SSTV16857
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLKB
CLK
VDD
GND
VREF
RESETB
D8
D9
D10
D11
D12
VDD
GND
D13
D14
48-Pin TSSOP & TVSOP
6.10 mm body, 0.50 mm pitch = TSSOP
4.40 mm body, 0.40 mm pitch = TSSOP (TVSOP)
8/1/03; V.0.10
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AS80SSTVF16857
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Truth Table1
Inputs
Q outputs
RESETB
CLK
CLKB
D
Q
L
X or floating
X or floating
X or floating
L
H
↑
↓
H
H
H
↑
↓
L
L
H
L or H
L or H
X
Q 02
1 H = high signal level, L = low signal level, ↑ = transition low to high, ↓ = transition high to low, X = don’t care.
2 Output level before the indicated steady state input conditions were established.
Description
The 14-bit PC16857 is a universal bus driver designed for 2.3 V to 2.7 V VDD operation and SSTL_2 I/O levels,
except for the LVCMOS RESETB input.
Data flow from D to Q is controlled by the differential clock (CLK/CLKB) and a control signal (RESETB). The
positive edge of CLK is used to trigger the data flow, and CLKB is used to maintain sufficient noise margins,
whereas RESETB, an LVCMOS asynchronous signal, is intended for use only at power-up. PC16857 supports
low-power standby operation. A logic level low at RESETB assures that all internal registers and outputs (Q) are
reset to the logic low state, and that all input receivers, data (D), and clock (CLK/CLKB) are switched off. Note that
RESETB must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable
during power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB must be held
at a logic low level during power-up.
In the DDR DIMM application, RESETB is specified to be completely asynchronous with respect to CLK and
CLKB, therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power
standby state, the register will be cleared and the outputs will be driven to a logic low level quickly relative to the
time to disable the differential input receivers. This ensures there are no glitches on the output. When coming out
of low power standby state, however, the register will become active quickly relative to the time to enable the
differential input receivers. When the data inputs are at a logic level low and the clock is stable during the low-tohigh transition of RESETB until the input receivers are fully enabled, the design ensures that the outputs will
remain at a logic low level.
8/1/03, V.0.10
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AS80SSTVF16857
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Pin Configuration
Pin number
1, 2, 5, 6, 7, 10, 11, 14, 15, 18, 19, 20, 23, 24
3, 8, 13, 22, 27, 36, 46
4, 9, 12, 16, 21
25, 26, 29, 30, 31, 32, 33, 40, 41, 42, 43, 44, 47,48
38
39
28, 37, 45
34
35
Pin name
Q(14:1)
GND
VDDQ
D(14:1)
CLK
CLKB
VDD
RESETB
VREF
Type
Output
PWR
PWR
Input
Input
Input
PWR
Input
Input
Description
Data output
Ground
Output supply voltage
Data input
Positive clock input
Negative clock input
Core supply voltage
Reset (active low)
Input reference voltage
Absolute Maximum Ratings
Storage temperature
- 65° C to +150° C
Supply voltage
-0.5 to 3.6 V
1
Input voltage
Output voltage
-0.5 to VDD + 0.5
1,2
-0.5 to VDDQ + 0.5
Input clamp current
± 50 mA
Output clamp current
± 50 mA
Continuous output current
± 50 mA
VDD, VDDQ, or GND current/pin
Package thermal impedance
± 100 mA
3
55° C/W
1 The input and output negative voltage ratings may be excluded if the input and output clamp ratings are
observed.
2 This current will flow only when the output is in the high state level V0 > VDDQ.
3 The package thermal impedance is calculated in accordance with JESD 51.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only, and functional operation of the device at these or any other conditions
above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect product reliability.
8/1/03, V.0.10
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AS80SSTVF16857
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Recommended Operating Conditions
Guaranteed by design. Not 100% tested in production.
Parameter
VDD
VDDQ
VREF
VTT
VI
Description
Min
Max
Units
VDDQ
2.7
V
PC1600, PC2100,
PC2700
2.3
2.7
V
PC3200
2.5
2.7
V
Reference voltage
PC1600, PC2100,
PC2700
1.15
1.25
1.35
V
(VREF=VDDQ/2)
PC3200
1.25
1.3
1.35
V
VREF - 0.04
VREF
VREF + 0.04
V
VDD
V
Supply voltage
Output supply voltage
Termination voltage
Input voltage
VIH(DC)
DC input high voltage
VIH(AC)
AC input high voltage
VIL(DC)
DC input low voltage
VIL(AC)
AC input low voltage
VIH
Input high voltage level
VIL
Input low voltage level
0
Data inputs
RESETB
VICR
Common mode input range
VID
Differential input voltage
VIX
Cross-point voltage of differential clock pair
IOH
CLK,CLKB
Typ
VREF + 0.15
V
VREF + 0.31
V
VREF - 0.15
V
VREF - 0.31
V
1.7
0.97
V
0.7
V
1.53
V
0.36
V
(VDDQ/2) + 0.2
V
High-level output current
-20
mA
IOL
Low-level output current
20
mA
TA
Operating free-air temperature
70
°C
8/1/03, V.0.10
(VDDQ/2) - 0.2
0
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AS80SSTVF16857
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DC Electrical Characteristics for PC1600, PC2100, and PC2700
TA = 0° C to 70° C, VDD = 2.5 ± 0.2 V, and VDDQ = 2.5 ± 0.2 V (unless otherwise stated)
Guaranteed by design. Not 100% tested in production.
Symbol
Parameters
VIK
VOH
VOL
II
IDD
All inputs
Test conditions
VDD
Min
Typ
Max
Units
-1.2
V
II = -18 mA
2.3 V
IOH = -100 µA
2.3 V to
2.7 V
VDD 0.2
V
IOH = -16 mA
2.3 V
1.95
V
IOL = 100 µA
2.3 V to
2.7 V
0.2
V
IOL = 16 mA
2.3 V
0.35
V
VI = VDD or GND
2.7 V
±5
µA
Standby (static)
RESETB = GND
2.7 V
0.01
µA
Operating
(static)
VI = VIH(AC) or VIL(AC),
RESETB = VDD
2.7 V
25
mA
Dynamic
operating (clock
only)
RESETB = VDD,
VI = VIH(AC) or VIL(AC),
CLK and CLKB = switching
50% duty cycle
2.7 V
IDDD
Dynamic
operating (per
each data input)
RESETB = VDD,
VI = VIH(AC) or VIL(AC),
CLK and CLKB switching
50% duty cycle
28
µA/
clock
MHz
15
µΑ/
clock
MHz/
data
input
IO = 0
2.7 V
One data input switching at
half clock frequency, 50% duty
cycle
rOH
Output high
IOH = -20 mA
2.3 V to
2.7 V
7
13.5
20
Ω
rOL
Output low
IOL = 20 mA
2.3 V to
2.7 V
7
13
20
Ω
rO(D)
|rOH - rOL| each
separate bit
IO = 20 mA, TA = 25° C
2.5 V
4
Ω
Data inputs
VI = VREF ± 310 mV,
2.5 V
2.5
3.5
pF
VICR = 1.25 V,
CI
CLK and CLKB
VI(PP) = 360 mV
2.5 V
2.5
3.5
pF
RESETB
VI=VDD or GND
2.5V
2.5
3.5
pF
8/1/03, V.0.10
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AS80SSTVF16857
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DC Electrical Characteristics for PC3200
TA = 0° C to 70° C, VDD = 2.6 ± 0.1 V, and VDDQ = 2.6 ± 0.1 V (unless otherwise stated)
Guaranteed by design. Not 100% tested in production.
Symbol
Parameters
VIK
VOH
VOL
II
IDD
All inputs
Test conditions
VDD
Min
Typ
Max
Units
-1.2
V
II = -18 mA
2.5 V
IOH = -100 µA
2.5 V to
2.7 V
VDD 0.2
V
IOH = -16 mA
2.5 V
1.95
V
IOL = 100 µA
2.5 V to
2.7 V
0.2
V
IOL = 16 mA
2.5 V
0.35
V
VI = VDD or GND
2.7 V
±5
µA
Standby (static)
RESETB = GND
2.7 V
0.01
µA
Operating
(static)
VI = VIH(AC) or VIL(AC),
RESETB = VDD
2.7 V
25
mA
Dynamic
operating (clock
only)
RESETB = VDD,
VI = VIH(AC) or VIL(AC),
CLK and CLKB = switching
50% duty cycle
2.7 V
IDDD
Dynamic
operating (per
each data input)
RESETB = VDD,
VI = VIH(AC) or VIL(AC),
CLK and CLKB switching
50% duty cycle
28
µA/
clock
MHz
15
µΑ/
clock
MHz/
data
input
IO = 0
2.7 V
One data input switching at
half clock frequency, 50% duty
cycle
rOH
Output high
IOH = -20 mA
2.5 V to
2.7 V
7
13.5
20
Ω
rOL
Output low
IOL = 20 mA
2.5 V to
2.7 V
7
13
20
Ω
rO(D)
|rOH - rOL| each
separate bit
IO = 20 mA, TA = 25° C
2.6 V
4
Ω
Data inputs
VI = VREF ± 310 mV,
2.6 V
2.5
3.5
pF
VICR = 1.25 V,
Ci
CLK and CLKB
VI(PP) = 360 mV
2.6 V
2.5
3.5
pF
RESETB
VI=VDD or GND
2.6V
2.5
3.5
pF
8/1/03, V.0.10
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Timing Requirements
(Over recommended operating free-air temperature range, unless otherwise noted.)
Guaranteed by design. Not 100% tested in production.
VDD = 2.5 V ± 0.2 V
Symbol
fclock
tw
tact
tinact
tSu
th
tSL
Parameters
Min
Max
Clock frequency
Min
Differential inputs inactive
22
22
ns
22
22
ns
3,5
3,5
Hold time, slow slew rate
ns
2
rate4,5
Hold time, fast slew rate
2.5
MHz
time1
Differential inputs inactive time
Setup time, fast slew rate
280
2.5
Units
Max
200
Pulse duration, CLK, CLKB high or low
Setup time, slow slew
VDD = 2.6 V ± 0.1 V
4,5
Data before CLK↑,
CLKB↓
0.75
0.4
ns
0.9
0.5
ns
Data after CLK↑,
CLKB↓
0.75
0.4
ns
0.9
0.5
ns
Output slew rate, measurement point at 20% and
80%
1
4
1
4
V/ns
1 Data inputes must be low a minimum time of tact max, after RESETB is taken high.
2 Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max, after RESETB is taken low.
3 For data signal input slew rate > 1V/ns.
4 For data signal input slew rate > 0.5 V/ns and < 1 V/ns.
5 CLK, CLKB signals input slew rates are > 1 V/ns.
Switching Characteristics for PC1600, PC2100, and PC2700
(Over recommended operating free-air temperature range unless otherwise noted)
(See test circuits and switching waveforms)
VDD = 2.5 V ± 0.2 V
Symbol
From (input)
To (output)
fmax
Min
Typ
Max
200
tpd
CLK, CLKB
Q
tphl
RESETB
Q
Units
MHz
1.1
2.8
ns
5.0
ns
Switching Characteristics for PC3200
(Over recommended operating free-air temperature range unless otherwise noted)
(See test circuits and switching waveforms)
VDD = 2.6 V ± 0.1 V
Symbol
From (input)
To (output)
Typ
Max
280
fmax
tpd
CLK, CLKB
Q
tphl
RESETB
Q
8/1/03, V.0.10
Min
1.1
Alliance Semiconductor
Units
MHz
2.2
ns
5.0
ns
P. 7 of 12
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Parameter Measurement Information:
VDD = 2.5 V ± 0.2 V for PC1600, PC2100,& PC2700 and VDD= 2.6 V ± 0.1V for PC3200
VTT
RL = 50 Ω
From output under test
Test point
CL = 30 pF1
Load circuit
1
CL includes probe and jig capacitance.
Voltage and Current Waveforms
In the following waveforms, note that all input pulses are supplied by generators having the following
characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, input slew rate = 1 V/ns ± 20% (unless otherwise specified).
The outputs are measured one at a time with one transition per measurement.
VTT = VREF = VDDQ/2.
VIH = VREF + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
VIL = VREF - 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
tPLH and tPHL are the same as tpd.
Input active and inactive times
LVCMOS RESETB
VDD/2
Input
VDD
VDD/2
0V
tact
tinact
IDD1
IDDH
90%
10%
1
IDDL
IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Pulse duration
tw
Input
8/1/03, V.0.10
VREF
VREF
VIH
VIL
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Setup and hold times
VI(pp)
VICR
Timing input
ts
Input
th
VREF
VREF
VIH
VIL
Propagation delay times
VI(pp)
Timing input
Output
VICR
VICR
tPLH
tPHL
VTT
VTT
LVCMOS RESETB
Input
VOH
VOL
VIH
VDD/2
VIL
tPHL
Output
VTT
VOH
VOL
8/1/03, V.0.10
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Package Dimensions (48- Pin TSSOP)
Millimeters
c
N
L
E1
E
Index area
Symbol
Min
Max
Min
Max
A
–
1.20
–
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.32
0.041
b
0.17
0.27
0,007
0.011
c
0.09
0.20
0.0035
0.008
D
E
12
D
α
A2
e
b
A1
6.10 mm (240 mil) body,
0.50 mm (0.020 mil) pitch TSSOP
E1
e
A
Seating plane
L
aaa C
N
See variations below
8.10 basic
6.00
6.20
0.50 basic
0.45
0.75
0.319 basic
0.236
0.244
0.020 basic
0.018
0.030
See variations below
a
0°
8°
0°
8°
aaa
–
0.10
–
0.004
Variations:
D (mm)
8/1/03, V.0.10
Inches
D (inch)
N
Min
Max
Min
Max
48
12.40
12.60
0.488
0.496
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Package Dimensions (Alternate Size)
Millimeters
c
N
L
E1
E
Index area
Symbol
Min
Max
Min
Max
A
–
1.20
–
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.32
0.041
b
0.13
0.23
0,005
0.009
c
0.09
0.20
0.0035
0.008
D
E
12
D
α
A2
e
b
A1
4.40 mm (173 mil) body,
0.40 mm (16 mil) pitch TVSOP
E1
e
A
Seating plane
L
aaa C
N
See variations below
6.40 basic
4.30
4.50
0.40 basic
0.45
0.75
0.252 basic
0.169
0.177
0.016 basic
0.018
0.030
See variations below
a
0°
8°
0°
8°
aaa
–
0.08
–
0.003
Variations:
D (mm)
8/1/03, V.0.10
Inches
D (inch)
N
Min
Max
Min
Max
48
9.60
9.80
0.378
0.386
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Ordering Information
Ordering Number
Marking
AS80SSTVF16857-48TT
AS80SSTVF16857T 48-pin TSSOP, tube
AS80SSTVF16857-48TR
AS80SSTVF16857T 48-pin TSSOP, tape and reel
AS80SSTVF16857-48VT
AS80SSTVF16857V 48-pin TVSOP, tube
AS80SSTVF16857-48VR
AS80SSTVF16857V 48-pin TVSOP, tape and reel
8/1/03, V.0.10
Package Type
Alliance Semiconductor
Quantity
per reel
Temperature
0°C to 70°C
2500
0°C to 70°C
0°C to 70°C
2500
0°C to 70°C
P. 12 of 12