Fairchild CD4049UBC Hex inverting buffer hex non-inverting buffer Datasheet

Revised April 2002
CD4049UBC • CD4050BC
Hex Inverting Buffer •
Hex Non-Inverting Buffer
General Description
Features
The CD4049UBC and CD4050BC hex buffers are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode
transistors. These devices feature logic level conversion
using only one supply voltage (VDD). The input signal high
level (VIH) can exceed the VDD supply voltage when these
devices are used for logic level conversions. These
devices are intended for use as hex buffers, CMOS to DTL/
TTL converters, or as CMOS current drivers, and at VDD =
5.0V, they can drive directly two DTL/TTL loads over the
full operating temperature range.
■ Wide supply voltage range:
3.0V to 15V
■ Direct drive to 2 TTL loads at 5.0V over full temperature
range
■ High source and sink current capability
■ Special input protection permits input voltages greater
than VDD
Applications
• CMOS hex inverter/buffer
• CMOS to DTL/TTL hex converter
• CMOS current “sink” or “source” driver
• CMOS HIGH-to-LOW logic level converter
Ordering Code:
Order Number
Package Number
CD4049UBCM
M16A
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4049UBCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
CD4050BCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4050BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP
CD4049UBC
CD4050BC
Top View
Top View
© 2002 Fairchild Semiconductor Corporation
DS005971
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CD4049UBC • CD4050BC Hex Inverting Buffer • Hex Non-Inverting Buffer
October 1987
CD4049UBC • CD4050BC
Schematic Diagrams
CD4049UBC
1 of 6 Identical Units
CD4050BC
1 of 6 Identical Units
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2
Recommended Operating
Conditions (Note 2)
(Note 2)
Supply Voltage (VDD)
−0.5V to +18V
Supply Voltage (VDD)
3V to 15V
Input Voltage (VIN)
−0.5V to +18V
Input Voltage (VIN)
0V to 15V
Voltage at Any Output Pin (VOUT)
−0.5V to VDD + 0.5V
Storage Temperature Range (TS)
−65°C to +150°C
Voltage at Any Output Pin (VOUT )
0 to VDD
Operating Temperature Range (TA)
Power Dissipation (PD)
−55°C to +125°C
CD4049UBC, CD4050BC
Dual-In-Line
700 mW
Small Outline
500 mW
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed; they are not meant to imply that
the devices should be operated at these limits. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides
conditions for actual device operation.
Lead Temperature (TL)
260°C
(Soldering, 10 seconds)
Note 2: VSS = 0V unless otherwise specified.
DC Electrical Characteristics (Note 3)
Symbol
IDD
VOL
Parameter
Quiescent Device Current
LOW Level Output Voltage
−55°C
Conditions
Min
Max
+25°C
Min
Typ
+125°C
Max
Min
Max
VDD = 5V
1.0
0.01
1.0
30
VDD = 10V
2.0
0.01
2.0
60
VDD = 15V
4.0
0.03
4.0
120
Units
µA
VIH = VDD, VIL = 0V,
|IO| < 1 µA
VOH
HIGH Level Output Voltage
VDD = 5V
0.05
0
0.05
0.05
VDD = 10V
0.05
0
0.05
0.05
VDD = 15V
0.05
0
0.05
0.05
V
VIH = VDD, VIL = 0V,
|IO| < 1 µA
VIL
LOW Level Input Voltage
(CD4050BC Only)
VIL
VIH
IOL
5
4.95
9.95
10
9.95
VDD = 15V
14.95
14.95
15
14.95
V
|IO| < 1 µA
VDD = 5V, VO = 0.5V
1.5
2.25
1.5
1.5
VDD = 10V, VO = 1V
3.0
4.5
3.0
3.0
VDD = 15V, VO = 1.5V
4.0
6.75
4.0
4.0
1.0
|IO| < 1 µA
VDD = 5V, VO = 4.5V
1.0
1.5
1.0
VDD = 10V, VO = 9V
2.0
2.5
2.0
2.0
VDD = 15V, VO = 13.5V
3.0
3.5
3.0
3.0
HIGH Level Input Voltage
VDD = 5V, VO = 4.5V
3.5
3.5
2.75
3.5
VDD = 10V, VO = 9V
7.0
7.0
5.5
7.0
VDD = 15V, VO = 13.5V
11.0
11.0
8.25
11.0
4.0
|IO| < 1 µA
(CD4049UBC Only)
VDD = 5V, VO = 0.5V
4.0
4.0
3.5
VDD = 10V, VO = 1V
8.0
8.0
7.5
8.0
VDD = 15V, VO = 1.5V
12.0
12.0
11.5
12.0
LOW Level Output Current
HIGH Level Output Current
Input Current
V
V
|IO| < 1 µA
HIGH Level Input Voltage
(Note 4)
IIN
4.95
(CD4049UBC Only)
(Note 4)
IOH
4.95
9.95
LOW Level Input Voltage
(CD4050BC Only)
VIH
VDD = 5V
VDD = 10V
V
V
VIH = VDD, VIL = 0V
VDD = 5V, VO = 0.4V
5.6
4.6
5
3.2
VDD = 10V, VO = 0.5V
12
9.8
12
6.8
VDD = 15V, VO = 1.5V
35
29
40
20
mA
VIH = VDD, VIL = 0V
VDD = 5V, VO = 4.6V
−1.3
−1.1
−1.6
−0.72
VDD = 10V, VO = 9.5V
−2.6
−2.2
−3.6
−1.5
VDD = 15V, VO = 13.5V
−8.0
−7.2
−12
−5
mA
VDD = 15V, VIN = 0V
−0.1
−10−5
−0.1
−1.0
VDD = 15V, VIN = 15V
0.1
10−5
0.1
1.0
µA
Note 3: VSS = 0V unless otherwise specified.
3
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CD4049UBC • CD4050BC
Absolute Maximum Ratings(Note 1)
CD4049UBC • CD4050BC
DC Electrical Characteristics
(Continued)
Note 4: These are peak output current capabilities. Continuous output current is rated at 12 mA maximum. The output current should not be allowed to
exceed this value for extended periods of time. IOL and IOH are tested one output at a time.
AC Electrical Characteristics
(Note 5)
CD4049UBC
TA = 25°C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise specified
Symbol
tPHL
Parameter
Propagation Delay Time
HIGH-to-LOW Level
tPLH
tTHL
tTLH
CIN
Typ
Max
VDD = 5V
Conditions
Min
30
65
VDD = 10V
20
40
VDD = 15V
15
30
Propagation Delay Time
VDD = 5V
45
85
LOW-to-HIGH Level
VDD = 10V
25
45
VDD = 15V
20
35
Transition Time
VDD = 5V
30
60
HIGH-to-LOW Level
VDD = 10V
20
40
VDD = 15V
15
30
Transition Time
VDD = 5V
60
120
LOW-to-HIGH Level
VDD = 10V
30
55
VDD = 15V
25
45
Any Input
15
22.5
Input Capacitance
Units
ns
ns
ns
ns
pF
Note 5: AC Parameters are guaranteed by DC correlated testing.
AC Electrical Characteristics
(Note 6)
CD4050BC
TA = 25°C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise specified
Symbol
tPHL
Parameter
Propagation Delay Time
HIGH-to-LOW Level
tPLH
tTHL
tTLH
CIN
Typ
Max
VDD = 5V
Conditions
Min
60
110
VDD = 10V
25
55
VDD = 15V
20
30
Propagation Delay Time
VDD = 5V
60
120
LOW-to-HIGH Level
VDD = 10V
30
55
VDD = 15V
25
45
Transition Time
VDD = 5V
30
60
HIGH-to-LOW Level
VDD = 10V
20
40
VDD = 15V
15
30
Transition Time
VDD = 5V
60
120
LOW-to-HIGH Level
VDD = 10V
30
55
VDD = 15V
25
45
Any Input
5
7.5
Input Capacitance
Note 6: AC Parameters are guaranteed by DC correlated testing.
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4
Units
ns
ns
ns
ns
pF
CD4049UBC • CD4050BC
Switching Time Waveforms
Typical Applications
CMOS to TLL or CMOS at a Lower VDD
VDD1 ≥ VDD2
In the case of the CD4049UBC the output drive capability increases with increasing input voltage.
E.g., If VDD1 = 10V the CD4049UBC could drive 4 TTL loads.
5
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CD4049UBC • CD4050BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
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6
CD4049UBC • CD4050BC Hex Inverting Buffer • Hex Non-Inverting Buffer
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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7
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