TI1 ADC78H90CIMTX 8-channel, 500 ksps, 12-bit a/d converter Datasheet

ADC78H90
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ADC78H90 8-Channel, 500 kSPS, 12-Bit A/D Converter
Check for Samples: ADC78H90
FEATURES
1
•
•
•
•
•
2
Eight input channels
Variable power management
Independent analog and digital supplies
SPI™/QSPI™/MICROWIRE™/DSP compatible
Packaged in 16-lead TSSOP
The ADC78H90 is packaged in a 16-lead TSSOP
package. Operation over the industrial temperature
range of −40°C to +85°C is ensured.
Connection Diagram
APPLICATIONS
•
•
•
•
•
1
CS
16
SCLK
AV DD
2
15
DOUT
AGND
3
14
DIN
AIN1
4
13
DV DD
Automotive Navigation
Portable Systems
Medical Instruments
Mobile Communications
Instrumentation and Control Systems
ADC78H90
AIN2
5
12
DGND
AIN3
6
11
AIN8
AIN4
7
10
AIN7
AIN5
8
9
AIN6
KEY SPECIFICATIONS
•
•
•
•
Conversion Rate: 500kSPS
DNL: ± 1LSB (max)
INL: ± 1LSB (max)
Power Consumption
– 3V Supply: 1.5 mW (typ)
– 5V Supply: 8.3 mW (typ)
DESCRIPTION
The ADC78H90 is a low-power, eight-channel CMOS
12-bit analog-to-digital converter with a conversion
throughput of 500 kSPS. The converter is based on a
successive-approximation register architecture with
an internal track-and-hold circuit. It can be configured
to accept up to eight input signals at inputs AIN1
through AIN8.
The output serial data is straight binary, and is
compatible with several standards, such as SPI™,
QSPI™, MICROWIRE™, and many common DSP
serial interfaces.
The ADC78H90 may be operated with independent
analog and digital supplies. The analog supply (AVDD)
can range from +2.7V to +5.25V, and the digital
supply (DVDD) can range from +2.7V to AVDD. Normal
power consumption using a +3V or +5V supply is 1.5
mW and 8.3 mW, respectively. The power-down
feature reduces the power consumption to just 0.3
µW using a +3V supply, or 0.5 µW using a +5V
supply.
Figure 1. 16-Lead TSSOP
See PW Package
Block Diagram
AIN1
.
.
.
T/H
MUX
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
AVDD
AGND
AGND
AIN8
DVDD
SCLK
ADC78H90
CONTROL
LOGIC
CS
DIN
DOUT
DGND
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Pin
No.
Symbol
Equivalent
Circuit
Description
ANALOG I/O
411
AIN1 to
AIN8
Analog inputs. These signals
can range from 0V to AVDD.
DIGITAL I/O
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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PIN DESCRIPTIONS AND EQUIVALENT
CIRCUITS (continued)
Pin
No.
16
15
14
1
Symbol
Equivalent
Circuit
Description
SCLK
Digital clock input. The range of
frequencies for this input is 50
kHz to 8 MHz, with ensured
performance at 8 MHz. This
clock directly controls the
conversion and readout
processes.
DOUT
Digital data output. The output
samples are clocked out of this
pin on falling edges of the
SCLK pin.
DIN
Digital data input. The
ADC78H90's Control Register
is loaded through this pin on
rising edges of the SCLK pin.
CS
Chip select. On the falling edge
of CS, a conversion process
begins. Conversions continue
as long as CS is held low.
PIN DESCRIPTIONS AND EQUIVALENT
CIRCUITS (continued)
Pin
No.
Symbol
Equivalent
Circuit
Description
AVDD
Positive analog supply pin. This
pin should be connected to a
quiet +2.7V to +5.25V source
and bypassed to GND with a 1
µF tantalum capacitor and a 0.1
µF ceramic monolithic capacitor
located within 1 cm of the
power pin.
13
DVDD
Positive digital supply pin. This
pin should be connected to a
+2.7V to AVDD supply, and
bypassed to GND with a 0.1 µF
ceramic monolithic capacitor
located within 1 cm of the
power pin.
3
AGND
The ground return for the
analog supply and signals.
12
DGND
The ground return for the digital
supply and signals.
2
POWER SUPPLY
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
Analog Supply Voltage AVDD
−0.3V to 6.5V
Digital Supply Voltage DVDD
−0.3V to AVDD + 0.3V, max 6.5V
Voltage on Any Pin to GND
−0.3V to AVDD +0.3V
(3)
±10 mA
Input Current at Any Pin
Package Input Current (3)
±20 mA
Power Dissipation at TA = 25°C
See
(4)
(5)
ESD Susceptibility
Human Body Model
Machine Model
2500V
250V
Soldering Temperature, Infrared,
10 seconds (6)
260°C
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
(1)
(2)
(3)
(4)
(5)
(6)
2
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN >VA or VD), the current at that pin should be
limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies
with an input current of 10 mA to two.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA)/θJA. In the 16-pinTSSOP, θJA is 96°C/W, so PDMAX = 1,200mW at 25°C and 625 mW at the maximum
operating ambient temperature of85°C. Note that the power consumption of this device under normal operation is a maximum of 12 mW.
The values for maximum power dissipation listed above will be reached only when the ADC78H90 is operated in a severe fault condition
(e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such
conditions should always be avoided.
Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO ohms
See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any
post 1986 Texas Instruments Linear Data Book, for other methods of soldering surface mount devices.
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Operating Ratings
(1) (2)
−40°C ≤ TA ≤ +85°C
Operating Temperature Range
AVDD Supply Voltage
+2.7V to +5.25V
DVDD Supply Voltage
+2.7V to AVDD
Digital Input Pins Voltage Range
-0.3V to AVDD
Clock Frequency
50 kHz to 8 MHz
Analog Input Voltage
(1)
(2)
0V to AVDD
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
All voltages are measured with respect to GND = 0V, unless otherwise specified.
Package Thermal Resistance
Package
θJA
16-lead TSSOP on 4-layer, 2 oz. PCB
96°C / W
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ADC78H90 Converter Electrical Characteristics
(1)
The following specifications apply for AVDD = DVDD = +2.7V to 5.25V, AGND = DGND = 0V, fSCLK = 8 MHz, fSAMPLE = 500
KSPS, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
Symbol
Parameter
Conditions
Limits
Typical
(2)
Units
STATIC CONVERTER CHARACTERISTICS
12
Bits
INL
Resolution with No Missing Codes
Integral Non-Linearity
AVDD = +5.0V, DVDD = +3.0V
±1
LSB (max)
DNL
Differential Non-Linearity
AVDD = +5.0V, DVDD = +3.0V
±1
LSB (max)
VOFF
Offset Error
AVDD = +5.0V, DVDD = +3.0V
±2
LSB (max)
OEM
Offset Error Match
AVDD = +5.0V, DVDD = +3.0V
±2
LSB (max)
GE
Gain Error
AVDD = +5.0V, DVDD = +3.0V
±3
LSB (max)
GEM
Gain Error Match
AVDD = +5.0V, DVDD = +3.0V
±3
LSB (max)
DYNAMIC CONVERTER CHARACTERISTICS
SINAD
Signal-to-Noise Plus Distortion Ratio
AVDD = +5.0V, DVDD = +3.0V,
fIN = 40.2 kHz, −0.02 dBFS
73
70
dB (min)
SNR
Signal-to-Noise Ratio
AVDD = +5.0V, DVDD = +3.0V,
fIN = 40.2 kHz, −0.02 dBFS
73
70.8
dB (min)
THD
Total Harmonic Distortion
AVDD = +5.0V, DVDD = +3.0V,
fIN = 40.2 kHz, −0.02 dBFS
−86
−74
dB (max)
SFDR
Spurious-Free Dynamic Range
AVDD = +5.0V, DVDD = +3.0V,
fIN = 40.2 kHz, −0.02 dBFS
88
75.6
dB (min)
ENOB
Effective Number of Bits
AVDD = +5.0V, DVDD = +3.0V,
11.8
11.3
Bits (min)
Channel-to-Channel Crosstalk
AVDD = +5.0V, DVDD = +3.0V,
fIN = 40.2 kHz
-82
dB
Intermodulation Distortion, Second
Order Terms
AVDD = +5.0V, DVDD = +3.0V,
fa = 40.161 kHz, fb = 41.015 kHz
-93
dB
Intermodulation Distortion, Third Order
Terms
AVDD = +5.0V, DVDD = +3.0V,
fa = 40.161 kHz, fb = 41.015 kHz
-90
dB
AVDD = +5V
11
MHz
AVDD = +3V
8
MHz
0 to AVDD
V
IMD
FPBW
-3 dB Full Power Bandwidth
ANALOG INPUT CHARACTERISTICS
VIN
Input Range
IDCL
DC Leakage Current
CINA
Input Capacitance
±1
µA (max)
Track Mode
33
pF
Hold Mode
3
pF
DIGITAL INPUT CHARACTERISTICS
DVDD = +4.75Vto +5.25V
2.4
DVDD = +2.7V to +3.6V
2.1
V (min)
Input Low Voltage
DVDD = +2.7V to +5.25V
0.8
V (max)
IIN
Input Current
VIN = 0V or DVDD
±0.01
±1
µA (max)
CIND
Digital Input Capacitance
2
4
pF (max)
DVDD −0.5
V (min)
VIH
Input High Voltage
VIL
V (min)
DIGITAL OUTPUT CHARACTERISTICS
VOH
Output High Voltage
ISOURCE = 200 µA, DVDD = +2.7V to
+5.25V
VOL
Output Low Voltage
ISINK = 200 µA
IOZH, IOZL TRI-STATE® Leakage Current
COUT
TRI-STATE® Output Capacitance
2
Output Coding
(1)
(2)
4
0.4
V (max)
±1
µA (max)
4
pF (max)
Straight (Natural) Binary
Data sheet min/max specification limits are ensured by design, test, or statistical analysis.
Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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ADC78H90 Converter Electrical Characteristics (1) (continued)
The following specifications apply for AVDD = DVDD = +2.7V to 5.25V, AGND = DGND = 0V, fSCLK = 8 MHz, fSAMPLE = 500
KSPS, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
Symbol
Parameter
Conditions
Typical
Limits
(2)
Units
POWER SUPPLY CHARACTERISTICS (CL = 10 pF)
AVDD,
DVDD
Analog and Digital Supply Voltages
AVDD ≥ DVDD
2.7
V (min)
5.25
V (max)
AVDD = DVDD = +4.75V to +5.25V,
fSAMPLE = 500 kSPS, fIN = 40 kHz
1.65
2.3
mA (max)
AVDD = DVDD = +2.7V to +3.6V,
fSAMPLE = 500 kSPS, fIN = 40 kHz
0.5
2.3
mA (max)
AVDD = DVDD = +4.75V to +5.25V,
fSAMPLE = 0 kSPS
200
nA
AVDD = DVDD = +2.7V to +3.6V,
fSAMPLE = 0 kSPS
200
nA
Power Consumption, Normal Mode
(Operational, CS low)
\AVDD = DVDD = +4.75V to +5.25V
8.3
12
mW (max)
AVDD = DVDD = +2.7V to +3.6V
1.5
8.3
mW (max)
Power Consumption, Shutdown (CS
high)
AVDD = DVDD = +4.75V to +5.25V
0.5
µW
AVDD = DVDD = +2.7V to +3.6V
0.3
µW
Total Supply Current, Normal Mode
(Operational, CS low)
IA + ID
Total Supply Current, Shutdown (CS
high)
PD
AC ELECTRICAL CHARACTERISTICS
fSCLK
Maximum Clock Frequency
fSMIN
Minimum Clock Frequency
fS
Maximum Sample Rate
500
KSPS (min)
tCONV
Conversion Time
13
SCLK cycles
DC
SCLK Duty Cycle
40
% (min)
60
% (max)
tACQ
Track/Hold Acquisition Time
Full-Scale Step Input
3
SCLK cycles
Throughput Time
Acquisition Time + Conversion Time
16
SCLK cycles
500
kSPS (min)
fRATE
Throughput Rate
tAD
Aperture Delay
8
MHz (min)
50
50
kHz
4
ns
ADC78H90 Timing Specifications
The following specifications apply for AVDD = DVDD = +2.7V to 5.25V, AGND = DGND = 0V, fSCLK = 8 MHz, fSAMPLE = 500
KSPS, CL = 50 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
Symbol
(1)
(2)
Parameter
Conditions
Typical
Limits
(1)
Units
t1a
Setup Time SCLK High to CS Falling
Edge
(2)
10
ns (min)
t1b
Hold time SCLK Low to CS Falling
Edge
(2)
10
ns (min)
t2
Delay from CS Until DOUT active
30
ns (max)
t3
Data Access Time after SCLK Falling
Edge
30
ns (max)
t4
Data Setup Time Prior to SCLK Rising
Edge
10
ns (min)
t5
Data Valid SCLK Hold Time
10
ns (min)
t6
SCLK High Pulse Width
0.4 x tSCLK
ns (min)
t7
SCLK Low Pulse Width
0.4 x tSCLK
ns (min)
t8
CS Rising Edge to DOUT HighImpedance
20
ns (max)
Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
Clock may be in any state (high or low) when CS is asserted, with the restrictions on setup and hold time given by t1a and t1b.
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Timing Diagrams
Figure 2. Timing Test Circuit
Figure 3. ADC78H90 Operational Timing Diagram
CS
tCONVERT
tACQ
t6
SCLK
1
2
3
4
Z3
Z2
Z1
7
8
16
t8
t3
Z0
DB11
DB10
DB9
DB8
DB1
DB0
t5
t4
DIN
6
t7
t2
DOUT
5
DONT DONTC ADD2
ADD1
ADD0 DONTC DONTC DONTC
Figure 4. ADC78H90 Serial Timing Diagram
6
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Figure 5. SCLK and CS Timing Parameters
Specification Definitions
ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold
capacitor to charge up to the input voltage.
APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the
input signal is acquired or held for conversion.
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
CROSSTALK is the coupling of energy from one channel into the other channel, or the amount of signal energy
from one analog input that appears at the measured analog input.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF - 1.5
LSB), after adjusting for offset error.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last
code transition). The deviation of any given code from this straight line is measured from the center of that
code value.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the
power in the second and third order intermodulation products to the sum of the power in both of the
original frequencies. IMD is usually expressed in dB.
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC78H90 is ensured
not to have any missing codes.
OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +
0.5 LSB).
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of
the input signal to the rms value of all of the other spectral components below half the clock frequency,
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including harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal and the peak spurious signal where a spurious signal is any signal present in the output
spectrum that is not present at the input, excluding d.c.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five
harmonic components at the output to the rms level of the input signal frequency as seen at the output.
THD is calculated as
THD = 20 ‡ log 10
A f22 +
+ A f6 2
A f12
where
•
•
Af1 is the RMS power of the input frequency at the output
Af2 through Af6 are the RMS power in the first 5 harmonic frequencies
(1)
THROUGHPUT TIME is the minimum time required between the start of two successive conversion. It is the
acquisition time plus the conversion time. In the case of the ADC78H90, this is 16 SCLK periods.
8
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Typical Performance Characteristics
TA = +25°C, fSAMPLE = 500 kSPS, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated.
DNL
DNL
Figure 6.
Figure 7.
INL
INL
Figure 8.
Figure 9.
DNL vs. Supply
INL vs. Supply
Figure 10.
Figure 11.
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Typical Performance Characteristics (continued)
TA = +25°C, fSAMPLE = 500 kSPS, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated.
10
SNR vs. Supply
THD vs. Supply
Figure 12.
Figure 13.
ENOB vs. Supply
SNR vs. Input Frequency
Figure 14.
Figure 15.
THD vs. Input Frequency
ENOB vs. Input Frequency
Figure 16.
Figure 17.
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Typical Performance Characteristics (continued)
TA = +25°C, fSAMPLE = 500 kSPS, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated.
Spectral Response
Spectral Response
Figure 18.
Figure 19.
Power Consumption vs. Throughput
Figure 20.
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APPLICATIONS INFORMATION
ADC78H90 OPERATION
The ADC78H90 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter. Simplified schematics of the ADC78H90 in both track and hold
operation are shown in Figure 21 and Figure 22, respectively. In Figure 21, the ADC78H90 is in track mode:
switch SW1 connects the sampling capacitor to one of eight analog input channels through the multiplexer, and
SW2 balances the comparator inputs. The ADC78H90 is in this state for the first three SCLK cycles after CS is
brought low.
There is no power-up delay or dummy conversions with the ADC78H90. The ADC is able to sample and convert
an input to full resolution in the first conversion immediately following power up. The first conversion result after
power up will be that of the first channel.
Figure 22 shows the ADC78H90 in hold mode: switch SW1 connects the sampling capacitor to ground,
maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs
the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until
the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital
representation of the analog input voltage. The ADC78H90 is in this state for the last thirteen SCLK cycles after
CS is brought low.
AIN1
CHARGE
REDISTRIBUTION
DAC
MUX
SAMPLING
CAPACITOR
SW1
AIN8
+
-
SW2
CONTROL
LOGIC
AGND
AVDD /2
Figure 21. ADC78H90 in Track Mode
AIN1
CHARGE
REDISTRIBUTION
DAC
MUX
AIN8
SAMPLING
CAPACITOR
+
SW1
SW2
CONTROL
LOGIC
-
AGND
AVDD /2
Figure 22. ADC78H90 in Hold Mode
The time when CS is low is considered a serial frame. Each of these frames should contain an integer multiple of
16 SCLK cycles, during which time a conversion is performed and clocked out at the DOUT pin and data is
clocked into the DIN pin to indicate the multiplexer address for the next conversion.
12
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USING THE ADC78H90
Figure 3 and Figure 4 for the ADC78H90 are shown in Timing Diagrams. CS, chip select, initiates conversions
and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of
serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB
first. Data to be written to the ADC78H90's Control Register is placed on DIN, the serial data input pin. New data
is written to DIN with each conversion.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain
an integer multiple of 16 rising SCLK edges. The ADC output data (DOUT) is in a high impedance state when
CS is high and is active when CS is low. Thus, CS acts as an output enable. Additionally, the device goes into a
power down state when CS is high.
During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13
SCLK cycles the conversion is accomplished and the data is clocked out, MSB first. If there is more than one
conversion in a frame, the ADC will re-enter the track mode on the falling edge of SCLK after the N*16th rising
edge of SCLK, and re-enter the hold/convert mode on the N*16+4th falling edge of SCLK, where "N" must be an
integer.
When CS is brought high, SCLK is internally gated off. If SCLK is in a low state when CS goes high, the
subsequent fall of CS will generate a falling edge of the internal version of SCLK, putting the ADC into the track
mode. This is seen by the ADC as the first falling edge of SCLK. If SCLK is in a high state when CS goes high,
the ADC enters the track mode on the first falling edge of SCLK after the falling edge of CS.
During each conversion, data is clocked into the DIN pin on the first 8 rising edges of SCLK after the fall of CS.
For each conversion, it is necessary to clock in the data indicating the input that is selected for the conversion
after the current one. See Table 1, Table 2, and Table 3.
If CS and SCLK go low simultaneously, it is the following rising edge of SCLK that is considered the first rising
edge for clocking data into DIN.
Table 1. Control Register Bits
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DONTC
DONTC
ADD2
ADD1
ADD0
DONTC
DONTC
DONTC
Table 2. Control Register Bit Descriptions
Bit #:
Symbol:
Description
7, 6, 2, 1, 0
DONTC
Don't care. The value of these bit do not affect the device.
5
ADD2
4
ADD1
These three bits determine which input channel will be sampled and converted on the next falling
edge of CS. The mapping between codes and channels is shown in Table 3.
3
ADD0
Table 3. Input Channel Selection
ADD2
ADD1
ADD0
Input Channel
0
0
0
AIN1 (Default)
0
0
1
AIN2
0
1
0
AIN3
0
1
1
AIN4
1
0
0
AIN5
1
0
1
AIN6
1
1
0
AIN7
1
1
1
AIN8
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ADC78H90
SNAS227D – NOVEMBER 2003 – REVISED MARCH 2013
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ADC78H90 TRANSFER FUNCTION
The output format of the ADC89H90 is straight binary. Code transitions occur midway between successive
integer LSB values. The LSB width for the ADC78H90 is AVDD / 4096. The ideal transfer characteristic is shown
in Figure 23. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB,
or a voltage of AVDD / 8192. Other code transitions occur at steps of one LSB.
Figure 23. Ideal Transfer Characteristic
TYPICAL APPLICATION CIRCUIT
A typical application of the ADC78H90 is shown in Figure 24. The split analog and digital supplies are both
provided in this example by the TI LP2950 low-dropout voltage regulator, available in a variety of fixed and
adjustable output voltages. The analog supply is bypassed with a capacitor network located close to the
ADC78H90. The digital supply is separated from the analog supply by an isolation resistor and conditioned with
additional bypass capacitors. The ADC78H90 uses the analog supply (AVDD) as its reference voltage, so it is
very important that AVDD be kept as clean as possible. Because of the ADC78H90's low power requirements, it is
also possible to use a precision reference as a power supply to maximize performance. The four-wire interface is
also shown connected to a microprocessor or DSP.
100:
LP2950
680 nF
0.1 PF
DVDD
AIN1
.
.
.
AVDD
ADC78H90
0.1 PF
5V
1 PF
0.1 PF
SCLK
CS
DIN
AIN8
1 PF
TANT
MICROPROCESSOR
DSP
DOUT
AGND
DGND
Figure 24. Typical Application Circuit
14
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SNAS227D – NOVEMBER 2003 – REVISED MARCH 2013
ANALOG INPUTS
An equivalent circuit for one of the ADC78H90's input channels is shown in Figure 25. Diodes D1 and D2 provide
ESD protection for the analog inputs. At no time should an analog input go beyond (AVDD + 300 mV) or (GND 300 mV), as these ESD diodes will begin conducting, which could result in erratic operation.
The capacitor C1 in Figure 25 has a typical value of 3 pF, and is mainly the package pin capacitance. Resistor
R1 is the on resistance of the multiplexer and track / hold switch, and is typically 500 ohms. Capacitor C2 is the
ADC78H90 sampling capacitor, and is typically 30 pF. The ADC78H90 will deliver best performance when driven
by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance. This is
especially important when using the ADC78H90 to sample AC signals. Also important when sampling dynamic
signals is a band-pass or low-pass filter to reduce harmonics and noise, improving dynamic performance.
Figure 25. Equivalent Input Circuit
DIGITAL INPUTS AND OUTPUTS
The ADC78H90's digital inputs (SCLK, CS, and DIN) are limited by and cannot exceed the analog supply voltage
AVDD. The digital input pins are not prone to latch-up; SCLK, CS, and DIN may be asserted before DVDD without
any risk.
POWER SUPPLY CONSIDERATIONS
The ADC78H90 has two supplies, although they could both have the same potential. There are two major power
supply concerns with this product. They are relative power supply levels, including power on sequencing, and the
effect of digital supply noise on the analog supply.
Power Management
The ADC78H90 is a dual-supply device. These two supplies share ESD resources, and thus care must be
exercised to ensure that the power supplies are applied in the correct sequence. To avoid turning on the ESD
diodes, the digital supply (DVDD) cannot exceed the analog supply (AVDD) by more than 300 mV. The
ADC78H90's analog power supply must, therefore, be applied before (or concurrently with) the digital power
supply.
The ADC78H90 is fully powered-up whenever CS is low, and fully powered-down whenever CS is high, with one
exception: the ADC78H90 automatically enters power-down mode between the 16th falling edge of a conversion
and the 1st falling edge of the subsequent conversion (see Figure 3).
The ADC78H90 can perform multiple conversions back to back; each conversion requires 16 SCLK cycles. The
ADC78H90 will perform conversions continuously as long as CS is held low.
The user may trade off throughput for power consumption by simply performing fewer conversions per unit time.
Figure 20 in Typical Performance Characteristics shows the typical power consumption of the ADC78H90 versus
throughput. To calculate the power consumption, simply multiply the fraction of time spent in the normal mode by
the normal mode power consumption (8.3 mW with AVDD = DVDD = +3.6V, for example), and add the fraction of
time spent in shutdown mode multiplied by the shutdown mode power dissipation (0.3 mW with AVDD = DVDD =
+3.6V).
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ADC78H90
SNAS227D – NOVEMBER 2003 – REVISED MARCH 2013
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Power Supply Noise Considerations
The charging of any output load capacitance requires current from the digital supply, DVDD. The current pulses
required from the supply to charge the output capacitance will cause voltage variations on the digital supply. If
these variations are large enough, they could cause degrade SNR and SINAD performance of the ADC.
Furthermore, if the analog and digital supplies are tied directly together, the noise on the digital supply will be
coupled directly into the analog supply, causing greater performance degradation than noise on the digital
supply. Furthermore, discharging the output capacitance when the digital output goes from a logic high to a logic
low will dump current into the die substrate, which is resistive. Load discharge currents will cause "ground
bounce" noise in the substrate that will degrade noise performance if that current is large enough. The larger is
the output capacitance, the more current flows through the die substrate and the greater is the noise coupled into
the analog channel, degrading noise performance.
The first solution is to decouple the analog and digital supplies from each other, or use separate supplies for
them, to keep digital noise out of the analog supply. To keep noise out of the digital supply, keep the output load
capacitance as small as practical. If the load capacitance is greater than 25 pF, use a 100 Ω series resistor at
the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge
current of the output capacitance and improve noise performance.
16
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SNAS227D – NOVEMBER 2003 – REVISED MARCH 2013
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 16
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17
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADC78H90CIMT
NRND
TSSOP
PW
16
92
TBD
Call TI
Call TI
-40 to 85
78H90
CIMT
ADC78H90CIMT/NOPB
ACTIVE
TSSOP
PW
16
92
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
78H90
CIMT
ADC78H90CIMTX/NOPB
ACTIVE
TSSOP
PW
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
78H90
CIMT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
ADC78H90CIMTX/NOPB TSSOP
PW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADC78H90CIMTX/NOPB
TSSOP
PW
16
2500
367.0
367.0
35.0
Pack Materials-Page 2
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