CS5111 CS5111 1.4A Switching Regulator with 5V, 100mA Linear Regulator with Watchdog, RESET and ENABLE Description The CS5111 is a dual output power supply integrated circuit. It contains a 5V ±2%, 100mA linear regulator, a watchdog timer, a linear output voltage monitor to provide a Power On Reset (POR) and a 1.4A current mode PWM switching regulator. Features below the regulation limit, RESET toggles low and remains low for the duration of the delay after proper output voltage regulation is restored. Additionally a reset pulse is issued if the correct watchdog is not received within the programmed time. Reset pulses continue until the correct watchdog signal is received. The reset pulse width and frequency, as well as the Power On Reset delay, are set by one external RC network. The 5V linear regulator is comprised of an error amplifier, reference, and supervisory functions. It has low internal supply current consumption and provides 1.2V (typical) dropout voltage at maximum load current. The current mode PWM switching regulator is comprised of an error amplifier with selectable feedback inputs, a current sense amplifier, an adjustable oscillator, and a 1.4A output power switch with anti-saturation control. The switching regulator can be configured in a variety of topologies. The watchdog timer circuitry monitors an input signal (WDI) from the microprocessor. It responds to the falling edge of this watchdog signal. If a correct watchdog signal is not received within the externally programmable time, a reset signal is issued. The CS5111 is load dump capable and has protection circuitry which includes overvoltage shutdown, current limit on the linear and switcher outputs, and an overtemperature limiter. The externally programmable active reset circuit operates correctly for an output voltage (VLIN) as low as 1V. During power up, or if the output voltage shifts ■ Linear Regulator 5V ± 2% @ 100mA ■ Switching Regulator 1.4A Peak Internal Switch 120kHz Maximum Switching Frequency 5V to 26V Operating Supply Range ■ Smart Functions Watchdog RESET ENABLE ■ Protection Overvoltage Overtemperature Current Limit ■ 54V Peak Transient Capability Block Diagram Multiplexer - Switcher Error Amplifier + VFB1 VFB2 SELECT COMP VSW Base Drive Logic COMP 1.4A - Gnd + Oscillator Switcher Shutdown - ENABLE VREG Over Voltage + Linear Error Amplifier - 1.25V CDELAY VLIN Current Limit Over Temperature Bandgap Reference RESET & Watchdog Timer RESET WDI Package Option 24 Lead SO Wide (Internally Fused Leads) + Current Sense Amplifier IBIAS COSC VIN VIN ENABLE 1 NC VREG NC VLIN VSW IBIAS Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd VFB1 RESET VFB2 CDelay SELECT WDI COMP COSC Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: [email protected] Web Site: www.cherry-semi.com Rev. 12/28/98 1 A ® Company CS5111 Absolute Maximum Ratings Logic Inputs/Outputs ( ENABLE , SELECT, WDI, RESET ) ................................................................................-0.3V to VLIN VLIN ................................................................................................................................................................................-0.3V to 10V VIN, VREG: DC Input Voltage .................................................................................................................................................-0.3V to 26V Peak Transient Voltage (40V Load Dump @ 14V VIN)....................................................................................-0.3V to 54V VSW Peak Transient Voltage .....................................................................................................................................................54V COSC, CDelay, COMP,VFB1, VFB2 ..................................................................................................................................-0.3V to VLIN Power Dissipation.............................................................................................................................................Internally Limited VLIN Output Current ........................................................................................................................................Internally Limited VSW Output Current .........................................................................................................................................Internally Limited RESET Output Sink Current ..................................................................................................................................................5mA ESD Susceptibility (Human Body Model)..............................................................................................................................2kV ESD Susceptibility (Machine Model).....................................................................................................................................200V Storage Temperature ...................................................................................................................................................-65 to 150°C Lead Temperature Soldering: Reflow (SMD styles only) ..........................................60 sec. max above 183°C, 230°C peak Electrical Characteristics: 5V ≤ VIN ≤ 26V and -40°C ≤ TJ ≤ 150°C, COUT = 100µF (ESR≤8Ω), CDelay = 0.1µF, RBIAS = 64.9kΩ, COSC = 390 pF, CCOMP = 0.1µF unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.0 mA 70 mA ■ General IIN Off Current 6.6V ≤ VIN ≤ 26V, ISW = 0A IIN On Current 6.6V ≤ VIN ≤ 26V, ISW = 1.4A IREG Current ILIN = 100mA, 6.6V ≤ VREG ≤ 26V Thermal Limit Guaranteed by design 160 6.6V ≤ VREG ≤ 26V, 1mA ≤ ILIN ≤ 100mA 4.9 ■ 5V Regulator Section VLIN Output Voltage Dropout Voltage (VREG - VLIN) @ ILIN = 100mA Overvoltage Shutdown Line Regulation 30 30 6.6V ≤ VREG ≤ 26V, ILIN = 5mA 6 mA 210 °C 5.0 5.1 V 1.2 1.5 V 34 38 V 5 25 mV 5 25 Load Regulation VREG = 19V, 1mA ≤ ILIN ≤ 100mA Current Limit 6.6V ≤ VREG ≤ 26V 120 DC Ripple Rejection 14V ≤ VREG ≤ 24V 60 75 ■ RESET Section Low Threshold (VRTL) VLIN Decreasing 4.05 4.25 4.45 V VLIN Increasing 4.20 4.45 4.70 V 140 190 240 mV High Threshold (VRTH) Hysteresis VRTH - VRTL Active High VLIN > VRTH, IRESET = -25µA Active Low VLIN = 1V, 10kΩ pullup from RESET to VLIN VLIN = 4V, IRESET = 1mA dB VLIN - 0.5 Delay Invalid WDI 6.25 Power On Delay VLIN crossing VRTH 6.25 2 mV mA V 8.78 0.4 0.7 V V 11.0 ms ms PARAMETER ■ Watchdog Input (WDI) VIH TEST CONDITIONS MIN TYP Peak WDI needed to activate RESET VIL MAX UNIT 2.0 V 0.8 V Hysteresis Note 1 25 50 mV Pull-Up Resistor WDI=0V 20 50 100 kΩ Low Threshold 6.25 8.78 11.0 ms Floating Input Voltage 3.5 V WDI Pulse Width 5 µs ■ Switcher Section Minimum Operating Input Voltage 5.0 V Switching Frequency Refer to Figure 1d. 80 95 110 kHz Switch Saturation Voltage ISW = 1.4A 0.7 1.1 1.6 V VSW = 7.5V with 50Ω load, Refer to Figure 1d. 120 Output Current Limit Max Switching Frequency 1.4 VFB1 Regulation Voltage VFB2 Regulation Voltage 2.5 A kHz 1.206 1.25 1.294 V 1.206 1.25 1.294 V 1 µA VFB1, VFB2 Input Current VFB1 = VFB2 = 5V Oscillator Charge Current COSC = 0V 35 40 45 µA Oscillator Discharge Current COSC = 4V 270 320 370 µA CDelay Charge Current CDelay = 0V 35 40 45 µA Switcher Max Duty Cycle VSW = 5V with 50Ω load, VFB1 = VFB2 = 1V 72 85 95 % Current Sense Amp Gain ISW = 2.3A 7 Error Amp DC Gain Error Amp Transconductance ■ ENABLE Input VIL 0.8 VIH 67 dB 2700 µA/V 1.24 V 1.30 Hysteresis 2.0 60 Input Impedance ■ Select Input VIL (Selects VFB1) 4.9 ≤ VLIN ≤ 5.1 VIH (Selects VFB2) 4.9 ≤ VLIN ≤ 5.1 SELECT Pull-Up SELECT = 0V Floating Input Voltage Note 1: Guaranteed by Design, not 100% tested in production. 3 10 20 0.8 1.25 V mV 40 kΩ V 1.25 2.0 V 10 24 50 kΩ 3.5 4.5 V CS5111 Electrical Characteristics: 5V ≤ VIN ≤ 26V and -40°C ≤ TJ ≤ 150°C, COUT=100µF(ESR ≤ 8Ω), CDelay = 0.1µF, RBIAS = 64.9k, COSC = 390 pF, CCOMP = 0.1µF unless otherwise specified. PACKAGE LEAD # LEAD SYMBOL FUNCTION 24 Lead SO Wide 1 VIN Supply Voltage. 2, 3 NC No connection. 4 VSW Collector of NPN power switch for switching regulator section. 5,6,7,8,17,18,19,20 Gnd Connected to the heat removing leads. 9 VFB1 Feedback input voltage 1 (referenced to 1.25V) 10 VFB2 Feedback input voltage 2 (referenced to 1.25V) 11 SELECT Logic level input that selects either VFB1 or VFB2. An open selects VFB2. Connect to Gnd to select VFB1. 12 COMP Output of the transconductance error amplifier. 13 COSC A capacitor connected to Gnd sets the switching frequency. Refer to Figure 1d. 14 WDI Watchdog input. Active on falling edge. 15 CDelay A capacitor connected to Gnd sets the Power On Reset and Watchdog time. 16 RESET RESET output. Active low if VLIN is below the regulation limit. If watchdog timeout is reached, a reset pulse train is issued. 21 IBIAS A resistor connected to Gnd sets internal bias currents as well as the COSC and CDelay charge currents. 22 VLIN Regulated 5V output from the linear regulator section. 23 VREG Input voltage to the linear regulator and the internal supply circuitry. 24 ENABLE Logic level input to shut down the switching regulator. Typical Performance Characteristics 4.5mA 0A 4.0mA IIN IREG - ILIN -10mA -20mA -30mA 3.5mA 0A -40mA 20mA 40mA 60mA 80mA 100mA 0A 0.5A 1.0A 1.5A 2.0A ISW ILIN Figure 1a. 5V Regulator Bias Current vs. Load Current. Figure 1b. Supply Current vs. Switch Current. 180 160 1.4V Frequency (kHz) 1.2V 1.0V VSW CS5111 Package Lead Description 0.8V 0.6V 0.4V 140 120 100 80 60 40 20 0.2V 0 0.0V 0A 0.5A 1.0A 1.5A 0 500 1000 1500 2000 2500 3000 2.0A COSC (pF) ISW Figure 1d. Oscillator Frequency (kHz) vs. COSC (pF), assuming RBIAS = 64.9kΩ. Figure 1c. Switch Saturation Voltage. 4 CS5111 Circuit Description VREG Over Voltage + R1 Linear Error Amplifier - Q2 Q3 Q1 R2 Current Limit 1.25V VLIN COUT = 100µF ESR < 8Ω R3 IBIAS Over Temperature Bandgap Reference RBIAS 64.9kΩ R4 R5 Cdelay RESET & Watchdog Timer RESET WDI Figure 2. Block diagram of 5V linear regulator portion of the CS5111. Using CDelay = 0.1µF and RBIAS = 64.9kΩ gives a time ranging from 6.25ms to 11ms assuming ideal components. Based on this, the software must be written so that the watchdog arrives at least every 6.25ms. In practice, the tolerance of CDelay and RBIAS must be taken into account when calculating the minimum watchdog time (tWDI). 5V Linear Regulator The 5V linear regulator consists of an error amplifier, bandgap voltage reference, and a composite pass transistor. The 5V linear regulator circuitry is shown in Figure 2. When an unregulated voltage greater than 6.6V is applied to the VREG input, a 5V regulated DC voltage will be present at VLIN. For proper operation of the 5V linear regulator, the IBIAS lead must have a 64.9kΩ pull down resistor to ground. A 100µF or larger capacitor with an ESR <8Ω must be connected between VLIN and ground. To operate the 5V linear regulator as an independent regulator (i.e. separate from the switching supply), the input voltage must be tied to the VREG lead. As the voltage at the VREG input is increased, Q1 is turned on. Q1 provides base drive for Q2 which in turn provides base current for Q3. As Q3 is turned on, the output voltage, VLIN, begins to rise as Q3’s output current charges the output capacitor, COUT. Once VLIN rises to a certain level, the error amplifier becomes biased and provides the appropriate amount of base current to Q1. The error amplifier monitors the scaled output voltage via an internal voltage divider, R2 through R5, and compares it to the bandgap voltage reference. The error amplifier output or error signal is an output current equal to the error amplifier’s input differential voltage times the transconductance of the amplifier. Therefore, the error amplifier varies the base current to Q1, which provides bias to Q2 and Q3, based on the difference between the reference voltage and the scaled VLIN output voltage. VREG RESET WDI VLIN tPOR Normal Operation Figure 3. Timing diagram for normal regulator operation. 50% Duty Cycle VREG RESET WDI Control Functions VLIN The watchdog timer circuitry monitors an input signal (WDI) from the microprocessor. It responds to the falling edge of this watchdog signal which it expects to see within an externally programmable time (see Figure 3). The watchdog time is given by: tWDI = 1.353 × CDelay RBIAS tPOR A A: Watchdog waiting for low-going transition on WDI B B: RESET stays low for tWDI time. Figure 4. Timing diagram when WDI fails to appear within the preset time interval, tWDI. 5 CS5111 Circuit Description: continued The switching regulator begins operation when VREG and VIN are raised above 5 volts. VREG is required since the switching supply’s control circuitry is powered through VLIN. VIN supplies the base drive to the switcher output transistor. The output transistor turns on when the oscillator starts to charge the capacitor on COSC. The output current will develop a voltage drop across the internal sense resistor (RS). This voltage drop produces a proportional voltage at the output of the current sense amplifier, which is compared to the output of the error amplifier. The error amplifier generates an output voltage which is proportional to the difference between the scaled down output boost voltage (VFB1 or VFB2) and the internal bandgap voltage reference. Once the current sense amplifier output exceeds the error amplifier’s output voltage, the output transistor is turned off. The energy stored in the inductor during the output transistor on time is transferred to the load when the output transistor is turned off. The output transistor is turned back on at the next rising edge of the oscillator. On a cycle by cycle basis, the current mode controller in a discontinuous mode of operation charges the inductor to the appropriate amount of energy, based on the energy demand of the load. Figure 7 shows the typical current and voltage waveforms for a boost supply operating in the discontinuous mode. If a correct watchdog signal is not received within the specified time a reset pulse train is issued until the correct watchdog signal is received. The nominal reset signal in this case is a 5 volt square wave with a 50% duty cycle as shown in Figure 4. The RESET signal frequency is given by: 1 fRESET = 2(tWDI) The Power On Reset (POR) and low voltage RESET use the same circuitry and issue a reset when the linear output voltage is below the regulation limit. After VLIN rises above the minimum specified value, RESET remains low for a fixed period tPOR as shown in Figure 5. The POR delay (tPOR) is given by: tPOR = 1.353 × CDelay RBIAS VLIN 4.45V 4.25V RESET VRLO VRPEAK NOTES: 1. Refer to Figure 1d to determine oscillator frequency. 2. The switching regulator can be disabled by providing a logic high at the ENABLE input. 3. The boost output voltage can be controlled dynamically by the feedback select input. If select is open, VFB2 is selected. If select is low, then VFB1 is selected. tPOR Figure 5a. The power on reset time interval (tPOR) begins when VLIN rises above 4.45V (typical). VLIN 5V 4.25V Protection Circuitry If the input voltage at VREG is increased above the overvoltage threshold, the drive to the linear and switcher output transistors is shut off. Therefore, VLIN is disabled and VSW can not be pulled low. The current out of VLIN is sensed in order to limit excessive power dissipation in the linear output transistor over the output range of 0V to regulation. Also, the current into VSW is sensed in order to provide the current limit function in the switcher output transistor. If the die temperature is increased above 160°C, either due to excessive ambient temperature or excessive power dissipation, the drive to the linear output transistor is reduced proportionally with increasing die temperature. Therefore, VLIN will decrease with increasing die temperature above 160°C. Since the switcher control circuitry is powered through VLIN, the switcher performance, including current limit, will be affected by the decrease in VLIN. RESET 5V tPOR Figure 5b. RESET signal is issued whenever VLIN falls below 4.25V (typical). Current Mode PWM Switching Circuitry The current mode PWM switching voltage regulator contains an error amplifier with selectable feedback inputs, a current sense amplifier, an adjustable oscillator and a 1.4A output power switch with antisaturation control. The switching regulator and external components, connected in a boost configuration, are shown in Figure 6. 6 CS5111 Circuit Description: continued VIN VLIN VOUT VSW COMP IBIAS Base Drive Current Sense Amplifier RS - COSC Gnd + Oscillator COUT 1.4A + RBIAS 64.9kΩ Logic ENABLE Switcher Shutdown 1.25V VREG Bandgap Reference Over Voltage COMP R1 VFB1 Switcher Error Amplifier - Multiplexer R2 VFB2 + R3 SELECT Figure 6: Block diagram of the 1.4A current mode control switching regulator portion of the CS5111 in a boost configuration. Application Notes Step 3 Next select the output voltage feedback sense resistor divider as follows (Figure 8). Design Procedure for Boost Topology This section outlines a procedure for designing a boost switching power supply operating in the discontinuous mode. For VFB1 active, choose a value for R1 and then solve for REQ where: Step 1 Determine the output power required by the load. POUT = IOUTVOUT (1) REQ = Step 2 Choose COSC based on the target oscillator frequency with an external resistor value, RBIAS = 64.9kΩ. (See Figure 1d). R1 VOUT -1 VFB1 . R1 For VFB2 active, find: VSW VFB1 = VOUT VOUT VIN ( REQ R1 + REQ ) REQ , (3b) VSAT t R2 = ISW VR2 IR2 = VFB1 - VFB2 VFB1/REQ . (3c) IPeak Then find R3, where: t 0 R3 = REQ - R2. ID IPeak 0 t Figure 7: Voltage and current waveforms for boost topology in CS5111. 7 { VFB1 VR2 R2 VFB2 R3 Figure 8. Feedback sense resistor divider connected between VOUT and ground. and then calculate R2 where: 0 VOUT (3a) (3d) CS5111 Application Notes: continued overall loop gain is 0dB at the crossover frequency, fCO. In addition, the gain slope should be -20dB/decade at the crossover frequency. The low frequency gain of the modulator (i.e. error amplifier output to output voltage) is: Step 4 Determine the maximum on time at the minimum oscillator frequency and VIN. For discontinuous operation, all of the stored energy in the inductor is transferred to the load prior to the next cycle. Since the current through the inductor cannot change instantaneously and the inductance is constant, a volt-second balance exists between the on time and off time. The voltage across the inductor during the on cycle is VIN and the voltage across the inductor during the off cycle is VOUT - VIN. Therefore: VINton = (VOUT -VIN)toff ∆VOUT ∆VEA [ 1- VIN(min) VOUT(max) ][ 1 fSW(min) √ RLoad L f , 2 (8a) (2.4V)/(7) VEA(max)/GCSA = =2.3A. 150mΩ RS Ipk(max) = (4a) ] Ipk(max) VEA(max) where where the maximum on time is: ton(max) ≈ = The VOUT/VEA transfer function has a pole at: . fp = 1/(πRLoadCOUT) , (4b) (8b) and a zero due to the output capacitor’s ESR at: fz = 1/(2πESR COUT). Step 5 Since the error amplifier reference voltage is 1.25V, the output voltage must be divided down or attenuated before being applied to the input of the error amplifier. The feedback resistor divider attenuation is: Calculate the maximum inductance allowed for discontinuous operation: L(max) = fSW(min) VIN2(min) ton2(max) 2 POUT/η (5) 1.25V . VOUT where η = efficiency. The error amplifier in the CS5111 is an operational transconductance amplifier (OTA), with a gain given by: Usually η = 0.75 is a good starting point. The IC’s power dissipation should be calculated after the peak current has been determined in Step 6. If the efficiency is less than originally assumed, decrease the efficiency and recalculate the maximum inductance and peak current. GOTA = gmZOUT where: Step 6 gm = Determine the peak inductor current at the minimum inductance, minimum VIN and maximum on time to make sure the inductor current doesn’t exceed 1.4A. Ipk = VIN(min) ton(max) L(min) ESR(min) = ∆Vripple Ipk (7b) (8e) For the error amplifier gain shown in Figure 10, a low frequency pole is generated by the error amplifier output impedance and C1. This is shown by the line AB with a 20dB/decade slope in Figure 12. The slope changes to zero at point B due to the zero at: Determine the minimum output capacitance and maximum ESR based on the allowable output voltage ripple. (7a) ∆IOUT . ∆VIN One possible error amplifier compensation scheme is shown in Figure 9. This gives the error amplifier a gain plot as shown in Figure 10. (6) Ipk 8f∆Vripple (8d) For the CS5111, gm = 2700µA/V typical. Step 7 COUT(min) = (8c) fz = 1/(2πR4C1). (8f) VOUT R1 In practice, it is normally necessary to use a larger capacitance value to obtain a low ESR. By placing capacitors in parallel, the equivalent ESR can be reduced. 1.25V + VFB1 M R2 VFB2 U C1 – X Error Amplifier R3 Step 8 Compensate the feedback loop to guarantee stability under all operating conditions. To do this, we calculate the modulator gain and the feedback resistor network attenuation and set the gain of the error amplifier so that the C2 R4 SELECT Figure 9. RC network used to compensate the error amplifier (OTA). 8 CS5111 Application Notes: continued VIN Pole due to error amplifier output impedance and C1 A fz = 1/2πR4C1 VOUT = 18V, Select > 2V VOUT = 16V, Select < 0.8V fP = 1/πR4C2 +G G C ENABLE NC VREG NC VLIN VSW IBIAS Gnd Gnd L=33µH B error amplifier gain -20dB/dec COUT 88µF (2) Gnd fP = 1/π RLoadCOUT R1 100kΩ Gnd fCO 0 R2 modulator gain + feedback resistor divider attenuation R3 946Ω (1) 7.5kΩ CS-5111 Gain (dB) VIN -G Gnd Gnd VFB1 RESET VFB2 CDelay COMP CCOMP 0.33µF Gnd Gnd SELECT 5V 100µF ESR<8Ω RBIAS = 64.9kΩ MICROPROCESSOR Cdelay 0.1µF WDI COSC COSC 390pF fz = 1/2π ESR COUT Figure 10. Bode plot of error amplifier (OTA) gain and modulator gain added to the feedback resistor divider attenuation. Figure 11. A typical application diagram with external components configured in a boost topology. A pole at point C: fp = 1/(πR4C2), Step 9 Finally the watchdog timer period and Power on Reset time is determined by: (8g) offsets the zero set by the ESR of the output capacitors. An alternative scheme uses a single capacitor as shown in Figure 11, to roll the gain off at a relatively low frequency. tDelay = 1.353 × CDelayRBIAS. (9) 100 100 75 75 ILIN (mA) ILIN (mA) Linear Regulator Output Current vs. Input Voltage ΘJA = 55°C/W VIN = 14V Max Total Power = 1.18W 50 Max Total Power = 1.86W 25 25 0 0 0 5 10 15 20 30 25 ΘJA = 35°C/W VIN = 14V 50 0 5 VREG (V) 10 15 20 25 30 VREG (V) Figure 12: The shaded area shows the safe operating area of the CS5111 as a function of ILIN, VREG, and ΘJA. Refer to the table below for typical loads and voltages. VREG (V) VIN (V) ILIN (mA) Linear Power Dissipation (W) 20 20 20 20 25 25 25 25 14 14 14 14 14 14 14 14 25 50 75 100 25 50 75 100 0.44 0.83 1.22 1.60 0.60 1.11 1.62 2.14 Worst Case Switcher Power Available (ΘJA = 55°C/W) (W) Worst Case Switcher Power Available (ΘJA = 35°C/W) (W) 0.74 0.35 * * 0.58 0.07 * * 1.42 1.03 0.64 0.26 1.26 0.75 0.24 * * Subjecting the CS5111 to these conditions will exceed the maximum total power that the part can handle, thereby forcing it into thermal limit. 9 CS5111 Package Specification PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA Thermal Data RΘJC typ typ RΘJA D Lead Count Metric Max Min 15.60 15.20 24 Lead SO Wide English Max Min .614 .598 24 Lead SO Wide 9 55 ˚C/W ˚C/W (internally fused leads) Surface Mount Wide Body (DW); 300 mil wide 7.60 (.299) 7.40 (.291) 10.65 (.419) 10.00 (.394) 0.51 (.020) 0.33 (.013) 1.27 (.050) BSC 2.49 (.098) 2.24 (.088) 1.27 (.050) 0.40 (.016) 2.65 (.104) 2.35 (.093) 0.32 (.013) 0.23 (.009) D REF: JEDEC MS-013 0.30 (.012) 0.10 (.004) Ordering Information Part Number CS5111YDWF24 CS5111YDWFR24 Rev. 12/28/98 Description 24 Lead SO Wide (internally fused leads) 24 Lead SO Wide (internally fused leads) (tape & reel) Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. 10 © 1999 Cherry Semiconductor Corporation