CY7C1041B 256K x 16 Static RAM Features (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). • High speed — tAA = 12 ns • Low active power Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. — 1540 mW (max.) • Low CMOS standby power (L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features Functional Description The CY7C1041B is a high-performance CMOS static RAM organized as 262,144 words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1041B is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout. Logic Block Diagram Pin Configuration SOJ TSOP II Top View 256K x 16 ARRAY 1024 x 4096 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER INPUT BUFFER A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 I/O0–I/O7 I/O8–I/O15 A9 A10 A 11 A 12 A 13 A14 A15 A16 A17 COLUMN DECODER Cypress Semiconductor Corporation Document #: 38-05142 Rev. *A BHE WE CE OE BLE • 3901 North First Street • 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 San Jose, CA 95134 • 408-943-2600 Revised March 24, 2005 CY7C1041B Selection Guide 7C1041B-12 7C1041B-15 7C1041B-17 7C1041B-20 7C1041B-25 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Unit 12 15 17 20 25 ns Com’l 200 190 180 170 160 mA Ind’l 220 210 200 190 180 Com’l Com’l L Ind’l 3 3 3 3 3 - 0.5 0.5 0.5 0.5 - 6 6 6 6 mA DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................–0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Operating Range Range Commercial Industrial Ambient Temperature[2] VCC 0°C to +70°C 5V ± 0.5 –40°C to +85°C Electrical Characteristics Over the Operating Range Parameter Description Test Conditions 7C1041B-12 7C1041B-15 7C1041B-17 Min. Min. Min. Max. 2.4 Max. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC + 0.5 2.2 VCC + 0.5 VIL Input LOW Voltage[1] –0.5 0.8 –0.5 0.4 Max. 2.4 0.4 Unit V 0.4 V 2.2 VCC + 0.5 V 0.8 –0.5 0.8 V IIX Input Load Current GND < VI < VCC –1 +1 –1 +1 –1 +1 mA IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 –1 +1 –1 +1 mA ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX ISB2 Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Com’l 200 190 180 mA Ind’l 220 210 200 mA 40 40 40 mA 3 3 3 mA - 0.5 0.5 mA - 6 6 mA Com’l Com’l Ind’l L Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the case temperature. Document #: 38-05142 Rev. *A Page 2 of 11 CY7C1041B Electrical Characteristics Over the Operating Range (continued) Test Conditions Parameter 7C1041B-20 Description Min. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage[1] IIX Input Load Current GND < VI < VCC IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX ISB2 Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 7C1041B-25 Max. Min. 2.4 Max. Unit 2.4 0.4 V 0.4 V 2.2 VCC + 0.5 2.2 VCC + 0.5 V –0.5 0.8 –0.5 0.8 V –1 +1 –1 +1 mA –1 +1 –1 +1 mA Com’l 170 160 mA Ind’l 190 180 mA 40 40 mA 3 3 mA 0.5 0.5 mA 6 6 mA Com’l Com’l L Ind’l Capacitance[3] Parameter Description CIN Input Capacitance COUT I/O Capacitance Test Conditions Max. TA = 25°C, f = 1 MHz, VCC = 5.0V Unit 8 pF 8 pF AC Test Loads and Waveforms R1 481Ω 5V R1 481Ω 5V OUTPUT 3.0V OUTPUT 30 pF R2 255Ω INCLUDING JIG AND SCOPE (a) 5 pF R2 255Ω INCLUDING JIG AND SCOPE (b) GND ≤ 3 ns ALL INPUT PULSES 90% 10% 90% 10% ≤ 3 ns THÉVENIN EQUIVALENT 167Ω 1.73V OUTPUT Equivalent to: Note: 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05142 Rev. *A Page 3 of 11 CY7C1041B Switching Characteristics[4] Over the Operating Range 7C1041B-12 Parameter Description Min. Max. 7C1041B-15 Min. Max. 7C1041B-17 Min. Max. Unit Read Cycle tpower VCC(typical) to the First Access[5] 1 tRC Read Cycle Time 12 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[6, 7] tLZCE CE LOW to Low Z[7] 1 15 12 3 3 3 3 7 0 7 3 6 ns ns ns 7 3 ns ns tHZCE CE HIGH to High tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 12 15 17 ns tDBE Byte Enable to Data Valid 6 7 7 ns tLZBE Byte Enable to Low Z tHZBE Byte Disable to High Z 7 ns 0 7 ns ns 17 7 0 6 ns 17 15 6 0 Z[6, 7] 17 15 12 µs 1 0 0 0 6 7 0 0 7 ns ns ns Write Cycle[8, 9] tWC Write Cycle Time 12 15 17 ns tSCE CE LOW to Write End 10 12 14 ns tAW Address Set-Up to Write End 10 12 14 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE WE Pulse Width 10 12 14 ns tSD Data Set-Up to Write End 7 8 8 ns tHD Data Hold from Write End 0 0 0 ns 3 3 3 ns WE HIGH to Low Z[7] tHZWE WE LOW to High Z[6, 7] tBW Byte Enable to End of Write tLZWE 6 10 7 12 7 12 ns ns Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. tpower time has to be provided initially before a read/write operation is started. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05142 Rev. *A Page 4 of 11 CY7C1041B Switching Characteristics[4] Over the Operating Range (continued) 7C1041B-20 Parameter Description Min. Max. 7C1041B-25 Min. Max. Unit Read Cycle tpower VCC(typical) to the First Access[5] 1 1 µs tRC Read Cycle Time 20 25 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z 8 0 OE HIGH to High Z CE LOW to Low tLZCE 3 Z[6, 7] CE HIGH to High tPU CE LOW to Power-Up tPD CE HIGH to Power-Down tDBE Byte Enable to Data Valid tLZBE Byte Enable to Low Z tHZBE Byte Disable to High Z 25 ns 10 ns ns 10 5 8 0 10 10 0 8 ns ns 25 8 0 ns ns 0 20 ns ns 0 8 Z[7] tHZCE 25 5 20 [6, 7] tHZOE WRITE 20 3 ns ns ns 10 ns CYCLE[8, 9] tWC Write Cycle Time 20 25 ns tSCE CE LOW to Write End 13 15 ns tAW Address Set-Up to Write End 13 15 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 13 15 ns tSD Data Set-Up to Write End 9 10 ns tHD Data Hold from Write End 0 0 ns 3 5 ns WE HIGH to Low Z[7] tHZWE WE LOW to High Z[6, 7] tBW Byte Enable to End of Write tLZWE 8 13 10 15 ns ns Data Retention Characteristics Over the Operating Range (L version only) Parameter Conditions[11] Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[3] Chip Deselect to Data Retention Time tR[10] Operation Recovery Time Min. Max. 2.0 Com’l L VCC = VDR = 3.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Unit V 200 mA 0 ns tRC ns Notes: 10. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds. 11. No input may exceed VCC + 0.5V. Document #: 38-05142 Rev. *A Page 5 of 11 CY7C1041B Data Retention Waveform DATA RETENTION MODE 3.0V VCC VDR > 2V 3.0V tR tCDR CE Switching Waveforms Read Cycle No. 1[12, 13] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[13, 14] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE DATA VALID HIGH IMPEDANCE tPD tPU 50% ICC 50% ISB Notes: 12. Device is continuously selected. OE, CE, BHE, and/or BHE = VIL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE transition LOW. Document #: 38-05142 Rev. *A Page 6 of 11 CY7C1041B Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[15, 16] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATAI/O Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATAI/O Notes: 15. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05142 Rev. *A Page 7 of 11 CY7C1041B Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Truth Table CE OE WE BLE BHE H X X X X High Z High Z Power Down Standby (ISB) L L H L L Data Out Data Out Read All bits Active (ICC) L L H L H Data Out High Z Read Lower bits only Active (ICC) L L H H L High Z Data Out Read Upper bits only Active (ICC) L X L L L Data In Data In Write All bits Active (ICC) L X L L H Data In High Z Write Lower bits only Active (ICC) L X L H L High Z Data In Write Upper bits only Active (ICC) L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) Document #: 38-05142 Rev. *A I/O0–I/O7 I/O8–I/O15 Mode Power Page 8 of 11 CY7C1041B Ordering Information Speed (ns) 12 15 17 20 25 15 17 20 25 Ordering Code Package Name Package Type CY7C1041B-12VC V34 44-Lead (400-Mil) Molded SOJ CY7C1041B-12VXC V34 44-Lead (400-Mil) Molded SOJ (Pb-free) CY7C1041B-12ZC Z44 44-Lead TSOP Type II CY7C1041B-12ZXC Z44 44-Lead TSOP Type II (Pb-free) CY7C1041B-15VC V34 44-Lead (400-Mil) Molded SOJ CY7C1041B-15VXC V34 44-Lead (400-Mil) Molded SOJ (Pb-free) CY7C1041BL-15VC V34 44-Lead (400-Mil) Molded SOJ CY7C1041B-15ZC Z44 44-Lead TSOP Type II CY7C1041B-15ZXC Z44 44-Lead TSOP Type II (Pb-free) CY7C1041BL-15ZC Z44 44-Lead TSOP Type II CY7C1041BL-15ZXC Z44 44-Lead TSOP Type II (Pb-free) CY7C1041B-17VC V34 44-Lead (400-Mil) Molded SOJ CY7C1041BL-17VC V34 44-Lead (400-Mil) Molded SOJ CY7C1041B-17ZC Z44 44-Lead TSOP Type II CY7C1041BL-17ZC Z44 44-Lead TSOP Type II CY7C1041B-20VC V34 44-Lead (400-Mil) Molded SOJ CY7C1041B-20VXC V34 44-Lead (400-Mil) Molded SOJ (Pb-free) CY7C1041BL-20VC V34 44-Lead (400-Mil) Molded SOJ CY7C1041BL-20VXC V34 44-Lead (400-Mil) Molded SOJ (Pb-free) CY7C1041B-20ZC Z44 44-Lead TSOP Type II CY7C1041B-20ZXC Z44 44-Lead TSOP Type II (Pb-free) CY7C1041BL-20ZC Z44 44-Lead TSOP Type II CY7C1041B-25VC V34 44-Lead (400-Mil) Molded SOJ CY7C1041BL-25VC V34 44-Lead (400-Mil) Molded SOJ CY7C1041B-25ZC Z44 44-Lead TSOP Type II CY7C1041BL-25ZC Z44 44-Lead TSOP Type II CY7C1041B-15ZI Z44 44-Lead TSOP Type II CY7C1041B-15ZXI Z44 44-Lead TSOP Type II (Pb-free) CY7C1041B-15VI V34 44-Lead (400-Mil) Molded SOJ CY7C1041B-15VXI V34 44-Lead (400-Mil) Molded SOJ (Pb-free) CY7C1041B-17ZI V34 44-Lead TSOP Type II CY7C1041B-17VI Z44 44-Lead (400-Mil) Molded SOJ CY7C1041B-20ZI Z44 44-Lead TSOP Type II CY7C1041B-20ZXI Z44 44-Lead TSOP Type II (Pb-free) CY7C1041B-20VI Z44 44-Lead (400-Mil) Molded SOJ CY7C1041B-20VXI Z44 44-Lead (400-Mil) Molded SOJ (Pb-free) CY7C1041B-25ZI Z44 44-Lead TSOP Type II CY7C1041B-25VI Z44 44-Lead (400-Mil) Molded SOJ Document #: 38-05142 Rev. *A Operating Range Commercial Industrial Page 9 of 11 CY7C1041B Package Diagrams 44-Lead (400-Mil) Molded SOJ V34 51-85082-*B 44-Pin TSOP II Z44 51-85087-*A All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05142 Rev. *A Page 10 of 11 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1041B Document History Page Document Title: CY7C1041B 256K x 16 Static RAM Document Number: 38-05142 REV. ECN NO. Issue Date Orig. of Change ** 109886 09/15/01 SZV Change from Spec number: 38-00938 to 38-05142 *A 341401 See ECN AJU Added Pb-free ordering information Document #: 38-05142 Rev. *A Description of Change Page 11 of 11