CLARE CPC7232KTR 8-channel high voltage analog switch with built-in bleeder resistor Datasheet

CPC7232
8-Channel High Voltage Analog Switch with
Built-in Bleeder Resistors
Features
Description
• Processed with BCDMOS on SOI (Silicon on
Insulator)
• Flexible High Voltage Supplies up to VPP-VNN+200V
• Output Bleed Resistors Built into the Device
• DC to 10MHz Analog Signal Frequency
• Surface Mount Package Available
• Low Quiescent Power Dissipation (< 1μA Typical)
• Output Switch On-Resistance Typically 20Ω
• TTL I/Os for 3.3V Interface
The CPC7232 is a low charge injection 8-channel
high-voltage analog switch integrated circuit (IC) for
use in applications requiring high voltage switching.
Bleeder resistors are incorporated into both terminals
of each output switch. Control of the high voltage
switching is via low voltage TTL logic level compatible
inputs for direct connectivity to the system controller.
Applications
• Ultrasound Imaging
• Printers
• Industrial Controls and Measurement
Because the CPC7232 is capable of switching high
load voltages and has a flexible load voltage range,
e.g. VPP/VNN: +40V/160V or +100V/100V, it is well
suited for many medical and industrial applications
such as medical ultrasound imaging, printers, and
industrial measurement equipment. The bleeder
resistors enable the discharge of capacitive loads,
such as piezoelectric transducers, connected to the
output switches of the CPC7232.
Figure 1. Block Diagram
LATCHES
LEVEL
SHIFTERS
VDD
DIN
OUTPUT
SWITCHES
VPP
D
LE
CL
SW0
D
LE
CL
SW1
D
LE
CL
SW2
DOUT
8 BIT
SHIFT
REGISTER
CLK
Switch manipulation is managed by an 8-bit serial to
parallel shift register whose outputs are buffered and
stored by an 8-bit transparent latch. Level shifters
buffer the latch outputs and operate the high voltage
switches.
Construction of the high voltage switches using
Clare's reliable BCDMOS process technology on SOI
(Silicon On Insulator) allow the switches to be
organized as solid state switches with direct gate
drive.
Ordering Information
Part Number Description
D
LE
CL
SW3
D
LE
CL
SW4
D
LE
CL
SW5
D
LE
CL
SW6
D
LE
CL
SW7
CPC7232W
CPC7232WTR
CPC7232K
CPC7232KTR
CL
LE
VNN
DS-CPC7232 - R00E
28-Lead PLCC in Tubes (37/Tube)
28-Lead PLCC Tape & Reel (500/Reel)
48-Lead LQFP in Trays (250/Tray)
48-Lead LQFP Tape & Reel (1000/Reel)
Pb
RGND
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RoHS
2002/95/EC
e3
1
CPC7232
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Package Pinout, PLCC-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Package Pinout, LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Logic Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.1 28-Pin PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.2 48-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Tape and Reel Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1 PLCC-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.2 LQFP-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Washing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
R00E
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2
CPC7232
1. Specifications
1.1 Package Pinout, PLCC-28
25
23
22
21
20
19
Pin
Name
Description
1
SW3
SW3 Output
26
18
2
SW3
SW3 Output
27
17
3
SW2
SW2 Output
4
SW2
SW2 Output
28
16
5
SW1
SW1 Output
1
15
6
SW1
SW1 Output
2
14
7
SW0
SW0 Output
8
SW0
SW0 Output
3
13
9
N/C
No connection
4
12
10
VPP
Switch positive high voltage supply
11
RGND
Ground for bleed resistors
12
VNN
Switch negative high voltage supply
13
GND
Ground
14
VDD
Logic positive voltage supply
15
N/C
No connection
16
DIN
Serial data input
17
CLK
Clock input, positive edge trigger
18
LE
Latch enable, active low
19
CL
Latch clear, active high clears latches and
opens switches
20
DOUT
Serial data output
21
SW7
SW7 Output
22
SW7
SW7 Output
23
SW6
SW6 Output
24
SW6
SW6 Output
25
SW5
SW5 Output
26
SW5
SW5 Output
27
SW4
SW4 Output
28
SW4
SW4 Output
5
R00E
24
1.2 Pin Description
6
7
8
9
10
11
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3
CPC7232
1.4 Pin Description
48
47
46
45
44
43
42
41
40
39
38
37
1.3 Package Pinout, LQFP-48
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
4
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Name
SW5
N/C
SW4
N/C
SW4
N/C
N/C
SW3
N/C
SW3
N/C
SW2
N/C
SW2
N/C
SW1
N/C
SW1
N/C
SW0
N/C
SW0
N/C
VPP
VNN
N/C
RGND
GND
VDD
N/C
N/C
N/C
DIN
CLK
LE
36
CL
37
38
39
40
41
42
43
44
45
46
47
48
DOUT
N/C
SW7
N/C
SW7
N/C
SW6
N/C
SW6
N/C
SW5
N/C
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Description
SW5 Output
No connection
SW4 Output
No connection
SW4 Output
No connection
No connection
SW3 Output
No connection
SW3 Output
No connection
SW2 Output
No connection
SW2 Output
No connection
SW1 Output
No connection
SW1 Output
No connection
SW0 Output
No connection
SW0 Output
No connection
Switch positive high voltage supply
Switch negative high voltage supply
No connection
Ground for bleed resistors
Ground
Logic positive supply voltage
No connection
No connection
No connection
Serial data input
Clock input, positive edge trigger
Latch enable, active low
Latch clear, active high clears latches and
opens switches
Serial data output
No connection
SW7 Output
No connection
SW7 Output
No connection
SW6 Output
No connection
SW6 Output
No connection
SW5 Output
No connection
R00E
CPC7232
1.5 Absolute Maximum Ratings
Absolute maximum electrical ratings are at 25°C.
Parameter
Min
Max
Units
-0.5
6
V
-
220
V
VPP Positive High Voltage Supply
-0.5
VNN+200
V
VNN Negative High Voltage Supply
-0.5
VPP-200
V
Logic input voltages
-0.5
VDD+0.3
V
Analog signal range
VNN
VPP
V
-
1
A
28-Lead PLCC
-
2.5
48-Lead LQFP
-
2.3
28-Lead PLCC
-
50
48-Lead LQFP
-
53
-60
+150
VDD Logic Power Supply Voltage
VPP - VNN Supply Voltage
Peak analog signal current per channel
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at conditions
beyond those indicated in the operational sections of this
data sheet is not implied.
Power dissipation
W
Thermal Resistance, Junction to Ambient
Storage temperature
°C/W
°C
1.6 Operating Conditions
Parameter
Symbol
Value
Logic power supply voltage 1, 3
VDD
4.5V to 6V
Positive high voltage supply 1, 3
VPP
40V to VNN + 200V
Negative high voltage supply 1, 3
VNN
-40V to -160V
Analog signal voltage, peak-to-peak 2
VSW
VNN+10V to VPP-10V
TA
0°C to 70°C
Operating temperature
1
Power up/down sequence is arbitrary except that GND must be powered-up first and powered-down last.
2
VSW must be VNN ≤ VSW ≤ VPP or floating during power up/down transition.
3
Rise and fall times of power supplies, VDD , VPP , and VNN , should not be less than 1ms.
R00E
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5
CPC7232
1.7 Electrical Characteristics
1.7.1 Switch Characteristics (over recommended operating conditions unless otherwise noted)
0°C
Parameter
Small signal switch on-resistance
Small signal switch
on-resistance matching
Symbol
RONS
+25°C
+70°C
Test Conditions
Units
min
max
min
typ
max
min
max
VPP=40V, VNN=-160V, ISW=5mA
-
30
-
26
38
-
48
VPP=40V, VNN=-160V, ISW=200mA
-
25
-
22
27
-
32
VPP=100V, VNN=-100V, ISW=5mA
-
25
-
22
27
-
30
VPP=100V, VNN=-100V, ISW=200mA
-
18
-
18
24
-
27
VPP=160V, VNN=-40V, ISW=5mA
-
23
-
20
25
-
30
VPP=160V, VNN=-40V, ISW=200mA
-
22
-
16
25
-
27
-
20
-
5
20
-
20
%
ΔRONS ISW=5mA, VPP=100V, VNN=-100V
Ω
Large signal switch on-resistance
RONL
VSW=VPP-10V, ISW=0.8A
-
-
-
15
-
-
-
Ω
Output bleed resistors
RINT
Output switch to RGND, IRINT=0.5mA
-
-
20
35
50
-
-
kΩ
Switch off leakage per switch
ISOL
VSW=VPP-10V and VNN+10V
-
5
-
0.4
10
-
15
μA
-
RL=100kΩ
-
100
-
0
100
-
100
DC offset, switch on
-
RL=100kΩ
-
100
-
0
100
-
100
Switch output peak current
-
VSW duty cycle = 0.1%
-
-
-
-
0.8
-
-
A
Duty cycle = 50%
-
-
-
-
50
-
-
kHz
-
20
-
-
20
-
20
V/ns
f=5MHz, 1kΩ/15pF load
-30
-
-30
-33
-
-30
-
f=5MHz, 50Ω load
-58
-
-58
-
-
-58
-
-60
-
-60
-
-
-60
-
dB
-
300
-
-
300
-
300
mA
DC offset, switch off
Output switch frequency
fSW
mV
VPP=160V, VNN=-40V
Maximum VSW slew rate
dV/dt
VPP=100V, VNN=-100V
VPP=40V, VNN=-160V
Off isolation
KO
Switch crosstalk
KCR
f=5MHz, 50Ω load
Output switch isolation diode
current
IID
300ns pulse width, 2.0% duty cycle
Off capacitance, SW to GND
CSG(OFF) VSW=0V, 1MHz
5
17
5
21
25
5
20
On capacitance, SW to GND
CSG(ON) VSW=0V, 1MHz
25
40
20
30
40
25
50
-
-
-
-
150
-
-
-
880
-
+VSPK
-VSPK
Output voltage spike
+VSPK
-VSPK
+VSPK
-VSPK
Charge injection
6
Q
dB
pF
VPP=40V, VNN=-160V, RL=50Ω
VPP=100V, VNN=-100V, RL=50Ω
mV
VPP=160V, VNN=-40V, RL=50Ω
VPP=100V, VNN=-100V, VSW=0V
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pC
R00E
CPC7232
1.7.2 Logic DC Characteristics (over recommended operating conditions unless otherwise noted)
0°C
Parameter
Symbol
+25°C
+70°C
Test Conditions
Units
min
max
min
typ
max
min
max
DOUT source capability
VOH
IOUT=--400μA
-
-
VDD-0.7
-
-
-
-
DOUT sink capability
VOL
IOUT=-+400μA
-
-
-
-
0.7
-
-
Logic input capacitance
CIN
-
10
-
-
10
-
10
Logic input high
VIH
4.75V < VDD < 5.25V
2
-
2
-
-
2
-
Logic input low
VIL
4.75V < VDD < 5.25V
-
0.8
-
-
0.8
-
0.8
-
V
pF
V
1.7.3 Logic AC Characteristics (over recommended operating conditions unless otherwise noted)
0°C
Parameter
Symbol
+25°C
70°C
Test Conditions
Units
min
max
min
typ
max
min
max
Setup time before LE rises
tSD
-
150
-
150
-
-
150
-
Time width of LE
tWLE
-
150
-
150
-
-
150
-
Clock delay time to Data Out
tDO
-
-
150
-
-
150
-
150
Time width of CL
tWCL
-
150
-
150
-
-
150
-
Setup time, data to clock
tSU
-
15
-
15
8
-
20
-
Hold time, data from clock
tH
-
35
-
35
-
-
35
-
-
5
-
-
5
-
5
MHz
-
50
-
-
50
-
50
ns
-
5
-
-
5
-
5
μs
Clock frequency
fCLK
Clock rise and fall times
tR, tF
Turn-on time
tON
Turn-off time
tOFF
R00E
50% duty cycle, fDATA=fCLK/2
VSW=VPP-10V, RL=10kΩ
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ns
7
CPC7232
1.7.4 Supply DC Characteristics (over recommended operating conditions unless otherwise noted)
0°C
Parameter
VPP quiescent supply current
VNN quiescent supply current
Symbol
IPPQ
INNQ
All switches off
All switches on, ISW=5mA
All switches off
All switches on, ISW=5mA
VPP=40V,
VNN=-160V
VPP operating supply current
IPP
50kHz output
switching
frequency with
no load
VPP=100V,
VNN=-100V
VPP=160V,
VNN=-40V
VPP=40V,
VNN=-160V
VNN operating supply current
INN
50kHz output
switching
frequency with
no load
VPP=100V,
VNN=-100V
VPP=160V,
VNN=-40V
VDD average supply current
IDD
VDD quiescent supply current
IDDQ
8
+25°C
+70°C
Test Conditions
fCLK=5MHz, VDD=5V
-
Units
min
max
min
typ
max
min
max
-
-
-
0.1
10
-
μA
-
-
-
-0.1
-10
-
-
-
6.5
-
-
7
-
8
-
5
-
-
5.5
-
5.5
-
5
-
-
5
-
5.5
-
6.5
-
-
7
-
8
-
5
-
-
5.5
-
5.5
-
5
-
-
5
-
5.5
-
4
-
-
4
-
4
mA
-
10
-
1
10
-
10
μA
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mA
mA
R00E
CPC7232
2. Functional Description
The CPC7232 takes a serial stream of input data
along with a synchronous clock signal. As the clock
transits from low to high, the data at the input of each
shift register is shifted through from SR(n) to SR(n+1).
A high data bit, a "1," represents an ON switch; a low
data bit, a "0," represents an OFF switch. Data is input
and shifted through the internal shift register until all
eight shift register positions, SR0 through SR7, are in
the desired state.
DIN: The data-in line presents data bits to the
CPC7232 to be shifted through the internal shift
register.
CLK: The clock signal's rising edge is associated only
with shifting data into and through the shift register.
CL: The clear line overrides all other inputs. When CL
is high, the shift register is cleared to all 0s and all
latches are set low, which causes all output switches
to be turned OFF immediately. When CL is low, all
output switches remain in whatever state they are in,
ON or OFF, in response to CLK, latch inputs, and the
LE signal.
LE: latch enable controls the state of the latches and
thus the state of the eight switches. If LE is high, then
the latches do not change states, but retain their most
recent status: either ON or OFF. With LE high, input
data and CLK have no effect on the state of the output
switches. If LE is low, then all latch outputs and their
switch states follow the inputs from the shift register.
LE is overridden by CL: no matter what state LE is in,
CL clears the latches. See “Truth Table” on page 10.
Two or more CPC7232 devices can be cascaded to
form an n-switch arrangement. The DOUT pin of the
first is connected to the DIN pin of the next in the
series. All devices are connected to the same clock
(CLK) signal. LE of all devices would normally be
connected, as would CL, but this is not necessary.
The first data bit applied to DIN of the CPC7232,
whether it's a single device or several cascaded
devices, ripples through to the last switch output in line
after the application of a full clocking sequence of 8
clock pulses per CPC7232. Setting the serial I/O
device to output the most significant bit (MSB) first,
results in the MSB appearing on SW7 of the last
device in line after a full clocking sequence.
DIN
DIN
CLK
CLK
SW0
CPC7232
CL
CL
LE
LE
DOUT: The data-out pin is the output of SR7. After
eight clock pulses, the first bit of eight input data bits is
shifted to SR7 and appears on DOUT.
SW7
DOUT
DIN
CLK
SW0
CPC7232
CL
SW0 - SW7: The CPC7232 provides eight
high-voltage SPST output switches with a typical
on-resistance of 20. The two connections of each
switch are not polarity-sensitive.
LE
SW7
DOUT
VPP and VNN: Voltage inputs to the level shifters for
each switch channel that translate the voltage level of
the latch output signals to an appropriate level for the
voltages being switched.
The high-voltage output switches are turned on and off
in response to the data sent into the latches from the
shift register: data 0 turns a switch OFF, data 1 turns a
switch ON.
DIN
CLK
SW0
CPC7232
CL
LE
DOUT
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SW7
9
CPC7232
2.1 Truth Table
D0
D1
D2
D3
D4
D5
D6
D7
LE
CL
SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
OFF
ON
L
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
HOLD PREVIOUS STATE
OFF OFF OFF OFF OFF OFF OFF OFF
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L? H transition CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift
register data flows through the latch.
4. DOUT is high when switch 7 is on.
5. Shift register clocking has no effect on the switch states if LE is H.
6. The clear input overrides all other inputs.
2.2 Logic Timing Waveforms
DN-1
DN
DIN
50%
LE
50%
DN+1
50%
50%
tWLE
tSD
tSU
tDO
DOUT
tH
50%
tOFF
VOUT OFF
(TYP)
50%
50%
CLK
tON
90%
10%
ON
CL
50%
50%
tWCL
10
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R00E
CPC7232
3. Manufacturing Information
3.1 Mechanical Dimensions
3.1.1 28-Pin PLCC Package
28-Pin PLCC Package
Recommended PCB Land Pattern
12.319/12.573
(0.485/0.495)
11.430/11.582
(0.450/0.456)
10.90
(0.429)
0.020 MIN
(0.004 MIN)
11.430/11.582
(0.4500.456)
12.319/12.573
(0.485/0.495)
0.65
(0.026)
Pin 1
10.90
(0.429)
0.660/0.813
(0.026/0.032)
0.330/0.533
(0.013/0.021)
2.40
(0.094)
2.286/3.048
(0.090/0.120)
1.27 TYP
(0.050 TYP)
1.27
(0.050)
4.191/4.572
(0.165/0.180)
Dimensions
mm(Max)/mm(Min)
(inches(Max/inches(Min))
3.1.2 48-Pin LQFP Package
48-Pin LQFP Package
Recommended PCB Land Pattern
9.00 ± 0.20
(0.354 ± 0.008)
7.00 ± 0.10
(0.276 ± 0.004)
7.00 ± 0.10
(0.276 ± 0.004)
9.00 ± 0.20
(0.354 ± 0.008)
0.50
(0.020)
8.50
(0.335)
Pin 48
Pin 1
0.22 ± 0.05
(0.009 ± 0.002)
1.40 ± 0.05
(0.055 ± 0.002)
0.05 Min / 0.15 Max
(0.002 Min - 0.006 Max)
0.50
(0.020)
0.30
(0.012)
1.45
(0.057)
Dimensions
mm
(inches)
0.60, +0.15/-0.10
(0.024, +0.006/-0.004)
R00E
8.50
(0.335)
1.60 Max
(0.063Max)
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11
CPC7232
3.2 Tape and Reel Specifications
3.2.1 PLCC-28
330.2 DIA.
(13.00 DIA.)
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
Embossed Carrier
2.0±0.10
(0.079±0.004)
4.0
(0.157)
16.00±0.10
(0.63±0.004)
13.0±0.10
(0.512±0.004)
TBD
1.75±0.10
(0.069±0.004)
11.5±0.1
(0.453±0.004)
24.0±0.3
(0.945±0.012)
13.0±0.10
(0.512±0.004)
4.9±0.10
(0.193±0.004)
Dimensions
mm
(inches)
Embossment
3.2.2 LQFP-48
330.2 DIA.
(13.00 DIA.)
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
2.00±0.10
(0.079±0.004)
9.30±0.10
(0.366±0.004)
4.00
(0.157)
1.75±0.10
(0.069±0.004)
12.00±0.10
(0.47±0.004)
7.5±0.1
(0.295±0.004)
2.20±0.10
(0.087±0.004)
Embossed Carrier
1.60±0.10
(0.063±0.004)
6.40±0.10
(0.252)
9.30±0.10
(0.366±0.004)
Dimensions
mm
(inches)
16.0±0.3
(0.629±0.012
Embossment
12
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R00E
CPC7232
3.3 Soldering
For proper assembly, the component must be
processed in accordance with the current revision of
IPC/JEDEC standard, J-STD-020. Failure to follow the
recommended guidelines may cause permanent
damage to the device resulting in impaired
performance and/or a reduced lifetime expectancy.
3.4 Washing
Clare does not recommend ultrasonic cleaning of this
part.
Pb
RoHS
2002/95/EC
e3
For additional information please visit www.clare.com
Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set
forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its
products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into
the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a
person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice.
Specification: DS-DS-CPC7232-R00E
© Copyright 2009, Clare, Inc.
All rights reserved. Printed in USA.
4/20/09
R00E
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13
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