ETC1 EX256-FTQ49 Ex family fpgas Datasheet

v3.0
eX Family FPGAs
Le a di n g E d ge P er f o r m a n ce
• 240 MHz System Performance
Sp e ci f i c a t i on s
• Individual Output Slew Rate Control
• 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V
Input Tolerance and 5.0V Drive Strength
• Software Design Support with Actel Designer Series and
Libero Tools
• 3,000 to 12,000 Available System Gates
• Up to 100% Resource Utilization with 100% Pin Locking
• As Many as 512 Maximum Flip-Flops (Using CC Macros)
• Deterministic Timing
• 0.22µ CMOS Process Technology
• Unique In-System Diagnostic and Verification Capability
with Silicon Explorer II
• 3.9ns Clock-to-Out (Pad-to-Pad)
• 350 MHz Internal Performance
• Up to 132 User-Programmable I/O Pins
• Boundary Scan Testing in Compliance with IEEE Standard
1149.1 (JTAG)
Fe a t ur es
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
• High-Performance, Low-Power Antifuse FPGA
• LP/Sleep Mode for Additional Power Savings
• Advanced Small-footprint Packages
G en er al D e sc r i p t i on
• Hot-Swap Compliant I/Os
The eX family of FPGAs is a low-cost solution for low-power,
high-performance designs. The inherent low power
attributes of the antifuse technology, coupled with an
additional low static power mode, make these devices ideal
for power-sensitive applications. Fabricated with an
advanced 0.22µ CMOS antifuse technology, these devices
achieve high performance with no power penalty.
• Single-Chip Solution
• Nonvolatile
• Live on power up
• Power-Up/Down Friendly (No Sequencing Required for
Supply Voltages)
• Configurable Weak-Resistor Pull-Up or Pull-Down for
Tristated Outputs during Power Up
eX P r o du ct Pr o f i l e
Device
eX64
eX128
eX256
Capacity
System Gates
Typical Gates
3,000
2,000
6,000
4,000
12,000
8,000
Register Cells (Dedicated Flip-Flops)
64
128
256
Combinatorial Cells
128
256
512
Maximum User I/Os
Speed Grades
Temperature Grades
Package (by pin count)
TQFP
CSP
D e ce m b e r 2 0 0 1
© 2001 Actel Corporation
84
100
132
–F, Std, –P
–F, Std, –P
–F, Std, –P
C, I
C, I
C, I
64, 100
49, 128
64, 100
49, 128
100
128, 180
1
e X F a m il y F P GA s
O r d e r i n g I nf o r m a t i o n
eX128
–P
TQ
100
Application (Temperature Range)
Blank = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
PP = Pre-production
Package Lead Count
Package Type
TQ = Thin (1.4mm) Quad Flat Pack
CS = Chip-Scale Package (0.8mm pitch)
Speed Grade
Blank = Standard Speed
–P = Approximately 30% Faster than Standard
–F = Approximately 40% Slower than Standard
Part Number
eX64 =
eX128 =
eX256 =
64 Dedicated Flip-Flops (3,000 System Gates)
128 Dedicated Flip-Flops (6,000 System Gates)
256 Dedicated Flip-Flops (12,000 System Gates)
Pr od uc t P l a n
Speed Grade
Application
–F
Std
–P
C
I†
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
Available
Applications:
eX64 Device
64-Pin Thin Quad Flat Pack (TQFP)
100-Pin Thin Quad Flat Pack (TQFP)
49-Pin Chip Scale Package (CSP)
128-Pin Chip Scale Package (CSP)
eX128 Device
64-Pin Thin Quad Flat Pack (TQFP)
100-Pin Thin Quad Flat Pack (TQFP)
49-Pin Chip Scale Package (CSP)
128-Pin Chip Scale Package (CSP)
eX256 Device
100-Pin Thin Quad Flat Pack (TQFP)
✔
128-Pin Chip Scale Package (CSP)
✔
180-Pin Chip Scale Package (CSP)
✔
Contact your Actel sales representative for product availability.
Speed Grade: –P = Approx. 30% faster than Standard
Availability: ✔ =
–F = Approx. 40% slower than Standard
C = Commercial
I = Industrial
† Only Std Speed Grade
Pl a s t i c D e vi c e Re so u r ce s
User I/Os (including clock buffers)
Device
TQFP 64-Pin
TQFP 100-Pin
CSP 49-Pin
CSP 128-Pin
CSP 180-Pin
eX64
41
56
36
84
—
eX128
46
70
36
100
—
100
132
eX256
Package Definitions:
2
—
81
—
TQFP = Thin Quad Flat Pack, CSP = Chip Scale Package
v3.0
e X F a m il y F P GA s
eX F am i l y A r c hi t e c t ur e
The C-cell implements a range of combinatorial functions
up to 5 inputs (Figure 2). Inclusion of the DB input and its
associated inverter function dramatically increases the
number of combinatorial functions that can be
implemented in a single module from 800 options in
previous architectures to more than 4,000 in the eX
architecture.
The eX family architecture uses a “sea-of-modules”
structure where the entire floor of the device is covered
with a grid of logic modules with virtually no chip area lost
to interconnect elements or routing. Interconnection
among these logic modules is achieved using Actel’s
patented
metal-to-metal
programmable
antifuse
interconnect elements. Actel’s eX family provides two types
of logic modules, the register cell (R-cell) and the
combinatorial cell (C-cell).
M o d ule O r g a n i z a t io n
Actel has arranged all C-cell and R-cell logic modules into
horizontal banks called Clusters. The eX devices contain
one type of Cluster, which contains two C-cells and one
R-cell.
The R-cell contains a flip-flop featuring asynchronous clear,
asynchronous preset, and clock enable (using the S0 and S1
lines) control signals (Figure 1). The R-cell registers
feature programmable clock polarity selectable on a
register-by-register basis. This provides additional flexibility
while allowing mapping of synthesized functions into the eX
FPGA. The clock source for the R-cell can be chosen from
either the hard-wired clock or the routed clock.
S0
To increase design efficiency and device performance, Actel
has further organized these modules into SuperClusters
(Figure 3 on page 4). The eX devices contain one type of
SuperClusters, which are two-wide groupings of one type of
clusters.
Routed
Data Input S1
PSET
DirectConnect
Input
D
Y
Q
HCLK
CLKA,
CLKB,
Internal Logic
CLR
CKS
CKP
Figure 1 • R-Cell
D0
D1
Y
D2
D3
Sa
Sb
DB
A0
B0
A1
B1
Figure 2 • C-Cell
v3.0
3
e X F a m il y F P GA s
Rou ti ng Res our ces
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect, which enable extremely
fast and predictable interconnection of modules within
Clusters and SuperClusters (Figure 4). This routing
architecture also dramatically reduces the number of
antifuses required to complete a circuit, ensuring the
highest possible performance.
DirectConnect is a horizontal routing resource that provides
connections from a C-cell to its neighboring R-cell in a given
SuperCluster. DirectConnect uses a hard-wired signal path
requiring no programmable interconnection to achieve its
fast signal propagation time of less than 0.1 ns (–P speed
grade).
FastConnect enables horizontal routing between any two
logic modules within a given SuperCluster and vertical
routing with the SuperCluster immediately below it. Only
one programmable connection is used in a FastConnect
path, delivering maximum pin-to-pin propagation of 0.3 ns
(–P speed grade).
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources known as segmented routing and high-drive
routing. Actel’s segmented routing structure provides a
variety of track lengths for extremely fast routing between
SuperClusters. The exact combination of track lengths and
antifuses within each path is chosen by the 100 percent
automatic place-and-route software to minimize signal
propagation delays.
R-Cell
S0
C-Cell
D0
Routed
Data Input S1
D1
PSET
Y
D2
DirectConnect
Input
D
Q
D3
Y
Sa
Sb
HCLK
CLKA,
CLKB,
Internal Logic
CLR
DB
CKS
CKP
A0
Cluster 1
B0
A1
B1
Cluster 1
Type 1 SuperCluster
Figure 3 • Cluster Organization
DirectConnect
• No antifuses
• 0.1 ns routing delay
Type 1 SuperClusters
FastConnect
• One antifuse
• 0.3 ns routing delay
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
Figure 4 • DirectConnect and FastConnect for Type 1 SuperClusters
4
v3.0
e X F a m il y F P GA s
Cl ock Res our ce s
Actel’s high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hardwired from
the HCLK buffer to the clock select MUX in each R-Cell.
HCLK cannot be connected to combinational logic. This
provides a fast propagation path for the clock signal,
enabling the 3.9ns clock-to-out (pad-to-pad) performance of
the eX devices. The hard-wired clock is tuned to provide a
clock skew of less than 0.1ns worst case.
The remaining two clocks (CLKA, CLKB) are global clocks
that can be sourced from external pins or from internal
logic signals within the eX device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
CLKA or CLKB is sourced from internal logic signals then
the external clock pin cannot be used for any other input
and must be tied low or high. Figure 5 describes the clock
circuit used for the constant load HCLK. Figure 6 describes
the CLKA and CLKB circuit used in eX devices.
Constant Load
Clock Network
platform upon which to integrate the functionality
previously contained in CPLDs. In addition, designs that
previously would have required a gate array to meet
performance goals can now be integrated into an eX device
with dramatic improvements in cost and time to market.
Using timing-driven place-and-route tools, designers can
achieve highly deterministic device performance.
I/O Modules
Each I/O on an eX device can be configured as an input, an
output, a tristate output, or a bidirectional pin. Even without
the inclusion of dedicated I/O registers, these I/Os, in
combination with array registers, can achieve clock-to-out
(pad-to-pad) timing as fast as 3.9ns. I/O cells that have
embedded latches and flip-flops require instantiation in HDL
code; this is a design complication not encountered in eX
FPGAs. Fast pin-to-pin timing ensures that the device will
have little trouble interfacing with any other device in the
system, which in turn enables parallel design of system
components and reduces overall design time. See Table 1 for
more information.
Table 1 • I/O Features
Function
Description
Input Buffer
Threshold
Selection
• TTL/3.3V LVTTL
• 2.5V LVCMOS 2
Clock Network
Flexible
Output
Driver
Output
Buffer
“Hot-Swap” Capability
From Internal Logic
HCLKBUF
Figure 5 • eX HCLK Clock Pad
CLKBUF
CLKBUFI
CLKINT
CLKINTI
• 3.3V LVTTL
• 5.0V TTL/CMOS
• I/O on an unpowered device does not
sink current
• Can be used for “cold sparing”
Selectable on an individual I/O basis
Individually selectable low-slew option
Power Up
Figure 6 • eX Routed Clock Buffer
O t he r A r c hi t ec tu ral Fe atu r e s
Individually selectable pull ups and pull
downs during power up (default is to power
up in tristate)
Enables deterministic power up of device
T echno log y
Actel’s eX family is implemented on a high-voltage twin-well
CMOS process using 0.22µ design rules. The metal-to-metal
antifuse is made up of a combination of amorphous silicon
and dielectric material with barrier metals and has an “on”
state resistance of 25Ω with a capacitance of 1.0 fF for low
signal impedance.
P erf orm a nce
The combination of architectural features described above
enables eX devices to operate with internal clock
frequencies exceeding 350 MHz for very fast execution of
complex logic functions. Thus, the eX family is an optimal
VCCA and VCCI can be powered in any order
Hot S wa ppin g
eX I/Os are configured to be hot swappable. During power
up/down (or partial up/down), all I/Os are tristated. VCCA
and VCCI do not have to be stable during power up/down,
and they do not require a specific power-up or power-down
sequence in order to avoid damage to the eX devices. After
the eX device is plugged into an electrically active system,
the device will not degrade the reliability of or cause
damage to the host system. The device’s output pins are
driven to a high impedance state until normal chip
v3.0
5
e X F a m il y F P GA s
operating conditions are reached. Please see the Actel SX-A
and RT54SX-S Devices in Hot-Swap and Cold-Sparing
Applications application note for more information on hot
swapping.
P ower R equ ir em ent s
The eX family supports mixed voltage operation and is
designed to tolerate 5.0V inputs in each case (Table 2).
Power consumption is extremely low due to the very short
distances signals, which are required to travel to complete a
circuit. Power requirements are further reduced because of
the small number of low-resistance antifuses in the path.
The antifuse architecture does not require active circuitry
to hold a charge (as do SRAM or EPROM), making it the
lowest-power architecture FPGA available today. Also, when
the device is in low power mode, the clock pins must not
float. They must be driven either HIGH or LOW. We
recommend that signals driving the clock pins be fixed at
HIGH or LOW rather than toggle to achieve maximum power
efficiency.
Table 2 • Supply Voltages
eX64
eX128
eX256
Maximum Maximum
Input
Output
Tolerance
Drive
VCCA
VCCI
2.5V
2.5V
5.0V
2.5V
2.5V
3.3V
5.0V
3.3V
2.5V
5.0V
5.0V
5.0V
Low P ower Mode
The new Actel eX family has been designed with a Low
Power Mode. This feature, activated with a special LP pin, is
particularly useful for battery-operated systems where
battery life is a primary concern. In this mode, the core of
the device is turned off and the device consumes minimal
power with low standby current. In addition, all input
buffers are turned off, and all outputs and bidirectional
buffers are tristated when the device enters this mode.
Since the core of the device is turned off, the states of the
registers are lost. The device must be re-initialized when
normal operating mode is achieved.
2.5V LP/Sleep Mode Specifications
Typical Conditions, VCCA, VCCI = 2.5V, TJ = 25° C
Product
Low Power Standby Current
Units
eX64
100
µA
eX128
111
µA
eX256
134
µA
in conjunction with the program fuse. The functionality of
each pin is described in Table 3. In the dedicated test mode,
TCK, TDI, and TDO are dedicated pins and cannot be used
as regular I/Os. In flexible mode, TMS should be set HIGH
through a pull-up resistor of 10kΩ. TMS can be pulled LOW
to initiate the test sequence.
Table 3 • Boundary Scan Pin Functionality
Program Fuse Blown
(Dedicated Test Mode)
Program Fuse Not Blown
(Flexible Mode)
TCK, TDI, TDO are
dedicated BST pins
TCK, TDI, TDO are flexible
and may be used as I/Os
No need for pull-up resistor
for TMS
Use a pull-up resistor of
10kΩ on TMS
C onfi gur ing Di agn ost i c P in s
The JTAG and Probe pins (TDI, TCK, TMS, TDO, PRA, and
PRB) are placed in the desired mode by selecting the
appropriate check boxes in the “Variation” dialog window.
This dialog window is accessible through the Design Setup
Wizard under the Tools menu in Actel's Designer software.
T RS T P i n
When the “Reserve JTAG Reset” box is checked, the TRST
pin will become a Boundary Scan Reset pin. In this mode,
the TRST pin will function as an asynchronous, active-low
input to initialize or reset the BST circuit. An internal
pull-up resistor will be automatically enabled on the TRST
pin.
The TRST pin will function as a user I/O when the “Reserve
JTAG Reset” box is not checked. The internal pull-up
resistor will be disabled in this mode.
D edic at ed T e st M ode
When the “Reserve JTAG” box is checked, the eX device is
placed in Dedicated Test mode, which configures the TDI,
TCK, and TDO pins for BST or in-circuit verification with
Silicon Explorer II. An internal pull-up resistor is
automatically enabled on both the TMS and TDI pins. In
Dedicated Test Mode, TCK, TDI, and TDO are dedicated test
pins and become unavailable for pin assignment in the Pin
Editor. The TMS pin will function as specified in the IEEE
1149.1 (JTAG) Specification.
Fl exi ble Mo de
Bou ndar y S can T es ti ng (BS T )
When the “Reserve JTAG” box is not selected (default
setting in Designer software), eX is placed in Flexible mode,
which allows the TDI, TCK, and TDO pins to function as user
I/Os or BST pins. In this mode the internal pull-up resistors
on the TMS and TDI pins are disabled. An external 10kΩ
pull-up resistor to VCCI is required on the TMS pin.
All eX devices are IEEE 1149.1 compliant. eX devices offer
superior diagnostic and testing capabilities by providing
Boundary Scan Testing (BST) and probing capabilities.
These functions are controlled through the special test pins
The TDI, TCK, and TDO pins are transformed from user I/Os
into BST pins when a rising edge on TCK is detected while
TMS is at logical low. Once the BST pins are in test mode
they will remain in BST mode until the internal BST state
6
v3.0
e X F a m il y F P GA s
The Program fuse determines whether the device is in
Dedicated Test or Flexible mode. The default (fuse not
programmed) is Flexible mode.
verification and logic analysis tool that can sample data at
100 MHz (asynchronous) or 66 MHz (synchronous). Silicon
Explorer II attaches to a PC’s standard COM port, turning
the PC into a fully functional 18-channel logic analyzer.
Silicon Explorer II allows designers to complete the design
verification process at their desks and reduces verification
time from several hours per cycle to only a few seconds.
Dev el opm ent To ol S uppor t
eX P ro be Cir cu it C ont ro l Pi ns
The eX devices are fully supported by Actel’s line of FPGA
development tools, including the Actel Designer Series suite
and Libero, the FPGA design tool suite. Designer Series,
Actel’s suite of FPGA development tools for PCs and
Workstations, includes the ACTgen Macro Builder, timing
driven place-and-route, timing analysis tools, and fuse file
generation. Libero is a design management environment
that integrates the needed design tools, streamlines the
design flow, manages all design and log files, and passes
necessary design data between tools. Libero includes
Synplify, ViewDraw, Actel’s Designer Series, ModelSim HDL
Simulator, WaveFormer Lite, and Actel Silicon Explorer.
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TCK, TMS and TDO) to select the desired nets for
verification. The selected internal nets are assigned to the
PRA/PRB pins for observation. Figure 7 illustrates the
interconnection between Silicon Explorer II and the FPGA
to perform in-circuit verification. The TRST pin is equipped
with an internal pull-up resistor. To remove the boundary
scan state machine from the reset state during probing, it is
recommended that the TRST pin be left floating.
machine reaches the “logic reset” state. At this point the
BST pins will be released and will function as regular I/O
pins. The “logic reset” state is reached five TCK cycles after
the TMS pin is set to logical HIGH.
De si gn C ons id era ti ons
For prototyping, the TDI, TCK, TDO, PRA, and PRB pins
should not be used as input or bidirectional ports. Because
these pins are active during probing, critical signals input
through these pins are not available while probing. In
addition, the Security Fuse should not be programmed
because doing so disables the probe circuitry.
Channels
16
In addition, the eX devices contain internal probe circuitry
that provides built-in access to the output of every C-cell,
R-cell, and routed clock in the design, enabling 100-percent
real-time observation and analysis of a device's internal
logic nodes without design iteration. The probe circuitry is
accessed by Silicon Explorer II, an easy-to-use integrated
eX FPGA
TDI
TCK
TMS
Serial Connection
Silicon Explorer II
TDO
PRA
PRB
Figure 7 • Probe Setup
v3.0
7
e X F a m il y F P GA s
2. 5 V / 3. 3 V / 5. 0 V O p er a t i n g C on di t i on s
R ecom m en ded Oper at ing C ondi ti ons
Abs ol ut e M axim u m Ra ti ngs 1
Symbol
Parameter
Parameter
Limits
Units
VCCI
DC Supply Voltage
–0.3 to +6.0
V
VCCA
DC Supply Voltage
–0.3 to +3.0
V
VI
Input Voltage
–0.5 to +5.5
V
VO
Output Voltage
–0.5 to +VCCI + 0.5
V
TSTG
Storage Temperature
–65 to +150
°C
Note:
1. Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. Exposure
to absolute maximum rated conditions for extended periods
may affect device reliability. Devices should not be operated
outside the Recommended Operating Conditions.
Commercial
Industrial
Units
Temperature
Range1
0 to +70
–40 to +85
°C
2.5V Power Supply
Range (VCCA, VCCI)
2.3-2.7
2.3-2.7
V
3.3V Power Supply
Range (VCCI)
3.0-3.6
3.0-3.6
V
5.0V Power Supply
Range (VCCI)
4.75-5.25
4.5-5.5
V
Note:
1. Ambient temperature (TA).
T ypi cal eX S t andb y Cur r ent at 25° C
VCCA= 2.5V
VCCI = 2.5V
VCCA = 2.5V
VCCI = 3.3V
eX64
397µA
497µA
eX128
696µA
795µA
eX256
698µA
796µA
Product
2.5 V El ect r ical S pe cif i cat io ns
Commercial
Symbol
VOH
VOL
Parameter
Min.
Max.
Industrial
Min.
Max.
Units
VDD = MIN, VI = VIH or VIL
(IOH = -100µA) 2.1
2.1
V
VDD = MIN, VI = VIH or VIL
(IOH = -1 mA)
2.0
2.0
V
VDD = MIN, VI = VIH or VIL
(IOH = -2 mA)
1.7
1.7
V
VDD = MIN, VI = VIH or VIL
(IOL= 100µA)
0.2
0.2
V
VDD = MIN, VI = VIH or VIL
(IOL= 1mA)
0.4
0.4
V
VDD = MIN,VI = VIH or VIL
(IOL= 2 mA)
0.7
0.7
V
0.7
V
VIL
Input Low Voltage, VOUT ≤ VVOL(max)
-0.3
VIH
Input High Voltage, VOUT ≥ VVOH(min)
1.7 VDD + 0.3 1.7 VDD + 0.3
V
3-State Output Leakage Current, VOUT = VCCI or GND
–10
10
µA
IOZ
tR, tF
1,2
CIO
–10
Input Transition Time tR, tF
10
10
ns
I/O Capacitance
10
10
pF
Standby Current
1.0
3.0
mA
Curve5
Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html.
Notes:
1. tR is the transition time from 0.7 V to 1.7V.
2. tF is the transition time from 1.7V to 0.7V.
3. ICC max Commercial –F = 5.0mA
4. ICC=ICCI + ICCA
8
10
-0.3
3,4
ICC
IV
0.7
v3.0
e X F a m il y F P GA s
3.3 V El ect r ica l S pe cif i cat io ns
Commercial
Symbol
Parameter
Min.
VDD = MIN, VI = VIH or VIL
VOH
VOL
Max.
Industrial
Min.
Max.
Units
VDD = MIN, VI = VIH or VIL
(IOH = -1mA) 0.9 VCCI
(IOH = -8mA)
2.4
0.9 VCCI
V
2.4
V
VDD = MIN, VI = VIH or VIL
(IOL= 1mA)
0.1 VCCI
0.1 VCCI
V
VDD = MIN, VI = VIH or VIL
(IOL= 12mA)
0.4
0.4
V
0.8
0.8
V
VIL
Input Low Voltage
VIH
Input High Voltage
2.0
IIL/ IIH
Input Leakage Current, VIN = VCCI or GND
–10
10
–10
10
µA
IOZ
3-State Output Leakage Current, VOUT = VCCI or GND
–10
10
–10
10
µA
tR, tF
1,2
CIO
ICC
3,4
2.0
V
Input Transition Time tR, tF
10
10
ns
I/O Capacitance
10
10
pF
Standby Current
1.5
10
mA
IV Curve5 Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html.
Notes:
1. tR is the transition time from 0.8 V to 2.0V.
2. tF is the transition time from 2.0V to 0.8V.
3. ICC max Commercial –F=5.0mA
4. ICC=ICCI + ICCA
5.0V Electrical Specifications
Commercial
Symbol
VOH
VOL
Parameter
Min.
Max.
Industrial
Min.
Max.
Units
VDD = MIN, VI = VIH or VIL
(IOH = -1mA) 0.9 VCCI
VDD = MIN, VI = VIH or VIL
(IOH = -8mA)
VDD = MIN, VI = VIH or VIL
(IOL= 1mA)
0.1 VCCI
0.1 VCCI
V
VDD = MIN, VI = VIH or VIL
(IOL= 12mA)
0.4
0.4
V
0.8
V
2.4
0.9 VCCI
V
2.4
V
VIL
Input Low Voltage
VIH
Input High Voltage
2.0
IIL/ IIH
Input Leakage Current, VIN = VCCI or GND
–10
10
–10
10
µA
IOZ
3-State Output Leakage Current, VOUT = VCCI or GND
–10
10
–10
10
µA
tR, tF
1,2
0.8
2.0
V
Input Transition Time tR, tF
10
10
ns
CIO
I/O Capacitance
10
10
pF
ICC3,4
Standby Current
15
20
mA
IV
Curve5
Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html
Notes:
1. tR is the transition time from 0.8 V to 2.0V.
2. tF is the transition time from 2.0V to 0.8V.
3. ICC max Commercial –F=20mA
4. ICC=ICCI + ICCA
v3.0
9
e X F a m il y F P GA s
eX D yna m ic P ower C ons um pt io n – Hi gh F re quenc y
300
Power (mW)
250
200
eX64
150
eX128
100
eX256
50
0
50
100
150
200
Frequency (MHz)
Notes:
1. Device filled with 16-bit counters.
2. VCCA, VCCI = 2.7V, device tested at room temperature.
eX D yna m ic P ower C ons um pt io n – Low Fr eq uency
80
70
Power (mW)
60
50
eX64
40
eX128
30
eX256
20
10
0
0
10
20
30
Frequency (MHz)
Notes:
1. Device filled with 16-bit counters.
2. VCCA, VCCI = 2.7V, device tested at room temperature.
10
v3.0
40
50
e X F a m il y F P GA s
T ota l Dy nam ic P owe r ( m W )
180
Total Dynamic Power (mW)
160
140
120
32-bit Decoder
100
8 x 8-bit Counters
80
SDRAM Controller
60
40
20
0
0
25
50
75
100
125
150
175
200
Frequency (MHz)
S ys te m P owe r at 5% , 10 %, a nd 1 5% D ut y Cy cle
12,000
System Power (uW)
10,000
8,000
5% DC
6,000
10% DC
15% DC
4,000
2,000
0
0
10
20
30
40
50
60
Frequency (MHz)
v3.0
11
e X F a m il y F P GA s
Ju n ct i o n Te m p er a t u r e ( T J )
θja = Junction to ambient of package. θja numbers are
located in the Package Thermal Characteristics section
below.
The temperature variable in the Designer Series software
refers to the junction temperature, not the ambient
temperature. This is an important distinction because the
heat generated from dynamic power consumption is usually
hotter than the ambient temperature. Equation 1, shown
below, can be used to calculate junction temperature.
Junction Temperature = ∆T + Ta
P ac k ag e T h er m al C h ar a c t er i st i c s
The device junction to case thermal characteristic is θjc,
and the junction to ambient air characteristic is θja. The
thermal characteristics for θja are shown with two different
air flow rates.
(1)
Where:
Ta = Ambient Temperature
The maximum junction temperature is 150°C.
∆T = Temperature gradient between junction (silicon) and
ambient
A sample calculation of the absolute maximum power
dissipation allowed for a TQFP 100-pin package at
commercial temperature and still air is as follows:
∆T = θja * P
P = Power
Max. junction temp. (°C) – Max. ambient temp. (°C) 150°C – 70°C
Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------- = ----------------------------------- = 2.1W
θ ja (°C/W)
37.5°C/W
Package Type
Pin Count
θjc
θja
Still Air
θja
300 ft/min
Units
Thin Quad Flat Pack (TQFP)
64
14
51.2
35
°C/W
Thin Quad Flat Pack (TQFP)
100
12
37.5
30
°C/W
Chip Scale Package (CSP)
49
3
71.3
56.0
°C/W
Chip Scale Package (CSP)
128
3
54.1
47.8
°C/W
Chip Scale Package (CSP)
180
3
57.8
51
°C/W
12
v3.0
e X F a m il y F P GA s
eX T i m i n g M o de l *
Input Delays
I/O Module
t INYH = 0.7 ns
Internal Delays
Combinatorial
Cell
t IRD1 = 0.3 ns
t IRD2 = 0.4 ns
t PD = 0.7 ns
Predicted
Routing
Delays
Output Delays
I/O Module
t DHL = 2.6 ns
t RD1 = 0.3 ns
t RD4 = 0.7 ns
t RD8 = 1.2 ns
I/O Module
Register
Cell
t ENZL= 1.9 ns
t SUD = 0.5 ns
t HD = 0.0 ns
Routed
Clock
t RCKH = 1.3 ns
t RD1 = 0.3 ns
t DHL = 2.6 ns
I/O Module
Register
Cell
t ENZL= 1.9 ns
t IRD1 = 0.3 ns
t SUD = 0.5ns
t HD = 0.0 ns
Hard-Wired
Clock
Q
t RCO= 0.6 ns
(100% Load)
I/O Module
t INYH = 0.7 ns
D
t HCKH = 1.1 ns
D
Q
t RD1 = 0.3 ns
t DHL = 2.6 ns
t RCO= 0.6 ns
*Values shown for eX128–P, worst-case commercial conditions (5.0V, 35pF Pad Load).
H ar d-W i re d C loc k
Ro ute d C loc k
External Setup = tINYH + tIRD1 + tSUD – tHCKH
External Setup = tINYH + tIRD2 + tSUD – tRCKH
= 0.7 + 0.3 + 0.5 – 1.1 = 0.4 ns
= 0.7 + 0.4 + 0.5 – 1.3= 0.3 ns
Clock-to-Out (Pad-to-Pad), typical
Clock-to-Out (Pad-to-Pad), typical
= tHCKH + tRCO + tRD1 + tDHL
= tRCKH + tRCO + tRD1 + tDHL
= 1.1 + 0.6 + 0.3 + 2.6 = 4.6 ns
= 1.3+ 0.6 + 0.3 + 2.6 = 4.8 ns
v3.0
13
e X F a m il y F P GA s
O ut p u t B uf f e r D e l ay s
E
D
VCC
In
50%
Out
VOL
PAD To AC test loads (shown below)
TRIBUFF
VCC
50%
VOH
GND
En
1.5V
1.5V
50%
VCC
VCC
GND
50%
1.5V
Out
En
Out
GND
10%
VOL
tDLH
tENZL
tDHL
90%
1.5V
tENZH
tENLZ
GND
50%
VOH
50%
tENHZ
A C T e st L oa d s
Load 3
(Used to measure disable delays)
Load 2
(Used to measure enable delays)
Load 1
(Used to measure
propagation delay)
To the output
under test
VCC
35 pF
To the output
under test
VCC
GND
R to VCC for tPZL
R to GND for tPZH
R = 1 kΩ
GND
R to VCC for tPLZ
R to GND for tPHZ
R = 1 kΩ
To the output
under test
5 pF
35 pF
I n pu t B uf f er D e l ay s
PAD
INBUF
C- C e l l D el a ys
S
A
B
Y
Y
VCC
3V
In
Out
GND
1.5V 1.5V
VCC
50%
0V
S, A or B
50% 50%
VCC
Out
GND
50%
50%
tPD
50%
tPD
VCC
Out
50%
tPD
14
GND
v3.0
GND
tPD
50%
e X F a m il y F P GA s
C el l T i m i n g C h ar a c t er i st i c s
Fl ip- Flo ps
D
Q
PRESET
CLK
CLR
(Positive edge triggered)
tHD
D
tHP
tHPWH,
tRPWH
tSUD
CLK
tHPWL,
tRPWL
tRCO
Q
tCLR
tPRESET
CLR
tWASYN
PRESET
Ti m i ng C ha r a ct e r i s t i c s
Long T r acks
Timing characteristics for eX devices fall into three
categories: family-dependent, device-dependent, and
design-dependent. The input and output buffer
characteristics are common to all eX family members.
Internal routing delays are device-dependent. Design
dependency means actual delays are not determined until
after placement and routing of the user’s design are
complete. Delay values may then be determined by using
the Timer utility or performing simulation with post-layout
delays.
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows, columns,
or modules. Long tracks employ three to five antifuse
connections. This increases capacitance and resistance,
resulting in longer net delays for macros connected to long
tracks. Typically, no more than six percent of nets in a fully
utilized device require long tracks. Long tracks contribute
approximately 4 ns to 8.4 ns delay. This additional delay is
represented statistically in higher fanout routing delays.
Cr it ic al Net s and T ypi cal Ne ts
eX devices are manufactured with a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case processing.
Maximum timing parameters reflect minimum operating
voltage, maximum operating temperature, and worst-case
processing.
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most timing
critical paths. Critical nets are determined by net property
assignment prior to placement and routing. Up to
six percent of the nets in a design may be designated as
critical.
T im in g D er at ing
Te m p er a t u r e an d Vo l t a ge D er at i n g Fa ct or s
( N or m ali z ed to W or st - Cas e Com m er ci al, T J = 70 ° C, V C C A = 2.3 V)
Junction Temperature (TJ)
VCCA
–55
–40
0
25
70
85
125
2.3
0.75
0.79
0.88
0.89
1.00
1.04
1.16
2.5
0.70
0.74
0.82
0.83
0.93
0.97
1.08
2.7
0.66
0.69
0.79
0.79
0.88
0.92
1.02
v3.0
15
e X F a m il y F P GA s
eX F am i l y T i m i ng C ha r a ct er i s t i c s
( W or st -C as e C om m er cia l Cond it ion s, V C C A = 2.3 V , T J = 70 ° C )
‘–P’ Speed
Parameter
Description
C-Cell Propagation
tPD
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Delays1
Internal Array Module
0.7
1.0
1.4
ns
0.1
0.1
0.2
ns
2
Predicted Routing Delays
tDC
FO=1 Routing Delay, DirectConnect
tFC
FO=1 Routing Delay, FastConnect
0.3
0.5
0.7
ns
tRD1
FO=1 Routing Delay
0.3
0.5
0.7
ns
tRD2
FO=2 Routing Delay
0.4
0.6
0.8
ns
tRD3
FO=3 Routing Delay
0.5
0.8
1.1
ns
tRD4
FO=4 Routing Delay
0.7
1.0
1.3
ns
tRD8
FO=8 Routing Delay
1.2
1.7
2.4
ns
tRD12
FO=12 Routing Delay
1.7
2.5
3.5
ns
tRCO
Sequential Clock-to-Q
0.6
0.9
1.3
ns
tCLR
Asynchronous Clear-to-Q
0.6
0.8
1.2
ns
tPRESET
Asynchronous Preset-to-Q
1.3
ns
tSUD
Flip-Flop Data Input Set-Up
tHD
Flip-Flop Data Input Hold
0.0
0.0
0.0
ns
tWASYN
Asynchronous Pulse Width
1.3
1.9
2.6
ns
tRECASYN
Asynchronous Recovery Time
0.3
0.5
0.7
ns
tHASYN
Asynchronous Hold Time
0.3
0.5
0.7
ns
R-Cell Timing
0.7
0.5
0.9
0.7
1.0
ns
2.5V Input Module Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
0.6
0.9
1.3
ns
tINYL
Input Data Pad-to-Y LOW
0.8
1.1
1.5
ns
3.3V Input Module Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
0.7
1.0
1.4
ns
tINYL
Input Data Pad-to-Y LOW
0.9
1.3
1.8
ns
5.0V Input Module Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
0.7
1.0
1.4
ns
tINYL
Input Data Pad-to-Y LOW
0.9
1.3
1.8
ns
Input Module Predicted Routing Delays2
tIRD1
FO=1 Routing Delay
0.3
0.4
0.5
ns
tIRD2
FO=2 Routing Delay
0.4
0.6
0.8
ns
tIRD3
FO=3 Routing Delay
0.5
0.8
1.1
ns
tIRD4
FO=4 Routing Delay
0.7
1.0
1.3
ns
tIRD8
FO=8 Routing Delay
1.2
1.7
2.4
ns
tIRD12
FO=12 Routing Delay
1.7
2.5
3.5
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.
16
v3.0
e X F a m il y F P GA s
eX F am i l y T i m i ng C ha r a ct er i s t i c s (Continued)
( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 4 .75V , T J = 7 0°C )
‘–P’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Dedicated (Hard-Wired) Array Clock Networks
tHCKH
tHCKL
Input LOW to HIGH
(Pad to R-Cell Input)
1.1
1.6
2.3
ns
Input HIGH to LOW
(Pad to R-Cell Input)
1.1
1.6
2.3
ns
tHPWH
Minimum Pulse Width HIGH
1.4
2.0
2.8
ns
tHPWL
Minimum Pulse Width LOW
1.4
2.0
2.8
ns
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
<0.1
2.8
<0.1
4.0
<0.1
5.6
ns
ns
357
250
178
MHz
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) MAX.
1.1
1.6
2.2
ns
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) MAX.
1.0
1.4
2.0
ns
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) MAX.
1.2
1.7
2.4
ns
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) MAX.
1.2
1.7
2.4
ns
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) MAX.
1.3
1.9
2.6
ns
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) MAX.
1.3
1.9
2.6
ns
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
tRPWH
Min. Pulse Width HIGH
1.5
2.1
3.0
ns
tRPWL
Min. Pulse Width LOW
1.5
2.1
3.0
ns
tRCKSW1
Maximum Skew (Light Load)
0.2
0.3
0.4
ns
tRCKSW1
Maximum Skew (50% Load)
0.1
0.2
0.3
ns
tRCKSW1
Maximum Skew (100% Load)
0.1
0.1
0.2
ns
Note:
1. Clock skew improves as the clock network becomes more heavily loaded.
v3.0
17
e X F a m il y F P GA s
eX F am i l y T i m i ng C ha r a ct er i s t i c s (Continued)
( W or st -C as e C om m er cia l Cond it ion s V C C A = 2. 3V , V C C I = 2. 3V or 3 .0V , T J = 70 °C )
‘–P’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Dedicated (Hard-Wired) Array Clock Networks
tHCKH
tHCKL
Input LOW to HIGH
(Pad to R-Cell Input)
1.1
1.6
2.3
Input HIGH to LOW
(Pad to R-Cell Input)
1.1
1.6
2.3
ns
ns
tHPWH
Minimum Pulse Width HIGH
1.4
2.0
2.8
ns
tHPWL
Minimum Pulse Width LOW
1.4
2.0
2.8
ns
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
<0.1
2.8
<0.1
4.0
<0.1
5.6
ns
ns
357
250
178
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) MAX.
1.0
1.4
2.0
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) MAX.
1.0
1.4
2.0
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) MAX.
1.2
1.7
2.4
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) MAX.
1.2
1.7
2.4
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) MAX.
1.4
2.0
2.8
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) MAX.
1.4
2.0
2.8
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
tRPWH
tRPWL
ns
ns
ns
ns
ns
ns
Min. Pulse Width HIGH
1.4
2.0
2.8
ns
Min. Pulse Width LOW
1.4
2.0
2.8
ns
tRCKSW
1
Maximum Skew (Light Load)
0.2
0.3
0.4
ns
tRCKSW
1
Maximum Skew (50% Load)
0.2
0.2
0.3
ns
tRCKSW
1
Maximum Skew (100% Load)
0.1
0.1
0.2
ns
Note:
1. Clock skew improves as the clock network becomes more heavily loaded.
18
v3.0
e X F a m il y F P GA s
eX F am i l y T i m i ng C ha r a ct er i s t i c s (Continued)
(Worst-Case Commercial Conditions V CCA = 2.3V, T J = 70°C)
‘–P’ Speed
Parameter
Description
2.5V LVTTL Output Module
Min.
Timing1 (VCCI =
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
2.3V)
tDLH
Data-to-Pad LOW to HIGH
3.3
4.7
6.6
ns
tDHL
Data-to-Pad HIGH to LOW
3.5
5.0
7.0
ns
tDHLS
Data-to-Pad HIGH to LOW—Low Slew
11.6
16.6
23.2
ns
tENZL
Enable-to-Pad, Z to L
2.5
3.6
5.1
ns
tENZLS
Enable-to-Pad Z to L—Low Slew
11.8
16.9
23.7
ns
tENZH
Enable-to-Pad, Z to H
3.4
4.9
6.9
ns
tENLZ
Enable-to-Pad, L to Z
2.1
3.0
4.2
ns
tENHZ
Enable-to-Pad, H to Z
2.4
5.67
7.94
ns
dTLH
Delta Delay vs. Load LOW to HIGH
0.034
0.046
0.066
ns/pF
dTHL
Delta Delay vs. Load HIGH to LOW
0.016
0.022
0.05
ns/pF
dTHLS
Delta Delay vs. Load HIGH to LOW—Low
Slew
0.05
0.072
0.1
ns/pF
3.3V LVTTL Output Module Timing1 (VCCI = 3.0V)
tDLH
Data-to-Pad LOW to HIGH
2.8
4.0
5.6
ns
tDHL
Data-to-Pad HIGH to LOW
2.7
3.9
5.4
ns
tDHLS
Data-to-Pad HIGH to LOW—Low Slew
9.7
13.9
19.5
ns
tENZL
Enable-to-Pad, Z to L
2.2
3.2
4.4
ns
tENZLS
Enable-to-Pad Z to L—Low Slew
9.7
13.9
19.6
ns
tENZH
Enable-to-Pad, Z to H
2.8
4.0
5.6
ns
tENLZ
Enable-to-Pad, L to Z
2.8
4.0
5.6
ns
tENHZ
Enable-to-Pad, H to Z
2.6
3.8
5.3
ns
dTLH
Delta Delay vs. Load LOW to HIGH
0.02
0.03
0.046
ns/pF
dTHL
Delta Delay vs. Load HIGH to LOW
0.016
0.022
0.05
ns/pF
dTHLS
Delta Delay vs. Load HIGH to LOW—Low
Slew
0.05
0.072
0.1
ns/pF
5.0V TTL Output Module Timing1 (VCCI = 4.75V)
tDLH
Data-to-Pad LOW to HIGH
2.0
2.9
4.0
ns
tDHL
Data-to-Pad HIGH to LOW
2.6
3.7
5.2
ns
tDHLS
Data-to-Pad HIGH to LOW—Low Slew
6.8
9.7
13.6
ns
tENZL
Enable-to-Pad, Z to L
1.9
2.7
3.8
ns
tENZLS
Enable-to-Pad Z to L—Low Slew
6.8
9.8
13.7
ns
tENZH
Enable-to-Pad, Z to H
2.1
3.0
4.1
ns
tENLZ
Enable-to-Pad, L to Z
Note:
1. Delays based on 35 pF loading.
3.3
4.8
6.6
ns
v3.0
19
e X F a m il y F P GA s
Pi n D es c r i pt i on
CLKA/B
Clock A and B
TCK, I/O
Test Clock
These pins are clock inputs for clock distribution networks.
Input levels are compatible with standard TTL or LVTTL
specifications. The clock input is buffered prior to clocking
the R-cells. If not used, this pin must be set LOW or HIGH on
the board. It must not be left floating.
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active when
the TMS pin is set LOW (refer to Table 3 on page 6). This pin
functions as an I/O when the boundary scan state machine
reaches the “logic reset” state.
GND
TDI, I/O
Ground
LOW supply voltage.
HCLK
Dedicated (Hard-wired)
Array Clock
This pin is the clock input for sequential modules. Input
levels are compatible with standard TTL or LVTTL
specifications. This input is directly wired to each R-cell and
offers clock speeds independent of the number of R-cells
being driven. If not used, this pin must be set LOW or HIGH
on the board. It must not be left floating.
I/O
Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations, input
and output levels are compatible with standard TTL or
LVTTL specifications. Unused I/O pins are automatically
tristated by the Designer Series software.
LP
Low Power Pin
Controls the low power mode of the eX devices. The device
is placed in the low power mode by connecting the LP pin
to logic high. In low power mode, all I/Os are tristated, all
input buffers are turned OFF, and the core of the devices is
turned OFF. To exit the low power mode, the LP pin must
be set LOW. The device enters the low power mode 800ns
after the LP pin is driven to a logic HIGH. It will resume
normal operation in 200µs after the LP pin is driven to a
logic low. The logic high level on the LP pin must never
exceed the VSV voltage. Refer to the VSV pin description.
NC
No Connection
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
PRA, I/O
PRB, I/O
Probe A/B
The Probe pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the other probe pin to
allow real-time diagnostic output of any signal path within
the device. The Probe pin can be used as a user-defined I/O
when verification has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality.
20
Test Data Input
Serial input for boundary scan testing and diagnostic probe.
In flexible mode, TDI is active when the TMS pin is set LOW
(refer to Table 3 on page 6). This pin functions as an I/O
when the boundary scan state machine reaches the “logic
reset” state.
TDO, I/O
Test Data Output
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer to Table 3
on page 6). This pin functions as an I/O when the boundary
scan state machine reaches the "logic reset" state. When
Silicon Explorer is being used, TDO will act as an output
when the "checksum" command is run. It will return to user
IO when "checksum" is complete.
TMS
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1 Boundary
Scan pins (TCK, TDI, TDO, TRST). In flexible mode when
the TMS pin is set LOW, the TCK, TDI, and TDO pins are
boundary scan pins (refer to Table 3 on page 6). Once the
boundary scan pins are in test mode, they will remain in that
mode until the internal boundary scan state machine
reaches the “logic reset” state. At this point, the boundary
scan pins will be released and will function as regular I/O
pins. The “logic reset” state is reached 5 TCK cycles after
the TMS pin is set HIGH. In dedicated test mode, TMS
functions as specified in the IEEE 1149.1 specifications.
TRST, I/O
Boundary Scan Reset Pin
Once it is configured as the JTAG Reset pin, the TRST pin
functions as an active-low input to asynchronously initialize
or reset the boundary scan circuit. The TRST pin is equipped
with an internal pull-up resistor. This pin functions as an I/O
when the “Reserve JTAG Reset Pin” is not selected in
Designer.
V C CI
Supply Voltage
Supply voltage for I/Os. See Table 2 on page 6.
V C CA
Supply Voltage
Supply voltage for Array. See Table 2 on page 6.
VSV
Programming Voltage
Supply voltage used for device programming. This pin can be
tied to VCCA or VCCI but cannot exceed 3.6V. If the security
fuse is programmed, the VSV limit is extended to 6.0V.
v3.0
e X F a m il y F P GA s
Pa c ka ge P i n A s si g nm e n t s
64- Pi n TQ F P (T op Vi ew)
64
1
64-Pin
TQFP
v3.0
21
e X F a m il y F P GA s
64- Pi n TQ F P
1.
22
Pin Number
eX64
Function
eX128
Function
Pin Number
eX64
Function
eX128
Function
1
GND
GND
33
GND
GND
2
TDI, I/O
TDI, I/O
34
I/O
I/O
3
I/O
I/O
35
I/O
I/O
VSV1
4
TMS
TMS
36
VSV1
5
GND
GND
37
VCCI
VCCI
6
VCCI
VCCI
38
I/O
I/O
7
I/O
I/O
39
I/O
I/O
8
I/O
I/O
40
NC
I/O
9
NC
I/O
41
NC
I/O
10
NC
I/O
42
I/O
I/O
11
TRST, I/O
TRST, I/O
43
I/O
I/O
12
I/O
I/O
44
VCCA
VCCA
13
NC
I/O
45
GND/LP1
GND/ LP1
14
GND
GND
46
GND
GND
15
I/O
I/O
47
I/O
I/O
16
I/O
I/O
48
I/O
I/O
17
I/O
I/O
49
I/O
I/O
18
I/O
I/O
50
I/O
I/O
19
VCCI
VCCI
51
I/O
I/O
20
I/O
I/O
52
VCCI
VCCI
21
PRB, I/O
PRB, I/O
53
I/O
I/O
22
VCCA
VCCA
54
I/O
I/O
23
GND
GND
55
CLKA
CLKA
24
I/O
I/O
56
CLKB
CLKB
25
HCLK
HCLK
57
VCCA
VCCA
26
I/O
I/O
58
GND
GND
27
I/O
I/O
59
PRA, I/O
PRA, I/O
28
I/O
I/O
60
I/O
I/O
29
I/O
I/O
61
VCCI
VCCI
30
I/O
I/O
62
I/O
I/O
31
I/O
I/O
63
I/O
I/O
64
TCK, I/O
TCK, I/O
32
TDO, I/O
TDO, I/O
Please read the VSV and LP pin descriptions for restrictions on their use.
v3.0
e X F a m il y F P GA s
Pa c ka ge P i n A s si g nm e n t s (Continued)
1 0 0 -P in T QF P ( To p V ie w )
100
1
100-Pin
TQFP
v3.0
23
e X F a m il y F P GA s
100- T Q FP
Pin Number
1.
24
eX64
Function
eX128
Function
eX256
Function
Pin Number
eX64
Function
eX128
Function
eX256
Function
1
GND
GND
GND
51
GND
GND
GND
2
3
TDI, I/O
NC
TDI, I/O
NC
TDI, I/O
I/O
52
53
NC
NC
NC
NC
I/O
I/O
4
NC
NC
I/O
54
NC
NC
I/O
5
6
NC
I/O
NC
I/O
I/O
I/O
55
56
I/O
I/O
I/O
I/O
I/O
I/O
7
TMS
TMS
TMS
57
VSV1
VSV1
VSV1
8
9
VCCI
GND
VCCI
GND
VCCI
GND
58
59
VCCI
NC
VCCI
I/O
VCCI
I/O
10
NC
I/O
I/O
60
I/O
I/O
I/O
11
12
NC
I/O
I/O
I/O
I/O
I/O
61
62
NC
I/O
I/O
I/O
I/O
I/O
13
NC
I/O
I/O
63
NC
I/O
I/O
14
15
I/O
NC
I/O
I/O
I/O
I/O
64
65
I/O
NC
I/O
I/O
I/O
I/O
16
TRST, I/O
TRST, I/O
TRST, I/O
66
I/O
I/O
I/O
17
NC
I/O
I/O
67
VCCA
18
I/O
I/O
I/O
68
GND/LP1
VCCA
GND/LP1
VCCA
GND/LP1
19
NC
I/O
I/O
69
GND
GND
GND
20
VCCI
21
I/O
VCCI
I/O
VCCI
I/O
70
71
I/O
I/O
I/O
I/O
I/O
I/O
22
NC
I/O
I/O
72
NC
I/O
I/O
23
24
NC
NC
NC
NC
I/O
I/O
73
74
NC
NC
NC
NC
I/O
I/O
25
I/O
I/O
I/O
75
NC
NC
I/O
26
I/O
I/O
I/O
76
NC
I/O
I/O
27
I/O
I/O
I/O
77
I/O
I/O
I/O
28
I/O
I/O
I/O
78
I/O
I/O
I/O
29
30
I/O
I/O
I/O
I/O
I/O
I/O
79
80
I/O
I/O
I/O
I/O
I/O
I/O
31
I/O
I/O
I/O
81
I/O
I/O
I/O
32
I/O
I/O
I/O
82
VCCI
VCCI
VCCI
33
34
I/O
PRB, I/O
I/O
PRB, I/O
I/O
PRB, I/O
83
84
I/O
I/O
I/O
I/O
I/O
I/O
I/O
35
VCCA
VCCA
VCCA
85
I/O
I/O
36
GND
GND
GND
86
I/O
I/O
I/O
37
NC
NC
NC
87
CLKA
CLKB
CLKA
38
I/O
I/O
I/O
88
CLKA
CLKB
39
HCLK
HCLK
HCLK
89
NC
NC
NC
40
I/O
I/O
I/O
90
VCCA
VCCA
VCCA
GND
GND
GND
PRA, I/O
CLKB
41
I/O
I/O
I/O
91
42
I/O
I/O
I/O
92
PRA, I/O
PRA, I/O
43
I/O
I/O
I/O
93
I/O
I/O
I/O
44
VCCI
VCCI
VCCI
94
I/O
I/O
I/O
45
I/O
I/O
I/O
95
I/O
I/O
I/O
46
I/O
I/O
I/O
96
I/O
I/O
I/O
47
I/O
I/O
I/O
97
I/O
I/O
I/O
98
I/O
I/O
I/O
I/O
I/O
48
49
50
TDO, I/O
NC
TDO, I/O
I/O
TDO, I/O
I/O
99
100
I/O
I/O
TCK, I/O
TCK, I/O
I/O
TCK, I/O
Please read the VSV and LP pin descriptions for restrictions on their use.
v3.0
I/O
e X F a m il y F P GA s
Pa c ka ge P i n A s si g nm e n t s (Continued)
49- Pi n CS P
( T op V ie w)
A1 Ball Pad Corner
1
2
3
4
5
6
7
A
B
C
D
E
F
G
49- Pi n CS P
1.
Pin Number
eX64
Function
eX128
Function
Pin Number
eX64
Function
eX128
Function
A1
I/O
I/O
D5
VSV1
VSV1
A2
I/O
I/O
D6
I/O
I/O
A3
I/O
I/O
D7
I/O
I/O
A4
I/O
I/O
E1
I/O
I/O
A5
VCCA
VCCA
E2
TRST, I/O
TRST, I/O
A6
I/O
I/O
E3
VCCI
VCCI
A7
I/O
I/O
E4
GND
GND
B1
TCK, I/O
TCK, I/O
E5
I/O
I/O
B2
I/O
I/O
E6
I/O
I/O
B3
I/O
I/O
E7
VCCI
VCCI
B4
PRA, I/O
PRA, I/O
F1
I/O
I/O
B5
CLKA
CLKA
F2
I/O
I/O
B6
I/O
I/O
F3
I/O
I/O
B7
GND/LP1
GND/LP1
F4
I/O
I/O
C1
I/O
I/O
F5
HCLK
HCLK
C2
TDI, I/O
TDI, I/O
F6
I/O
I/O
C3
VCCI
VCCI
F7
TDO, I/O
TDO, I/O
C4
GND
GND
G1
I/O
I/O
C5
CLKB
CLKB
G2
I/O
I/O
C6
VCCA
VCCA
G3
I/O
I/O
C7
I/O
I/O
G4
PRB, I/O
PRB, I/O
D1
I/O
I/O
G5
VCCA
VCCA
D2
TMS
TMS
G6
I/O
I/O
D3
GND
GND
G7
I/O
I/O
D4
GND
GND
Please read the VSV and LP pin descriptions for restrictions on their use.
v3.0
25
e X F a m il y F P GA s
Pa c ka ge P i n A s si g nm e n t s (Continued)
128- P in CS P
( T op Vie w)
A1 Ball Pad Corner
1
2
3
4
A
B
C
D
E
F
G
H
J
K
L
M
26
v3.0
5
6
7
8
9
10
11
12
e X F a m il y F P GA s
128- CS P
Pin Number
eX64
Function
eX128
Function
eX256
Function
Pin Number
eX64
Function
eX128
Function
eX256
Function
A1
I/O
I/O
I/O
D4
I/O
I/O
I/O
A2
TCK, I/O
TCK, I/O
TCK, I/O
D5
I/O
I/O
I/O
A3
VCCI
VCCI
VCCI
D6
GND
GND
GND
A4
I/O
I/O
I/O
D7
I/O
I/O
I/O
A5
I/O
I/O
I/O
D8
GND
GND
GND
A6
VCCA
VCCA
VCCA
D9
I/O
I/O
I/O
A7
I/O
I/O
I/O
D10
I/O
I/O
I/O
A8
I/O
I/O
I/O
D11
I/O
I/O
I/O
A9
VCCI
VCCI
VCCI
D12
VCCI
VCCI
VCCI
A10
I/O
I/O
I/O
E1
NC
I/O
I/O
A11
I/O
I/O
I/O
E2
VCCI
VCCI
VCCI
A12
I/O
I/O
I/O
E3
I/O
I/O
I/O
B1
TMS
TMS
TMS
E4
GND
GND
GND
B2
I/O
I/O
I/O
E9
GND
GND
GND
B3
I/O
I/O
I/O
E10
I/O
I/O
I/O
GND/LP1
GND/LP1
B4
I/O
I/O
I/O
E11
GND/LP1
B5
I/O
I/O
I/O
E12
VCCA
VCCA
VCCA
B6
PRA, I/O
PRA, I/O
PRA, I/O
F1
NC
I/O
I/O
B7
CLKB
CLKB
CLKB
F2
NC
I/O
I/O
B8
I/O
I/O
I/O
F3
NC
I/O
I/O
B9
I/O
I/O
I/O
F4
I/O
I/O
I/O
B10
I/O
I/O
I/O
F9
GND
GND
GND
B11
GND
GND
GND
F10
NC
I/O
I/O
B12
I/O
I/O
I/O
F11
I/O
I/O
I/O
C1
I/O
I/O
I/O
F12
I/O
I/O
I/O
C2
TDI, I/O
TDI, I/O
TDI, I/O
G1
NC
I/O
I/O
C3
I/O
I/O
I/O
G2
TRST, I/O
TRST, I/O
TRST, I/O
C4
I/O
I/O
I/O
G3
I/O
I/O
I/O
C5
I/O
I/O
I/O
G4
GND
GND
GND
C6
CLKA
CLKA
CLKA
G9
GND
GND
GND
C7
I/O
I/O
I/O
G10
NC
I/O
I/O
C8
I/O
I/O
I/O
G11
I/O
I/O
I/O
C9
I/O
I/O
I/O
G12
NC
I/O
I/O
C10
NC
I/O
I/O
H1
GND
GND
GND
C11
NC
I/O
I/O
H2
I/O
I/O
I/O
C12
I/O
I/O
I/O
H3
VCCI
VCCI
VCCI
D1
NC
I/O
I/O
H4
GND
GND
GND
D2
I/O
I/O
I/O
H9
I/O
I/O
I/O
D3
I/O
I/O
I/O
H10
VCCI
VCCI
VCCI
v3.0
27
e X F a m il y F P GA s
128- CS P
Pin Number
eX64
Function
eX128
Function
eX256
Function
Pin Number
eX64
Function
eX128
Function
eX256
Function
H11
VSV1
VSV1
VSV1
K12
I/O
I/O
I/O
H12
NC
I/O
I/O
L1
I/O
I/O
I/O
L2
I/O
I/O
I/O
1.
28
1
J1
NC
NC
VSV
J2
I/O
I/O
I/O
L3
NC
I/O
I/O
J3
VCCI
VCCI
VCCI
L4
I/O
I/O
I/O
J4
I/O
I/O
I/O
L5
I/O
I/O
I/O
J5
I/O
I/O
I/O
L6
I/O
I/O
I/O
J6
I/O
I/O
I/O
L7
I/O
I/O
I/O
J7
GND
GND
GND
L8
I/O
I/O
I/O
J8
I/O
I/O
I/O
L9
I/O
I/O
I/O
J9
GND
GND
GND
L10
I/O
I/O
I/O
J10
I/O
I/O
I/O
L11
NC
I/O
I/O
J11
I/O
I/O
I/O
L12
VCCI
VCCI
VCCI
J12
NC
I/O
I/O
M1
GND
GND
GND
K1
NC
I/O
I/O
M2
I/O
I/O
I/O
K2
I/O
I/O
I/O
M3
I/O
I/O
I/O
K3
I/O
I/O
I/O
M4
I/O
I/O
I/O
K4
I/O
I/O
I/O
M5
I/O
I/O
I/O
K5
I/O
I/O
I/O
M6
I/O
I/O
I/O
K6
PRB, I/O
PRB, I/O
PRB, I/O
M7
VCCA
VCCA
VCCA
K7
HCLK
HCLK
HCLK
M8
I/O
I/O
I/O
K8
I/O
I/O
I/O
M9
I/O
I/O
I/O
K9
I/O
I/O
I/O
M10
I/O
I/O
I/O
K10
I/O
I/O
I/O
M11
I/O
I/O
I/O
K11
TDO, I/O
TDO, I/O
TDO, I/O
M12
I/O
I/O
I/O
Please read the VSV and LP pin descriptions for restrictions on their use.
v3.0
e X F a m il y F P GA s
Pa c ka ge P i n A s si g nm e n t s (Continued)
180- P in CS P
( T op Vi ew)
A1 Ball Pad Corner
1
2
3
4
5
6
7
8
9 10
11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
v3.0
29
e X F a m il y F P GA s
180- P in CS P
Pin Number
1.
30
eX256
Function
Pin Number
eX256
Function
Pin Number
A1
I/O
D6
I/O
A2
I/O
D7
CLKA
A3
GND
D8
I/O
A4
NC
D9
I/O
A5
NC
D10
I/O
A6
NC
D11
I/O
A7
NC
D12
I/O
A8
NC
D13
I/O
A9
NC
D14
I/O
A10
NC
E1
I/O
A11
NC
E2
I/O
A12
I/O
E3
I/O
A13
I/O
E4
I/O
A14
I/O
E5
I/O
B1
I/O
E6
I/O
B2
I/O
E7
GND
B3
TCK, I/O
E8
I/O
B4
VCCI
E9
GND
B5
I/O
E10
I/O
B6
I/O
E11
I/O
B7
VCCA
E12
I/O
B8
I/O
E13
VCCI
B9
I/O
E14
I/O
B10
VCCI
F1
I/O
B11
I/O
F2
I/O
B12
I/O
F3
VCCI
B13
I/O
F4
I/O
B14
I/O
F5
GND
C1
I/O
F10
GND
C2
TMS
F11
I/O
C3
I/O
F12
GND/LP1
C4
I/O
F13
VCCA
C5
I/O
F14
I/O
C6
I/O
G1
VCCA
C7
PRA, I/O
G2
I/O
C8
CLKB
G3
I/O
C9
I/O
G4
I/O
C10
I/O
G5
I/O
C11
I/O
G10
GND
C12
GND
G11
I/O
C13
I/O
G12
I/O
C14
I/O
G13
I/O
D1
I/O
G14
VCCA
D2
I/O
H1
I/O
D3
TDI, I/O
H2
I/O
D4
I/O
H3
TRST, I/O
D5
I/O
H4
I/O
Please read the VSV and LP pin descriptions for restrictions on their use.
v3.0
H5
H10
H11
H12
H13
H14
J1
J2
J3
J4
J5
J10
J11
J12
J13
J14
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
M1
M2
M3
eX256
Function
GND
GND
I/O
I/O
I/O
I/O
I/O
GND
I/O
VCCI
GND
I/O
VCCI
VSV1
I/O
I/O
I/O
VSV1
I/O
VCCI
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
HCLK
I/O
I/O
I/O
TDO, I/O
I/O
I/O
I/O
I/O
I/O
Pin Number
eX256
Function
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
NC
NC
NC
NC
NC
GND
I/O
I/O
e X F a m il y F P GA s
Li s t o f C ha ng e s
The following table lists critical changes that were made in the current version of the document.
Previous version
v2.0.1
Advanced v0.4
Advanced v0.3
Changes in current version (v3.0)
Page
The “Recommended Operating Conditions” on page 8 has been changed.
page 8
The “3.3V Electrical Specifications” on page 9 has been updated.
page 9
The “5.0V Electrical Specifications” on page 9 has been updated.
page 9
The “Total Dynamic Power (mW)” on page 11 is new.
page 11
The System Power at 5%, 10%, and 15% Duty Cycle is new.
page 11
The “eX Timing Model*” on page 13 has been updated.
page 13
The I/O Features table, Table 1 on page 5, was updated.
page 5
The table, “2.5V LP/Sleep Mode Specifications Typical Conditions, VCCA, VCCI =
2.5V, TJ = 25° C” on page 6, was updated.
page 6
“Typical eX Standby Current at 25°C” on page 8 is a new table.
page 8
The table in the section, “Package Thermal Characteristics” on page 12 has been
updated for the 49-Pin CSP.
page 11
The “eX Timing Model*” on page 13 has been updated.
page 12
The timing numbers found in, “eX Family Timing Characteristics” on page 16 have
been updated.
pages 15-18
The VSV pin has been added to the “Pin Description” on page 20.
page 18
Please see the following pin tables for the VSV pin and an important footnote
including the pin: “64-Pin TQFP” on page 22,“100-TQFP” on page 24,“49-Pin CSP”
on page 25,“128-CSP” on page 27, and “180-Pin CSP” on page 30.
pages- 21, 23, 24,
26, 27, 29
The figure, “100-Pin TQFP (Top View)” on page 23 has been updated.
page 22
In the Product Profile table, the Maximum User I/Os for eX64 was changed to 84.
page 1
In the Product Profile table, the Maximum User I/Os for eX128 was changed to 100. page 1
The Mechanical Drawings section has been removed from the data sheet. The
mechanical drawings are now contained in a separate document, “Package
Characteristics and Mechanical Drawings,” available on the Actel web site.
Advanced v0.2
Advanced v.1
A new section describing Clock Resources has been added.
page 5
A new table describing I/O Features has been added.
page 6
The Pin Description section has been updated and clarified.
page 21
The original Electrical Specifications table was separated into two tables (2.5V and
3.3/5.0V). In both tables, several different currents are specified for VOH and VOL.
Page 8 and 9
A new table listing 2.5V low power specifications and associated power graphs were
page 9
added.
Pin functions for eX256 TQ100 have been added to the 100-TQFP table.
page 25
A CS49 pin drawing and pin assignment table including eX64 and eX128 pin
functions have been added.
page 26
A CS128 pin drawing and pin assignment table including eX64, eX128, and eX256
pin functions have been added.
pages 26-27
A CS180 pin drawing and pin assignment table for eX256 pin functions have been
added.
pages 27, 31
The following table note was added to the eX Timing Characteristics table for
clarification: Clock skew improves as the clock network becomes more heavily
loaded.
pages 14-15
v3.0
31
e X F a m il y F P GA s
D at a S he et Ca t e g o r i e s
In order to provide the latest information to designers, some data sheets are published before data has been fully
characterized. Product Briefs are modified versions of data sheets. Data sheets are marked as “Advanced,” “Preliminary,” and
“Web-only.” The definition of these categories are as follows:
P rod uct B ri ef
The product brief is a modified version of an Advanced data sheet containing general product information. This brief
summarizes specific device and family information for non-release products.
Adv anc ed
The data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. This
information can be used as estimates, but not for production.
P rel im i nar y
The data sheet contains information based on simulation and/or initial characterization. The information is believed to be
correct, but changes are possible.
Unm ar ked (pr odu ct ion)
The data sheet contains information that is considered to be final.
W eb- only V er si ons
Web-only versions have three numbers in the version number (example: v2.0.1). A web-only version means Actel is posting
the data sheet so customers have the latest information, but we are not printing the version because some information is
going to change shortly after posting.
32
v3.0
e X F a m il y F P GA s
v3.0
33
e X F a m il y F P GA s
34
v3.0
e X F a m il y F P GA s
v3.0
35
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Europe Ltd.
Maxfli Court, Riverside Way
Camberley, Surrey GU15 3YL
United Kingdom
Tel: +44 (0)1276 401450
Fax: +44 (0)1276 401490
Actel Corporation
955 East Arques Avenue
Sunnyvale, California 94086
USA
Tel: (408) 739-1010
Fax: (408) 739-1540
Actel Asia-Pacific
EXOS Ebisu Bldg. 4F
1-24-14 Ebisu Shibuya-ku
Tokyo 150 Japan
Tel: +81 03-3445-7671
Fax: +81 03-3445-7668
5172154-4/12.01