Cypress CY7C4255V 8 k/16 k/32 k/64 k x 18 low voltage deep sync fifo Datasheet

CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
8 K/16 K/32 K/64 K × 18 Low Voltage
Deep Sync FIFOs
32 K/64 K × 18 Low Voltage Deep Sync FIFOs
Features
Functional Description
■
3.3 V operation for low power consumption and easy integration
into low voltage systems
■
High speed, low power, first-in first-out (FIFO) memories
■
8 K × 18 (CY7C4255V)
■
16 K × 18 (CY7C4265V)
■
32 K × 18 (CY7C4275V)
■
64 K × 18 (CY7C4285V)
■
0.35 micron CMOS for optimum speed and power
■
High speed 100 MHz operation (10 ns read/write cycle times)
■
Low power
❐ ICC = 30 mA
❐ ISB = 4 mA
■
Fully asynchronous and simultaneous read and write operation
■
Empty, Full, Half Full, and programmable Almost Empty and
Almost Full status flags
■
Retransmit function
■
Output Enable (OE) pin
■
Independent read and write enable pins
■
Supports free running 50% duty cycle clock inputs
■
Width Expansion Capability
■
Depth Expansion Capability
■
64-pin 10×10 STQFP
■
Pin compatible density upgrade to CY7C42X5V-ASC families
■
Pin compatible 3.3 V solutions for CY7C4255/65/75/85V
The CY7C4255/65/75/85V are high speed, low power, first-in
first-out (FIFO) memories with clocked read and write interfaces.
All are 18 bits wide and are pin and functionally compatible to the
CY7C42X5V
Synchronous
FIFO
family.
The
CY7C4255/65/75/85V can be cascaded to increase FIFO depth.
Programmable features include Almost Full/Almost Empty flags.
These FIFOs provide solutions for a wide variety of data
buffering needs, including high speed data acquisition,
multiprocessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and a write enable
pin (WEN).
When WEN is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is
continually written into the FIFO on each cycle. The output port
is controlled in a similar manner by a free-running read clock
(RCLK) and a read enable pin (REN). In addition, the
CY7C4255/65/75/85V have an output enable pin (OE). The read
and write clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read or write applications. Clock frequencies up to 67 MHz are
achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI, RXI),
cascade output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of
the next device, and the WXO and RXO pins of the last device
must be connected to the WXI and RXI pins of the first device.
The FL pin of the first device is tied to VSS and the FL pin of all
the remaining devices must be tied to VCC .
Selection Guide
Parameter
7C4255/65/75/85V-10
7C4255/65/75/85V-15
Maximum Frequency (MHz)
100
66.7
Maximum Access Time (ns)
8
10
Minimum Cycle Time (ns)
10
15
Minimum Data or Enable Setup (ns)
3.5
4
Minimum Data or Enable Hold (ns)
0
0
Maximum Flag Delay (ns)
8
10
30
30
Active Power Supply Current (ICC1) (mA)
Commercial
Industrial
Cypress Semiconductor Corporation
Document Number: 38-06012 Rev. *D
•
198 Champion Court
35
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 31, 2010
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CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
Parameter
CY7C4255V
CY7C4265V
CY7C4275V
CY7C4285V
Density
8 K × 18
16 K × 18
32 K × 18
64 K × 18
Package
64-pin 10×10 TQFP
64-pin 10×10 TQFP
64-pin 10×10 TQFP
64-pin 10×10 TQFP
Logic Block Diagram
D0 – 17
INPUT
REGISTER
WCLK
WEN
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
High
Density
Dual-Port
RAM Array
WRITE
POINTER
RS
FL/RT
WXI
WXO/HF
RXI
RXO
Document Number: 38-06012 Rev. *D
FLAG
LOGIC
8Kx9
16Kx9
32Kx9
64Kx9
FF
EF
PAE
PAF
SMODE
READ
POINTER
RESET
LOGIC
EXPANSION
LOGIC
THREE-ST ATE
OUTPUT REGISTER
Q0 – 17
READ
CONTROL
OE
RCLK
REN
4275V–1
Page 2 of 24
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CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
Contents
Pinouts .............................................................................. 4
Functional Description ..................................................... 6
Architecture ...................................................................... 6
Resetting the FIFO ............................................................ 6
FIFO Operation ................................................................. 6
Programming .................................................................... 6
Flag Operation .................................................................. 6
Full Flag ....................................................................... 6
Empty Flag .................................................................. 6
Programmable Almost Empty/Almost Full Flag ........... 7
Retransmit ......................................................................... 7
Width Expansion Configuration ...................................... 7
Depth Expansion Configuration
(with Programmable Flags) ............................................. 8
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Document Number: 38-06012 Rev. *D
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 10
Switching Characteristics .............................................. 12
Switching Waveforms .................................................... 13
Ordering Information ...................................................... 21
Ordering Code Definitions ......................................... 21
Package Diagram ............................................................ 22
Acronyms ........................................................................ 23
Document Conventions ................................................. 23
Units of Measure ....................................................... 23
Document History Page ................................................. 24
Sales, Solutions, and Legal Information ...................... 24
Worldwide Sales and Design Support ....................... 24
Products .................................................................... 24
PSoC Solutions ......................................................... 24
Page 3 of 24
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CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
Pinouts
REN
LD
OE
RS
VCC
GND
EF
Q17
Q16
GND
Q15
VCC/SMODE
Figure 1. Pin Diagram - 64-pin STQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CY7C4255V
CY7C4265V
CY7C4275V
CY7C4285V
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
D16
D17
GND
RCLK
Top View
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q14
Q13
GND
Q12
Q11
VCC
Q10
Q9
GND
Q8
Q7
Q6
Q5
GND
Q4
VCC
Q3
Q0
Q1
GND
Q2
PAE
Document Number: 38-06012 Rev. *D
FL/RT
WCLK
WEN
WXI
VCC
PAF
RXI
FF
WXO/HF
RXO
4275V–3
Page 4 of 24
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CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
Table 1. Pin Definitions - CY7C4255/65/75/85V 64-pin STQFP
Signal Name
Description
IO
Function
D0–17
Data Inputs
I
Data inputs for an 18-bit bus.
Q0–17
Data Outputs
O
Data outputs for an 18-bit bus.
WEN
Write Enable
I
Enables the WCLK input.
REN
Read Enable
I
Enables the RCLK input.
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset
register.
WXO/HF
Write Expansion
Out/Half Full Flag
O
Dual Mode Pin:
Single device or width expansion – Half Full status flag
Cascaded – Write Expansion Out signal, connected to WXI of next device
EF
Empty Flag
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO. PAE is asynchronous when VCC/SMODE is tied to VCC.
It is synchronized to RCLK when V CC/SMODE is tied to VSS.
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when VCC/SMODE is tied to VCC.
It is synchronized to WCLK when V CC/SMODE is tied to VSS.
LD
Load
I
When LD is LOW, D0–17 (Q0–17) are written (read) into (from) the
programmable-flag-offset register.
FL/RT
First Load/
Retransmit
I
Dual Mode Pin:
Cascaded – The first device in the daisy chain has FL tied to VSS; all other devices have
FL tied to VCC. In standard mode or width expansion, FL is tied to VSS on all devices.
Not Cascaded – Tied to VSS . Retransmit function is also available in standalone mode
by strobing RT.
WXI
Write Expansion
Input
I
Cascaded – Connected to WXO of previous device
Not Cascaded – Tied to VSS
RXI
Read Expansion
Input
I
Cascaded – Connected to RXO of previous device
Not Cascaded – Tied to VSS
RXO
Read Expansion
Output
O
Cascaded – Connected to RXI of next device
RS
Reset
I
Resets device to empty condition. A reset is required before an initial read or write
operation after power up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If
OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
VCC/SMODE
Synchronous
Almost Empty/
Almost Full Flags
I
Dual Mode Pin:
Asynchronous Almost Empty/Almost Full flags – tied to VCC
Synchronous Almost Empty/Almost Full flags – tied to V SS
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
Document Number: 38-06012 Rev. *D
Page 5 of 24
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CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
Functional Description
Programming
The CY7C4255/65/75/85V provides five status pins. These pins
are decoded to determine one of five states: Empty, Almost
Empty, Half Full, Almost Full, and Full (see Table 3 on page 7).
The Half Full flag shares the WXO pin. This flag is valid in the
standalone and width expansion configurations. In the depth
expansion, this pin provides the expansion out (WXO)
information that is used to signal the next FIFO when it is to be
activated.
The CY7C4255/65/75/85V devices contain two 16-bit offset
registers. Data present on D0–15 during a program write
determine the distance from Empty (Full) that the Almost Empty
(Almost Full) flags become active. If the user elects not to
program the FIFO’s flags, the default offset values are used (see
Table 3 on page 7). When the Load LD pin is set LOW and WEN
is set LOW, data on the inputs D0–15 is written into the Empty
offset register on the first LOW-to-HIGH transition of the write
clock (WCLK). When the LD pin and WEN are held LOW then
data is written into the Full offset register on the second
LOW-to-HIGH transition of the write clock (WCLK). The third
transition of the write clock (WCLK) again writes to the Empty
offset register (see Table 2). All offset registers do not have to be
written at one time. One or two offset registers can be written and
then, by bringing the LD pin HIGH, the FIFO is returned to normal
read/write operation. When the LD pin is set LOW, and WEN is
LOW, the next offset register in sequence is written.
The Empty and Full flags are synchronous, that is, they change
state relative to either the read clock (RCLK) or the write clock
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag
architecture guarantees that the flags remain valid from one
clock cycle to the next. The Almost Empty/Almost Full flags
become synchronous if the VCC/SMODE is tied to VSS. All
configurations are fabricated using an advanced 0.35 
CMOS technology. Input ESD protection is greater than
2001 V, and latch-up is prevented by the use of guard rings.
Architecture
The CY7C4255/65/75/85V consists of an array of
8K/16K/32K/64K words of 18 bits each (implemented by a dual
port array of SRAM cells), a read pointer, a write pointer, control
signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, HF,
PAF, FF). The CY7C4255/65/75/85V also includes the control
signals WXI, RXI, WXO, RXO for depth expansion.
Resetting the FIFO
Upon power up, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs go LOW after the falling edge of
RS only if OE is asserted. For the FIFO to reset to its default
state, the user must not read or write while RS is LOW.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW. Then,
data can be read on the LOW-to-HIGH transition of the read
clock (RCLK).
Table 2. Write Offset Register
WCLK[1]
LD
WEN
0
0
Writing to offset registers:
Empty Offset
Full Offset
Selection
0
1
No Operation
1
0
Write Into FIFO
1
1
No Operation
FIFO Operation
When the WEN signal is active (LOW), data present on the D0–17
pins is written into the FIFO on each rising edge of the WCLK
signal. Similarly, when the REN signal is active LOW, data in the
FIFO memory is presented on the Q0–17 outputs. New data is
presented on each rising edge of RCLK while REN is active LOW
and OE is LOW. REN must set up tENS before RCLK for it to be
a valid read function. WEN must occur tENS before WCLK for it
to be a valid write function.
An output enable (OE) pin is provided to three-state the Q0–17
outputs when OE is deasserted. When OE is enabled (LOW),
data in the output register is available to the Q0–17 outputs after
tOE. If devices are cascaded, the OE function only outputs data
on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and under flow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0–17 outputs even
after additional reads occur.
Flag Operation
The CY7C4255/65/75/85V devices provide five flag pins to
indicate the condition of the FIFO contents. Empty and Full are
synchronous. PAE and PAF are synchronous if VCC/SMODE is
tied to VSS.
Full Flag
The Full Flag (FF) goes LOW when device is Full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN. FF is synchronized to WCLK, that is, it is
exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) goes LOW when the device is empty. Read
operations are inhibited whenever EF is LOW, regardless of the
state of REN. EF is synchronized to RCLK, that is, it is
exclusively updated by each rising edge of RCLK.
Note
1. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Document Number: 38-06012 Rev. *D
Page 6 of 24
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CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
Programmable Almost Empty/Almost Full Flag
The CY7C4255/65/75/85V features programmable Almost
Empty and Almost Full Flags. Each flag can be programmed
(described in section Programming on page 6) a specific
distance from the corresponding boundary flags (Empty or Full).
When the FIFO contains the number of words or fewer for which
the flags have been programmed, the PAF or PAE is asserted,
signifying that the FIFO is either Almost Full or Almost Empty.
See Table 3 for a description of programmable flags.
When the SMODE pin is tied LOW, the PAF flag signal transition
is caused by the rising edge of the write clock and the PAE flag
transition is caused by the rising edge of the read clock.
Table 3. Flag Truth Table
Number of Words in FIFO
7C4255V – 8 K × 18
0
7C4265V – 16 K × 18
H
H
L
L
1 to n
H
H
L
H
(n+1) to 32768
H
H
H
H
H
4097 to (8192–(m+1)) 8193 to (16384 –(m+1)) 16385 to (32768–(m+1)) 32769 to (65536 –(m+1))
H
H
L
H
H
(8192–m)[3] to 8192
(16384–m)[3] to 16384
(32768–m)[3] to 32767
(65536–m)[3] to 65535
H
L
L
H
H
8192
16384
32768
65536
L
L
L
H
H
(n+1) to 4096
1 to n
[2]
(n+1) to 8192
1 to n
0
FF PAF HF PAE EF
H
n[2]
0
7C4285V – 64 K × 18
H
1 to
0
7C4275V – 32 K × 18
[2]
[2]
(n+1) to 16384
Retransmit
Width Expansion Configuration
The retransmit feature is beneficial when transferring packets of
data. It enables the receipt of data to be acknowledged by the
receiver and retransmitted if necessary.
The CY7C4255/65/75/85V can be expanded in width to provide
word widths greater than 18 in increments of 18. During width
expansion mode, all control line inputs are common and all flags
are available. Empty (Full) flags must be created by ANDing the
Empty (Full) flags of every FIFO. The PAE and PAF flags can be
detected from any one device. This technique avoids reading
data from, or writing data to the FIFO that is “staggered” by one
clock cycle due to the variations in skew between RCLK and
WCLK. Figure 2 on page 8 demonstrates a 36-word width by
using two CY7C4255/65/75/85Vs.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred and at least one word has been read since
the last RS cycle. A HIGH pulse on RT resets the internal read
pointer to the first physical location of the FIFO. WCLK and
RCLK may be free running but must be disabled during and tRTR
after the retransmit pulse. With every valid read cycle after
retransmit, previously accessed data is read and the read pointer
is incremented until it is equal to the write pointer. Flags are
governed by the relative locations of the read and write pointers
and are updated during a retransmit cycle. Data written to the
FIFO after activation of RT are transmitted also. The full depth of
the FIFO can be repeatedly retransmitted.
Notes
2. n = Empty Offset (Default Values: CY7C4255/65/75/85V n = 127).
3. m = Full Offset (Default Values: CY7C4255/65/75/85V n = 127).
Document Number: 38-06012 Rev. *D
Page 7 of 24
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CY7C4275V, CY7C4285V
Figure 2. Block Diagram of 8 K/16 K/32 K/64 K × 18 Low Voltage Synchronous FIFO Memory in Width Expansion Configuration
RESET (RS)
DATA IN (D) 36
RESET (RS)
18
18
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE (REN)
WRITE ENABLE (WEN)
OUTPUT ENABLE (OE)
LOAD (LD)
PROGRAMMABLE(PAE)
7C4255V
7C4265V
7C4275V
7C4285V
HALF FULL FLAG (HF)
FF
PROGRAMMABLE (PAF)
7C4255V
7C4265V
7C4275V
7C4285V
FF
EF
EMPTY FLAG (EF)
EF
18
FULL FLAG (FF)
DATA OUT (Q)
36
18
FIRST LOAD (FL)
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
4275V–24
Depth Expansion Configuration (with Programmable Flags)
The CY7C4255/65/75/85V can easily be adapted to applications requiring more than 8 K/16 K/32 K/64 K words of buffering.
Figure 3 on page 9 shows Depth Expansion using three CY7C4255/65/75/85Vs. Maximum depth is limited only by signal loading.
Follow these steps:
1. The first device must be designated by grounding the First Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device.
4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device.
5. All Load (LD) pins are tied together.
6. The Half Full Flag (HF) is not available in the Depth Expansion Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by ORing together these respective flags for monitoring. The composite
PAE and PAF flags are not precise.
Document Number: 38-06012 Rev. *D
Page 8 of 24
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CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
Figure 3. Block Diagram of 8 K/16 K/32 K/64 K × 18 Low Voltage Synchronous FIFO Memory with Programmable Flags in
Depth Expansion Configuration
WXO RXO
7C4255V
7C4265V
7C4275V
7C4285V
VCC
FL
FF
EF
PAE
PAF
WXI RXI
WXO RXO
7C4255V
7C4265V
7C4275V
7C4285V
DATA IN (D)
VCC
DATA OUT (Q)
FL
FF
EF
PAF
PAE
WXI RXI
WRITE CLOCK (WCLK)
WXO RXO
WRITE ENABLE (WEN)
READ ENABLE (REN)
7C4255V
7C4265V
7C4275V
7C4285V
RESET (RS)
READ CLOCK (RCLK)
OUTPUT ENABLE (OE)
LOAD (LD)
FF
FF
PAF
EF
EF
PAFWXI RXI PAE
PAE
FIRST LOAD (FL)
4275V–25
Document Number: 38-06012 Rev. *D
Page 9 of 24
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CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
Exceeding maximum ratings[4] may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature .............................. –65 °C to +150 °C
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Supply Voltage to Ground Potential..... –0.5 V to VCC + 0.5 V
DC Voltage Applied to Outputs
in High Z State ..................................... –0.5 V to VCC + 0.5 V
Static Discharge Voltage.......................................... > 2001 V
(per MIL–STD–883, Method 3015)
Latch-Up Current .................................................... > 200 mA
Operating Range
Range
Commercial
[6]
Industrial
AmbientTemperature
VCC[5]
0 °C to +70 °C
3.3 V ± 300 mV
–40 °C to +85 °C
3.3 V ± 300 mV
DC Input Voltage  0.5 V to VCC + 0.5 V
Electrical Characteristics
Over the Operating Range [7]
Parameter
Description
Test Conditions
7C4255/85V-10
Min
Max
VOH
Output HIGH Voltage
VCC = Min, IOH = –1.0 mA
VCC = 3.0 V. IOH = –2.0 mA
VOL
Output LOW Voltage
VCC = Min, IOL = 4.0 mA
VCC = 3.0 V, IOL = 8.0 mA
VIH[8]
Input HIGH Voltage
2.0
VCC
[8]
Input LOW Voltage
–0.5
VIL
IIX
Input Leakage Current
IOZL
IOZH
Output OFF, High Z Current OE > VIH, VSS < VO < VCC
ICC1[9]
Active Power Supply
Current
Commercial
Average Standby Current
Commercial
ISB
[10]
VCC = Max
2.4
7C4255/65/75/85V-15
Min
Max
2.4
Unit
V
0.4
0.4
V
2.0
VCC
V
0.8
–0.5
0.8
V
–10
+10
–10
+10
A
–10
+10
–10
+10
A
30
mA
35
mA
4
mA
4
mA
30
Industrial
4
Industrial
Capacitance
Parameter[11]
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = 3.3 V
Max
Unit
5
pF
7
pF
Notes
4. The Voltage on any input or IO pin cannot exceed the power pin during power up.
5. VCC range for commercial –10 ns is 3.3 V ± 150 mV.
6. TA is the “instant on” case temperature.
7. See the last page of this specification for Group A subgroup testing information.
8. The VIH and V IL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the previous
device or VSS.
9. Input signals switch from 0 V to 3 V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded.
10. All inputs = VCC – 0.2 V, except RCLK and WCLK (which are at frequency = 0 MHz), and FL/RT which is at VSS. All outputs are unloaded.
11. Tested initially and after any design changes that may affect these parameters.
Document Number: 38-06012 Rev. *D
Page 10 of 24
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CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
Figure 4. AC Test Loads and Waveforms (–15) [12, 13]
R1 = 330 
ALL INPUT PULSES
3.3 V
OUTPUT
3.0 V
R2 = 510 
CL
90%
10%
GND
90%
10%
 3 ns
INCLUDING
JIG AND
SCOPE
4275V–4
Equivalent to:
 3 ns
THÉVENIN EQUIVALENT
200 
OUTPUT
4287V–5
2.0 V
Figure 5. AC Test Loads and Waveforms (–10)
VCC/2
50
I/O
ALL INPUT PULSES
3.0 V
GND
 3 ns
Z0 = 50
4275V–6
90%
10%
90%
10%
 3 ns
4275V–7
Notes
12. CL = 30 pF for all AC parameters except for tOHZ.
13. CL = 5 pF for tOHZ.
Document Number: 38-06012 Rev. *D
Page 11 of 24
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CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
Switching Characteristics
Over the Operating Range
Parameter
Description
7C4255/85V-10
Min
Max
7C4255/65/75/85V-15
Min
100
Max
Unit
tS
Clock Cycle Frequency
tA
Data Access Time
tCLK
Clock Cycle Time
10
15
ns
tCLKH
Clock HIGH Time
4.5
6
ns
tCLKL
Clock LOW Time
4.5
6
ns
tDS
Data Setup Time
3.5
4
ns
tDH
Data Hold Time
tENS
Enable Setup Time
tENH
Enable Hold Time
0
0
ns
tRS
Reset Pulse Width[14]
10
15
ns
tRSR
Reset Recovery Time
8
tRSF
Reset to Flag and Output Time
tPRT
Retransmit Pulse Width
60
60
ns
tRTR
Retransmit Recovery Time
90
90
ns
0
0
ns
2
8
2
tOLZ
Output Enable to Output in Low Z
tOE
Output Enable to Output Valid
MHz
10
ns
0
0
ns
3.5
4
ns
10
10
[15]
66.7
ns
15
ns
3
7
3
10
ns
3
7
3
8
ns
10
ns
tOHZ
Output Enable to Output in High
tWFF
Write Clock to Full Flag
tREF
Read Clock to Empty Flag
8
10
ns
tPAFasynch
Clock to Programmable Almost Full Flag[16]
(Asynchronous mode, VCC/SMODE tied to VCC)
15
16
ns
tPAFsynch
Clock to Programmable Almost Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)
8
10
ns
tPAEasynch
Clock to Programmable Almost Empty Flag[16]
(Asynchronous mode, VCC/SMODE tied to VCC)
15
16
ns
tPAEsynch
Clock to Programmable Almost Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)
8
10
ns
Z[15]
8
tHF
Clock to Half Full Flag
12
16
ns
tXO
Clock to Expansion Out
6
10
ns
tXI
Expansion in Pulse Width
4.5
6.5
ns
tXIS
Expansion in Setup Time
4
5
ns
tSKEW1
Skew Time between Read Clock and Write Clock for Full Flag
5
6
ns
tSKEW2
Skew Time between Read Clock and Write Clock for Empty Flag
5
6
ns
tSKEW3
Skew Time between Read Clock and Write Clock for Programmable
Almost Empty and Programmable Almost Full Flags
(Synchronous Mode only)
10
15
ns
Notes
14. Pulse widths less than minimum values are not allowed.
15. Values guaranteed by design, not currently tested.
16. tPAFasynch, tPAEasynch, after program register write are valid until 5 ns + tPAF(E).
Document Number: 38-06012 Rev. *D
Page 12 of 24
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CY7C4275V, CY7C4285V
Switching Waveforms
Figure 6. Write Cycle Timing
tCLK
tCLKH
tCLKL
WCLK
tDS
tDH
D0 –D17
tENS
tENH
WEN
NO OPERATION
tWFF
tWFF
FF
tSKEW1
[17]
RCLK
REN
Figure 7. Read Cycle Timing
tCLK
tCLKH
tCLKL
RCLK
tENS
tENH
REN
NO OPERATION
tREF
tREF
EF
tA
Q0 –Q17
VALID DATA
tOLZ
tOHZ
tOE
OE
tSKEW2[18]
WCLK
WEN
Notes
17. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
18. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF goes HIGH during the current clock cycle. If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.
Document Number: 38-06012 Rev. *D
Page 13 of 24
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CY7C4275V, CY7C4285V
Switching Waveforms (continued)
Figure 8. Reset Timing [19]
tRS
RS
tRSR
REN, WEN,
LD
tRSF
EF,PAE
tRSF
FF,PAF,
HF
tRSF
[20]
OE=1
Q0 – Q17
OE=0
Figure 9. First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
tDS
D0 –D17
D0 (FIRSTVALID WRITE)
D1
tENS
D2
D3
D4
[21]
tFRL
WEN
tSKEW2
RCLK
tREF
EF
REN
tA
Q0 –Q17
tA
D0
tOLZ
[22]
D1
tOE
OE
Notes
19. The clocks (RCLK, WCLK) can be free-running during reset.
20. After reset, the outputs are LOW if OE = 0 and three-state if OE = 1.
21. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2 × tCLK + tSKEW2 or
tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW).
22. The first word is always available the cycle after EF goes HIGH.
Document Number: 38-06012 Rev. *D
Page 14 of 24
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CY7C4275V, CY7C4285V
Switching Waveforms (continued)
Figure 10. Empty Flag Timing
WCLK
tDS
tDS
D0
D0 –D17
D1
tENH
tENS
tENH
tENS
WEN
[23]
[23]
tFRL
tFRL
RCLK
tREF
tSKEW2
tREF
tREF
tSKEW2
EF
REN
OE
tA
D0
Q0 –Q17
Figure 11. Full Flag Timing
NO WRITE
NO WRITE
WCLK
tSKEW1
[24]
tDS
tSKEW1
[24]
DATA WRITE
DATA WRITE
D0 –D17
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
tENH
tENS
tENH
REN
OE
LOW
tA
Q0 –Q17
DATA IN OUTPUT REGISTER
tA
DATA READ
NEXT DATA READ
Notes
23. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2 × tCLK + tSKEW2 or
tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW).
24. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
Document Number: 38-06012 Rev. *D
Page 15 of 24
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CY7C4275V, CY7C4285V
Switching Waveforms (continued)
Figure 12. Half Full Timing
tCLKH
tCLKL
WCLK
tENS tENH
WEN
tHF
HF
HALF FULL + 1
OR MORE
HALF FULL OR LESS
HALF FULL OR LESS
tHF
RCLK
tENS
REN
Figure 13. Programmable Almost Empty Flag Timing
tCLKH
tCLKL
WCLK
tENS tENH
WEN
tPAE
PAE
[25]
N + 1 WORDS
IN FIFO
tPAE
n WORDS IN FIFO
RCLK
tENS
REN
Note
25. PAE is offset = n. Number of data words into FIFO already = n.
Document Number: 38-06012 Rev. *D
Page 16 of 24
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CY7C4275V, CY7C4285V
Switching Waveforms (continued)
Figure 14. Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW))
tCLKL
tCLKH
WCLK
tENS tENH
WEN
Note 26
PAE
tSKEW3
N + 1 WORDS
IN FIFO
[27]
tPAE synch
Note 28
tPAE synch
RCLK
tENS
tENS tENH
REN
Figure 15. Programmable Almost Full Flag Timing
tCLKH
tCLKL
Note 26
WCLK
tENS tENH
WEN
PAF
[29]
tPAF
FULL– M WORDS
IN FIFO [30]
tPAF
FULL– (M+1) WORDS
IN FIFO [31]
RCLK
tENS
REN
Notes
26. PAF offset = m. Number of data words written into FIFO already = 8192 (m + 1) for the CY7C4255V, 16384 (m + 1) for the CY7C4265V, 32768  (m + 1) for the
CY7C4275V, and 65536 (m + 1) for the CY7C4285V.
27. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK
and the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK.
28. If a read is performed on this rising edge of the read clock, there are Empty + (n1) words in the FIFO when PAE goes LOW.
29. PAF is offset = m.
30. 8192 m words in CY7C4255V, 16384 m words in CY7C4265V, 32768m words in CY7C4275V, and 65536 m words in CY7C4285V.
31. 8192 (m + 1) words in CY7C4255V, 16384 (m + 1) words in CY7C4265V, 32768 (m + 1) words in CY7C4275V, and 65536 (m + 1) words in CY7C4285V.
Document Number: 38-06012 Rev. *D
Page 17 of 24
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CY7C4275V, CY7C4285V
Switching Waveforms (continued)
Figure 16. Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW))
Note 32
tCLKL
tCLKH
WCLK
tENS tENH
WEN
tPAF
PAF
FULL– M WORDS
IN FIFO [33]
FULL – M + 1 WORDS
IN FIFO
[34]
tSKEW3
tPAF synch
RCLK
tENS
tENS tENH
REN
Figure 17. Write Programmable Registers
tCLK
tCLKL
tCLKH
WCLK
tENS
tENH
LD
tENS
WEN
tDS
tDH
PAE OFFSET
D0 –D17
PAE OFFSET
PAF OFFSET
D0 – D11
Notes
32. If a write is performed on this rising edge of the write clock, there are Full  (m1) words of the FIFO when PAF goes LOW.
33. 8192 m words in CY7C4255V, 16384 m words in CY7C4265V, 32768m words in CY7C4275V, and 65536 m words in CY7C4285V.
34. tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK
and the rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge.
Document Number: 38-06012 Rev. *D
Page 18 of 24
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CY7C4275V, CY7C4285V
Switching Waveforms (continued)
Figure 18. Read Programmable Registers
tCLK
tCLKL
tCLKH
RCLK
tENS
tENH
LD
tENS
WEN
tA
UNKNOWN
Q0 –Q17
PAE OFFSET
PAF OFFSET
PAE OFFSET
Figure 19. Write Expansion Out Timing
tCLKH
WCLK
35
tXO
36
WXO
tXO
tENS
WEN
Figure 20. Read Expansion Out Timing
tCLKH
WCLK
35
tXO
RXO
tXO
tENS
REN
Figure 21. Write Expansion In Timing
tXI
WXI
WCLK
tXIS
Notes
35. Read from Last Physical Location.
36. Write to Last Physical Location.
Document Number: 38-06012 Rev. *D
Page 19 of 24
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CY7C4275V, CY7C4285V
Switching Waveforms (continued)
Figure 22. Read Expansion In Timing
tXI
RXI
tXIS
RCLK
Figure 23. Retransmit Timing [37, 38, 39]
FL/RT
tPRT
tRTR
REN/WEN
EF/FF
and all
async flags
HF/PAE/PAF
Notes
37. Clocks are free-running in this case.
38. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags are valid at tRTR.
39. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags.
Document Number: 38-06012 Rev. *D
Page 20 of 24
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CY7C4275V, CY7C4285V
Ordering Information
8 K × 18 Low-Voltage Deep Sync FIFO
Speed (ns)
10
Ordering Code
Package Diagram
CY7C4255V–10ASC
51-85051
CY7C4255V–10ASXC
15
CY7C4255V–15ASC
51-85051
CY7C4255V–15ASXC
CY7C4255V–15ASXI
51-85051
CY7C4255V–15ASI
Package Type
64-pin Thin Quad Flat Pack (10 × 10 × 1.4 mm)
64-pin Thin Quad Flat Pack (10 × 10 × 1.4 mm) (Pb-free)
64-pin Thin Quad Flat Pack (10 × 10 × 1.4 mm)
64-pin Thin Quad Flat Pack (10 × 10 × 1.4 mm) (Pb-free)
64-pin Thin Quad Flat Pack (10 × 10 × 1.4 mm) (Pb-free)
Operating Range
Commercial
Commercial
Industrial
64-pin Thin Quad Flat Pack (10 × 10 × 1.4 mm)
16 K × 18 Low-Voltage Deep Sync FIFO
Speed (ns)
15
Ordering Code
Package Diagram
CY7C4265V–15ASC
51-85051
Package Type
64-pin Thin Quad Flat Pack (10 × 10 × 1.4 mm)
Operating Range
Commercial
32 K × 18 Low-Voltage Deep Sync FIFO
Speed (ns)
15
Ordering Code
Package Diagram
CY7C4275V–15ASC
51-85051
CY7C4275V–15ASXC
Package Type
64-pin Thin Quad Flat Pack (10 × 10 × 1.4 mm)
64-pin Thin Quad Flat Pack (10 × 10 × 1.4 mm) (Pb-free)
Operating Range
Commercial
64 K × 18 Low-Voltage Deep Sync FIFO
Speed (ns)
10
Ordering Code
Package Diagram
CY7C4285V–10ASC
CY7C4285V–10ASXC
15
CY7C4285V–15ASXC
51-85051
51-85051
CY7C4285V–15ASC
CY7C4285V–15ASI
CY7C4285V–15ASXI
Package Type
64-pin Thin Quad Flat Pack (10 × 10 × 1.4 mm)
Operating Range
Commercial
64-pin Thin Quad Flat Pack (10 × 10 × 1.4 mm) (Pb-free)
64-pin Thin Quad Flat Pack (10 × 10 × 1.4 mm) (Pb-free)
Commercial
64-pin Thin Quad Flat Pack (10 × 10 × 1.4 mm)
51-85051
64-pin Thin Quad Flat Pack (10 × 10 × 1.4 mm)
64-pin Thin Quad Flat Pack (10 × 10 × 1.4 mm) (Pb-free)
Industrial
Ordering Code Definitions
CY 7C 4 2X 5
V - XX AS X X
Temperature Range: X = C or I
C = Commercial; I = Industrial
X = Pb-free (RoHS Compliant)
Package Type: AS = STQFP
Speed: XX = 10 ns or 15 ns
V = 3.3 V
Width: 5 = ×18
Depth: 2X = 25 or 26 or 27 or 28
25 = 8 Kb; 26 = 16 Kb; 27 = 32 Kb; 28 = 64 Kb
FIFO
7C = Dual Port
Company ID: CY = Cypress
Document Number: 38-06012 Rev. *D
Page 21 of 24
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Package Diagram
Figure 24. 64-pin Thin Plastic Quad Flat Pack (10 × 10 × 1.4 mm)
51-85051 *B
Document Number: 38-06012 Rev. *D
Page 22 of 24
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Acronyms
Acronym
Description
CMOS
complementary metal oxide semiconductor
FIFO
first-in first-out
I/O
input/output
OE
output enable
REN
read enable
RCLK
read clock
RT
Retransmit
RS
Reset
TQFP
thin quad flat pack
WCLK
write clock
WEN
write enable
Document Conventions
Units of Measure
Symbol
Unit of Measure
ns
nano seconds
V
Volts
µA
micro Amperes
mA
milli Amperes
ms
milli seconds
mV
milli Volts
MHz
Mega Hertz
pF
pico Farad
W
Watts
°C
degree Celcius
Document Number: 38-06012 Rev. *D
Page 23 of 24
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Document History Page
Document Title: CY7C4255V/CY7C4265V/CY7C4275V/CY7C4285V 8 K/16 K/32 K/64 K × 18 Low Voltage Deep Sync FIFOs
Document Number: 38-06012
REV.
ECN
Orig. of
Change
Submission
Date
**
106473
SZV
09/10/01
Change from Spec number: 38-00654 to 38-06012
12/26/02
Power up requirements added to Maximum Ratings Information
Description of Change
*A
122264
RBI
*B
2556036
VKN/AESA
08/22/2008 Updated ordering information and data sheet template.
*C
2896039
RAME
03/19/2010 Added Contents
Updated package diagram
Removed inactive parts from Ordering information table
Updated links in Sales, Solutions and Legal Information
*D
3123000
ADMU
12/31/2010 Removed speed bin -25
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated in new template.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
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closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2001-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-06012 Rev. *D
Revised December 31, 2010
Page 24 of 24
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