ATMEL AT87C52X2-3CSUL 8-bit microcontroller 8 kbytes rom/otp, romless Datasheet

Features
• 80C52 Compatible
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
– 8051 Pin and Instruction Compatible
– Four 8-bit I/O Ports
– Three 16-bit Timer/Counters
– 256 Bytes Scratchpad RAM
High-speed Architecture
40 MHz at 5V, 30 MHz at 3V
X2 Speed Improvement Capability (6 Clocks/Machine Cycle)
– 30 MHz at 5V, 20 MHz at 3V (Equivalent to 60 MHz at 5V, 40 MHz at 3V)
Dual Data Pointer
On-chip ROM/EPROM (8Kbytes)
Programmable Clock Out and Up/Down Timer/Counter 2
Asynchronous Port Reset
Interrupt Structure with
– 6 Interrupt Sources
– 4 Level Priority Interrupt System
Full Duplex Enhanced UART
– Framing Error Detection
– Automatic Address Recognition
Low EMI (Inhibit ALE)
Power Control Modes
– Idle Mode
– Power-down Mode
– Power-off Flag
Once Mode (On-chip Emulation)
Power Supply: 4.5 - 5.5V, 2.7 - 5.5V
Temperature Ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC)
Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44 (13.9 footprint)
Description
TS80C52X2 is high performance CMOS ROM, OTP, EPROM and ROMless versions
of the 80C51 CMOS single chip 8-bit microcontroller.
The TS80C52X2 retains all features of the 80C51 with extended ROM/EPROM
capacity (8 Kbytes), 256 bytes of internal RAM, a 6-source, 4-level interrupt system,
an on-chip oscilator and three timer/counters.
8-bit
Microcontroller
8 Kbytes
ROM/OTP,
ROMless
TS80C32X2
TS87C52X2
TS80C52X2
AT80C32X2
AT80C52X2
AT87C52X2
In addition, the TS80C52X2 has a dual data pointer, a more versatile serial channel
that facilitates multiprocessor communication (EUART) and an X2 speed improvement mechanism.
The fully static design of the TS80C52X2 allows to reduce system power consumption
by bringing the clock frequency down to any value, even DC, without loss of data.
The TS80C52X2 has 2 software-selectable modes of reduced activity for further
reduction in power consumption. In the idle mode the CPU is frozen while the timers,
the serial port and the interrupt system are still operating. In the power-down mode the
RAM is saved and all other functions are inoperative.
Rev. 4184I–8051–02/08
Table 1. Memory Size
ROM (bytes)
EPROM (bytes)
TOTAL RAM (bytes)
TS80C32X2
0
0
256
TS80C52X2
8k
0
256
TS87C52X2
0
8k
256
(3) (3)
(1)
XTAL1
EUART
XTAL2
ALE/ PROG
RAM
256x8
C51
CORE
PSEN
ROM
/EPROM
8Kx8
T2
T2EX
Vss
Vcc
TxD
RxD
Block Diagram
(1)
Timer2
IB-bus
CPU
EA/VPP
Timer 0
Timer 1
(2)
Notes:
2
INT
Ctrl
Parallel I/O Ports & Ext. Bus
P3
P2
P1
P0
INT1
(2) (2)
T1
(2) (2)
INT0
Port 0 Port 1 Port 2 Port 3
RESET
WR
(2)
T0
RD
1. Alternate function of Port 1
2. Alternate function of Port 3
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
SFR Mapping
The Special Function Registers (SFRs) of the TS80C52X2 fall into the following
categories:
•
C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
•
I/O port registers: P0, P1, P2, P3
•
Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2,
RCAP2L, RCAP2H
•
Serial I/O port registers: SADDR, SADEN, SBUF, SCON
•
Power and clock control registers: PCON
•
Interrupt system registers: IE, IP, IPH
•
Others: AUXR, CKCON
3
4184I–8051–02/08
Table 2. All SFRs with their address and their reset value
Bit
Addressable
0/8
Non Bit Addressable
1/9
2/A
3/B
4/C
5/D
6/E
7/F
F8h
F0h
FFh
B
0000 0000
F7h
E8h
E0h
EFh
ACC
0000 0000
E7h
D8
h
DFh
D0
h
PSW
0000 0000
C8
h
T2CON
0000 0000
D7h
T2MOD
XXXX XX00
RCAP2L
0000 0000
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000
CFh
C0
h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
C7h
IP
SADEN
XX00 0000
0000 0000
BFh
P3
IPH
XX00 0000
1111 1111
IE
SADDR
0X00 0000
0000 0000
AFh
P2
AUXR1
1111 1111
XXXX XXX0
SCON
SBUF
0000 0000
XXXX XXXX
B7h
A7h
9Fh
P1
97h
1111 1111
TCON
TMOD
TL0
TL1
TH0
TH1
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
P0
1111 1111
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
0/8
1/9
2/A
3/B
AUXR
XXXXXXX0
CKCON
XXXX XXX0
PCON
00X1 0000
4/C
5/D
6/E
8Fh
87h
7/F
Reserved
4
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
7
8
34
33
P0.5 / A5
9
32
P0.7 / A7
31
30
EA/VPP
ALE/PROG
PSEN
P2.7 / A15
P2.6 / A14
P2.5 / A13
9
37
RST
P0.6/AD6
10
36
P3.0/RxD
P0.7/AD7
NIC*
11
12
EA/VPP
P3.1/TxD
13
35
34
33
P3.2/INT0
P3.3/INT1
14
15
32
31
PSEN
P3.4/T0
P3.5/T1
16
30
23
P2.2 / A10
P2.6/A14
17
29
22
21
P2.1 / A9
P2.5/A13
PLCC/CQPJ 44
P0.5/AD5
NIC*
ALE/PROG
P2.7/A15
P2.3/A11
P2.4/A12
P2.2/A10
P2.0 / A8
P2.1/A9
P3.6/WR
18 19 20 21 22 23 24 25 26 27 28
NIC*
P2.0/A8
24
P1.7
P0.3/AD3
17
18
19
20
P0.4/AD4
P0.2/AD2
25
P2.4 / A12
P2.3 / A11
P1.4
VSS
16
39
38
P0.1/AD1
XTAL1
26
P1.6
7
8
P0.0/AD0
P3.7/RD
XTAL2
14
15
VCC
P3.5/T1
P3.6/WR
13
CDIL40
29
28
27
P1.0/T2
P3.4/T0
11
12
PDIL/
P1.1/T2EX
P3.2/INT0
P3.3/INT1
10
P1.2
P3.0/RxD
P3.1/TxD
6 5 4 3 2 1 44 43 42 41 40
P1.5
P0.6 / A6
P1.3
P1.7
RST
P0.2/AD2
P0.3/AD3
P1.6
P0.1/AD1
P0.3 / A3
P0.4 / A4
P0.0/AD0
36
35
VCC
6
VSS1/NIC*
5
P1.0/T2
P1.4
P1.5
P1.1/T2EX
P0.1 / A1
P0.2 / A2
VSS
37
VSS1/NIC*
3
4
P1.2
P0.0 / A0
XTAL1
VCC
39
38
P1.3
40
2
XTAL2
1
P3.7/RD
P1.0 / T2
P1.1 / T2EX
P1.2
P1.3
P1.4
Pin Configuration
44 43 42 41 40 39 38 37 36 35 34
P1.5
1
P1.6
2
P1.7
RST
3
4
P3.0/RxD
5
NIC*
6
7
8
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
33
32
P0.4/AD4
31
P0.6/AD6
30
P0.7/AD7
29
28
EA/VPP
27
ALE/PROG
PSEN
9
26
25
10
24
P2.6/A14
11
23
P2.5/A13
PQFP44
VQFP44
P0.5/AD5
NIC*
P2.7/A15
P2.3/A11
P2.4/A12
P2.2/A10
P2.1/A9
NIC*
P2.0/A8
VSS
XTAL1
XTAL2
P3.7/RD
P3.6/WR
12 13 14 15 16 17 18 19 20 21 22
*NIC: No Internal Connection
5
4184I–8051–02/08
Mnemonic
VSS
Pin Number
Type
Name and Function
DIL
LCC
VQFP
1.4
20
22
16
I
Ground: 0V reference
1
39
I
Optional Ground: Contact the Sales Office for ground
connection.
Power Supply: This is the power supply voltage for normal,
idle and power-down operation
Vss1
VCC
40
44
38
I
P0.0-P0.7
3932
4336
37-30
I/O
P1.0-P1.7
1-8
2-9
40-44
1-3
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0
pins that have 1s written to them float and can be used as
high impedance inputs.Port 0 pins must be polarized to Vcc
or Vss in order to prevent any parasitic current consumption.
Port 0 is also the multiplexed low-order address and data bus
during access to external program and data memory. In this
application, it uses strong internal pull-up when emitting 1s.
Port 0 also inputs the code bytes during EPROM
programming. External pull-ups are required during program
verification during which P0 outputs the code bytes.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 1 pins that have 1s written to them are pulled
high by the internal pull-ups and can be used as inputs. As
inputs, Port 1 pins that are externally pulled low will source
current because of the internal pull-ups. Port 1 also receives
the low-order address byte during memory programming and
verification.
Alternate functions for Port 1 include:
6
1
2
40
I/O
T2 (P1.0): Timer/Counter 2 external count input/Clockout
2
3
41
I
T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction
Control
P2.0-P2.7
2128
2431
18-25
I/O
P3.0-P3.7
1017
11,
1319
5,
7-13
I/O
10
11
5
I
RXD (P3.0): Serial input port
11
13
7
O
TXD (P3.1): Serial output port
12
14
8
I
INT0 (P3.2): External interrupt 0
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 2 pins that have 1s written to them are pulled
high by the internal pull-ups and can be used as inputs. As
inputs, Port 2 pins that are externally pulled low will source
current because of the internal pull-ups. Port 2 emits the highorder address byte during fetches from external program
memory and during accesses to external data memory that
use 16-bit addresses (MOVX atDPTR).In this application, it
uses strong internal pull-ups emitting 1s. During accesses to
external data memory that use 8-bit addresses (MOVX atRi),
port 2 emits the contents of the P2 SFR. Some Port 2 pins
receive the high order address bits during EPROM
programming and verification: P2.0 to P2.4
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 3 pins that have 1s written to them are pulled
high by the internal pull-ups and can be used as inputs. As
inputs, Port 3 pins that are externally pulled low will source
current because of the internal pull-ups. Port 3 also serves
the special features of the 80C51 family, as listed below.
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
Mnemonic
Pin Number
Type
Name and Function
DIL
LCC
VQFP
1.4
13
15
9
I
INT1 (P3.3): External interrupt 1
14
16
10
I
T0 (P3.4): Timer 0 external input
15
17
11
I
T1 (P3.5): Timer 1 external input
16
18
12
O
WR (P3.6): External data memory write strobe
17
19
13
O
RD (P3.7): External data memory read strobe
Reset
9
10
4
I
Reset: A high on this pin for two machine cycles while the
oscillator is running, resets the device. An internal diffused
resistor to VSS permits a power-on reset using only an
external capacitor to VCC.
ALE/PROG
30
33
27
PSEN
29
32
26
O
Program Store ENable: The read strobe to external program
memory. When executing code from the external program
memory, PSEN is activated twice each machine cycle, except
that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches
from internal program memory.
EA/VPP
31
35
29
I
External Access Enable/Programming Supply Voltage:
EA must be externally held low to enable the device to fetch
code from external program memory locations 0000H and
3FFFH (RB) or 7FFFH (RC), or FFFFH (RD). If EA is held
high, the device executes from internal program memory
unless the program counter contains an address greater than
3FFFH (RB) or 7FFFH (RC) EA must be held low for
ROMless devices. This pin also receives the 12.75V
programming supply voltage (VPP) during EPROM
programming. If security level 1 is programmed, EA will be
internally latched on Reset.
XTAL1
19
21
15
I
Crystal 1: Input to the inverting oscillator amplifier and input
to the internal clock generator circuits.
XTAL2
18
20
14
O
Crystal 2: Output from the inverting oscillator amplifier
O (I) Address Latch Enable/Program Pulse: Output pulse for
latching the low byte of the address during an access to
external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency,
and can be used for external timing or clocking. Note that one
ALE pulse is skipped during each access to external data
memory. This pin is also the program pulse input (PROG)
during EPROM programming. ALE can be disabled by setting
SFR’s AUXR.0 bit. With this bit set, ALE will be inactive
during internal fetches.
7
4184I–8051–02/08
TS80C52X2
Enhanced Features
X2 Feature
In comparison to the original 80C52, the TS80C52X2 implements some new features,
which are:
•
The X2 option
•
The Dual Data Pointer
•
The 4 level interrupt priority system
•
The power-off flag
•
The ONCE mode
•
The ALE disabling
•
Some enhanced features are also located in the UART and the Timer 2
The TS80C52X2 core needs only 6 clock periods per machine cycle. This feature called
”X2” provides the following advantages:
•
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power
•
Save power consumption while keeping same CPU power (oscillator power saving)
•
Save power consumption by dividing dynamically operating frequency by 2 in
operating and idle modes
•
Increase CPU power by 2 while keeping same crystal frequency
In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
Description
The clock for the whole circuit and peripheral is first divided by two before being used by
the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1
input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic
ratio between 40 to 60%. Figure 1. shows the clock generation block diagram. X2 bit is
validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD
mode. Figure 2 shows the mode switching waveforms.
Figure 1. Clock Generation Diagram
2
XTAL1
FXTAL
XTAL1:2
state machine: 6 clock cycles.
0
1
CPU control
FOSC
X2
CKCON reg
8
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
Figure 2. Mode Switching Waveforms
XTAL1
XTAL1:2
X2 bit
CPU clock
STD Mode
X2 Mode
STD Mode
The X2 bit in the CKCON register (See Table 3.) allows to switch from 12 clock cycles
per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated
(STD mode). Setting this bit activates the X2 feature (X2 mode).
Note:
In order to prevent any incorrect operation while operating in X2 mode, user must be
aware that all peripherals using clock frequency as time reference (UART, timers) will
have their time reference divided by two. For example a free running timer generating an
interrupt every 20 ms will then generate an interrupt every 10 ms. UART with 4800 baud
rate will have 9600 baud rate.
Table 3. CKCON Register
CKCON - Clock Control Register (8Fh)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
X2
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
X2
CPU and peripheral clock bit
Clear to select 12 clock periods per machine cycle (STD mode, FOSC=FXTAL/2).
Set to select 6 clock periods per machine cycle (X2 mode, FOSC=FXTAL).
Reset Value = XXXX XXX0b
Not bit addressable
For further details on the X2 feature, please refer to ANM072 available on the web
(http://www.atmel.com)
9
4184I–8051–02/08
The additional data pointer can be used to speed up code execution and reduce code
size in a number of ways.
Dual Data Pointer
Register (Ddptr)
The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external
memory, and a single bit called
DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them
(Refer to Figure 3).
Figure 3. Use of Dual Pointer
External Data Memory
7
0
DPS
DPTR1
AUXR1(A2H)
DPTR0
DPH(83H) DPL(82H)
Table 4. AUXR1: Auxiliary Register 1
7
6
5
4
3
2
1
0
-
-
-
-
GF3
0
-
DPS
Bit
Bit
Number
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
GF3
2
0
Reserved
Always stuck at 0
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
DPS
Description
This bit is a general purpose user flag
Data Pointer Selection
Clear to select DPTR0.
Set to select DPTR1.
Reset Value = XXXX XXX0
Not bit addressable
10
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
Application
Software can take advantage of the additional data pointers to both increase speed and
reduce code size, for example, block operations (copy, compare, search ...) are well
served by using one data pointer as a ’source’ pointer and the other one as a "destination" pointer.
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,atDPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX atDPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1
SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example,
only the fact that DPS is toggled in the proper sequence matters, not its actual value. In
other words, the block move routine works the same whether DPS is '0' or '1' on entry.
Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in
the opposite state.
11
4184I–8051–02/08
The timer 2 in the TS80C52X2 is compatible with the timer 2 in the 80C52.
It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2
and TL2, connected in cascade. It is controlled by T2CON register (See Table 5) and
T2MOD register (See Table 6). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2
selects FOSC/12 (timer operation) or external pin T2 (counter operation) as the timer
clock input. Setting TR2 allows TL2 to be incremented by the selected input.
Timer 2
Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These
modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON), as
described in the Atmel 8-bit Microcontroller Hardware description.
Refer to the Atmel 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes.
In TS80C52X2 Timer 2 includes the following enhancements:
Auto-reload Mode
•
Auto-reload mode with up or down counter
•
Programmable clock-output
The Auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the
Atmel 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an
Up/down timer/counter as shown in Figure 4. In this mode the T2EX pin controls the
direction of count.
When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the
TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value
in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.
When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the
timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.
The underflow sets TF2 flag and reloads FFFFh into the timer registers.
The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide
17-bit resolution.
12
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
Figure 4. Auto-reload Mode Up/Down Counter (DCEN = 1)
(:6 in X2 mode)
:12
0
XTAL1
FOSC
FXTAL
1
T2
TR2
C/T2
T2CONreg
T2CONreg
(DOWN COUNTING RELOAD
FFh
FFh
(8-bit)
(8-bit)
T2EX:
if DCEN=1, 1=UP
if DCEN=1, 0=DOWN
if DCEN = 0, up counting
TOGGL
T2CONreg
EXF2
TL2
(8-bit)
TH2
(8-bit)
TF2
T2CONreg
TIMER 2
INTERRUPT
RCAP2L RCAP2H
(8-bit)
(8-bit)
(UP COUNTING RELOAD VALUE)
Programmable Clock-output
In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 5) . The input clock increments TL2 at frequency FOSC/2. The timer
repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H
and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do
not generate interrupts. The formula gives the clock-out frequency as a function of the
system oscillator frequency and the value in the RCAP2H and RCAP2L registers :
F
osc
Clock – OutFrequency = ----------------------------------------------------------------------------------------4 × ( 65536 – RCAP2H ⁄ RCAP2L )
For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz
(FOSC/216) to 4 MHz (FOSC/4). The generated clock signal is brought out to T2 pin (P1.0).
Timer 2 is programmed for the clock-out mode as follows:
•
Set T2OE bit in T2MOD register.
•
Clear C/T2 bit in T2CON register.
•
Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L
registers.
•
Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the
reload value or a different one depending on the application.
•
To start the timer, set TR2 run control bit in T2CON register.
It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not
independent since both functions use the values in the RCAP2H and RCAP2L registers.
13
4184I–8051–02/08
Figure 5. Clock-Out Mode C/T2 = 0
XTAL1
:2
(:1 in X2 mode)
TR2
T2CON reg
TL2
(8-bit)
TH2
(8-bit)
OVERFLOW
Toggle
RCAP2L
(8-bit)
RCAP2H
(8-bit)
T2
Q
D
T2OE
T2MOD reg
EXF2
T2EX
EXEN2
T2CON reg
14
TIMER 2
INTERRUPT
T2CON reg
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
Table 5. T2CON Register
T2CON - Timer 2 Control Register (C8h)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Number
7
Bit
Mnemonic Description
TF2
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
6
EXF2
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2
interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter
mode (DCEN = 1)
5
RCLK
Receive Clock bit
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
4
TCLK
Transmit Clock bit
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Clear to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if timer 2 is not used to clock the serial port.
3
EXEN2
2
TR2
1
C/T2#
Timer/Counter 2 select bit
Clear for timer operation (input from internal clock system: FOSC).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0
for clock out mode.
CP/RL2#
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to Auto-reload on
timer 2 overflow.
Clear to Auto-reload on timer 2 overflows or negative transitions on T2EX pin if
EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
0
Timer 2 Run control bit
Clear to turn off timer 2.
Set to turn on timer 2.
Reset Value = 0000 0000b
Bit addressable
15
4184I–8051–02/08
Table 6. T2MOD Register
T2MOD - Timer 2 Mode Control Register (C9h)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
T2OE
DCEN
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
T2OE
Timer 2 Output Enable bit
Clear to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.
0
DCEN
Down Counter Enable bit
Clear to disable timer 2 as up/down counter.
Set to enable timer 2 as up/down counter.
Reset Value = XXXX XX00b
Not bit addressable
16
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
The serial I/O port in the TS80C52X2 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as
an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex
modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates
TS80C52X2 Serial I/O
Port
Serial I/O port includes the following enhancements:
•
Framing error detection
•
Automatic address recognition
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2
and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 6).
Framing Error Detection
Figure 6. Framing Error Block Diagram
SM0/FE SM1
SM2
REN
TB8
RB8
TI
RI
SCON (98h)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SM0 to UART mode control (SMOD = 0)TS80C52X2
SMOD1SMOD0
-
POF
GF1
GF0
PD
PCON (87h)
IDL
To UART framing error control
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register (See Table 9.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a reset can clear FE bit. Subsequently received frames with valid stop
bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the
last data bit (See Figure 7. and Figure 8.).
Figure 7. UART Timings in Mode 1
RXD
D0
Start
bit
D1
D2
D3
D4
Data byte
D5
D6
D7
Stop
bit
RI
SMOD0=X
FE
SMOD0=1
17
4184I–8051–02/08
Figure 8. UART Timings in Modes 2 and 3
RXD
D0
D1
D2
Start
bit
D3
D4
Data byte
D5
D6
D7
D8
Ninth Stop
bit
bit
RI
SMOD0=0
RI
SMOD0=1
FE
SMOD0=1
Automatic Address
Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor
communication feature by allowing the serial port to examine the address of each
incoming command frame. Only when the serial port recognizes its own address, the
receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU
is not interrupted by command frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this
configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the
received command frame address matches the device’s address and is terminated by a
valid stop bit.
To support automatic address recognition, a device is identified by a given address and
a broadcast address.
Note:
Given Address
The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
Each device has an individual address that is specified in SADDR register; the SADEN
register is a mask byte that contains don’t-care bits (defined by zeros) to form the
device’s given address. The don’t-care bits provide the flexibility to address one or more
slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111
1111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
SADEN1111 1001b
Given1111 0XX1b
Slave C:SADDR1111 0010b
SADEN1111 1101b
Given1111 00X1b
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g.
18
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with
slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both
set (e.g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0
set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b).
Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers
with zeros defined as don’t-care bits, e.g.:
SADDR 0101 0110b
SADEN 1111 1100b
Broadcast =SADDR OR SADEN1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however
in most applications, a broadcast address is FFh. The following is an example of using
broadcast addresses:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Broadcast1111 1X11b,
Slave B:SADDR1111 0011b
SADEN1111 1001b
Broadcast1111 1X11B,
Slave C:SADDR=1111 0010b
SADEN1111 1101b
Broadcast1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with
all of the slaves, the master must send an address FFh. To communicate with slaves A
and B, but not slave C, the master can send and address FBh.
Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and
broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial
port will reply to any address, and so, that it is backwards compatible with the 80C51
microcontrollers that do not support automatic address recognition.
Table 7. SADEN Register
SADEN - Slave Address Mask Register (B9h)
7
6
5
4
3
2
1
0
3
2
1
0
Reset Value = 0000 0000b
Not bit addressable
Table 8. SADDR Register
SADDR - Slave Address Register (A9h)
7
6
5
4
Reset Value = 0000 0000b
Not bit addressable
19
4184I–8051–02/08
Table 9. SCON Register
SCON - Serial Control Register (98h)
7
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Number
7
Bit
Mnemonic Description
FE
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
SM0
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
SM1
Serial port Mode bit 1
Mode Description
SM0 SM1
0
0
0
Shift Register
0
1
1
8-bit UART
1
0
2
9-bit UART
1
1
3
9-bit UART
5
SM2
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1. This bit should be cleared in mode 0.
4
REN
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
3
TB8
6
Baud Rate
FXTAL/12 (/6 in X2 mode)
Variable
FXTAL/64 or FXTAL/32 (/32, /16 in X2 mode)
Variable
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.
2
RB8
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1
0
TI
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the
stop bit in the other modes.
RI
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 7. and Figure
8. in the other modes.
Reset Value = 0000 0000b
Bit addressable
20
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
Table 10. PCON Register
PCON - Power Control Register (87h)
7
6
5
4
3
2
1
0
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
Bit
Bit
Number
Mnemonic
7
SMOD1
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6
SMOD0
Serial port Mode bit 0
Clear to select SM0 bit in SCON register.
Set to to select FE bit in SCON register.
5
-
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
POF
Power-off Flag
Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set
by software.
3
GF1
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2
GF0
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1
PD
Power-down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0
IDL
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
Reset Value = 00X1 0000b
Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset
doesn’t affect the value of this bit.
21
4184I–8051–02/08
Interrupt System
The TS80C52X2 has a total of 6 interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (timers 0, 1 and 2) and the serial port interrupt. These interrupts are shown in Figure 9.
Figure 9. Interrupt Control System
High priority
interrupt
IPH, IP
INT0
3
IE0
0
3
TF0
0
INT1
Interrupt
polling
sequence, decreasing from
high to low priority
3
IE1
0
3
TF1
0
RI
TI
3
TF2
EXF2
3
0
0
Individual Enable
Low priority
interrupt
Global Disable
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (See Table 12.). This register also contains a
global disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (See Table 13.) and in the
Interrupt Priority High register (See Table 14.). shows the bit values and priority levels
associated with each combination.
Table 11. Priority Level Bit Values
IPH.x
IP.x
Interrupt Level Priority
0
0
0 (Lowest)
0
1
1
1
0
2
1
1
3 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another
low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of higher priority level is serviced. If interrupt requests of the same priority level
22
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
are received simultaneously, an internal polling sequence determines which request is
serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Table 12. IE Register
IE - Interrupt Enable Register (A8h)
7
6
5
4
3
2
1
0
EA
-
ET2
ES
ET1
EX1
ET0
EX0
Bit
Number
Bit
Mnemonic Description
Enable All interrupt bit
Clear to disable all interrupts.
Set to enable all interrupts.
If EA=1, each interrupt source is individually enabled or disabled by setting or
clearing its own interrupt enable bit.
7
EA
6
-
5
ET2
Timer 2 overflow interrupt Enable bit
Clear to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
4
ES
Serial port Enable bit
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
3
ET1
Timer 1 overflow interrupt Enable bit
Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2
EX1
External interrupt 1 Enable bit
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
1
ET0
Timer 0 overflow interrupt Enable bit
Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0
EX0
External interrupt 0 Enable bit
Clear to disable external interrupt 0.
Set to enable external interrupt 0.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = 0X00 0000b
Bit addressable
23
4184I–8051–02/08
Table 13. IP Register
IP - Interrupt Priority Register (B8h)
7
6
5
4
3
2
1
0
-
-
PT2
PS
PT1
PX1
PT0
PX0
Bit
Bit
Number
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
PT2
Timer 2 overflow interrupt Priority bit
Refer to PT2H for priority level.
4
PS
Serial port Priority bit
Refer to PSH for priority level.
3
PT1
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
2
PX1
External interrupt 1 Priority bit
Refer to PX1H for priority level.
1
PT0
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
0
PX0
External interrupt 0 Priority bit
Refer to PX0H for priority level.
Description
Reset Value = XX00 0000b
Bit addressable
24
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
Table 14. IPH Register
IPH - Interrupt Priority High Register (B7h)
7
6
5
4
3
2
1
0
-
-
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
4
3
2
1
0
PT2H
Timer 2 overflow interrupt Priority High bit
PT2H PT2 Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PSH
Serial port Priority High bit
PSH PS
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PT1H
Timer 1 overflow interrupt Priority High bit
PT1H PT1 Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PX1H
External interrupt 1 Priority High bit
PX1H PX1 Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PT0H
Timer 0 overflow interrupt Priority High bit
PT0H PT0 Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PX0H
External interrupt 0 Priority High bit
PX0H PX0 Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
Reset Value = XX00 0000b
Not bit addressable
25
4184I–8051–02/08
An instruction that sets PCON.0 causes that to be the last instruction executed before
going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the
CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirely : the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during Idle. The port pins hold
the logical states they had at the time Idle was activated. ALE and PSEN hold at logic
high levels.
Idle mode
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause
PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to be executed will be the one following
the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during normal operation or during an Idle. For example, an instruction that activates Idle
can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt
service routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycles (24 oscillator periods) to complete the reset.
Power-down Mode
To save maximum power, a power-down mode can be invoked by software (Refer to
Table 10., PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked powerdown mode is the last instruction executed. The internal RAM and SFRs retain their
value until the power-down mode is terminated. VCC can be lowered to save further
power. Either a hardware reset or an external interrupt can cause an exit from powerdown. To properly terminate power-down, the reset or external interrupt should not be
executed before VCC is restored to its normal operating level and must be held active
long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 and INT1 are useful to exit from power-down. For that,
interrupt must be enabled and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as
detailed in Figure 10. When both interrupts are enabled, the oscillator restarts as soon
as one of the two inputs is held low and power down exit will be completed when the first
input will be released. In this case the higher priority interrupt service routine is executed.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the
one following the instruction that put TS80C52X2 into power-down mode.
Figure 10. Power-down Exit Waveform
INT0
INT1
XTAL1
Active phase
26
Power-down phase
Oscillator restart phase
Active phase
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
Exit from power-down by reset redefines all the SFRs, exit from power-down by external
interrupt does no affect the SFRs.
Exit from power-down by either reset or external interrupt does not affect the internal
RAM content.
Note:
If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence
is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and
idle mode is not entered.
Table 15. The State of Ports During Idle and Power-down Modes
Mode
Program
Memory
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Idle
Internal
1
1
Port
Data(1)
Port Data
Port Data
Port Data
Idle
External
1
1
Floating
Port Data
Address
Port Data
Power
Down
Internal
0
0
Port
Data(1)
Port Data
Port Data
Port Data
Power
Down
External
0
0
Floating
Port Data
Port Data
Port Data
Note:
1. Port 0 can force a "zero" level. A "one" will leave port floating.
27
4184I–8051–02/08
ONCETM Mode (ON Chip
Emulation)
The ONCE mode facilitates testing and debugging of systems using TS80C52X2 without removing the circuit from the board. The ONCE mode is invoked by driving certain
pins of the TS80C52X2; the following sequence must be exercised:
•
Pull ALE low while the device is in reset (RST high) and PSEN is high.
•
Hold ALE low as RST is deactivated.
While the TS80C52X2 is in ONCE mode, an emulator or test CPU can be used to drive
the circuit Table 26. shows the status of the port pins during ONCE mode.
Normal operation is restored when normal reset is applied.
Table 16. External Pin Status during ONCE Mode
28
ALE
PSEN
Port 0
Port 1
Port 2
Port 3
XTAL1/2
Weak pullup
Weak pullup
Float
Weak pullup
Weak pullup
Weak pullup
Active
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
Power-off Flag
The power-off flag allows the user to distinguish between a “cold start” reset and a
“warm start” reset.
A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while
VCC is still applied to the device and could be generated for example by an exit from
power-down.
The power-off flag (POF) is located in PCON register (See Table 17.). POF is set by
hardware when VCC rises from 0 to its nominal voltage. The POF can be set or cleared
by software allowing the user to determine the type of reset.
The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value,
reading POF bit will return indeterminate value.
Table 17. PCON Register
PCON - Power Control Register (87h)
7
6
5
4
3
2
1
0
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
Bit
Bit
Number
Mnemonic
7
SMOD1
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6
SMOD0
Serial port Mode bit 0
Clear to select SM0 bit in SCON register.
Set to to select FE bit in SCON register.
5
-
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
POF
Power-off Flag
Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be
set by software.
3
GF1
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2
GF0
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1
PD
Power-down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0
IDL
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
Reset Value = 00X1 0000b
Not bit addressable
29
4184I–8051–02/08
Reduced EMI Mode
The ALE signal is used to demultiplex address and data buses on port 0 when used with
external program or data memory. Nevertheless, during internal code execution, ALE
signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting
AO bit.
The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no
longer output but remains active during MOVX and MOVC instructions and external
fetches. During ALE disabling, ALE pin is weakly pulled high.
Table 18. AUXR Register
AUXR - Auxiliary Register (8Eh)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
AO
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
AO
ALE Output bit
Clear to restore ALE operation during internal fetches.
Set to disable ALE operation during internal fetches.
Reset Value = XXXX XXX0b
Not bit addressable
30
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
TS80C52X2
ROM Structure
The TS80C52X2 ROM memory is divided in three different arrays:
•
the code array:8 Kbytes.
•
the encryption array:64 bytes.
•
the signature array:4 bytes.
ROM Lock System
The program Lock system, when programmed, protects the on-chip program against
software piracy.
Encryption Array
Within the ROM array are 64 bytes of encryption array that are initially unprogrammed
(all FF’s). Every time a byte is addressed during program verify, 6 address lines are
used to select a byte of the encryption array. This byte is then exclusive-NOR’ed
(XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with the
encryption array in the unprogrammed state, will return the code in its original, unmodified form.
When using the encryption array, one important factor needs to be considered. If a byte
has the value FFh, verifying the byte will produce the encryption byte value. If a large
block (>64 bytes) of code is left unprogrammed, a verification routine will display the
content of the encryption array. For this reason all the unused code bytes should be programmed with random values. This will ensure program protection.
Program Lock Bits
The lock bits when programmed according to Table 19. will provide different level of protection for the on-chip code and data.
Table 19. Program Lock bits
Program Lock Bits
Security
level
LB1
LB2
LB3
1
U
U
U
No program lock features enabled. Code verify will still be
encrypted by the encryption array if programmed. MOVC instruction
executed from external program memory returns non encrypted
data.
2
P
U
U
MOVC instruction executed from external program memory are
disabled from fetching code bytes from internal memory, EA is
sampled and latched on reset.
Protection Description
U: unprogrammed
P: programmed
Signature bytes
The TS80C52X2 contains 4 factory programmed signatures bytes. To read these bytes,
perform the process described in section 9.
Verify Algorithm
Refer to Section “Verify Algorithm”.
31
4184I–8051–02/08
EPROM Structure
The TS87C52X2 is divided in two different arrays:
•
the code array: 8 Kbytes
•
the encryption array: 64 bytes
In addition a third non programmable array is implemented:
•
the signature array: 4 bytes
EPROM Lock System
The program Lock system, when programmed, protects the on-chip program against
software piracy.
Encryption Array
Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time a byte is addressed during program verify, 6 address
lines are used to select a byte of the encryption array. This byte is then exclusiveNOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm,
with the encryption array in the unprogrammed state, will return the code in its original,
unmodified form.
When using the encryption array, one important factor needs to be considered. If a byte
has the value FFh, verifying the byte will produce the encryption byte value. If a large
block (>64 bytes) of code is left unprogrammed, a verification routine will display the
content of the encryption array. For this reason all the unused code bytes should be programmed with random values. This will ensure program protection.
Program Lock Bits
The three lock bits, when programmed according to Table 1., will provide different level
of protection for the on-chip code and data.
Program Lock Bits
Security
level
1
LB1
U
LB2
U
LB3
Protection Description
U
No program lock features enabled. Code verify will still be
encrypted by the encryption array if programmed. MOVC
instruction executed from external program memory returns non
encrypted data.
2
P
U
U
MOVC instruction executed from external program memory are
disabled from fetching code bytes from internal memory, EA is
sampled and latched on reset, and further programming of the
EPROM is disabled.
3
U
P
U
Same as 2, also verify is disabled.
4
U
U
P
Same as 3, also external execution is disabled.
U: unprogrammed
P: programmed
WARNING: Security level 2 and 3 should only be programmed after EPROM and Core
verification.
Signature Bytes
The TS80/87C52X2 contains 4 factory programmed signatures bytes. To read these
bytes, perform the process described in section 9.
EPROM Programming
Set-up modes
32
In order to program and verify the EPROM or to read the signature bytes, the
TS87C52X2 is placed in specific set-up modes (See Figure 11.).
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
Control and program signals must be held at the levels indicated in Table 35.
Definition of terms
Address Lines: P1.0-P1.7, P2.0-P2.4 respectively for A0-A12
Data Lines: P0.0-P0.7 for D0-D7
Control Signals: RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7.
Program Signals: ALE/PROG, EA/VPP.
Table 20. EPROM Set-up Modes
Mode
EA/
VPP
P2.6
P2.7
P3.3
P3.6
P3.7
12.75V
0
1
1
1
1
1
0
0
1
1
12.75V
0
1
0
1
1
0
0
0
0
0
12.75V
1
1
1
1
1
1
0
12.75V
1
1
1
0
0
1
0
12.75V
1
0
1
1
0
RST
PSEN
Program Code data
1
0
Verify Code data
1
0
Program Encryption
Array Address 0-3Fh
1
0
Read Signature Bytes
1
0
Program Lock bit 1
1
Program Lock bit 2
Program Lock bit 3
ALE/
PROG
1
1
1
Figure 11. Set-Up Modes Configuration
+5V
PROGRAM SIGNALS*
EA/VPP
VCC
ALE/PROG
CONTROL SIGNALS*
4 to 6 MHz
RST
PSEN
P2.6
P2.7
P3.3
P3.6
P3.7
XTAL1
P0.0-P0.7
D0-D7
P1.0-P1.7
A0-A7
P2.0-P2.4
A8-A12
VSS
GND
* See Table 31. for proper value on these inputs
33
4184I–8051–02/08
The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and
decreases the number of pulses applied during byte programming from 25 to 1.
Programming Algorithm
To program the TS87C52X2 the following sequence must be exercised:
•
Step 1: Activate the combination of control signals.
•
Step 2: Input the valid address on the address lines.
•
Step 3: Input the appropriate data on the data lines.
•
Step 4: Raise EA/VPP from VCC to VPP (typical 12.75V).
•
Step 5: Pulse ALE/PROG once.
•
Step 6: Lower EA/VPP from VPP to VCC
Repeat step 2 through 6 changing the address and data for the entire array or until the
end of the object file is reached (See Figure 12.).
Code array verify must be done after each byte or block of bytes is programmed. In
either case, a complete verify of the programmed array will ensure reliable programming
of the TS87C52X2.
Verify Algorithm
P 2.7 is used to enable data output.
To verify the TS87C52X2 code the following sequence must be exercised:
•
Step 1: Activate the combination of program and control signals.
•
Step 2: Input the valid address on the address lines.
•
Step 3: Read data on the data lines.
Repeat step 2 through 3 changing the address for the entire array verification (See Figure 12.)
The encryption array cannot be directly verified. Verification of the encryption array is
done by observing that the code array is well encrypted.
Figure 12. Programming and Verification Signal’s Waveform
Programming Cycle
Read/Verify Cycle
A0-A12
D0-D7
Data In
Data Out
100µs
ALE/PROG
EA/VPP
12.75V
5V
0V
Control signals
EPROM Erasure
(Windowed Packages
Only)
Erasing the EPROM erases the code array, the encryption array and the lock bits returning the parts to full functionality.
Erasure Characteristics
The recommended erasure procedure is exposure to ultraviolet light (at 2537 Å) to an
integrated dose at least 15 W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of
34
Erasure leaves all the EPROM cells in a 1’s state (FF).
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
12,000 µW/cm2 rating for 30 minutes, at a distance of about 25 mm, should be sufficient.
An exposure of 1 hour is recommended with most of standard erasers.
Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately 4,000 Å. Since sunlight and fluorescent lighting have
wavelengths in this range, exposure to these light sources over an extended time (about
1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this type of exposure, it is suggested
that an opaque label be placed over the window.
Signature Bytes
The TS80/87C52X2 has four signature bytes in location 30h, 31h, 60h and 61h. To read
these bytes follow the procedure for EPROM verify but activate the control lines provided in Table 31. for Read Signature Bytes. Table 35. shows the content of the
signature byte for the TS80/87C52X2.
Table 21. Signature Bytes Content
Location
Contents
Comment
30h
58h
Manufacturer Code: Atmel
31h
57h
Family Code: C51 X2
60h
2Dh
Product name: TS80C52X2
60h
ADh
Product name:TS87C52X2
60h
20h
Product name: TS80C32X2
61h
FFh
Product revision number
35
4184I–8051–02/08
Electrical
Characteristics
Absolute Maximum
Ratings(1)
Notes:
Ambiant Temperature Under Bias:
C = commercial......................................................0°C to 70°C
I = industrial ........................................................-40°C to 85°C
Storage Temperature .................................... -65°C to + 150°C
Voltage on VCC to VSS .........................................-0.5V to + 7 V
Voltage on VPP to VSS .......................................-0.5V to + 13 V
Voltage on Any Pin to VSS ..........................-0.5V to VCC + 0.5V
Power Dissipation ........................................................... 1 W(2)
Power Consumption
Measurement
1. Stresses at or above those listed under “ Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions may affect device reliability.
2. This value is based on the maximum allowable die
temperature and the thermal resistance of the
package.
Since the introduction of the first C51 devices, every manufacturer made operating Icc
measurements under reset, which made sense for the designs were the CPU was running under reset. In Atmel new devices, the CPU is no more active during reset, so the
power consumption is very low but is not really representative of what will happen in the
customer system. That’s why, while keeping measurements under Reset, Atmel presents a new way to measure the operating Icc:
Using an internal test ROM, the following code is executed:
Label:
SJMP Label (80 FE)
Ports 1, 2, 3 are disconnected, Port 0 is tied to FFh, EA = Vcc, RST = Vss, XTAL2 is not
connected and XTAL1 is driven by the clock.
This is much more representative of the real operating Icc.
DC Parameters for
Standard Voltage
TA = 0°C to +70°C; VSS = 0 V; VCC = 5V ± 10%; F = 0 to 40 MHz.
TA = -40°C to +85°C; VSS = 0 V; VCC = 5V ± 10%; F = 0 to 40 MHz.
Table 22. DC Parameters in Standard Voltage
Symbol
Parameter
Min
VIL
Input Low Voltage
VIH
Input High Voltage except XTAL1, RST
VIH1
Input High Voltage, XTAL1, RST
VOL
VOL1
VOL2
36
Output Low Voltage, ports 1, 2, 3
Output Low Voltage, port 0
(6)
Output Low Voltage, ALE, PSEN
(6)
Typ
Max
Unit
Test Conditions
-0.5
0.2 VCC - 0.1
V
0.2 VCC + 0.9
VCC + 0.5
V
0.7 VCC
VCC + 0.5
V
0.3
V
IOL = 100 µA(4)
0.45
V
IOL = 1.6 mA(4)
1.0
V
IOL = 3.5 mA(4)
0.3
V
IOL = 200 µA(4)
0.45
V
IOL = 3.2 mA(4)
1.0
V
IOL = 7.0 mA(4)
0.3
V
IOL = 100 µA(4)
0.45
V
IOL = 1.6 mA(4)
1.0
V
IOL = 3.5 mA(4)
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
Table 22. DC Parameters in Standard Voltage (Continued)
Symbol
VOH
VOH1
VOH2
RRST
Parameter
Min
Output High Voltage, ports 1, 2, 3
Output High Voltage, port 0
Output High Voltage,ALE, PSEN
RST Pulldown Resistor
Typ
Max
Unit
VCC - 0.3
V
VCC - 0.7
V
VCC - 1.5
V
VCC - 0.3
V
VCC - 0.7
V
VCC - 1.5
V
VCC - 0.3
V
VCC - 0.7
V
VCC - 1.5
V
50
90 (5)
200
kΩ
Test Conditions
IOH = -10 µA
IOH = -30 µA
IOH = -60 µA
VCC = 5V ± 10%
IOH = -200 µA
IOH = -3.2 mA
IOH = -7.0 mA
VCC = 5V ± 10%
IOH = -100 µA
IOH = -1.6 mA
IOH = -3.5 mA
VCC = 5V ± 10%
IIL
Logical 0 Input Current ports 1, 2 and 3
-50
µA
Vin = 0.45V
ILI
Input Leakage Current
±10
µA
0.45V < Vin < VCC
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3
-650
µA
Vin = 2.0 V
CIO
Capacitance of I/O Buffer
10
pF
Fc = 1 MHz
TA = 25°C
IPD
Power Down Current
50
µA
2.0 V < VCC < 5.5V(3)
20 (5)
ICC
under
Power Supply Current Maximum values, X1 mode: (7)
RESET
ICC
operating
1 + 0.4 Freq
(MHz)
at12MHz 5.8
at16MHz 7.4
Power Supply Current Maximum values, X1 mode:
(7)
3 + 0.6 Freq
(MHz)
at12MHz 10.2
mA
mA
at16MHz 12.6
ICC
idle
Power Supply Current Maximum values, X1 mode: (7)
0.25+0.3 Freq
(MHz)
at12MHz 3.9
mA
VCC = 5.5V(1)
VCC = 5.5V(8)
VCC = 5.5V(2)
at16MHz 5.1
37
4184I–8051–02/08
DC Parameters for Low
Voltage
TA = 0°C to +70°C; VSS = 0 V; VCC = 2.7 V to 5.5V ; F = 0 to 30 MHz.
TA = -40°C to +85°C; VSS = 0 V; VCC = 2.7 V to 5.5V ; F = 0 to 30 MHz.
Table 23. DC Parameters for Low Voltage
Symbol
Parameter
Min
VIL
Input Low Voltage
VIH
Input High Voltage except XTAL1, RST
VIH1
Input High Voltage, XTAL1, RST
VOL
Max
Unit
-0.5
0.2 VCC - 0.1
V
0.2 VCC + 0.9
VCC + 0.5
V
0.7 VCC
VCC + 0.5
V
Output Low Voltage, ports 1, 2, 3 (6)
0.45
V
IOL = 0.8 mA(4)
VOL1
Output Low Voltage, port 0, ALE, PSEN (6)
0.45
V
IOL = 1.6 mA(4)
VOH
Output High Voltage, ports 1, 2, 3
0.9 VCC
V
IOH = -10 µA
VOH1
Output High Voltage, port 0, ALE, PSEN
0.9 VCC
V
IOH = -40 µA
IIL
Logical 0 Input Current ports 1, 2 and 3
-50
µA
Vin = 0.45V
ILI
Input Leakage Current
±10
µA
0.45V < Vin < VCC
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3
-650
µA
Vin = 2.0 V
200
kΩ
10
pF
RRST
RST Pulldown Resistor
CIO
Capacitance of I/O Buffer
IPD
Power Down Current
ICC
under
RESET
ICC
operating
Power Supply Current Maximum values, X1
mode: (7)
50
Typ
90
(5)
20 (5)
50
(5)
30
10
1 + 0.2 Freq
(MHz)
at12MHz 3.4
idle
Fc = 1 MHz
TA = 25°C
VCC = 2.0 V to 5.5V(3)
µA
VCC = 2.0 V to 3.3 V(3)
mA
VCC = 3.3 V(1)
at16MHz 4.2
Power Supply Current Maximum values, X1
mode: (7)
1 + 0.3 Freq
(MHz)
at12MHz 4.6
at16MHz 5.8
ICC
Test Conditions
Power Supply Current Maximum values, X1
mode: (7)
mA
VCC = 3.3 V(8)
0.15 Freq
(MHz) + 0.2
at12MHz 2
mA
VCC = 3.3 V(2)
at16MHz 2.6
Notes:
38
1. ICC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 17.), VIL =
VSS + 0.5V,
VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used..
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC 0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 15.).
3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 16.).
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
7. For other values, please contact your sales office.
8. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 17.), VIL =
VSS + 0.5V,
VIH = VCC - 0.5V; XTAL2 N.C.; EA = Port 0 = VCC; RST = VSS. The internal ROM runs the code 80 FE (label: SJMP label). ICC
would be slightly higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is
the worst case.
Figure 13. ICC Test Condition, under reset
VCC
ICC
VCC
P0
VCC
RST
(NC)
CLOCK
SIGNAL
VCC
EA
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 14. Operating ICC Test Condition
VCC
ICC
VCC
P0
Reset = Vss after a high pulse
during at least 24 clock cycles
RST
(NC)
CLOCK
SIGNAL
VCC
EA
XTAL2
XTAL1
All other pins are disconnected.
VSS
Figure 15. ICC Test Condition, Idle Mode
VCC
ICC
VCC
Reset = Vss after a high pulse
during at least 24 clock cycles
RST
(NC)
CLOCK
SIGNAL
VCC
P0
XTAL2
XTAL1
VSS
EA
All other pins are disconnected.
39
4184I–8051–02/08
Figure 16. ICC Test Condition, Power-down Mode
VCC
ICC
VCC
Reset = Vss after a high pulse
during at least 24 clock cycles
(NC)
VCC
P0
RST
EA
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 17. Clock Signal Waveform for ICC Tests in Active and Idle Modes
VCC-0.5V
0.45V
TCLCH
TCHCL
TCLCH = TCHCL = 5ns.
0.7VCC
0.2VCC-0.1
AC Parameters
Explanation of the AC
Symbols
Each timing symbol has 5 characters. The first character is always a “T” (stands for
time). The other characters, depending on their positions, stand for the name of a signal
or the logical status of that signal. The following is a list of all the characters and what
they stand for.
Example:TAVLL = Time for Address Valid to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.
TA = 0 to +70°C (commercial temperature range); VSS = 0 V; VCC = 5V ± 10%; -M and -V
ranges.
TA = -40°C to +85°C (industrial temperature range); VSS = 0 V; VCC = 5V ± 10%; -M and
-V ranges.
TA = 0 to +70°C (commercial temperature range); VSS = 0 V; 2.7 V < VCC < 5.5V; -L
range.
TA = -40°C to +85°C (industrial temperature range); VSS = 0 V; 2.7 V < VCC < 5.5V; -L
range.
Table 24. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3,
and ALE and PSEN signals. Timings will be guaranteed if these capacitances are
respected. Higher capacitance values can be used, but timings will then be degraded.
Table 24. Load Capacitance versus speed range, in pF
-M
-V
-L
Port 0
100
50
100
Port 1, 2, 3
80
50
80
ALE / PSEN
100
30
100
Table 5., Table 29. and Table 32. give the description of each AC symbols.
Table 27., Table 30. and Table 33. give for each range the AC parameter.
40
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
Table 28., Table 31. and Table 34. give the frequency derating formula of the AC parameter. To calculate each AC symbols, take the x value corresponding to the speed grade
you need (-M, -V or -L) and replace this value in the formula. Values of the frequency
must be limited to the corresponding speed grade:
Table 25. Max frequency for derating formula regarding the speed grade
-M X1 mode
-M X2 mode
-V X1 mode
-V X2 mode
-L X1 mode
-L X2 mode
Freq (MHz)
40
20
40
30
30
20
T (ns)
25
50
25
33.3
33.3
50
Example:
TLLIV in X2 mode for a -V part at 20 MHz (T = 1/20E6 = 50 ns):
x= 22 (Table 28.)
T= 50ns
TLLIV= 2T - x = 2 x 50 - 22 = 78ns
External Program Memory
Characteristics
Table 26. Symbol Description
Symbol
T
Parameter
Oscillator clock period
TLHLL
ALE pulse width
TAVLL
Address Valid to ALE
TLLAX
Address Hold After ALE
TLLIV
ALE to Valid Instruction In
TLLPL
ALE to PSEN
TPLPH
PSEN Pulse Width
TPLIV
PSEN to Valid Instruction In
TPXIX
Input Instruction Hold After PSEN
TPXIZ
Input Instruction FloatAfter PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid Instruction In
TPLAZ
PSEN Low to Address Float
41
4184I–8051–02/08
Table 27. AC Parameters for Fix Clock
-V
X2 mode
30 MHz
-M
Speed
40 MHz
Max
60 MHz
equiv.
Max
-L
-L
standard
mode 40
MHz
X2 mode
standard
mode
40 MHz
equiv.
Min
25
33
25
50
33
ns
TLHLL
40
25
42
35
52
ns
TAVLL
10
4
12
5
13
ns
TLLAX
10
4
12
5
13
ns
78
Max
Units
T
45
Max
30 MHz
Min
70
Min
20 MHz
Symbol
TLLIV
Min
-V
Min
Max
65
98
ns
TLLPL
15
9
17
10
18
ns
TPLPH
55
35
60
50
75
ns
TPLIV
TPXIX
35
0
25
50
0
30
0
0
55
0
ns
ns
TPXIZ
18
12
20
10
18
ns
TAVIV
85
53
95
80
122
ns
TPLAZ
10
10
10
10
10
ns
Table 28. AC Parameters for a Variable Clock: derating formula
42
Symbol
Type
Standard
Clock
X2 Clock
-M
-V
-L
Units
TLHLL
Min
2T-x
T-x
10
8
15
ns
TAVLL
Min
T-x
0.5 T - x
15
13
20
ns
TLLAX
Min
T-x
0.5 T - x
15
13
20
ns
TLLIV
Max
4T-x
2T-x
30
22
35
ns
TLLPL
Min
T-x
0.5 T - x
10
8
15
ns
TPLPH
Min
3T-x
1.5 T - x
20
15
25
ns
TPLIV
Max
3T-x
1.5 T - x
40
25
45
ns
TPXIX
Min
x
x
0
0
0
ns
TPXIZ
Max
T-x
0.5 T - x
7
5
15
ns
TAVIV
Max
5T-x
2.5 T - x
40
30
45
ns
TPLAZ
Max
x
x
10
10
10
ns
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
External Program Memory
Read Cycle
Figure 18. External Program Memory Read Cycle
12 TCLCL
TLHLL
TLLIV
ALE
TLLPL
TPLPH
PSEN
PORT 0
TLLAX
TAVLL
INSTR IN
TPLIV
TPLAZ
A0-A7
TPXIX
INSTR IN
TPXAV
TPXIZ
A0-A7
INSTR IN
TAVIV
PORT 2
ADDRESS
OR SFR-P2
External Data Memory
Characteristics
ADDRESS A8-A15
ADDRESS A8-A15
Table 29. Symbol Description
Symbol
Parameter
TRLRH
RD Pulse Width
TWLWH
WR Pulse Width
TRLDV
RD to Valid Data In
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
TLLDV
ALE to Valid Data In
TAVDV
Address to Valid Data In
TLLWL
ALE to WR or RD
TAVWL
Address to WR or RD
TQVWX
Data Valid to WR Transition
TQVWH
Data set-up to WR High
TWHQX
Data Hold After WR
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE high
43
4184I–8051–02/08
Table 30. AC Parameters for a Fix Clock
-V
X2 mode
30 MHz
Speed
-M
40 MHz
175
ns
TWLWH
130
85
135
125
175
ns
102
0
Max
Units
125
0
Min
30 MHz
135
60
Max
40 MHz
equiv.
85
0
Min
20 MHz
130
Min
95
0
Max
137
0
ns
ns
TRHDZ
30
18
35
25
42
ns
TLLDV
160
98
165
155
222
ns
TAVDV
165
100
175
160
235
ns
130
ns
TLLWL
50
TAVWL
75
47
80
70
103
ns
TQVWX
10
7
15
5
13
ns
TQVWH
160
107
165
155
213
ns
TWHQX
15
9
17
10
18
ns
TRLAZ
TWHLH
44
standard
mode 40
MHz
TRLRH
100
Max
-L
standard
mode
Min
TRHDX
Min
-L
X2 mode
Symbol
TRLDV
Max
60 MHz
equiv.
-V
100
30
0
10
40
70
55
0
7
27
95
45
0
15
35
105
70
0
5
45
13
0
ns
53
ns
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
Table 31. AC Parameters for a Variable Clock: Derating Formula
Symbol
Type
Standard
Clock
X2 Clock
-M
-V
-L
Units
TRLRH
Min
6T-x
3T-x
20
15
25
ns
TWLWH
Min
6T-x
3T-x
20
15
25
ns
TRLDV
Max
5T-x
2.5 T - x
25
23
30
ns
TRHDX
Min
x
x
0
0
0
ns
TRHDZ
Max
2T-x
T-x
20
15
25
ns
TLLDV
Max
8T-x
4T -x
40
35
45
ns
TAVDV
Max
9T-x
4.5 T - x
60
50
65
ns
TLLWL
Min
3T-x
1.5 T - x
25
20
30
ns
TLLWL
Max
3T+x
1.5 T + x
25
20
30
ns
TAVWL
Min
4T-x
2T-x
25
20
30
ns
TQVWX
Min
T-x
0.5 T - x
15
10
20
ns
TQVWH
Min
7T-x
3.5 T - x
15
10
20
ns
TWHQX
Min
T-x
0.5 T - x
10
8
15
ns
TRLAZ
Max
x
x
0
0
0
ns
TWHLH
Min
T-x
0.5 T - x
15
10
20
ns
TWHLH
Max
T+x
0.5 T + x
15
10
20
ns
External Data Memory Write
Cycle
Figure 19. External Data Memory Write Cycle
TWHLH
ALE
PSEN
TLLWL
TWLWH
WR
TLLAX
PORT 0
PORT 2
A0-A7
ADDRESS
OR SFR-P2
TQVWX
TQVWH
TWHQX
DATA OUT
TAVWL
ADDRESS A8-A15 OR SFR P2
45
4184I–8051–02/08
External Data Memory Read
Cycle
Figure 20. External Data Memory Read Cycle
TWHLH
TLLDV
ALE
PSEN
TLLWL
TRLRH
TRLDV
RD
TLLAX
PORT 0
PORT 2
TRHDZ
TAVDV
TRHDX
A0-A7
TRLAZ
TAVWL
ADDRESS
OR SFR-P2
Serial Port Timing - Shift
Register Mode
DATA IN
ADDRESS A8-A15 OR SFR P2
Table 32. Symbol Description
Symbol
Parameter
TXLXL
Serial port clock cycle time
TQVHX
Output data set-up to clock rising edge
TXHQX
Output data hold after clock rising edge
TXHDX
Input data hold after clock rising edge
TXHDV
Clock rising edge to input data valid
Table 33. AC Parameters for a Fix Clock
-V
X2 mode
30 MHz
-M
Speed
Max
60 MHz
equiv.
Max
standard
mode 40
MHz
-L
20 MHz
standard
mode
Max
Max
200
300
300
400
ns
TQVHX
200
117
200
200
283
ns
TXHQX
30
13
30
30
47
ns
TXHDX
0
0
0
0
0
ns
117
Min
Units
300
117
Min
30 MHz
TXLXL
34
Min
40 MHz
equiv.
Min
117
Min
-L
X2 mode
Symbol
TXHDV
46
40 MHz
-V
Max
200
ns
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
Table 34. AC Parameters for a Variable Clock: Derating Formula
Symbol
Type
Standard
Clock
X2 Clock
TXLXL
Min
12 T
6T
TQVHX
Min
10 T - x
5T-x
50
50
50
ns
TXHQX
Min
2T-x
T-x
20
20
20
ns
TXHDX
Min
x
x
0
0
0
ns
TXHDV
Max
10 T - x
5 T- x
133
133
133
ns
-M
-V
-L
Units
ns
Shift Register Timing
Waveforms
Figure 21. Shift Register Timing Waveforms
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
TXLXL
CLOCK
TQVXH
OUTPUT DATA
WRITE to SBUF
INPUT DATA
CLEAR RI
TXHQX
0
1
2
3
4
5
6
7
TXHDX
TXHDV
VALID
VALID
VALID
SET TI
VALID
VALID
VALID
VALID
VALID
SET RI
47
4184I–8051–02/08
EPROM Programming and
Verification Characteristics
TA = 21°C to 27°C; VSS = 0V; VCC = 5V ± 10% while programming. VCC = operating
range while verifying.
Table 35. EPROM Programming Parameters
Symbol
Parameter
Min
Max
Units
VPP
Programming Supply Voltage
12.5
13
V
IPP
Programming Supply Current
75
mA
6
MHz
1/TCLCL
Oscillator Frquency
4
TAVGL
Address Setup to PROG Low
48 TCLCL
TGHAX
Adress Hold after PROG
48 TCLCL
TDVGL
Data Setup to PROG Low
48 TCLCL
TGHDX
Data Hold after PROG
48 TCLCL
TEHSH
(Enable) High to VPP
48 TCLCL
TSHGL
VPP Setup to PROG Low
10
µs
TGHSL
VPP Hold after PROG
10
µs
TGLGH
PROG Width
90
TAVQV
Address to Valid Data
48 TCLCL
TELQV
ENABLE Low to Data Valid
48 TCLCL
TEHQZ
Data Float after ENABLE
0
110
µs
48 TCLCL
EPROM Programming and
Verification Waveforms
Figure 22. EPROM Programming and Verification Waveforms
PROGRAMMING
P1.0-P1.7
P2.0-P2.5
P3.4-P3.5*
P
ADDRESS
ADDRESS
TAVQV
P0
DATA OUT
DATA IN
TGHDX
TGHAX
TDVGL
TAVGL
ALE/PROG
EA/VPP
VERIFICATION
TSHGL
TGLGH
VCC
CONTROL
SIGNALS
(ENABLE)
TGHSL
VPP
TEHSH
VCC
TELQV
TEHQZ
* 8KB: up to P2.4, 16KB: up to P2.5, 32KB: up to P3.4, 64KB: up to P3.5
48
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
External Clock Drive
Characteristics (XTAL1)
Table 36. AC Parameters
Symbol
Parameter
Min
Max
Units
TCLCL
Oscillator Period
25
ns
TCHCX
High Time
5
ns
TCLCX
Low Time
5
ns
TCLCH
Rise Time
5
ns
TCHCL
Fall Time
5
ns
60
%
TCHCX/TCLCX
Cyclic ratio in X2 mode
40
External Clock Drive
Waveforms
Figure 23. External Clock Drive Waveforms
VCC-0.5V
0.45V
0.7VCC
0.2VCC-0.1 V
TCHCL
TCLCX
TCHCX
TCLCH
TCLCL
AC Testing Input/Output
Waveforms
Figure 24. AC Testing Input/Output Waveforms
VCC-0.5V
INPUT/OUTPUT
0.2VCC+0.9
0.2VCC-0.1
0.45V
AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”.
Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”.
Float Waveforms
Figure 25. Float Waveforms
FLOAT
VOH-0.1 V VLOAD
VOL+0.1 V
VLOAD+0.1 V
VLOAD-0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load
voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level
occurs. IOL/IOH ≥ ± 20mA.
49
4184I–8051–02/08
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2
divided by two.
Clock Waveforms
Figure 26. Clock Waveforms
INTERNAL
CLOCK
STATE4
P1P2
STATE5
STATE6
STATE1
STATE2
P1P2
P1P2
P1P2
P1P2
STATE3
P1P2
STATE4
P1P2
STATE5
P1P2
XTAL2
ALE
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
EXTERNAL PROGRAM MEMORY FETCH
PSEN
P0
DATA
SAMPLED
FLOAT
P2 (EXT)
PCL OUT
DATA
SAMPLED
FLOAT
PCL OUT
DATA
SAMPLED
FLOAT
PCL OUT
INDICATES ADDRESS TRANSITIONS
READ CYCLE
RD
P0
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
DPL OR Rt
FLOAT
P2
INDICATES DPH OR P2 SFR TO PCH TRANSITION
WRITE CYCLE
WR
P0
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
DPL OR Rt
DATA OUT
P2
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
PORT OPERATION
OLD DATA
P0 PINS SAMPLED
NEW DATA
P0 PINS SAMPLED
MOV DEST P0
MOV DEST PORT (P1, P2, P3)
(INCLUDES INT0, INT1, TO, T1)
P1, P2, P3 PINS SAMPLED
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
RXD SAMPLED
P1, P2, P3 PINS SAMPLED
RXD SAMPLED
This diagram indicates when signals are clocked internally. The time it takes the signals
to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is
dependent on variables such as temperature and pin loading. Propagation also varies
from output to output and component. Typically though (TA = 25°C fully loaded) RD and
WR propagation delays are approximately 50ns. The other signals are typically 85 ns.
Propagation delays are incorporated in the AC specifications.
50
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
Ordering Information
Table 37. Possible Ordering Entries
Part Number(3)
Memory Size
Supply Voltage
Temperature
Range
Max Frequency
Package
Packing
TS80C32X2-MCA
TS80C32X2-MCB
TS80C32X2-MCC
TS80C32X2-MCE
TS80C32X2-LCA
TS80C32X2-LCB
TS80C32X2-LCC
TS80C32X2-LCE
TS80C32X2-VCA
TS80C32X2-VCB
TS80C32X2-VCC
TS80C32X2-VCE
OBSOLETE
TS80C32X2-MIA
TS80C32X2-MIB
TS80C32X2-MIC
TS80C32X2-MIE
TS80C32X2-LIA
TS80C32X2-LIB
TS80C32X2-LIC
TS80C32X2-LIE
TS80C32X2-VIA
TS80C32X2-VIB
TS80C32X2-VIC
TS80C32X2-VIE
AT80C32X2-3CSUM
ROMLess
5V ±10%
Industrial & Green
40 MHz(1)
PDIL40
Stick
AT80C32X2-SLSUM
ROMLess
5V ±10%
Industrial & Green
40 MHz(1)
PLCC44
Stick
(1)
VQFP44
Tray
AT80C32X2-RLTUM
ROMLess
5V ±10%
Industrial & Green
40 MHz
AT80C32X2-RLRUM
ROMLess
5V ±10%
Industrial & Green
40 MHz(1)
VQFP44
Tape & Reel
(1)
PLCC44
Tape & Reel
PDIL40
Stick
AT80C32X2-SLRUM
ROMLess
5V ±10%
Industrial & Green
40 MHz
AT80C32X2-3CSUL
ROMLess
2.7 to 5.5V
Industrial & Green
30 MHz(1)
52
4184I–8051–02/08
Table 37. Possible Ordering Entries (Continued)
Part Number(3)
Memory Size
Supply Voltage
Temperature
Range
Max Frequency
Package
AT80C32X2-SLSUL
ROMLess
2.7 to 5.5V
Industrial & Green
30 MHz(1)
PLCC44
Stick
AT80C32X2-RLTUL
ROMLess
2.7 to 5.5V
Industrial & Green
30 MHz(1)
VQFP44
Tray
AT80C32X2-3CSUV
ROMLess
5V ±10%
Industrial & Green
60 MHz(3)
PDIL40
Stick
AT80C32X2-SLSUV
ROMLess
5V ±10%
Industrial & Green
60 MHz(3)
PLCC44
Stick
AT80C32X2-RLTUV
ROMLess
5V ±10%
Industrial & Green
60 MHz(3)
VQFP44
Tray
Packing
TS80C52X2zzz-MCA
TS80C52X2zzz-MCB
TS80C52X2zzz-MCC
TS80C52X2zzz-MCE
TS80C52X2zzz-LCA
TS80C52X2zzz-LCB
TS80C52X2zzz-LCC
TS80C52X2zzz-LCE
TS80C52X2zzz-VCA
TS80C52X2zzz-VCB
TS80C52X2zzz-VCC
TS80C52X2zzz-VCE
OBSOLETE
TS80C52X2zzz-MIA
TS80C52X2zzz-MIB
TS80C52X2zzz-MIC
TS80C52X2zzz-MIE
TS80C52X2zzz-LIA
TS80C52X2zzz-LIB
TS80C52X2zzz-LIC
TS80C52X2zzz-LIE
TS80C52X2zzz-VIA
TS80C52X2zzz-VIB
TS80C52X2zzz-VIC
TS80C52X2zzz-VIE
AT80C52X2zzz-3CSUM
8K ROM
5V ±10%
Industrial & Green
40 MHz(1)
PDIL40
Stick
AT80C52X2zzz-SLSUM
8K ROM
5V ±10%
Industrial & Green
40 MHz(1)
PLCC44
Stick
53
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
Table 37. Possible Ordering Entries (Continued)
Memory Size
Supply Voltage
Temperature
Range
Max Frequency
Package
AT80C52X2zzz-RLTUM
8K ROM
5V ±10%
Industrial & Green
40 MHz(1)
VQFP44
Tray
AT80C52X2zzz-3CSUL
8K ROM
2.7 to 5.5V
Industrial & Green
30 MHz(1)
PDIL40
Stick
AT80C52X2zzz-SLSUL
8K ROM
2.7 to 5.5V
Industrial & Green
30 MHz(1)
PLCC44
Stick
AT80C52X2zzz-RLTUL
8K ROM
2.7 to 5.5V
Industrial & Green
30 MHz(1)
VQFP44
Tray
AT80C52X2zzz-3CSUV
8K ROM
5V ±10%
Industrial & Green
60 MHz(3)
PDIL40
Stick
AT80C52X2zzz-SLSUV
8K ROM
5V ±10%
Industrial & Green
60 MHz(3)
PLCC44
Stick
AT80C52X2zzz-RLTUV
8K ROM
5V ±10%
Industrial & Green
60 MHz(3)
VQFP44
Tray
PDIL40
Stick
Part Number(3)
Packing
TS87C52X2-MCA
TS87C52X2-MCB
TS87C52X2-MCC
TS87C52X2-MCE
TS87C52X2-LCA
TS87C52X2-LCB
TS87C52X2-LCC
TS87C52X2-LCE
TS87C52X2-VCA
TS87C52X2-VCB
TS87C52X2-VCC
TS87C52X2-VCE
OBSOLETE
TS87C52X2-MIA
TS87C52X2-MIB
TS87C52X2-MIC
TS87C52X2-MIE
TS87C52X2-LIA
TS87C52X2-LIB
TS87C52X2-LIC
TS87C52X2-LIE
TS87C52X2-VIA
TS87C52X2-VIB
TS87C52X2-VIC
TS87C52X2-VIE
AT87C52X2-3CSUM
8K OTP
5V ±10%
Industrial & Green
40 MHz(1)
54
4184I–8051–02/08
Table 37. Possible Ordering Entries (Continued)
Part Number(3)
Memory Size
Supply Voltage
Temperature
Range
Max Frequency
Package
AT87C52X2-SLSUM
8K OTP
5V ±10%
Industrial & Green
40 MHz(1)
PLCC44
Stick
AT87C52X2-RLTUM
8K OTP
5V ±10%
Industrial & Green
40 MHz(1)
VQFP44
Tray
AT87C52X2-3CSUL
8K OTP
2.7 to 5.5V
Industrial & Green
30 MHz(1)
PDIL40
Stick
AT87C52X2-SLSUL
8K OTP
2.7 to 5.5V
Industrial & Green
30 MHz(1)
PLCC44
Stick
AT87C52X2-RLTUL
8K OTP
2.7 to 5.5V
Industrial & Green
30 MHz(1)
VQFP44
Tray
AT87C52X2-3CSUV
8K OTP
5V ±10%
Industrial & Green
60 MHz(3)
PDIL40
Stick
AT87C52X2-SLSUV
8K OTP
5V ±10%
Industrial & Green
60 MHz(3)
PLCC44
Stick
AT87C52X2-RLTUV
8K OTP
5V ±10%
Industrial & Green
60 MHz(3)
VQFP44
Tray
Notes:
55
Packing
1. 20 MHz in X2 Mode.
2. Tape and Reel available for SL, PQFP and RL packages
3. 30 MHz in X2 Mode.
TS8xCx2X2
4184I–8051–02/08
Atmel Headquarters
Atmel Operations
Corporate Headquarters
Memory
2325 Orchard Parkway
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TEL 1(408) 441-0311
FAX 1(408) 487-2600
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Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
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TEL 1(408) 441-0311
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Postfach 3535
74025 Heilbronn, Germany
TEL (49) 71-31-67-0
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TEL 1(408) 441-0311
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