CS22220 Data Sheet
Wireless PCMCIA Controller
1
Description
The Cirrus Logic CS22220 Wireless Network Controller enables high performance, 11 Megabits per
second digital wireless data connectivity for PCMCIA, mobile, embedded systems and other cost
sensitive applications.
The CS22220 is a highly integrated single-chip PCMCIA solution for wireless networks supporting
video, audio, voice, and data traffic. The programmable controller executes Cirrus Logic’s
Whitecap™2 networking protocol that provides Wi-Fi™ (802.11b) compliance as well as multimedia
and quality of service (QoS) support. The device includes several high performance components
including an ARM7TDMI RISC processor core, a Forward Error Correction (FEC) codec and a
wireless radio MAC supporting up to11 Mbps throughput. The CS22220 utilizes state of the art
0.18um CMOS process and is housed in a 208 FPBGA compact (15mm x 15mm) package, which
has low-lead inductance suitable for highly integrated radio applications. The core is powered at 1.8
V with 3.3V (5.0V tolerant) I/O to reduce overall power consumption. In addition, the CS22220
supports low power management for the host and radio interfaces.
The CS22220 is designed to be an integral part of a PC card (PCMCIA 2.1/JEIDA 4.2). The
PCMCIA host interface also supports both little endian and big endian protocol for easy interfacing
to popular microprocessors in embedded system applications.
PCMCIA Host or Embedded CPU
Networking Data
802.11b compatible
2.4 GHz
Digital Radio
PHY Transceiver
2.4 GHz Direct Sequence
Spread Spectrum
11 Mbps
Wireless
Baseband I/F
System Memory
SDRAM (Up to 4MB)
SRAM (Up to 256KB)
CS22220
Wireless
PCMCIA
Controller
Boot ROM/Flash
(Up to 1MB)
Figure 1. Example System Block Diagram
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Features
Embedded ARM Core and System Support Logic
• High performance ARM7TDMI RISC processor core up to 77MHz
• 4KB integrated, one-way set associative, unified, write through cache
• Individual interrupt for each functional block
• Two 23-bit programmable (periodic or one-shot) general purpose timers
• 8 Dword (32-bits) memory write and read buffers for high system performance
• Abort cycle detection and reporting for debugging
• ARM performance monitoring function for system fine-tuning
• Programmable performance improvement logic based on system configuration
Enhanced Memory Controller Unit
• Programmable memory controller unit supporting SDRAM /async SRAM/Boot ROM/Flash
interface
•
16-bit data bus with 12-bit address supporting up to 4MB up to 103 MHz (100/133MHz SDRAM)
• 8-bit data bus with addressing support up to 1MB of boot ROM/Flash.
• Programmable SDRAM timing and size parameters such as CAS latencies and number of
banks, columns, and rows
• Flexible independent DMA engines for PCMCIA and digital radio functional units
FEC codec
• High performance Reed-Solomon coding for error correction (255:239 block coding)
• Reduces error probability of a typical 10e-3 error rate environment to 10e-9
• Programmable rate FEC engine to optimize channel efficiency
• Low latency, fully pipelined hardware encoding and decoding. Supports byte-wise single cycle
throughput up to 77MHz, with a sustain rate of 77MBps.
• Double buffering (63 Dword read/write buffer) to enhance system performance
Digital Radio MAC Interface
• Glue-less interface to 802.11b baseband transceivers
• Up to 11Mbps data rates
• 32 Dword transmit/receive FIFO
• Supports clear channel assessment (CCA)
Power Management
• Host (PCMCIA) ACPI compliant
• Programmable sleep timer for ARM core and system low power management
• Independent power management control for individual functional units
• Supports variable rate radio transmit, receive, and standby radio power modes
Clock and PLL Interface
• Single 44MHz crystal oscillator reference clock
• Internal PLL to generate internal and on board clocks
PCMCIA Interface
• 16 bit PCMCIA I/O target device supporting memory map or program I/O using 11 address bits
• Independent DMA controller to transfer data between PCMCIA and main memory
• Fully compliant with PCMCIA 2.1/JEIDA 4.2 standard
• Supports big endian and little endian (default) data formats
• Supports custom mode for embedded applications where the interface becomes a generic
memory address/data interface
Chip Processing and Packaging
• 208 FPBGA package and 0.18um state of the art CMOS process
• 1.8 V core for low power consumption. 3.3V I/O - 5V tolerant I/O
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IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet
available. "Advance" product information describes products that are in development and subject to development changes.
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and
reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind
(express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of
sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation
of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the
basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the
property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask
work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights of the
information contained herein and gives consent for copies to be made of the information only for use within your organization
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copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
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technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be
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Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade
Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH,
PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS").
CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFESUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN
SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product
names in this document may be trademarks or service marks of their respective owners.
Use of this product in any manner that complies with the MPEG-2 video standard as defined in ISO
documents IS 13818-1 (including annexes C, D, F, J, and K), IS 13818-2 (including annexes A, B,
C, and D, but excluding scalable extensions), and IS 13818-4 (only as it is needed to clarify IS
13818-2) is expressly prohibited without a license under applicable patents in the MPEG-2 patent
portfolio, which license is available from MPEG LA, L.L.C. 250 Steele Street, Suite 300, Denver,
Colorado 80296.
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Functional Description
System Memory
Figure 2. Block Diagram of Major Functional Units
Memory/Boot ROM
Controller
Arbiter
DMA
DMA
PCMCIA
JTAG/Test Interface
Read/Write Buffer
PCMCIA
Controller
w/DMA Ctrl
ARM 7TDMI
Interrupt
controller
Timer
(2)
4KB
Cache
Radio MAC
w/ DMA Ctrl
Digital Radio
Interface
System Control Bus
Sleep
Timer
FEC codec
Clock/PLL
Crystal or
Oscillator
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3.1
Embedded ARM Core and System Support Logic
The processing elements of the CS22220 include the ARM7TDMI core and its associated
system control logic. The ARM processor and system controller consists of a memory
management unit, 4-KB write through cache controller, 20 IRQ and 4 FIRQ interrupt
controller, and 2 general purpose timers. The ARM processor and integrated system
support logic provide the necessary execution engine to support a real time multi-tasking
operating system, the network protocol stack, and firmware services.
Memory Management Unit
ARM instructions and data are fetched from system memory a cache-line (4/8 – Dwords
/Programmable) at a time when caching is turned on. During a cache line fill, critical word
data, i.e., the access that caused the miss, is forwarded to the ARM and also written into
the data RAM cache. The non-critical words in the line fetched following the critical word
are then written to the cache on a Dword basis, as they become available.
Memory writes are posted to dual 4-Dwords (32-bit) memory write posting buffers. Write
posts use the sequential addressing feature on the memory bus. With dual buffering an out
of sequence write will post to one write buffer while the other buffer is flushed to memory.
There is one 8Dword Read Buffer in the MEM block. The buffer is used for both cacheable
and non-cacheable memory space.
Interrupt Controller
The interrupt controller provides two interrupt channels to the ARM processor. One
interrupt channel is presented to the ARM on its nFIQ, and the other channel is presented
on its nIRQ pin. These are referred to as the FIQ channel and the IRQ channel. Both
channels operate in identical but independent fashion. The FIQ channel has a higher
priority on the ARM processor than the IRQ channel.
The interrupt controller includes a CONTROL register for each logical interrupt in the ARM
Complex. The CONTROL register serves the following main purposes:
•
•
•
Provides the mapping between the EXT_INT inputs (physical interrupts) and the logical
interrupt
Selects the particular type of signaling expected on the EXT_INT inputs: level, edge,
active level high/low etc.
Enable or disable a logical interrupt
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Digital Radio Interface
The CS22220 digital radio MAC I/F supports multiple radio baseband and RF interfaces.
The baseband registers can be programmed during the configuration time using the control
port interface. The MAC also provides the capability of programming the signal, service and
length on per packet basis without ARM intervention. This significantly improves the
performance of the system.
There are three primary digital interface ports for the CS22220 that are used for
configuration and during normal operation.
These ports are:
• The Control Port, which is used to configure, set power consumption modes, write
and/or read the status of the radio base band registers.
• The TX Port, which is used to output the data that needs to be transmitted from the
network processor.
• The RX Port, which is used to input the received demodulated data to the network
processor
3.3
FEC Codec
The FEC codec performs Reed-Solomon coding to protect the data before it is transmitted
to a noisy channel. It is a similar code as employed by the digital broadcast industry, such
as ITU-T J.83 for DVB. The RS(255, 8) code implemented by the CS22220 can reduce
error probability to 1/10e-9 in a typical 1/10e-3 error rate environment.
The
encoder/decoder can be programmed to vary the coding block length (N) and correctable
error (t) to optimize the tradeoff between channel utilization and data protection. The range
of N is currently set to be from 20 to 255, and the t is 8. The symbol size is fixed at 8 bits.
Coding parameters can be set real time, allowing maximum flexibility for the system to
adjust the FEC setting, such as block size, in order to optimize channel efficiency. The
encoder also has a very low latency of two cycles. Both the encoder and decoder are fully
pipelined in structure to achieve single cycle throughput. The FEC can be disabled in
firmware.
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3.4
Programmable Memory Controller
The CS22220 incorporates a general-purpose memory controller. The memory controller
supports both SDRAM/async SRAM memory interface and a FLASH memory interface.
In the RAM configuration, the system memory interface supports up to 4-Mbyte of 16-bit
SDRAM running at frequency up to 103 MHz (using 133MHz SDRAM) single-state access
cycles or 256KB of 16 bit async SRAM. The memory controller provides programming of
SDRAM parameters such as CAS latency, refresh rate and etc; these registers are located
in miscellaneous configuration registers. The CS22220 memory controller supports the
power saving feature of the SDRAM by toggling the clock enable (CKE) signal. When there
are no pending memory requests from any internal requester, the CS22220 will keep CKE
low to cause the SDRAM to stay in power down mode. Once a memory request is active,
the CS22220 will assert CKE high to cause the SDRAM to come out of power down mode.
Typically, this can reduce memory power consumption by up to 50%.
In ROM configuration, firmware for CS22220 is stored in non-volatile memory and is
accessed through the boot ROM interface. The maximum addressable ROM space
supported is 1MB. ROM read/write and output enable are shared with RAM control pins.
3.5
PCMCIA Interface
The PC-Card interface implemented in Cirrus Logic CS22220 is fully compliant with
PCMCIA 2.1/JEIDA 4.2. The interface supports 16 data bits PCMCIA program I/O and
memory mapped accesses using 11 address bits. PCMCIA interface allows laptop users to
connect to home network to access data and multimedia streams with ease. The interface
provides both memory and I/O access.
The PCMCIA interface incorporates an independent DMA controller to transfer data to/from
the main memory. The ARM has the flexibility in controlling how often it is interrupted and
simplifies the packet transmit/receive protocol. The DMA controller is programmed during
power up.
The CS22220 PCcard interface incorporates a custom mode, which can be used for
embedded applications, by bypassing the standard PC card Pnp configuration
requirements. This interface thus becomes a generic asynchronous 16 bit data interface.
This mode is useful when interfacing the CS22220 wireless network controller directly to an
embedded micro-controller capable of supporting a 16 bit data bus.
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Pinout and Signal Descriptions
Figure 3. CS22220 Logical Pin Groupings
NPCE1
SMCLK
NPCE2
nSMCS[1:0]
NPCOE
nSMRAS
System
Memory
Interface
JTAG
Interface
nPCWE
nSMCAS
nSMWE
SMDQM[1:0]
nPERR, nSERR
CS22220
Controller
nPCREG
nPCIORD
SMCKE
SMA[11:0]
PCIOWR
SMD[15:0]
PCA[10:0]
nBRCE
PCD[15:0]
nPCIRQ
nPCINPACK
TDO
nPCSTSCHG
TDI
nPCWAIT
TCK
NIOIS16
TMS
EXT_RESET
PCMCIA
Interface
nTRST
Clock Interface
PLL Power
Interface
XTRACLK
XTALCLKIN
TXCLK
XTALOUT
TXPE
TXD
PLLAGND
TXRDY
PLLAVCC
CCA
BBRNW
PLLDVCC
PLLDGND
nRESETB
BBAS
PLLPLUS
nBBCS
TXPAPE
NTEST
TXPEBB
RXPEBB
BBSCLK
BBSDX
SYNTHLE
nRPD
RXCLK
MDRDY
RXD
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Digital Radio
Interface
This section provides detailed information on the CS22220 signals. The signal descriptions are
useful for hardware designers who are interfacing the CS22220 with other devices.
System Memory Interface
The system memory interface supports standard SDRAM interface, async SRAM and FLASH.
There are a total of 38 signals in this interface.
SMCLK
Output
System mem clock for SDRAM. Currently the interface supports 100
MHz for a maximum bandwidth of 200Mbytes/sec.
nSMCS0
Output
Chip select bit 0. This signal is used to select or deselect the SDRAM for
command entry. When SMNCS is low it qualifies the sampling of
nSMRAS, nSMCAS and nSMWE. Also, used as testmode(2) when
NTEST pin is '0'.
nSMCS1
Output
Chip select bit 1.
nBRCE
Output
Chip select for ROM access. This signal is used to select or deselect the
boot ROM memory.
nSMRAS
Output
Row address select. Used in combination with nSMCAS, nSMWE and
nSMCS to specify which SDRAM page to open for access. Also used
during reset to latch in the strap value for clk_bypass; if set to a '1' implies
bypassing clock module; whatever clk is applied on the input clock is
used for memclk and ctlclk. Also shared as the ROMOE signal.
nSMCAS
Output
Column address select. Used in combination with nSMRAS, nSMWE and
nSMCS to specify which piece of data to access in selected page. Also
used during reset to latch in the strap value for same_freq; if set to a '1'
implies internal mem_clk and arm_clk are running at the same frequency
and 180 degrees out of phase.
nSMWE
Output
Write enable. Used in combination with nSMRAS, nSMCAS, and
nSMWE to specify whether the current cycle is a read or a write cycle.
Also used during reset to latch in the strap value for tst_bypass; if set to a
'1' implies PLL bypass. Also shared as the ROMWE to do flash
programming.
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SMDQM[1:0]
Output
Data mask bit 1:0. These signals function as byte enable lines masking
unwanted bytes on memory writes. Also, used as testmode(1:0) when
NTEST pin is '0'.
SMCKE
Output
Clock enable. SMCKE is used to enable and disable clocking of internal
RAM logic.
SMA0
Output
Address bit0. The address bus specifies either the row address or
column address. Also, this is shared as boot-ROM address bit0. Also
used during reset to latch in the strap value for pccsel, if set to a '1'
implies pccard mode
SMA1
Output
Address bit1. Also, this is shared as boot-ROM address bit1. This pin
should be pull-down.
SMA2
Output
Address bit2. Also, this is shared as boot-ROM address bit2. This pin
should be pull-down.
SMA3
Output
Address bit3. Also shared as boot-ROM address bit3. This pin should be
pull-down.
SMA4
Output
Address bit4. Also shared as boot-ROM address bit4. Also used during
reset to latch in the strap value for romcfg; if set to a '1' implies pccard
configuration data should be downloaded from ROM.
SMA5
Output
Address bit5. Also shared as boot-ROM address bit5. Also used during
reset to latch in the strap value for test_rst_enb; if set to a '0' implies
normal operation mode.
SMA6
Output
Address bit6. Also shared as boot-ROM address bit6. Also used during
reset to latch in the strap value for freq_sel(0). Freq_sel(2:0) is used to
select the multiplication factor for the internal PLL (000=1x, and 111=8x).
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SMA7
Output
Address bit7. Also shared as boot-ROM address bit7. Also used during
reset to latch in the strap value for freq_sel(1). Freq_sel(2:0) is used to
select the multiplication factor for the internal PLL (000=1x, and 111=8x).
SMA8
Output
Address bit8. Also shared as boot-ROM address bit8. Also used during
reset to latch in the strap value for freq_sel(2). Freq_sel(2:0) is used to
select the multiplication factor for the internal PLL (000=1x, and 111=8x).
SMA9
Output
Address bit9. Also shared as boot-ROM address bit9. Also used during
reset to latch in the strap value for sdram_delay(0). Sdram_delay(2:0) is
used to select the delay factor for the internal memory clock (000=0ns,
and 111=1.75ns with each .25ns increments).
SMA10
Output
Address bit10. Also shared as boot-ROM address bit10. Also used during
reset to latch in the strap value for sdram_delay(1). Sdram_delay(2:0) is
used to select the delay factor for the internal memory clock (000=0ns,
and 111=1.75ns with each .25ns increments).
SMA11
Output
Address bit11. Also shared as boot-ROM address bit11. Also used during
reset to latch in the strap value for sdram_delay(2). Sdram_delay(2:0) is
used to select the delay factor for the internal memory clock (000=0ns,
and 111=1.75ns with each .25ns increments).
SMD[7:0]
Bi-directional
Data bus. The data bus contains the data to be written to memory on a
write cycle and the read return data on a read cycle.
SMD[15:8]
Bi-directional
Shared data bus. The data bus contains the data to be written to RAM
memory on a write cycle and the read return data on a read cycle. Data
bit [15:8] is also shared as boot ROM address bit [19:12].
Digital Radio Interface
All radio input buffers are Schmitt triggered input buffers. There are total of 26 signals in this
interface.
TXCLK
Input
Transmit clock is a clock input from the radio baseband processor. This
signal is used to clock out the transmit data on the rising edge of TXCLK.
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TXPEBB
Output
Baseband transmit power enable, an output from the MAC to the radio
baseband processor. When active, the baseband processor transmitter is
configured to be operational, otherwise the transmitter is in standby
mode.
TXD
Output
It is the serial data output from the MAC to the radio baseband processor.
The data is transmitted serially with the LSB first. The data is driven by
the MAC on the rising edge of TXCLK and is sampled by the radio
baseband processor on the falling or rising edge of TXCLK depending on
baseband requirements.
TXRDY
Input
Transmit data ready is an input to the MAC from the radio baseband
processor to indicate that the radio baseband processor is ready to
receive the data packet over the TXD signal. The signal is sampled by the
MAC on the rising edge of TXCLK.
CCA
Input
Clear channel assessment is an input from the radio baseband processor
to signal that the channel is clear to transmit. When this signal is a 0, the
channel is clear to transmit. When this signal is a 1, the channel is not
clear to transmit. This helps the MAC to determine when to switch from
receive to transmit mode.
BBRNW
Output
Baseband read/write is an output from the MAC to indicate the direction
of the SD bus when used for reading or writing data. This signal has to be
setup to the rising edge of BBSCLK for the baseband processor and is
driven on the rising edge of the ARMCLK corresponding the falling edge
of BBSCLK.
nRESETBB
Output
Baseband reset is an output of the MAC to reset the baseband processor.
BBAS
Output
Baseband address strobe is used to envelop the address or the data on
the BBSDX bus. A logic 1 envelops the address and a logic 0 envelops
the data. This signal has to be setup to the rising edge of BBSCLK for the
baseband processor and is driven on the falling edge of BBSCLK.
nBBCS
Output
Baseband chip select is an active low output to activate the serial control
port. When inactive the SD, BBSCLK, BBAS and BBRNW signals are
‘don’t cares’.
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TXPAPE
Output
Radio power amplifier power enable is a software-controlled output. This
signal is used to gate power to the power amplifier.
TXPE
Output
Radio transmit power enable indicates if transmit mode is enabled. When
low, this signal indicates transmitter is in standby mode.
RXPEBB
Output
Baseband receive power enable is an output that indicates if the MAC is
in receive mode. Output to baseband processor enables receive mode in
baseband processor.
BBSCLK
Output
Baseband serial clock is a programmable output generated by dividing
ARM_CLK by 14 (default). This clock is used for the serial control port to
sample the control and data signals.
BBSDX
Bi-directional
Baseband serial data is a bi-directional serial data bus, which is used to
transfer address and data to/from the internal registers of the baseband
processor.
SYNTHLE
Output
Synthesizer latch enable is an active high signal used to send data to the
synthesizer.
nRPD
Output
Radio power down enable. This active low signal is used to power
management purpose for the radio circuitry.
RXCLK
Input
This is an input from the baseband processor. It is used to clock in
received data from baseband processor.
MDRDY
Input
Receive data ready is an input signal from the baseband processor,
indicating a data packet is ready to be transferred to the MAC. The signal
returns to an inactive state when there is no more receiver data or when
the link has been interrupted. This signal is sampled on the falling or
rising edge of RXCLK depending on baseband requirements.
RXD
Input
Receive data is an input from the baseband processor transferring
demodulated header information and data in a serial format. The data is
frame aligned with MD_RDY. This signal is sampled on the falling or
rising edge of RXCLK depending on baseband requirements.
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DACAVCC
Input
Analog power for DAC. This is 3.3V.
DACAGND
Input
Analog ground for DAC.
PLL and Clock Interface
There are three clock pins and five PLL power pins. There are a total of 8 signals in this interface.
XTAL_CLKIN
Input
44 MHz reference clock input/crystal clock input.
XTALOUT
Input
Reference crystal clock output.
XTRACLK
Input
Second clock input to the clock module. This input clock is used
depending on the clock configuration, which is determined by three
strapping pin values.
PLLAGND
Input
Analog PLL ground.
PLLAVCC
Input
Analog PLL power. This is 3.3V.
PLLDGND
Input
Digital PLL ground.
PLLDVCC
Input
Digital PLL power. This is 1.8V.
PLLPLUS
Input
Analog PLL ground.
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PC Card Interface
The PC Card interface is PCMCIA 2.1 fully compliant interface. The following provides detail pin
description.
PCD[15:0]
Bi-directional
Data lines. The data bus contains the data to be written on a write cycle
and the read return data on a read cycle.
PCA[10:0]
Input
Address lines. Signal PCA[10:0] are address bus input lines. PCA10 is
the most significant bit. During memory word access mode, A0 is not
used. During I/O word access cycle, A0 must be negated.
nPCE[2:1]
Input
Card enable. These lines are active low input signals. nPCE1 enables
even numbered addresses and nPCE2 enables odd numbered
addresses.
nPOE
Input
Output enable. This signal is used to gate memory read data from
memory card.
nPCWE
Input
Write enable. This is active low input signal is used for strobing memory
write data into the memory card.
nPCREG
Input
Attribute memory select. Assertion of this signal indicates the access is
limited to attribute memory and to I/O space. Attribute memory is a
separate accessed section of card memory and is generally used to
record card capacity and other configuration and attribute information.
nPCIREQ
Output
Interrupt request. This signal is asserted to indicate to the host system
that a PC card device requires host software service.
nPCSTSCHG
Output
PC card status changed – Not supported. This pin is used as a mode
strap pin. When asserted during reset, PC CARD I/F uses the big endian
protocol; otherwise pulled low (Default), it uses the little endian protocol.
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nPCWAIT
Output
The wait signal is asserted by a PC card to delay completion of the
memory access or I/O access.
nIOIS16
Output
The nIOIS16 output signal is asserted when the address at the socket
corresponds to an I/O address to which the card responds, and the I/O
port addressed is capable of 16-bit access.
nPCINPACK
Output
Input port acknowledge. This output signal is asserted when the PC card
is selected and can respond to an I/O read cycle at the address on the
address bus.
nPCIORD
Input
The host asserts nIORD to read data from a PC card’s I/O space.
nPCIOWR
Input
The host asserts nPCIOWR to write data to a PC card’s I/O space.
System and PC Card Reset
EXT_RESET
Input
The reset signal clears the configuration option register and places the
card in an unconfigured state.The system must place the RESET signal in
a high-Z state during card power up. The signal must remain high
impedance for at least 1 msec after Vcc becomes valid.
JTAG Interface
TDO
Output
Test data output. This input has an integral pull up.
TDI
Input
Test data input.
TCK
Input
Test clock signal.
TMS
Input
Test mode select. This input has an internal pull up.
nTRST
Input
Test interface reset. This input has an internal pull up.
CS22220 Wireless PCMCIA Controller
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DS557PP2
Rev. 3.0
Miscellaneous Interface
NTEST
Input
Chip test mode pin. Used in conjunction with SMNCS0, SMDQM[0:1].
Pull up for normal operation
SPIO_0:8,12:15
Bi-directional
Special purpose I/O reserved for supporting custom interfaces.
* Check with Cirrus Logic support for supported options and
usage.
Power and Ground
VCC (5V and 3.3V)
1
Input
5V inputs. There are a total of 3 pins.
VDD (3.3V)
Input
3.3V inputs. There are a total of 22 pins.
VEE (1.8V)
Input
1.8V inputs to the core. There are a total of 9 pins.
VSS
Input
Ground. There are total of 28 pins.
1
5V or 3.3V depending on desired PCMCIA configuration
CS22220 Wireless PCMCIA Controller
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DS557PP2
Rev. 3.0
Figure 4. CS22220 208 Pin FPBGA Pinout Diagram
CS22220 Wireless PCMCIA Controller
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DS557PP2
Rev. 3.0
Table 1. Pin Listing by Name
ball
A07
A13
B08
C03
C07
C08
C12
R05
T06
H17
K17
H15
J16
H14
T04
C16
D11
C13
D12
B12
H01
G15
L15
M03
M02
G02
C02
L03
L02
H03
M04
F03
D01
G03
K02
G14
K14
C11
E02
E03
E01
F02
G04
F01
G01
H02
name
(N/C)
(N/C)
(N/C)
(N/C)
(N/C)
(N/C)
(N/C)
(N/C)
(N/C)
BBAS
BBNCS
BBRNW
BBSCLK
BBSDX
CAL_EN
CCA
DACAVDD
DACAVSS
RSVD
RSVD
EXT_RESET
MDRDY
NBRCE
NPCE1
NPCE2
NPCINPACK
NPCIOIS16
NPCIORD
NPCIOWR
NPCIREQ
NPCOE
NPCREG
NPCSTSCHG
NPCWAIT
NPCWE
NRESETBB
NTEST
NTRST
PCA00
PCA01
PCA02
PCA03
PCA04
PCA05
PCA06
PCA07
ball
K03
L04
L01
E04
D03
C01
R03
R01
P02
N01
N02
D02
D04
B02
R02
P03
P01
N03
N04
A16
D14
B15
A17
A15
F15
B16
U01
T03
E14
P06
U05
P05
U04
T05
A02
A03
A04
A05
A06
B05
B06
C04
D06
G17
F14
F17
name
PCA08
PCA09
PCA10
PCD00
PCD01
PCD02
PCD03
PCD04
PCD05
PCD06
PCD07
PCD08
PCD09
PCD10
PCD11
PCD12
PCD13
PCD14
PCD15
PLLAGND
PLLAVCC
PLLDGND
PLLDVCC
PLLPLUS
RLINK
RNPD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RXCLK
RXD
RXPEBB
CS22220 Wireless PCMCIA Controller
ball
T16
U17
P14
T17
R17
P15
N14
P17
N15
M14
M16
M15
U07
U11
T08
R10
P11
T11
R11
P12
R12
P13
U12
R13
U13
U14
R14
U15
U16
R15
U06
T07
P08
R06
P07
L16
L14
U03
P04
J17
A10
B10
C10
D10
D17
D15
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name
SMA00
SMA01
SMA02
SMA03
SMA04
SMA05
SMA06
SMA07
SMA08
SMA09
SMA10
SMA11
SMCKE
SMCLK
SMD00
SMD01
SMD02
SMD03
SMD04
SMD05
SMD06
SMD07
SMD08
SMD09
SMD10
SMD11
SMD12
SMD13
SMD14
SMD15
SMDQM00
SMDQM01
SMNCAS
SMNCS00
SMNCS01
SMNRAS
SMNWE
SYNTH_LE1
SYNTH_LE2
SYNTHLE
TCK
TDI
TDO
TMS
TXCLK
TXD
ball
E16
B17
E15
D16
A01
J01
T02
B03
A12
B04
B11
B14
C06
C15
D09
E17
F04
G16
J15
K01
N17
P16
R04
R08
T01
T10
T12
T14
U09
A09
C09
D07
J03
J04
J14
K16
R09
T09
A08
A11
A14
B01
B07
B09
C05
C17
name
TXPAPE
TXPE
TXPEBB
TXRDY
VCC
VCC
VCC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DS557PP2
Rev. 3.0
ball
D08
F16
H04
H16
J02
K04
K15
name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Ball
L17
M01
M17
N16
P09
P10
R07
name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CS22220 Wireless PCMCIA Controller
ball
R16
T13
T15
U02
U08
U10
D05
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name
VSS
VSS
VSS
VSS
VSS
VSS
WC_WiFi
ball
C14
D13
B13
name
XTALCLKIN
XTALOUT
XTRACLK
DS557PP2
Rev. 3.0
Table 2. Pin Listing by Ball
ball
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
name
VCC
RSVD
RSVD
RSVD
RSVD
RSVD
(N/C)
VSS
VEE
TCK
VSS
VDD
(N/C)
VSS
PLLPLUS
PLLAGND
PLLDVCC
VSS
PCD10
VDD
VDD
RSVD
RSVD
VSS
(N/C)
VSS
TDI
VDD
RSVD
XTRACLK
VDD
PLLDGND
RNPD
TXPE
PCD02
NPCIOIS16
(N/C)
RSVD
VSS
VDD
(N/C)
(N/C)
VEE
TDO
NTRST
Ball
C12
C13
C14
C15
C16
C17
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
E01
E02
E03
E04
E14
E15
E16
E17
F01
F02
F03
F04
F14
F15
F16
F17
G01
G02
G03
G04
G14
G15
name
(N/C)
DACAVSS
XTALCLKIN
VDD
CCA
VSS
NPCSTSCHG
PCD08
PCD01
PCD09
WC_WiFi
RSVD
VEE
VSS
VDD
TMS
DACAVDD
RSVD
XTALOUT
PLLAVCC
TXD
TXRDY
TXCLK
PCA02
PCA00
PCA01
PCD00
RSVD
TXPEBB
TXPAPE
VDD
PCA05
PCA03
NPCREG
VDD
RXD
RLINK
VSS
RXPEBB
PCA06
NPCINPACK
NPCWAIT
PCA04
NRESETBB
MDRDY
CS22220 Wireless PCMCIA Controller
ball
G16
G17
H01
H02
H03
H04
H14
H15
H16
H17
J01
J02
J03
J04
J14
J15
J16
J17
K01
K02
K03
K04
K14
K15
K16
K17
L01
L02
L03
L04
L14
L15
L16
L17
M01
M02
M03
M04
M14
M15
M16
M17
N01
N02
N03
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name
VDD
RXCLK
EXT_RESET
PCA07
NPCIREQ
VSS
BBSDX
BBRNW
VSS
BBAS
VCC
VSS
VEE
VEE
VEE
VDD
BBSCLK
SYNTHLE
VDD
NPCWE
PCA08
VSS
NTEST
VSS
VEE
BBNCS
PCA10
NPCIOWR
NPCIORD
PCA09
SMNWE
NBRCE
SMNRAS
VSS
VSS
NPCE2
NPCE1
NPCOE
SMA09
SMA11
SMA10
VSS
PCD06
PCD07
PCD14
ball
N04
N14
N15
N16
N17
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
P17
R01
R02
R03
R04
R05
R06
R07
R08
R09
R10
R11
R12
R13
R14
R15
R16
R17
T01
T02
T03
T04
T05
T06
name
PCD15
SMA06
SMA08
VSS
VDD
PCD13
PCD05
PCD12
SYNTH_LE2
RSVD
RSVD
SMNCS01
SMNCAS
VSS
VSS
SMD02
SMD05
SMD07
SMA02
SMA05
VDD
SMA07
PCD04
PCD11
PCD03
VDD
(N/C)
SMNCS00
VSS
VDD
VEE
SMD01
SMD04
SMD06
SMD09
SMD12
SMD15
VSS
SMA04
VDD
VCC
RSVD
CAL_EN
RSVD
N/C
DS557PP2
Rev. 3.0
ball
T07
T08
T09
T10
T11
T12
T13
name
SMDQM01
SMD00
VEE
VDD
SMD03
VDD
VSS
ball
T14
T15
T16
T17
U01
U02
U03
name
VDD
VSS
SMA00
SMA03
RSVD
VSS
SYNTH_LE1
CS22220 Wireless PCMCIA Controller
ball
U04
U05
U06
U07
U08
U09
U10
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name
RSVD
RSVD
SMDQM00
SMCKE
VSS
VDD
VSS
ball
U11
U12
U13
U14
U15
U16
U17
name
SMCLK
SMD08
SMD10
SMD11
SMD13
SMD14
SMA01
DS557PP2
Rev. 3.0
5
Specifications
Table 3. Absolute Maximum Ratings
Symbol
Parameter
VEE
VDD
VIN
IIN
TSTGP
Voltage at Core
DC Supply ( I/O)
Input Voltage
DC Input Current
Storage Temperature
Range
Limits
Units
-0.18 to 2.0
-0.3 to 3.9
-0.1 to VDD + 0.3
+/- 10
-40 to 125
V
V
V
µA
°C
Table 4. Recommended Operating Conditions
Symbol
VDD
VEE
XTALIN
FTCK
TA
TJ
Parameter
DC Supply
1
Input frequency
JTAG clock frequency
Ambient Temperature
Junction Temperature
Limits
3.15 to 3.60 (3V I/O)
1.6 to 2.0 (core)
44
0 to 10
0 to +70
0 to +105
Units
V
MHz
MHz
°C
°C
Notes:
1. The XTALIN & XTALOUT pins have minimal ESD protection.
2. This device may have ESD sensitivity above 500V HBM per JESD22-A114. Normal ESD precautions
need to be followed.
Table 5. Capacitance
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Value
3.4
4.0
Units
pF
pF
Table 6. DC Characteristics
Symbol
VIL
VIH
VOL
VOH
IIL
IOZ
IDD
IEE
Parameter
Voltage Input Low
Voltage Input High
Voltage Output Low
Voltage Output High
Input Leakage Current
3-State Output Leakage Current
Dynamic Supply Current
Note 1
CS22220 Wireless PCMCIA Controller
Condition
IOL = 800 µA
IOH = 800 µA
VIN = VSS or VDD
VOH = VSS or VDD
VDD = 3.3V
VDD = 1.8V
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Min
Typ.
-0.50
0.7 * VDD
VSS - 0.1
-10
-10
Max
0.3 * VDD
VDD + 0.3
VSS + 0.1
10
10
35
135
DS557PP2
Units
V
V
V
V
µA
µA
mA
Rev. 3.0
5.1
AC Characteristics and Timing
Table 7. System Memory Interface Timings
Parameter
tdSMD
tdSMA
tdSMDQM
tdSMNCS
tdSMNWE
tdSMCKE
tdSMNCAS
tdSMNRAS
TperSMCLK
TsuSMD
ThSMD
Parameter Description
SMCLK to SMD[31:0] output delay
SMCLK to SMA[11:0] output delay
SMCLK to SMDQM[3:0] output delay
SMCLK to SMNCS[1:0] output delay
SMCLK to SMNWE output delay
SMCLK to SMCKE output delay
SMCLK to SMNCAS output delay
SMCLK to SMNRAS output delay
SMCLK period
SMD[31:0] setup to SMCLK
SMD[31:0] hold from SMCLK
Min
72
1.0
2.4
Max
7
4.7
5.1
4.1
4.5
4.3
4.0
5.0
103
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Outputs are loaded with 35pf on SMD, 25pf on SMA, SMDQM, SMNRAS, and SMNCAS and 20pf on SMCLK,
SMNCS, and SMCKE.
2. An attempt has been made to balance the setup time needed by the SDRAM and the setup needed by CS22210 to
read data. If there is a problem meeting setup on the SDRAM, there is a programmable delay line on SMCLK which
can help meet the setup time. Care must be taken, however, not to violate the setup on the return read data. The
delay can be increased by a multiple of 0.25ns by using the SMA[11:09] pins to selectively set the clock delay .
SMCLK
tdSMD
WRITE DATA
SMD[15:0]
tdSMA
ROW ADDR
SMA[13:0]
COLUMN ADDR
tdSMDQM
SMDQM[1:0]
tdSMNCS
SMNCS[1:0]
tdSMNWE
SMNWE
tdSMCKE
SMCKE
tdSMNRAS
SMNRAS
tdSMNCAS
SMNCAS
Figure 5. System Memory Interface ‘Write’ Timing Diagram
CS22220 Wireless PCMCIA Controller
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DS557PP2
Rev. 3.0
tperSMCLK
SMCLK
thSMD
tsuSMD
DATA
SMD[15:0]
tdSMA
SMA[13:0]
ROW ADDR
COLUMN ADDR
SMDQM[1:0]
tdSMNCS
ACTIVE
SMNCS[1:0]
SMNWE
tdSMCKE
SMCKE
tdSMNRAS
SMNRAS
tdSMNCAS
SMNCAS
Figure 6. System Memory Interface 'Read' Timing Diagram
CS22220 Wireless PCMCIA Controller
25 of 34
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DS557PP2
Rev. 3.0
Table 8. ROM/Flash Memory ‘Read’ Timing
Item
Symbol
Clock Period
(1)
tperSMCLK
tid SMD
CE to SMD Latched Data (2)
tf SMRAS
OE de-asserted to OE asserted (3)
Min
72 MHz
Max
103 MHz
221 ns
6(tperSMCLK)
tACC
220 ns
SMCLK to SMA output delay
td SMA
4.0 ns
SMCLK to BRCE output delay (CE)
td BRCE
4.5 ns
SMCLK to SMRAS output delay (OE)
td SMRAS
5.0 ns
SMD setup to SMCLK
tsu SMD
1.0 ns
SMD hold from SMCLK
th SMD
2.4 ns
ROM address to output delay
(4)
1. The memclock timing is derived by bootstrap PLL settings. Synchronous modes at 77 MHz & 72
MHz are currently supported.
2. tid SMD is based on the fm_romrdlat register settings – default is 09h max. (77Mhz ~ 17 times
SMCLK = 221ns).
3. tf SMRAS is the minimum time required before the next OE is active on the bus (6 times SMCLK).
The ROM device must release the bus within this time frame (77MHz ~ 78 ns).
4. Based on default fm_romrdlat register settings (note: 09h translates to 11h) see fm_romrdlat register
settings for more information)
SMRAS
SMD
tf
t ld
SMCLK
tper
SMCLK
SMD
tsu
t ACC
SMD
th
DATA
SMD[7:0]
SMA
td
ADDRESS
SMA[11:0], SMD[13:8]
SMNWE
BRCE
td
BRCE
td
BRCE (CE)
SMRAS
td
SMRAS
td
SMRAS (OE)
Figure 7. ROM Memory Interface 'Read' Timing Diagram
CS22220 Wireless PCMCIA Controller
26 of 34
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DS557PP2
Rev. 3.0
5.2
PCMCIA Interface Timing Diagrams
tc(R)
ta(A)
th(A)
PC_A[25:0], PC_NREG
ta(CE)
tv(A)
tsu(CE)
PC_NCE
tsu(A)
th(CE)
ta(OE)
PC_NOE
tv(WT-OE)
tdis(CE)
tw(WT)
PC_NWAIT
ten(OE)
tdis(OE)
tv(WT)
PC_D[15:0]
Figure 8. Attribute/Common Memory ‘Read’ Timing Diagram
Table 9. Common Memory ‘Read’ Timing Specification
Speed Version
Item
Read Cycle Time
Address Accesss Time
Card Enable Access Time
Output Enable Access Time
Output Disable Time from PC_NOE
Output Disable Time from PC_NCE
Data Valid from Address Change
Address Setup Time
Address Hold Time
Card Enable Setup Time
Card Enable Hold Time
PC_NWAIT Valid from PC_NOE
PC_NWAIT Pulse Width
Data Setup for PC_NWAIT Released
CS22220 Wireless PCMCIA Controller
Symbol
tcR
ta (A)
ta (CE)
ta (OE)
tdis (OE)
ten (CE)
tv (A)
tsu (A)
th (A)
tsu (CE)
th (CE)
tv (WT-OE)
tw (WT)
tv (WT)
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100 ns
Min
100
Max
100
100
50
50
5
0
10
15
0
15
35
12 us
0
DS557PP2
Rev. 3.0
Table 10. Attribute Memory ‘Read’ Timing Specification
Speed Version
Item
Read Cycle Time
Address Accesss Time
Card Enable Access Time
Output Enable Access Time
Output Disable Time from PC_NOE
Output Enable Time from PC_NCE
Data Valid from Address Change
Address Setup Time
Address Hold Time
Card Enable Setup Time
Card Enable Hold Time
PC_NWAIT Valid from PC_NOE
PC_NWAIT Pulse Width
Data Setup for PC_NWAIT Released
Symbol
600 ns
Min
600
tcR
ta (A)
ta (CE)
ta (OE)
tdis (OE)
ten (OE)
tv (A)
tsu (A)
th (A)
tsu (CE)
th (CE)
tv (WT-OE)
tw (WT)
tv (WT)
Max
600
600
300
150
5
0
100
35
0
35
100
12 us
0
tc(W)
PC_A[25:0], PC_NREG
tsu(CE-WEH)
tsu(CE)
PC_NCE
th(CE)
tsu(A-WEH)
PC_NOE
tsu(A)
trec(WE)
tw (WE)
PC_NWE
tv(WT-WE)
tv(WT)
tw (WT)
PC_NWAIT
tsu(OE-WE)
th(OE-WE)
tsu(D-WEH)
PC_D[15:0](Din)
th(D)
Valid Data Input
tdis(OE)
tdis(WE)
ten(OE)
ten(WE)
PC_D[15:0](Dout)
Figure 9. Memory ‘Write’ Timing Diagram
CS22220 Wireless PCMCIA Controller
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DS557PP2
Rev. 3.0
Table 11. Common Memory ‘Write’ Timing Specification
Speed Version
Item
Write Cycle time
Write Pulse Width
Address Setup Time
Address Setup Time for PC_NWE
Card Enable Setup Time for PC_NWE
Data Setup time for PC_NWE
Data Hold Time
Write Recovery Time
Output Disable Time from PC_NWE
Output Disable Time from PC_NOE
Output Enable Time from PC_NWE
Output Enable Time from PC_NOE
Output Enable Setup from PC_NWE
Output Enable Hold from PC_NWE
Card Enable Setup Time
Card Enable Hold Time
PC_NWAIT Valid from PC_NWE
PC_NWAIT Pulse Width
PC_NWE High from PC_NWAIT Released
Symbol
tcW
tw (WE)
tsu (A)
tsu (A-WEH)
tsu (CE-WEH)
tsu (D-WEH)
th (D)
trec (WE)
tdis (WE)
tdis (OE)
ten (WE)
ten (OE)
tsu (OE-WE)
th (OE-WE)
tsu (CE)
th (CE)
tv (WT-WE)
tw (WT)
100 ns
Min
100
60
10
70
70
40
15
15
Max
50
50
5
5
10
10
0
15
35
12 us
0
Table 12. Attribute Memory ‘Write’ Timing Specification
Speed Version
Item
Write Cycle time
Write Pulse Width
Address Setup Time
Address Setup Time for PC_NWE
Card Enable Setup Time for PC_NWE
Data Setup time for PC_NWE
Data Hold Time
Write Recovery Time
Output Disable Time from PC_NWE
Output Disable Time from PC_NOE
Output Enable Time from PC_NWE
Output Enable Time from PC_NOE
Output Enable Setup from PC_NWE
Output Enable Hold from PC_NWE
Card Enable Setup Time
Card Enable Hold Time
PC_NWAIT Valid from PC_NWE
PC_NWAIT Pulse Width
PC_NWE High from PC_NWAIT Released
CS22220 Wireless PCMCIA Controller
Symbol
tcW
tw (WE)
tsu (A)
tsu (A-WEH)
tsu (CE-WEH)
tsu (D-WEH)
th (D)
trec (WE)
tdis (WE)
tdis (OE)
ten (WE)
ten (OE)
tsu (OE-WE)
th (OE-WE)
tsu (CE)
th (CE)
tv (WT-WE)
tw (WT)
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600 ns
Min
600
300
50
350
300
150
70
70
Max
150
150
5
5
35
35
0
35
100
12 us
0
DS557PP2
Rev. 3.0
PC_A[25:0]
th A (IORD)
tsu REG (IORD)
PC_NREG
th REG (IORD)
tsu CE (IORD)
PC_NCE
th CE (IORD)
tw (IORD)
PC_NIORD
tdr INPACK (ADR)
tsu A (IORD)
PC_NINPACK
tdr IOIS16 (ADR)
tdf INPACK (IORD)
PC_IOIS16
td (IORD)
tdr (WT)
tdf IOIS16 (ADR)
PC_NWAIT
tdf WT (IORD)
tw (WT)
th (IORD)
PC_D[15:0]
Figure 10. I/O ‘Read’ Timing Diagram
Table 13. I/O ‘Read’ (Input) Timing Specification
Item
Data Delay after PC_NIORD
Data Hold following PC_NIORD
PC_NIORD Width Time
Address Setup before PC_NIORD
Address Hold following PC_NIORD
PC_NCE Setup before PC_NIORD
PC_NCE Hold following PC_NIORD
PC_NREG Setup before PC_NIORD
PC_NREG Hold before PC_NIORD
PC_NINPACK Delay Falling from PC_NIORD
PC_NINPACK Delay Rising from PC_NIORD
PC_NIOIS16 Delay Falling from Address
PC_NIOIS16 Delay Rising from Address
PC_NWAIT Delay Falling from PC_NIORD
Data Delay from PC_NWAIT Rising
PC_NWAIT Width Time
CS22220 Wireless PCMCIA Controller
Symbol
td (IORD)
th (IORD)
tw IORD
tsu A (IORD)
th A (IORD)
tsu CE (IORD)
th CE (IORD)
tsu REG (IORD)
th REG (IORD)
tdf INPACK (IORD)
tdr INPACK (IORD)
tdf IOIS16 (ADR)
tdr IOIS16 (ADR)
td WT (IORD)
tdr (WT)
tw (WT)
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Min
0
165
70
20
5
20
5
0
0
DS557PP2
Max
100
45
45
35
35
35
0
12,000
Rev. 3.0
PC_A[25:0]
tsu REG (IOWR)
th A (IOWR)
th REG (IOWR)
PC_NREG
tsu CE (IOWR)
PC_NCE
th CE (IOWR)
tw (IOWR)
PC_NIOWR
tdr IOIS16 (ADR)
tsu A (IOWR)
PC_IOIS16
tdf IOIS16 (ADR)
tdf WT (IOWR)
tdr IOWR (WT)
PC_NWAIT
tw (WT)
th (IOWR)
PC_D[15:0]
tsu (IOWR)
Figure 11. I/O ‘Write’ Timing Diagram
Table 14. I/O ‘Write’ (Output) Timing Specification
Item
Data Setup after PC_NIOWR
Data Hold following PC_NIOWR
PC_NIOWR Width Time
Address Setup before PC_NIOWR
Address Hold following PC_NIOWR
PC_NCE Setup before PC_NIOWR
PC_NCE Hold following PC_NIOWR
PC_NREG Setup before PC_NIOWR
PC_NREG Hold following PC_NIOWR
PC_NIOIS16 Delay Falling from Address
PC_NIOIS16 Delay Rising from Address
PC_NWAIT Delay Falling from PC_NIOWR
PC_NWAIT Width Time
PC_NIOWR Width Time
CS22220 Wireless PCMCIA Controller
Symbol
td (NIOWR)
th (NIOWR)
tw IOWR
tsu A (NIOWR)
th A (NIOWR)
tsu CE (NIOWR)
th CE (NIOWR)
tsu REG (NIOWR)
th REG (NIOWR)
tdf IOIS16 (ADR)
tdr IOIS16 (ADR)
td WT (NIOWR)
tw (WT)
tdr IOWR (WT)
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Min
60
30
165
70
20
5
20
5
0
Max
35
35
35
12,000
0
DS557PP2
Rev. 3.0
Table 15. Radio MAC AC Timings – Intersil Modes
Parameter
tdBBAS
tdBBRNW
tdnBBCS
tdBBSDX
TsuBBSDX
ThBBSDX
tdTXD
tdTXD
TsuRXD
ThRXD
TsuMDRDY
ThMDRDY
tdTXPEBB
tdRXPEBB
TsuTXRDY
ThTXRDY
TdutyRXCLK 2
TdutyTXCLK 2
Notes:
1.
2.
3.
4.
5.
Parameter Description
BBAS output delay from falling BBSCLK
BBRNW output delay from falling BBSCLK
nBBCS output delay from falling BBSCLK
BBSDX output delay from falling BBSCLK
BBSDX setup to rising edge of BBSCLK
BBSDX hold from rising edge of BBSCLK
TXD output delay from rising TXCLK (SMAC
Mode)
TXD output delay from rising TXCLK (RMAC
Mode)
RXD setup to rising edge of RXCLK
RXD hold from rising edge of RXCLK
MDRDY setup to falling edge of RXCLK
MDRDY hold from falling edge of RXCLK
TXPEBB output delay from rising TXCLK
RXPEBB output delay from rising RXCLK
TXRDY setup to falling edge of TXCLK
TXRDY hold from falling edge of TXCLK
RXCLK period
TXCLK period
Min
Max
8.2
8.0
59.0
7.0
33.5
Units
ns
ns
ns
ns
ns
ns
ns
15.4
ns
15.0
16.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14.8
0.0
1.0
1.8
2
1
6.5
0
See Note
See Note
CCA signal is double synchronized to ARMCLKIN.
ARMCLK must be at least 4 times the TXCLK and RXCLK frequency.
Harris baseband (3824/3824A) generates RXCLK and TXCLK of 4 Mhz. the duty cycle varies between 33-40%
with a high time of 90.9ns and low time that alternates between 136 and 182ns. The clock period varies between
227 and 272 ns, giving an effective period of 250ns.
TXD delay in 802.11b mode is the result of sampling the TXCLK with the ctlclk, therefore the maximum delay
is equal to two ctlclk periods plus the flop-to-output delay. In this table, ctlclk is assumed to have a 13 ns
period.
BBNCS output delay = [(1/ARMCLK freq)*ceiling(SER_CLK_DIV/2)] + 7ns, the specified value is based on
ARMCLK of 77 Mhz and SER_CLK_DIV=8.
CS22220 Wireless PCMCIA Controller
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DS557PP2
Rev. 3.0
Table 16. Radio MAC AC Timings – RFMD Modes
Parameter
tdBBRNW
tdnBBCS
tdBBSDX
TsuBBSDX
ThBBSDX
tdTXD
tdTXD
TsuRXD
ThRXD
TsuMDRDY
ThMDRDY
tdTXPEBB
tdRXPEBB
TsuTXRDY
ThTXRDY
Notes:
1.
2.
3.
4.
Parameter Description
BBRNW output delay from falling BBSCLK
nBBCS output delay from falling BBSCLK
BBSDX output delay from falling BBSCLK
BBSDX setup to rising edge of BBSCLK
BBSDX hold from rising edge of BBSCLK
TXD output delay from rising TXCLK (SMAC
Mode)
TXD output delay from rising TXCLK (RMAC
Mode)
RXD setup to rising edge of RXCLK
RXD hold from rising edge of RXCLK
MDRDY setup to falling edge of RXCLK
MDRDY hold from falling edge of RXCLK
TXPEBB output delay from rising TXCLK
RXPEBB output delay from rising RXCLK
TXRDY setup to falling edge of TXCLK
TXRDY hold from falling edge of TXCLK
Min
Max
6.7
110.79
7.0
33.5
Units
ns
ns
ns
ns
ns
ns
15.4
ns
14.5
0.0
1.0
1.8
2
1
ns
ns
ns
ns
ns
ns
ns
ns
15.0
16.0
6.5
0
CCA signal is double synchronized to ARMCLKIN.
ARMCLK must be at least 4 times the TXCLK and RXCLK frequency.
TXD delay in 802.11b mode is the result of sampling the TXCLK with the ctlclk, therefore the maximum delay
is equal to two ctlclk periods plus the flop-to-output delay. In this table, ctlclk is assumed to have a 13 ns
period.
BBNCS output delay = [(1/ARMCLK freq)*ceiling(SER_CLK_DIV/2)] + 7ns, the specified value is based on
ARMCLK of 77 Mhz and SER_CLK_DIV=8.
Table 17. Package Specifications
Symbol
θJC
θJA
TJ_MAX
Parameter
Junction-to-Case Thermal
Resistance
Junction-to-Open Air Thermal
Resistance
Max Junction Temperature
Value
2.5
Units
26.9
°C/W
105
°C
°C/W
Notes:
1. ARMCLK / MEMCLK = 77MHz
CS22220 Wireless PCMCIA Controller
33 of 34
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DS557PP2
Rev. 3.0
6
Packaging
The CS22220 Controller is available in a 208 Fine Pitch Ball Grid Array (FPBGA) package.
Figure 12 contains the package mechanical drawing.
Figure 12. CS22220 208 FPBGA-pin Mechanical Drawing
CS22220 Wireless PCMCIA Controller
34 of 34
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DS557PP2
Rev. 3.0