Am29LV320MH/L Data Sheet RETIRED PRODUCT This product has been retired and is not available for designs. For new and current designs, S29GL032A supersedes Am29LV320M H/L and is the factory-recommended migration path. Please refer to the S29GL032A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. April 2005 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Publication Number 26517 Revision B Amendment +3 Issue Date December 14, 2005 THIS PAGE LEFT INTENTIONALLY BLANK. Am29LV320MH/L 32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit™ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O™ Control This product has been retired and is not available for designs. For new and current designs, S29GL032A supersedes Am29LV320M H/L and is the factory-recommended migration path. Please refer to the S29GL032A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES Single power supply operation — 3 V for read, erase, and program operations VersatileI/O™ control — Device generates data output voltages and tolerates data input voltages on the DQ inputs/outputs as determined by the voltage on the VIO pin; operates from 1.65 to 3.6 V Manufactured on 0.23 µm MirrorBit process technology SecSi™ (Secured Silicon) Sector region — 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence — May be programmed and locked at the factory or by the customer Flexible sector architecture — Sixty-four 32 Kword/64-Kbyte sectors Compatibility with JEDEC standards — Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection Minimum 100,000 erase cycle guarantee per sector 20-year data retention at 125°C PERFORMANCE CHARACTERISTICS High performance — 90 ns access time — 25 ns page read times — 0.5 s typical sector erase time — 15 µs typical effective write buffer word programming time: 16-word/32-byte write buffer reduces overall programming time for multiple-word/byte updates — 4-word/8-byte page read buffer — 16-word/32-byte write buffer Low power consumption (typical values at 3.0 V, 5 MHz) — 13 mA typical active read current — 50 mA typical erase/program current — 1 µA typical standby mode current Package options — 56-pin TSOP — 64-ball Fortified BGA SOFTWARE & HARDWARE FEATURES Software features — Program Suspend & Resume: read other sectors before programming operation is completed — Erase Suspend & Resume: read/program other sectors before an erase operation is completed — Data# polling & toggle bits provide status — Unlock Bypass Program command reduces overall multiple-word programming time — CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices Hardware features — Sector Group Protection: hardware-level method of preventing write operations within a sector group — Temporary Sector Unprotect: VID-level method of changing code in locked sectors — WP#/ACC input: Write Protect input (WP#) protects first or last sector regardless of sector protection settings ACC (high voltage) accelerates programming time for higher throughput during system production — Hardware reset input (RESET#) resets device — Ready/Busy# output (RY/BY#) indicates program or erase cycle completion This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 26517 Rev: B Amendment/3 Issue Date: December 14, 2005 Refer to AMD’s Website (www.amd.com) for the latest information. D A T A S H E E T GENERAL DESCRIPTION The Am29LV320MH/L is a 32 Mbit, 3.0 volt single power supply flash memory device organized as 2,097,152 words or 4,194,304 bytes. The device has an 8-bit/16-bit bus and can be programmed either in the host system or in standard EPROM programmers. An access time of 90, 100, 110, or 120 ns is available. Note that each access time has a specific operating voltage range (VCC) and an I/O voltage range (VIO), as specified in the Product Selector Guide and the Ordering Information sections. The device is offered in a 56-pin TSOP or 64-ball Fortified BGA package. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V CC input, a high-voltage accelerated program (ACC) feature provides shorter programming times through increased current on the WP#/ACC input. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase operation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. The VersatileI/O™ (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on the CE# control input and DQ I/Os to 2 the same voltage level that is asserted on the VIO pin. Refer to the Ordering Information section for valid VIO options. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses have been stable for a specified period of time. The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the WP#/ACC pin. The protected sector will still be protected even during accelerated programming. The SecSi™ (Secured Silicon) Sector provides a 128-word/256-byte area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur. AMD MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection. Am29LV320MH/L December 14, 2005 D A T A S H E E T MIRRORBIT 32 MBIT DEVICE FAMILY Device Bus Sector Architecture Packages VIO RY/BY# WP#, ACC WP# Protection x8 Uniform (64 Kbyte) 40-pin TSOP (std. & rev. pinout), 48-ball FBGA Yes Yes ACC only No WP# LV320MT/B x8/x16 Boot (8 x 8 Kbyte at top & bottom) 48-pin TSOP, 48-ball Fine-pitch BGA, 64-ball Fortified BGA No Yes WP#/ACC pin 2 x 8 Kbyte top or bottom LV320MH/L x8/x16 Uniform (64 Kbyte) 56-pin TSOP (std. & rev. pinout), 64 Fortified BGA Yes Yes WP#/ACC pin 1 x 64 Kbyte high or low LV033MU RELATED DOCUMENTS To download related documents, click on the following links or go to www.amd.com→Flash Memory→Product Information→MirrorBit→Flash Information→Technical Documentation. MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read December 14, 2005 Implementing a Common Layout for AMD MirrorBit and Intel StrataFlash Memory Devices Migrating from Single-byte to Three-byte Device IDs AMD MirrorBit™ White Paper Am29LV320MH/L 3 D A T A S H E E T TABLE OF CONTENTS Continuity of Specifications ....................................................... i For More Information ................................................................. i Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10 Table 1. Device Bus Operations ..................................................... 10 Word/Byte Configuration ........................................................ 10 VersatileIO™ (VIO) Control ..................................................... 10 Requirements for Reading Array Data ................................... 11 Page Mode Read ............................................................................11 Writing Commands/Command Sequences ............................ 11 Write Buffer .....................................................................................11 Accelerated Program Operation ......................................................11 Autoselect Functions .......................................................................11 Standby Mode ........................................................................ 11 Automatic Sleep Mode ........................................................... 12 RESET#: Hardware Reset Pin ............................................... 12 Output Disable Mode .............................................................. 12 Table 2. Sector Address Table........................................................ 13 Autoselect Mode ..................................................................... 15 Table 3. Autoselect Codes, (High Voltage Method) ....................... 15 Sector Group Protection and Unprotection ............................. 16 Figure 7. Erase Operation .............................................................. 30 Command Definitions ............................................................. 31 Table 10. Command Definitions (x16 Mode, BYTE# = VIH) ........... 31 Table 11. Command Definitions (x8 Mode, BYTE# = VIL).............. 32 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 33 DQ7: Data# Polling ................................................................. 33 Figure 8. Data# Polling Algorithm .................................................. 33 RY/BY#: Ready/Busy# ............................................................ 34 DQ6: Toggle Bit I .................................................................... 34 Figure 9. Toggle Bit Algorithm ........................................................ 35 DQ2: Toggle Bit II ................................................................... 35 Reading Toggle Bits DQ6/DQ2 ............................................... 35 DQ5: Exceeded Timing Limits ................................................ 36 DQ3: Sector Erase Timer ....................................................... 36 DQ1: Write-to-Buffer Abort ..................................................... 36 Table 12. Write Operation Status................................................... 36 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 37 Figure 10. Maximum Negative Overshoot Waveform ................... 37 Figure 11. Maximum Positive Overshoot Waveform ..................... 37 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 37 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 12. Test Setup .................................................................... 39 Table 13. Test Specifications ......................................................... 39 Table 4. Sector Group Protection/Unprotection Address Table ..... 16 Key to Switching Waveforms. . . . . . . . . . . . . . . . 39 Write Protect (WP#) ................................................................ 17 Temporary Sector Group Unprotect ....................................... 17 Figure 13. Input Waveforms and Measurement Levels ...................................................................... 39 Figure 1. Temporary Sector Group Unprotect Operation ................17 Figure 2. In-System Sector Group Protect/Unprotect Algorithms ...18 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 40 Read-Only Operations ........................................................... 40 SecSi (Secured Silicon) Sector Flash Memory Region .......... 19 Figure 14. Read Operation Timing ................................................. 40 Figure 15. Page Read Timings ...................................................... 41 Table 5. SecSi Sector Contents ...................................................... 19 Figure 3. SecSi Sector Protect Verify ..............................................20 Hardware Data Protection ...................................................... 20 Low VCC Write Inhibit .....................................................................20 Write Pulse “Glitch” Protection ........................................................20 Logical Inhibit ..................................................................................20 Power-Up Write Inhibit ....................................................................20 Common Flash Memory Interface (CFI) . . . . . . . 20 Table 6. CFI Query Identification String ..........................................21 Table 7. System Interface String..................................................... 21 Table 8. Device Geometry Definition ..............................................22 Table 9. Primary Vendor-Specific Extended Query ........................23 Command Definitions . . . . . . . . . . . . . . . . . . . . . 23 Reading Array Data ................................................................ 23 Reset Command ..................................................................... 24 Autoselect Command Sequence ............................................ 24 Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 24 Word/Byte Program Command Sequence ............................. 24 Unlock Bypass Command Sequence ..............................................25 Write Buffer Programming ...............................................................25 Accelerated Program ......................................................................26 Figure 4. Write Buffer Programming Operation ...............................27 Figure 5. Program Operation ..........................................................28 Program Suspend/Program Resume Command Sequence ... 28 Figure 6. Program Suspend/Program Resume ...............................29 Chip Erase Command Sequence ........................................... 29 4 Sector Erase Command Sequence ........................................ 29 Erase Suspend/Erase Resume Commands ........................... 30 Hardware Reset (RESET#) .................................................... 42 Figure 16. Reset Timings ............................................................... 42 Erase and Program Operations .............................................. 43 Figure 17. Program Operation Timings .......................................... 44 Figure 18. Accelerated Program Timing Diagram .......................... 44 Figure 19. Chip/Sector Erase Operation Timings .......................... 45 Figure 20. Data# Polling Timings (During Embedded Algorithms) . 46 Figure 21. Toggle Bit Timings (During Embedded Algorithms) ...... 47 Figure 22. DQ2 vs. DQ6 ................................................................. 47 Temporary Sector Unprotect .................................................. 48 Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 48 Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 49 Alternate CE# Controlled Erase and Program Operations ..... 50 Figure 25. Alternate CE# Controlled Write (Erase/Program) Operation Timings .......................................................................... 51 Erase And Programming Performance. . . . . . . . 52 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 52 TSOP Pin and BGA Package Capacitance . . . . . 53 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 54 TS056/TSR056—56-Pin Standard and Reverse Pinout Thin Small Outline Package (TSOP) .............................................. 54 LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm Package .................................................................................. 55 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 56 Am29LV320MH/L December 14, 2005 D A T A S H E E T PRODUCT SELECTOR GUIDE Part Number Am29LV320MH/L 90R (VIO = 3.0–3.6 V) VCC = 3.0–3.6 V 101R (VIO = 2.7–3.6 V) 112R (VIO = 1.65–3.6 V) 120R (VIO = 1.65–3.6 V) Speed Option 112 (VIO = 1.65–3.6 V) 101 (VIO = 2.7–3.6 V) VCC = 2.7–3.6 V 120 (VIO = 1.65–3.6 V) Max. Access Time (ns) 90 100 110 120 Max. CE# Access Time (ns) 90 100 110 120 Max. Page access Time (tPACC) 25 30 30 40 30 40 Max. OE# Access Time (ns) 25 30 30 40 30 40 Note: 1. See “AC Characteristics” for full specifications. 2. For the Am29LV320MH/L device, the last numeric digit in the speed option (e.g. 90R, 101, 112, 120) is used for internal purposes only. Please use OPNs as listed when placing orders. BLOCK DIAGRAM DQ0–DQ15 (A-1) RY/BY# VCC Sector Switches VSS VIO Erase Voltage Generator Input/Output Buffers RESET# WE# WP#/ACC BYTE# State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE# OE# VCC Detector Timer A20–A0 December 14, 2005 Am29LV320MH/L Address Latch STB STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix 5 D A T A S H E E T CONNECTION DIAGRAMS 6 NC NC A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# NC WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NC NC A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 NC VIO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56-Pin Standard TSOP 56-Pin Reverse TSOP Am29LV320MH/L 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 NC NC A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 NC VIO NC NC A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# NC WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC December 14, 2005 D A T A S H E E T CONNECTION DIAGRAMS 64-Ball Fortified BGA Top View, Balls Facing Down A8 B8 C8 D8 E8 F8 G8 H8 NC NC NC VIO VSS NC NC NC A7 B7 C7 D7 E7 F7 G7 H7 A13 A12 A14 A15 A16 A6 B6 C6 D6 E6 F6 VSS G6 H6 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 A5 B5 C5 D5 E5 F5 G5 H5 WE# RESET# NC A19 DQ5 DQ12 VCC DQ4 A4 B4 RY/BY# WP#/ACC C4 D4 E4 F4 G4 H4 A18 A20 DQ2 DQ10 DQ11 DQ3 A3 B3 C3 D3 E3 F3 G3 H3 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A2 B2 C2 D2 E2 F2 G2 H2 A3 A4 A2 A1 A0 CE# OE# VSS A1 B1 C1 D1 E1 F1 G1 H1 NC NC NC NC NC VIO NC NC Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP, BGA, SSOP, PDIP, PLCC). December 14, 2005 BYTE# DQ15/A-1 The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Am29LV320MH/L 7 D A T A S H E E T PIN DESCRIPTION A20–A0 LOGIC SYMBOL = 21 Address inputs 21 DQ14–DQ0 = 15 Data inputs/outputs A20–A0 DQ15/A-1 = DQ15 (Data input/output, word mode), A-1 (LSB Address input, byte mode) CE# CE# = Chip Enable input OE# OE# = Output Enable input WE# WE# = Write Enable input WP#/ACC WP#/ACC = Hardware Write Protect input/Programming Acceleration input RESET# RESET# = Hardware Reset Pin input RY/BY# = Ready/Busy output BYTE# = Selects 8-bit or 16-bit mode VCC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VIO = Output Buffer power VSS = Device Ground NC = Pin Not Connected Internally 8 VIO 16 or 8 DQ15–DQ0 (A-1) RY/BY# BYTE# Am29LV320MH/L December 14, 2005 D A T A S H E E T ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29LV320M H 120R PC I TEMPERATURE RANGE I = Industrial (–40°C to +85°C) F = Industrial (–40°C to +85°C) with Pb-free Packages PACKAGE TYPE E = 56-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 056) F = 56-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR056) PC = 64-Ball Fortified Ball Grid Array 1.0 mm pitch, 13 x 11 mm package (LAA064) SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE AND WP# PROTECTION (WP# = VIL) H = Uniform sector device, highest address sector protected L = Uniform sector device, lowest address sector protected DEVICE NUMBER/DESCRIPTION Am29LV320M 32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit™ Uniform Sector Flash Memory with VersatileIO™ Control, 3.0 Volt-only Read, Program, and Erase Valid Combinations for TSOP Package Speed (ns) VIO Range Am29LV320MH90R, Am29LV320ML90R 90 3.0–3.6 V Am29LV320MH101, Am29LV320ML101 100 2.7–3.6 V Am29LV320MH112, Am29LV320ML112 110 1.65–3.6 V 120 Am29LV320MH101R, Am29LV320ML101R VCC Range 3.0–3.6 V Valid Combinations for Fortified BGA Package Order Number Package Marking Speed (ns) VIO Range VCC Range 3.0– 3.6 V Am29LV320MH90R, Am29LV320ML90R L320MH90N, L320ML90N 90 3.0– 3.6 V Am29LV320MH101, Am29LV320ML101 L320MH01P, L320ML01P 100 2.7– 3.6 V 1.65–3.6 V Am29LV320MH112, Am29LV320ML112 L320MH11P, L320ML11P 110 1.65– 3.6 V 100 2.7–3.6 V Am29LV320MH120, Am29LV320ML120 PCI, L320MH12P, PCF L320ML12P 120 1.65– 3.6 V Am29LV320MH112R, Am29LV320ML112R 110 1.65–3.6 V Am29LV320MH120R, Am29LV320ML120R 120 1.65–3.6 V Am29LV320MH120, Am29LV320ML120 EI, FI, EF 2.7–3.6 V 3.0–3.6 V I, F Am29LV320MH101R, Am29LV320ML101R L320MH01N, L320ML01N 100 2.7– 3.6 V Am29LV320MH112R, Am29LV320ML112R L320MH11N, L320ML11N 110 1.65– 3.6 V Am29LV320MH120R, Am29LV320ML120R L320MH12N, L320ML12N 120 1.65– 3.6 V 2.7– 3.6 V 3.0– 3.6 V Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Note: For the Am29LV320MH/L device, the last numeric digit in the speed option (e.g. 90R, 101, 112, 120) is used for internal purposes only. Please use OPNs as listed when placing orders. December 14, 2005 Am29LV320MH/L 9 D A T A S H E E T DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the Table 1. register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Device Bus Operations DQ8–DQ15 CE# OE# WE# RESET# WP# ACC Addresses (Note 2) DQ0– DQ7 BYTE# = VIH Read L L H H X X AIN DOUT DOUT Write (Program/Erase) L H L H (Note 3) X AIN (Note 4) (Note 4) Accelerated Program L H L H (Note 3) VHH AIN (Note 4) (Note 4) VCC ± 0.3 V X X VCC ± 0.3 V X H X High-Z High-Z High-Z Output Disable L H H H X X X High-Z High-Z High-Z Reset X X X L X X X High-Z High-Z High-Z Sector Group Protect (Note 2) L H L VID H X SA, A6 =L, A3=L, A2=L, A1=H, A0=L (Note 4) X X Sector Group Unprotect (Note 2) L H L VID H X SA, A6=H, A3=L, A2=L, A1=H, A0=L (Note 4) X X Temporary Sector Group Unprotect X X X VID H X AIN Operation Standby (Note 4) (Note 4) BYTE# = VIL DQ8–DQ14 = High-Z, DQ15 = A-1 High-Z Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A20:A0 in word mode; A20:A-1 in byte mode. Sector addresses are A20:A15 in both modes. 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group Protection and Unprotection” section. 3. If WP# = VIL, the first or last sector remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as determined by the method described in “Sector Group Protection and Unprotection”. All sectors are unprotected when shipped from the factory (The SecSi Sector may be factory protected depending on version ordered.) 4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2). Word/Byte Configuration The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0–DQ15 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O 10 pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. VersatileIO™ (VIO) Control The VersatileIO™ (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on CE# and DQ I/Os to the same voltage level that is asserted on VIO. See “Ordering Information” on page 9 for VIO options on this device. Am29LV320MH/L December 14, 2005 D A T A S H E E T For example, a VI/O of 1.65–3.6 volts allows for I/O at the 1.8 or 3 volt levels, driving and receiving signals to and from other 1.8 or 3 V devices on the same data bus. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 13 for the timing diagram. Refer to the DC Characteristics table for the active current specification on reading array data. Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the device is 4 words/8 bytes. The appropriate page is selected by the higher address bits A(max)–A2. Address bits A1–A0 in word mode (A1–A-1 in byte mode) determine the specific word within a page. This is an asynchronous operation; the microprocessor supplies the specific word location. The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted and reasserted for a subsequent access, the access time is t ACC or t CE . Fast page mode accesses are obtained by keeping the “read-page addresses” constant and changing the “intra-read page” addresses. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the December 14, 2005 Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indicates the address space that each sector occupies. Refer to the DC Characteristics table for the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Write Buffer Write Buffer Programming allows the system to write a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. See “Write Buffer” for more information. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. In addition, no external pullup is necessary since the WP#/ACC pin has internal pullup to VCC. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, Am29LV320MH/L 11 D A T A S H E E T and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. Refer to the DC Characteristics table for the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Refer to the DC Characteristics table for the automatic sleep mode current specification. 12 RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. Refer to the AC Characteristics tables for RESET# parameters and to Figure 16 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Am29LV320MH/L December 14, 2005 D A T A S H E E T Table 2. Sector Address Table A20-A15 Sector Sector Size (Kbytes/Kwords) 8-bit Address Range (in hexadecimal) 16-bit Address Range (in hexadecimal) SA0 0 0 0 0 0 0 64/32 000000–00FFFF 000000–007FFF SA1 0 0 0 0 0 1 64/32 010000–01FFFF 008000–00FFFF SA2 0 0 0 0 1 0 64/32 020000–02FFFF 010000–017FFF SA3 0 0 0 0 1 1 64/32 030000–03FFFF 018000–01FFFF SA4 0 0 0 1 0 0 64/32 040000–04FFFF 020000–027FFF SA5 0 0 0 1 0 1 64/32 050000–05FFFF 028000–02FFFF SA6 0 0 0 1 1 0 64/32 060000–06FFFF 030000–037FFF SA7 0 0 0 1 1 1 64/32 070000–07FFFF 038000–03FFFF SA8 0 0 1 0 0 0 64/32 080000–08FFFF 040000–047FFF SA9 0 0 1 0 0 1 64/32 090000–09FFFF 048000–04FFFF SA10 0 0 1 0 1 0 64/32 0A0000–0AFFFF 050000–057FFF SA11 0 0 1 0 1 1 64/32 0B0000–0BFFFF 058000–05FFFF SA12 0 0 1 1 0 0 64/32 0C0000–0CFFFF 060000–067FFF SA13 0 0 1 1 0 1 64/32 0D0000–0DFFFF 068000–06FFFF SA14 0 0 1 1 1 0 64/32 0E0000–0EFFFF 070000–077FFF SA15 0 0 1 1 1 1 64/32 0F0000–0FFFFF 078000–07FFFF SA16 0 1 0 0 0 0 64/32 100000–10FFFF 080000–087FFF SA17 0 1 0 0 0 1 64/32 110000–11FFFF 088000–08FFFF SA18 0 1 0 0 1 0 64/32 120000–12FFFF 090000–097FFF SA19 0 1 0 0 1 1 64/32 130000–13FFFF 098000–09FFFF SA20 0 1 0 1 0 0 64/32 140000–14FFFF 0A0000–0A7FFF SA21 0 1 0 1 0 1 64/32 150000–15FFFF 0A8000–0AFFFF SA22 0 1 0 1 1 0 64/32 160000–16FFFF 0B0000–0B7FFF SA23 0 1 0 1 1 1 64/32 170000–17FFFF 0B8000–0BFFFF SA24 0 1 1 0 0 0 64/32 180000–18FFFF 0C0000–0C7FFF SA25 0 1 1 0 0 1 64/32 190000–19FFFF 0C8000–0CFFFF SA26 0 1 1 0 1 0 64/32 1A0000–1AFFFF 0D0000–0D7FFF SA27 0 1 1 0 1 1 64/32 1B0000–1BFFFF 0D8000–0DFFFF SA28 0 1 1 1 0 0 64/32 1C0000–1CFFFF 0E0000–0E7FFF SA29 0 1 1 1 0 1 64/32 1D0000–1DFFFF 0E8000–0EFFFF SA30 0 1 1 1 1 0 64/32 1E0000–1EFFFF 0F0000–0F7FFF SA31 0 1 1 1 1 1 64/32 1F0000–1FFFFF 0F8000–0FFFFF SA32 1 0 0 0 0 0 64/32 200000–20FFFF 100000–107FFF SA33 1 0 0 0 0 1 64/32 210000–21FFFF 108000–10FFFF SA34 1 0 0 0 1 0 64/32 220000–22FFFF 110000–117FFF SA35 1 0 0 0 1 1 64/32 230000–23FFFF 118000–11FFFF SA36 1 0 0 1 0 0 64/32 240000–24FFFF 120000–127FFF SA37 1 0 0 1 0 1 64/32 250000–25FFFF 128000–12FFFF SA38 1 0 0 1 1 0 64/32 260000–26FFFF 130000–137FFF SA39 1 0 0 1 1 1 64/32 270000–27FFFF 138000–13FFFF SA40 1 0 1 0 0 0 64/32 280000–28FFFF 140000–147FFF SA41 1 0 1 0 0 1 64/32 290000–29FFFF 148000–14FFFF SA42 1 0 1 0 1 0 64/32 2A0000–2AFFFF 150000–157FFF SA43 1 0 1 0 1 1 64/32 2B0000–2BFFFF 158000–15FFFF December 14, 2005 Am29LV320MH/L 13 D A T A S H E E T Table 2. Sector Address Table (Continued) A20-A15 Sector Sector Size (Kbytes/Kwords) 8-bit Address Range (in hexadecimal) 16-bit Address Range (in hexadecimal) SA44 1 0 1 1 0 0 64/32 2C0000–2CFFFF 160000–167FFF SA45 1 0 1 1 0 1 64/32 2D0000–2DFFFF 168000–16FFFF SA46 1 0 1 1 1 0 64/32 2E0000–2EFFFF 170000–177FFF SA47 1 0 1 1 1 1 64/32 2F0000–2FFFFF 178000–17FFFF SA48 1 1 0 0 0 0 64/32 300000–30FFFF 180000–187FFF SA49 1 1 0 0 0 1 64/32 310000–31FFFF 188000–18FFFF SA50 1 1 0 0 1 0 64/32 320000–32FFFF 190000–197FFF SA51 1 1 0 0 1 1 64/32 330000–33FFFF 198000–19FFFF SA52 1 1 0 1 0 0 64/32 340000–34FFFF 1A0000–1A7FFF SA53 1 1 0 1 0 1 64/32 350000–35FFFF 1A8000–1AFFFF SA54 1 1 0 1 1 0 64/32 360000–36FFFF 1B0000–1B7FFF SA55 1 1 0 1 1 1 64/32 370000–37FFFF 1B8000–1BFFFF SA56 1 1 1 0 0 0 64/32 380000–38FFFF 1C0000–1C7FFF SA57 1 1 1 0 0 1 64/32 390000–39FFFF 1C8000–1CFFFF SA58 1 1 1 0 1 0 64/32 3A0000–3AFFFF 1D0000–1D7FFF SA59 1 1 1 0 1 1 64/32 3B0000–3BFFFF 1D8000–1DFFFF SA60 1 1 1 1 0 0 64/32 3C0000–3CFFFF 1E0000–1E7FFF SA61 1 1 1 1 0 1 64/32 3D0000–3DFFFF 1E8000–1EFFFF SA62 1 1 1 1 1 0 64/32 3E0000–3EFFFF 1F0000–1F7FFF SA63 1 1 1 1 1 1 64/32 3F0000–3FFFFF 1F8000–1FFFFF Notes: The address range is A20:A-1 in byte mode (BYTE# = VIL) or A20:A0 in word mode (BYTE# = VIH). 14 Am29LV320MH/L December 14, 2005 D A T A S H E E T Autoselect Mode In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 2). Table 3 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0. The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Tables 10 and 11. This method does not require VID. Refer to the Autoselect Command Sequence section for more information. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A3, A2, A1, and A0 must be as shown in Table 3. Table 3. CE# Manufacturer ID: AMD L Device ID Description OE# WE# L H Autoselect Codes, (High Voltage Method) A20 A14 to to A15 A10 X X A8 to A7 A6 A5 to A4 A3 to A2 A1 A0 VID X L X L L L 00 X 01h L L H 22 X 7Eh H H L 22 X 1Dh H H H 22 X 00h Cycle 1 Cycle 2 L L H X X DQ8 to DQ15 A9 VID X L X Cycle 3 BYTE# BYTE# = VIH = VIL DQ7 to DQ0 Sector Protection Verification L L H SA X VID X L X L H L X X 01h (protected), 00h (unprotected) SecSi Sector Indicator Bit (DQ7), WP# protects highest address sector L L H X X VID X L X L H H X X 98h (factory locked), 18h (not factory locked) SecSi Sector Indicator Bit (DQ7), WP# protects lowest address sector L L H X X VID X L X L H H X X 88h (factory locked), 08h (not factory locked) Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. December 14, 2005 Am29LV320MH/L 15 D A T A S H E E T Sector Group Protection and Unprotection Table 4. Sector Group Protection/Unprotection Address Table The hardware sector group protection feature disables both program and erase operations in any sector group. In this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see Table 4). The hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. Sector group protection/unprotection can be implemented via two methods. Sector Group A20–A15 SA0 000000 SA1 000001 SA2 000010 SA3 000011 Sector protection/unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 24 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector group unprotect, all unprotected sector groups must first be protected prior to the first sector group unprotect write cycle. The device is shipped with all sector groups unprotected. AMD offers the option of programming and protecting sector groups at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector group is protected or unprotected. See the Autoselect Mode section for details. 16 Am29LV320MH/L SA4–SA7 0001xx SA8–SA11 0010xx SA12–SA15 0011xx SA16–SA19 0100xx SA20–SA23 0101xx SA24–SA27 0110xx SA28–SA31 0111xx SA32–SA35 1000xx SA36–SA39 1001xx SA40–SA43 1010xx SA44–SA47 1011xx SA48–SA51 1100xx SA52–SA55 1101xx SA56–SA59 1110xx SA60 111100 SA61 111101 SA62 111110 SA63 111111 December 14, 2005 D A T A S H E E T Write Protect (WP#) The Write Protect function provides a hardware method of protecting the first or last sector without using VID. Write Protect is one of two functions provided by the WP#/ACC input. shows the algorithm, and Figure 23 shows the timing diagrams, for this feature. START If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the first or last sector independently of whether those sectors were protected or unprotected using the method described in “Sector Group Protection and Unprotection”. Note that if WP#/ACC is at VIL when the device is in the standby mode, the maximum input load current is increased. See the table in “DC Characteristics”. RESET# = VID (Note 1) Perform Erase or Program Operations If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the first or last sector was previously set to be protected or unprotected using the method described in “Sector Group Protection and Unprotection”. Note: No external pullup is necessary since the WP#/ACC pin has internal pullup to VCC. RESET# = VIH Temporary Sector Group Unprotect Completed (Note 2) Temporary Sector Group Unprotect (Note: In this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see Table 4). This feature allows temporary unprotection of previously protected sector groups to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once VID is removed from the RESET# pin, all the previously protected sector groups are protected again. Figure 1 December 14, 2005 Notes: 1. All protected sector groups unprotected (If WP# = VIL, the first or last sector will remain protected). 2. All previously protected sector groups are protected once again. Am29LV320MH/L Figure 1. Temporary Sector Group Unprotect Operation 17 D A T A S H E E T START START PLSCNT = 1 RESET# = VID Wait 1 μs Temporary Sector Group Unprotect Mode No PLSCNT = 1 Protect all sector groups: The indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address RESET# = VID Wait 1 μs First Write Cycle = 60h? First Write Cycle = 60h? Temporary Sector Group Unprotect Mode Yes Yes Set up sector group address No All sector groups protected? Yes Sector Group Protect: Write 60h to sector group address with A6–A0 = 0xx0010 Set up first sector group address Sector Group Unprotect: Write 60h to sector group address with A6–A0 = 1xx0010 Wait 150 µs Verify Sector Group Protect: Write 40h to sector group address with A6–A0 = 0xx0010 Increment PLSCNT No Reset PLSCNT = 1 Read from sector group address with A6–A0 = 0xx0010 Wait 15 ms Verify Sector Group Unprotect: Write 40h to sector group address with A6–A0 = 1xx0010 Increment PLSCNT No No PLSCNT = 25? Read from sector group address with A6–A0 = 1xx0010 Data = 01h? Yes No Yes Device failed Protect another sector group? Yes PLSCNT = 1000? No Yes Remove VID from RESET# Device failed Write reset command Sector Group Protect Algorithm Set up next sector group address No Data = 00h? Yes Last sector group verified? No Yes Sector Group Protect complete Sector Group Unprotect Algorithm Remove VID from RESET# Write reset command Sector Group Unprotect complete Figure 2. 18 In-System Sector Group Protect/Unprotect Algorithms Am29LV320MH/L December 14, 2005 D A T A S H E E T SecSi (Secured Silicon) Sector Flash Memory Region Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. Unless otherwise specified, the device is shipped such that the customer may program and protect the 256-byte SecSi sector. AMD offers the device with the SecSi Sector either customer lockable (standard shipping option) or factory locked (contact an AMD sales representative for ordering information). The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to program the sector after receiving the device. The customer-lockable version also has the SecSi Sector Indicator Bit permanently set to a “0.” The factory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. The SecSi sector address space in this device is allocated as follows: Table 5. SecSi Sector Address Range 000000h–000007h SecSi Sector Contents Customer Lockable Determined by customer 000008h–00007Fh ESN Factory Locked ExpressFlash Factory Locked ESN ESN or determined by customer Unavailable Determined by customer The system accesses the SecSi Sector through a command sequence (see “Enter SecSi Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the first sector (SA0). This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to sector SA0. December 14, 2005 The system may program the SecSi Sector using the write-buffer, accelerated and/or unlock bypass methods, in addition to the standard programming command sequence. See Command Definitions. Programming and protecting the SecSi Sector must be used with caution since, once protected, there is no procedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. The SecSi Sector area can be protected using one of the following procedures: ■ Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, except that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. ■ To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is programmed, locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing within the remainder of the array. Factory Locked: SecSi Sector Programmed and Protected At the Factory In devices with an ESN, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. An ESN Factory Locked device has an 16-byte random ESN at addresses 000000h–000007h. Please contact your local AMD sales representative for details on ordering ESN Factory Locked devices. Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service (Express Flash Factory Locked). The devices are then shipped from AMD’s factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Am29LV320MH/L 19 D A T A S H E E T caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. START RESET# = VIH or VID Wait 1 μs Write 60h to any address Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Remove VIH or VID from RESET# Write reset command Write Pulse “Glitch” Protection Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Figure 3. SecSi Sector Protect Verify complete Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. SecSi Sector Protect Verify Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Tables 10 and 11 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 6–9. To terminate reading CFI data, the system must write the reset command. 20 The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 6–9. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies of these documents. Am29LV320MH/L December 14, 2005 D A T A S H E E T Table 6. CFI Query Identification String Addresses (x16) Addresses (x8) Data 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h Query Unique ASCII string “QRY” 13h 14h 26h 28h 0002h 0000h Primary OEM Command Set 15h 16h 2Ah 2Ch 0040h 0000h Address for Primary Extended Table 17h 18h 2Eh 30h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 32h 34h 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) Description Table 7. System Interface String Addresses (x16) Addresses (x8) Data 1Bh 36h 0027h VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 38h 0036h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 3Eh 0007h Typical timeout per single byte/word write 2N µs 20h 40h 0007h Typical timeout for Min. size buffer write 2N µs (00h = not supported) 21h 42h 000Ah Typical timeout per individual block erase 2N ms 22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 46h 0001h Max. timeout for byte/word write 2N times typical 24h 48h 0005h Max. timeout for buffer write 2N times typical 25h 4Ah 0004h Max. timeout per individual block erase 2N times typical 26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported) December 14, 2005 Description Am29LV320MH/L 21 D A T A S H E E T Table 8. Addresses (x16) 22 Addresses (x8) Device Geometry Definition Data Description N 27h 4Eh 0016h Device Size = 2 byte 28h 29h 50h 52h 0002h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 54h 56h 0005h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported) 2Ch 58h 0001h Number of Erase Block Regions within device (01h = uniform device, 02h = boot device) 2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 003Fh 0000h 0000h 0001h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 0000h 0000h 0000h 0000h Erase Block Region 2 Information (refer to CFI publication 100) 35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0000h 0000h 0000h 0000h Erase Block Region 3 Information (refer to CFI publication 100) 39h 3Ah 3Bh 3Ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h Erase Block Region 4 Information (refer to CFI publication 100) Am29LV320MH/L December 14, 2005 D A T A S H E E T Table 9. Primary Vendor-Specific Extended Query Addresses (x16) Addresses (x8) Data 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h Query-unique ASCII string “PRI” 43h 86h 0031h Major version number, ASCII 44h 88h 0033h Minor version number, ASCII 45h 8Ah 0008h Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Description Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit 46h 8Ch 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 8Eh 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 90h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 92h 0004h Sector Protect/Unprotect scheme 04 = 29LV800 mode 4Ah 94h 0000h Simultaneous Operation 00 = Not Supported, X = Number of Sectors in Bank 4Bh 96h 0000h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 98h 0001h Page Mode Type 00 = Not Supported, 01 = 4 Word/8 Byte Page, 02 = 8 Word/16 Byte Page 4Dh 9Ah 00B5h 4Eh 9Ch 00C5h 4Fh 9Eh 0004h/ 0005h 50h A0h 0001h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top WP# protect Program Suspend 00h = Not Supported, 01h = Supported COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Tables 10 and 11 define the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens December 14, 2005 first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after Am29LV320MH/L 23 D A T A S H E E T which the system can read data from any non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read parameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write the Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation. Autoselect Command Sequence The autoselect command sequence allows the host system to read several identifier codes at specific addresses: Identifier Code A7:A0 (x16) A6:A-1 (x8) Manufacturer ID 00h 00h Device ID, Cycle 1 01h 02h Device ID, Cycle 2 0Eh 1Ch Device ID, Cycle 3 0Fh 1Eh SecSi Sector Factory Protect 03h 06h Sector Protect Verify (SA)02h (SA)04h Note: The device ID is read over three cycles. SA = Sector Address Tables 10 and 11 show the address requirements and codes. This method is an alternative to that shown in Table 3, which is intended for PROM programmers and requires V ID on address pin A9. The autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence: The system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in Erase Suspend). Enter SecSi Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing an 8-word/16-byte random Electronic Serial Number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. Tables 10 and 11 show the address and data requirements for both command sequences. See also “SecSi (Secured Silicon) Sector Flash Memory Region” for further information. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Word/Byte Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written 24 Am29LV320MH/L December 14, 2005 D A T A S H E E T next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Tables 10 and 11 show the address and data requirements for the word/byte program command sequence, respectively. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a program operation is in progress. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Tables 10 and 11 show the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to the read mode. December 14, 2005 Write Buffer Programming Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system will program 6 unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits AMAX–A4. All subsequent add r e s s / d a t a p a i r s m u s t fa l l w i t h i n t h e selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer pages. This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. The host s y s t e m m u s t t h e r e fo r e a c c o u n t fo r l o a d i n g a write-buffer location more than once. The counter decrements for each data load operation, not for each unique write-buffer-address location. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. Am29LV320MH/L 25 D A T A S H E E T The write-buffer programming operation can be suspended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. command sequence must be written to reset the device for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is required when using Write-Buffer-Programming features in Unlock Bypass mode. The Write Buffer Programming Sequence can be aborted in the following ways: Accelerated Program ■ Load a value that is greater than the page buffer size during the Number of Locations to Program step. ■ Write to an address in a sector different than the one specified during the Write-Buffer-Load command. ■ Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. ■ Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset 26 The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. In addition, no external pullup is necessary since the WP#/ACC pin has internal pullup to VCC. Figure 5 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 17 for timing diagrams. Am29LV320MH/L December 14, 2005 D A T A S H E E T Write “Write to Buffer” command and Sector Address Part of “Write to Buffer” Command Sequence Write number of addresses to program minus 1(WC) and Sector Address Write first address/data Yes WC = 0 ? No Write to a different sector address Abort Write to Buffer Operation? Yes Write to buffer ABORTED. Must write “Write-to-buffer Abort Reset” command sequence to return to read mode. No (Note 1) Write next address/data pair WC = WC - 1 Write program buffer to flash sector address Notes: Read DQ7 - DQ0 at Last Loaded Address When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page. 2. DQ7 may change simultaneously with DQ5. Therefore, DQ7 should be verified. 3. If this flowchart location was reached because DQ5= “1”, then the device FAILED. If this flowchart location was reached because DQ1= “1”, then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be written before the device can begin another operation. If DQ1=1, write the Write-Buffer-Programming-Abort-Reset command. if DQ5=1, write the Reset command. 4. See Table 11 for command sequences required for write buffer programming. Yes DQ7 = Data? No 1. No No DQ1 = 1? DQ5 = 1? Yes Yes Read DQ7 - DQ0 with address = Last Loaded Address (Note 2) DQ7 = Data? Yes No (Note 3) FAIL or ABORT Figure 4. December 14, 2005 PASS Write Buffer Programming Operation Am29LV320MH/L 27 D A T A S H E E T Program Suspend/Program Resume Command Sequence START The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the program operation within 15 μs (maximum) 5μs typical and updates the status bits. Addresses are not required when writing the Program Suspend command. Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? Yes Increment Address No Last Address? Yes Programming Completed Note: See Tables 10 and 11 for program command sequence. Figure 5. Program Operation No After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the SecSi Sector area (One-time Program area), then user must use the proper command sequences to enter and exit this region. The system may also write the autoselect command sequence when the device is in the Program Suspend mode. The system can read as many autoselect codes as required. When the device exits the autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information. The system must write the Program Resume command (address bits are don’t care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device has resume programming. 28 Am29LV320MH/L December 14, 2005 D A T A S H E E T When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to the Write Operation Status section for information on these status bits. Program Operation or Write-to-Buffer Sequence in Progress Write address/data XXXh/B0h Write Program Suspend Command Sequence Command is also valid for Erase-suspended-program operations Wait 15 μs Read data as required Autoselect and SecSi Sector read operations are also allowed Data cannot be read from erase- or program-suspended sectors Done reading? No Write Program Resume Command Sequence Device reverts to operation prior to Program Suspend Figure 6. Figure 7 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams. Sector Erase Command Sequence Yes Write address/data XXXh/30h Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Program Suspend/Program Resume Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Tables 10 and 11 show the address and data requirements for the chip erase command sequence. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a erase operation is in progress. Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Tables 10 and 11 show the address and data requirements for the sector erase command sequence. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a erase operation is in progress. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the ris- December 14, 2005 Am29LV320MH/L 29 D A T A S H E E T ing edge of the final WE# pulse in the command sequence. Refer to the Write Operation Status section for more information. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector. Refer to the Write Operation Status section for information on these status bits. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the Autoselect Mode and Autoselect Command Sequence sections for details. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 7 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. To resume the sector erase operation, the system must write the Erase Resume command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Note: During an erase operation, this flash device performs multiple internal operations which are invisible to the system. When an erase operation is suspended, any of the internal operations that were not fully completed must be restarted. As such, if this flash device is continually issued suspend/resume commands in rapid succession, erase progress will be impeded as a function of the number of suspends. The result will be a longer cumulative erase time than without suspends. Note that the additional suspends do not affect device reliability or future performance. In most systems rapid erase/suspend activity occurs only briefly. In such cases, erase performance will not be significantly impacted. START Write Erase Command Sequence (Notes 1, 2) When the Erase Suspend command is written during the sector erase operation, the device requires a typical of 5 µs (maximum of 20 μs) to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. Data Poll to Erasing Bank from System After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard word program operation. No Data = FFh? Yes Erasure Completed Notes: 1. See Tables 10 and 11 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 7. 30 Embedded Erase algorithm in progress Am29LV320MH/L Erase Operation December 14, 2005 D A T A S H E E T Command Definitions Table 10. Read (Note 5) Autoselect (Note 7) Reset (Note 6) Bus Cycles (Notes 2–5) Cycles Command Sequence (Note 1) Command Definitions (x16 Mode, BYTE# = VIH) Addr Data 1 RA RD First Second Addr Data Third Addr Fourth Data Addr Fifth Data 1 XXX F0 Manufacturer ID 4 555 AA 2AA 55 555 90 X00 0001 Device ID (Note 8) 6 555 AA 2AA 55 555 90 X01 227E SecSi™ Sector Factory Protect (Note 9) 4 555 AA 2AA 55 555 90 X03 (Note 9) Sector Group Protect Verify (Note 10) 4 555 AA 2AA 55 555 90 (SA)X02 00/01 Sixth Addr Data Addr Data X0E XX1D X0F XX00 PD Enter SecSi Sector Region 3 555 AA 2AA 55 555 88 Exit SecSi Sector Region 4 555 AA 2AA 55 555 90 XXX 00 Program 4 555 AA 2AA 55 555 A0 PA PD Write to Buffer (Note 11) 6 555 AA 2AA 55 SA 25 SA WC PA PD WBL Program Buffer to Flash 1 SA 29 Write to Buffer Abort Reset (Note 12) 3 555 AA 2AA 55 555 F0 Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass Program (Note 13) 2 XXX A0 PA PD Unlock Bypass Reset (Note 14) 2 XXX 90 XXX 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Program/Erase Suspend (Note 15) 1 XXX B0 Program/Erase Resume (Note 16) 1 XXX 30 CFI Query (Note 17) 1 55 98 Legend: X = Don’t care RA = Read Address of memory location to be read. RD = Read Data read from location RA during read operation. PA = Program Address. Addresses latch on falling edge of WE# or CE# pulse, whichever happens later. PD = Program Data for location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. address sector, data is 88h for factory locked and 08h for not factor locked. 3. Shaded cells indicate read cycles. All others are write cycles. 4. During unlock and command cycles, when lower address bits are 555 or 2AA as shown in table, address bits above A11 and data bits above DQ7 are don’t care. 5. 6. 7. No unlock or command cycles required when device is in read mode. Reset command is required to return to read mode (or to erase-suspend-read mode if previously in Erase Suspend) when device is in autoselect mode, or if DQ5 goes high while device is providing status information. Fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ15–DQ8 are don’t care. Except for RD, PD, and WC. See Autoselect Command Sequence section for more information. 8. Device ID must be read in three cycles. 9. If WP# protects highest address sector, data is 98h for factory locked and 18h for not factory locked. If WP# protects lowest December 14, 2005 SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A20–A15 uniquely select any sector. WBL = Write Buffer Location. Address must be within same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1. 10. Data is 00h for an unprotected sector group and 01h for a protected sector group. 11. Total number of cycles in command sequence is determined by number of words written to write buffer. Maximum number of cycles in command sequence is 21. 12. Command sequence resets device for next command after aborted write-to-buffer operation. 13. Unlock Bypass command is required prior to Unlock Bypass Program command. 14. Unlock Bypass Reset command is required to return to read mode when device is in unlock bypass mode. 15. System may read and program in non-erasing sectors, or enter autoselect mode, when in Erase Suspend mode. Erase Suspend command is valid only during a sector erase operation. 16. Erase Resume command is valid only during Erase Suspend mode. 17. Command is valid when device is ready to read array data or when device is in autoselect mode. Am29LV320MH/L 31 D A T A S H E E T Table 11. Read (Note 6) Autoselect (Note 8) Reset (Note 7) Bus Cycles (Notes 2–5) Cycles Command Sequence (Note 1) Command Definitions (x8 Mode, BYTE# = VIL) Addr Data 1 RA RD First Second Third Fourth Addr Data Addr Data Addr Fifth Data 1 XXX F0 Manufacturer ID 4 AAA AA 555 55 AAA 90 X00 01 Device ID (Note 9) 6 AAA AA 555 55 AAA 90 X02 7E SecSi™ Sector Factory Protect (Note 10) 4 AAA AA 555 55 AAA 90 X06 (Note 10) Sector Group Protect Verify (Note 11) 4 AAA AA 555 55 AAA 90 (SA)X04 00/01 Sixth Addr Data Addr Data X1C 1D X1E 00 Enter SecSi Sector Region 3 AAA AA 555 55 AAA 88 Exit SecSi Sector Region 4 AAA AA 555 55 AAA 90 XXX 00 Program 4 555 AA 2AA 55 555 A0 PA PD Write to Buffer (Note 12) 6 AAA AA 555 55 SA 25 SA BC PA PD WBL PD Program Buffer to Flash 1 SA 29 Write to Buffer Abort Reset (Note 13) 3 AAA AA 555 55 AAA F0 Unlock Bypass 3 AAA AA 555 55 AAA 20 Unlock Bypass Program (Note 13) 2 XXX A0 PA PD Unlock Bypass Reset (Note 15) 2 XXX 90 XXX 00 Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 Sector Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30 Program/Erase Suspend (Note 16) 1 XXX B0 Program/Erase Resume (Note 17) 1 XXX 30 CFI Query (Note 18) 1 AA 98 Legend: X = Don’t care RA = Read Address of memory location to be read. RD = Read Data read from location RA during read operation. PA = Program Address. Addresses latch on falling edge of WE# or CE# pulse, whichever happens later. PD = Program Data for location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A20–A15 uniquely select any sector. WBL = Write Buffer Location. Address must be within same write buffer page as PA. BC = Byte Count. Number of write buffer locations to load minus 1. address sector, data is 88h for factory locked and 08h for not factor locked. 2. All values are in hexadecimal. 3. Shaded cells indicate read cycles. All others are write cycles. 4. During unlock and command cycles, when lower address bits are 555 or AAA as shown in table, address bits above A11 are don’t care. 5. Unless otherwise noted, address bits A20–A11 are don’t cares. 6. No unlock or command cycles required when device is in read mode. 7. Reset command is required to return to read mode (or to erase-suspend-read mode if previously in Erase Suspend) when device is in autoselect mode, or if DQ5 goes high while device is providing status information. 11. Data is 00h for an unprotected sector group and 01h for a protected sector group. 12. Total number of cycles in command sequence is determined by number of words written to write buffer. Maximum number of cycles in command sequence is 21. 13. Command sequence resets device for next command after aborted write-to-buffer operation. 14. Unlock Bypass command is required prior to Unlock Bypass Program command. 15. Unlock Bypass Reset command is required to return to read mode when device is in unlock bypass mode. 8. Fourth cycle of autoselect command sequence is a read cycle. Data bits DQ15–DQ8 are don’t care. See Autoselect Command Sequence section or more information. 16. System may read and program in non-erasing sectors, or enter autoselect mode, when in Erase Suspend mode. Erase Suspend command is valid only during a sector erase operation. 9. Device ID must be read in three cycles. 17. Erase Resume command is valid only during Erase Suspend mode. 10. If WP# protects highest address sector, data is 98h for factory locked and 18h for not factory locked. If WP# protects lowest 32 18. Command is valid when device is ready to read array data or when device is in autoselect mode. Am29LV320MH/L December 14, 2005 D A T A S H E E T WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 12 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. valid data, the data outputs on DQ0–DQ6 may be still invalid. Valid data on DQ0–DQ7 will appear on successive read cycles. Table 12 shows the outputs for Data# Polling on DQ7. Figure 8 shows the Data# Polling algorithm. Figure 20 in the AC Characteristics section shows the Data# Polling timing diagram. DQ7: Data# Polling START The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to the read mode. Read DQ7–DQ0 Addr = VA DQ7 = Data? No No During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has December 14, 2005 Yes DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Am29LV320MH/L Figure 8. Data# Polling Algorithm 33 D A T A S H E E T RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 12 shows the outputs for RY/BY#. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. 34 After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 μs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 12 shows the outputs for Toggle Bit I on DQ6. Figure 9 shows the toggle bit algorithm. Figure 21 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II. Am29LV320MH/L December 14, 2005 D A T A S H E E T DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. START Read DQ7–DQ0 DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 12 to compare outputs for DQ2 and DQ6. Read DQ7–DQ0 Toggle Bit = Toggle? No Yes No Figure 9 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the RY/BY#: Ready/Busy# subsection. Figure 21 shows the toggle bit timing diagram. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. DQ5 = 1? Yes Read DQ7–DQ0 Twice Toggle Bit = Toggle? Reading Toggle Bits DQ6/DQ2 No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 9. Toggle Bit Algorithm Refer to Figure 9 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform December 14, 2005 Am29LV320MH/L 35 D A T A S H E E T other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 9). DQ5: Exceeded Timing Limits DQ5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” In all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- Table 12. Standard Mode Program Suspend Mode Erase Suspend Mode Write-toBuffer mand. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 12 shows the status of DQ3 relative to the other status bits. DQ1: Write-to-Buffer Abort DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a “1”. The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array data. See Write Buffer Write Operation Status DQ7 Status (Note 2) Embedded Program Algorithm DQ7# Embedded Erase Algorithm 0 Program-Suspended ProgramSector Suspend Non-Program Read Suspended Sector Erase-Suspended 1 EraseSector Suspend Non-Erase Suspended Read Sector Erase-Suspend-Program DQ7# (Embedded Program) Busy (Note 3) DQ7# Abort (Note 4) DQ7# DQ6 Toggle Toggle No toggle DQ5 (Note 1) 0 0 DQ3 N/A 1 DQ2 (Note 2) No toggle Toggle DQ1 0 N/A RY/BY# 0 0 Invalid (not allowed) 1 Data 1 0 N/A Toggle N/A Data 1 1 Toggle 0 N/A N/A N/A 0 Toggle Toggle 0 0 N/A N/A N/A N/A 0 1 0 0 Notes: 1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location. 4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation. 36 Am29LV320MH/L December 14, 2005 D A T A S H E E T ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied. . . . . . . . . . . . . . –65°C to +125°C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V 20 ns 20 ns +0.8 V –0.5 V –2.0 V VIO . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V 20 ns A9, OE#, ACC, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.5 V Figure 10. Maximum Negative Overshoot Waveform All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot V SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 10. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 11. 2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is –0.5 V. During voltage transitions, A9, OE#, ACC, and RESET# may overshoot V SS to –2.0 V for periods of up to 20 ns. See Figure 10. Maximum DC input voltage on pin A9, OE#, ACC, and RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns Figure 11. Maximum Positive Overshoot Waveform 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. OPERATING RANGES Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C Supply Voltages VCC full voltage range. . . . . . . . . . . . . . . . . . 2.7–3.6 V VCC regulated voltage range . . . . . . . . . . . . 3.0–3.6 V VIO (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . 1.65–3.6 V Notes: 1. Operating ranges define those limits between which the functionality of the device is guaranteed. 2. See Ordering Information section for valid VCC/VIO range combinations. The I/Os will not operate at 3 V when VIO = 1.8 V. December 14, 2005 Am29LV320MH/L 37 D A T A S H E E T DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description (Notes) Test Conditions Min Typ Max Unit ±1.0 µA ILI Input Load Current (1) VIN = VSS to VCC, VCC = VCC max ILIT A9, ACC Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA ILR Reset Leakage Current VCC = VCC max; RESET# = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (2, 3) CE# = VIL, OE# = VIH, ICC2 VCC Initial Page Read Current (2, 3) CE# = VIL, OE# = VIH ICC3 VCC Intra-Page Read Current (2, 3) CE# = VIL, OE# = VIH ICC4 VCC Active Write Current (3, 4) ICC5 5 MHz 3 34 1 MHz 13 43 1 MHz 4 50 10 MHz 40 80 10 MHz 3 20 33 MHz 6 40 mA CE# = VIL, OE# = VIH 50 60 mA VCC Standby Current (3) CE#, RESET# = VCC ± 0.3 V, WP# = VIH 1 5 µA ICC6 VCC Reset Current (3) RESET# = VSS ± 0.3 V, WP# = VIH 1 5 µA ICC7 Automatic Sleep Mode (3, 5) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V, WP# = VIH 1 5 µA VIL1 Input Low Voltage 1(5, 6) –0.5 0.8 V VIH1 Input High Voltage 1 (5, 6) 1.9 VCC + 0.5 V VIL2 Input Low Voltage 2 (5, 7) –0.5 0.3 x VIO V VIH2 Input High Voltage 2 (5, 7) 1.9 VIO + 0.5 V VHH Voltage for ACC Program Acceleration VCC = 2.7 –3.6 V 11.5 12.5 V VID Voltage for Autoselect and Temporary VCC = 2.7 –3.6 V Sector Unprotect 11.5 12.5 V VOL Output Low Voltage 0.15 x VIO V VOH1 VOH2 Output High Voltage IOL = 4.0 mA, VCC = VCC min = VIO mA mA IOH = –2.0 mA, VCC = VCC min = VIO 0.85 VIO V IOH = –100 µA, VCC = VCC min = VIO VIO–0.4 V VLKO Low VCC Lock-Out Voltage (8) 2.3 2.5 V VIL1 Input Low Voltage 1(5, 6) –0.5 0.8 V Notes: 1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 5.0 µA. 2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 3. Maximum ICC specifications are tested with VCC = VCCmax. 4. ICC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. TIf VIO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. If VIO < VCC, minimum VIH for CE# and DQ I/Os is 0.7 VIO. Maximum VIH for these connections is VIO + 0.3 V 6. VCC voltage requirements. 7. VIO voltage requirements. 8. Not 100% tested. 9. Includes RY/BY# 38 Am29LV320MH/L December 14, 2005 D A T A S H E E T TEST CONDITIONS Table 13. 3.3 V Test Condition 2.7 kΩ Device Under Test CL Test Specifications 6.2 kΩ All Speeds Output Load 1 TTL gate Output Load Capacitance, CL (including jig capacitance) 30 pF Input Rise and Fall Times 5 ns 0.0–3.0 V Input timing measurement reference levels (See Note) 1.5 V Output timing measurement reference levels 0.5 VIO V Input Pulse Levels Note: Diodes are IN3064 or equivalent Figure 12. Test Setup Unit Note: If VIO < VCC, the reference level is 0.5 VIO. KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H 3.0 V Input Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) 1.5 V Measurement Level 0.5 VIO V Output 0.0 V Note: If VIO < VCC, the input measurement reference level is 0.5 VIO. Figure 13. Input Waveforms and Measurement Levels December 14, 2005 Am29LV320MH/L 39 D A T A S H E E T AC CHARACTERISTICS Read-Only Operations Parameter Speed Options JEDE C Std. Description 90R 101, 101R Min 90 100 110 120 ns CE#, OE# = VIL Max 90 100 110 120 ns OE# = VIL Max 90 100 110 120 ns Max 25 30 30 40 30 40 ns Max 25 30 30 40 30 40 ns Test Setup tAVAV tRC Read Cycle Time (Note 1) tAVQV tACC Address to Output Delay tELQV tCE Chip Enable to Output Delay tPACC Page Access Time 112R 112 120R 120 Unit tGLQV tOE Output Enable to Output Delay tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Min 0 ns Read Min 0 ns Toggle and Data# Polling Min 10 ns Output Enable tOEH Hold Time (Note 1) Notes: 1. Not 100% tested. 2. See Figure 12 and Table 13 for test specifications. 3. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation VIO ≠ VCC. tRC Addresses Stable Addresses tACC CE# tRH tRH tDF tOE OE# tOEH WE# tCE tOH HIGH Z HIGH Z Output Valid Outputs RESET# RY/BY# 0V Figure 14. 40 Read Operation Timing Am29LV320MH/L December 14, 2005 D A T A S H E E T AC CHARACTERISTICS Same Page A21-A2 A1-A0 Aa Ab tPACC tACC Data Bus Qa Ad Ac tPACC Qb tPACC Qc Qd CE# OE# * Figure shows device in word mode. Addresses are A1–A-1 for byte mode. Figure 15. December 14, 2005 Page Read Timings Am29LV320MH/L 41 D A T A S H E E T AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std. Description All Speed Options Unit tReady RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 20 μs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min 50 ns tRPD RESET# Low to Standby Mode Min 20 μs Note: 1. Not 100% tested 2. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC.. RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#, OE# RESET# tRP Figure 16. 42 Reset Timings Am29LV320MH/L December 14, 2005 D A T A S H E E T AC CHARACTERISTICS Erase and Program Operations Parameter Speed Options 90R 101, 101R 112, 112R 90 100 110 120, 120R Unit JEDEC Std. Description tAVAV tWC Write Cycle Time (Note 1) Min tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 45 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 ns tWHDL tWPH Write Pulse Width High Min 30 ns Write Buffer Program Operation (Notes 2, 3) Typ 240 µs Per Byte Typ 7.5 µs Per Word Typ 15 µs Per Byte Typ 6.25 µs Per Word Typ 12.5 µs tWLAX Effective Write Buffer Program Operation (Notes 2, 4) tWHWH1 tWHWH1 Accelerated Effective Write Buffer Program Operation (Notes 2, 5) Byte Single Word/Byte Program Operation (Notes 2, 5) ns 60 Typ µs Word 60 Byte Accelerated Single Word/Byte Programming Operation (Note 2) tWHWH2 120 54 Typ µs Word 54 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tVHH VHH Rise and Fall Time (Note 1) Min 250 ns tVCS VCC Setup Time (Note 1) Min 50 µs tVCS tBUSY WE# to RY/BY# Min tPOLL Program Valid Before Status Polling (Note 7) Max 90 100 110 4 120 ns µs Notes: 1. Not 100% tested. 6. 2. See the “Erase And Programming Performance” section for more information. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. 7. 3. For 1–16 words/1–32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. 5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. December 14, 2005 Am29LV320MH/L 43 D A T A S H E E T AC CHARACTERISTICS Program Command Sequence (last two cycles) tAS tWC Addresses Read Status Data (last two cycles) 555h PA PA PA tAH CE# tCH OE# tPOLL tWP WE# tWPH tCS tDS tDH PD A0h Data tWHWH1 Status tBUSY DOUT tRB RY/BY# VCC tVCS Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode. Figure 17. Program Operation Timings VHH ACC VIL or VIH VIL or VIH tVHH Figure 18. 44 tVHH Accelerated Program Timing Diagram Am29LV320MH/L December 14, 2005 D A T A S H E E T AC CHARACTERISTICS Erase Command Sequence (last two cycles) tAS tWC 2AAh Addresses Read Status Data VA SA VA 555h for chip erase tAH CE# tCH OE# tWP WE# tWPH tCS tWHWH2 tDS tDH Data 55h In Progress 30h Complete 10 for Chip Erase tBUSY tRB RY/BY# tVCS VCC Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”. 2. Illustration shows device in word mode. Figure 19. December 14, 2005 Chip/Sector Erase Operation Timings Am29LV320MH/L 45 D A T A S H E E T AC CHARACTERISTICS tRC Addresses VA tPOLL VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH DQ15 and DQ7 DQ14–DQ8, DQ6–DQ0 Complement Complement Status Data Status Data True True Valid Data Valid Data High Z High Z tBUSY RY/BY# Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 20. 46 Data# Polling Timings (During Embedded Algorithms) Am29LV320MH/L December 14, 2005 D A T A S H E E T AC CHARACTERISTICS tAHT tAS Addresses tAHT tASO CE# tCEPH tOEH WE# tOEPH OE# tDH DQ6/DQ2 tOE Valid Status Valid Status Valid Status (first read) (second read) (stops toggling) Valid Data Valid Data RY/BY# Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle Figure 21. Enter Embedded Erasing WE# Erase Suspend Erase Toggle Bit Timings (During Embedded Algorithms) Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. Figure 22. December 14, 2005 DQ2 vs. DQ6 Am29LV320MH/L 47 D A T A S H E E T AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description tVIDR VID Rise and Fall Time (See Note) tRSP RESET# Setup Time for Temporary Sector Unprotect All Speed Options Unit Min 500 ns Min 4 µs Note: 1. Not 100% tested. 2. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. VID RESET# VID VSS, VIL, or VIH VSS, VIL, or VIH tVIDR tVIDR Program or Erase Command Sequence CE# WE# tRRB tRSP RY/BY# Figure 23. 48 Temporary Sector Group Unprotect Timing Diagram Am29LV320MH/L December 14, 2005 D A T A S H E E T AC CHARACTERISTICS VID VIH RESET# SA, A6, A3, A2, A1, A0 Valid* Valid* Sector Group Protect or Unprotect Data 60h 60h Valid* Verify 40h Status Sector Group Protect: 150 µs, Sector Group Unprotect: 15 ms 1 µs CE# WE# OE# * For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010. Figure 24. December 14, 2005 Sector Group Protect and Unprotect Timing Diagram Am29LV320MH/L 49 D A T A S H E E T AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Parameter Speed Options 90R 101, 101R 112, 112R 120, 120R Unit 90 100 110 120 ns JEDEC Std. Description tAVAV tWC Write Cycle Time (Note 1) Min tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 ns tDVEH tDS Data Setup Time Min 45 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 ns tEHEL tCPH CE# Pulse Width High Min 30 ns Write Buffer Program Operation (Notes 2, 3) Typ 240 µs Per Byte Typ 7.5 µs Per Word Typ 15 µs Per Byte Typ 6.25 µs Per Word Typ 12.5 µs Effective Write Buffer Program Operation (Notes 2, 4) tWHWH1 tWHWH1 Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Byte Single Word/Byte Program Operation (Note 2, 5) Word Accelerated Single Word/Byte Programming Operation (Note 2) tWHWH2 tWHWH2 tRH tPOLL 60 Typ µs 60 Byte 54 Typ Word µs 54 Sector Erase Operation (Note 2, 5) Typ 0.5 sec RESET High Time Before Write (Note 1) Min 50 ns Program Valid before Status Polling (Note 7) Max 4 µs Notes: 1. Not 100% tested. 2. 3. 4. 5. 6. 7. 50 See the “Erase And Programming Performance” section for more information. For 1–16 words/1–32 bytes programmed. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. Am29LV320MH/L December 14, 2005 D A T A S H E E T AC CHARACTERISTICS 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling Addresses PA tWC tAS tAH tWH WE# tPOLL tGHEL OE# tWHWH1 or 2 tCP CE# tWS tCPH tBUSY tDS tDH DQ7#, DQ15 Data tRH A0 for program 55 for erase DOUT PD for program 30 for sector erase 10 for chip erase RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Illustration shows device in word mode. Figure 25. December 14, 2005 Alternate CE# Controlled Write (Erase/Program) Operation Timings Am29LV320MH/L 51 D A T A S H E E T ERASE AND PROGRAMMING PERFORMANCE Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.5 3.5 sec Chip Erase Time 32 64 sec Excludes 00h programming prior to erasure (Note 6) Single Word/Byte Program Time (Note 3) 60 600 µs Accelerated Single Word/Byte Program Time (Note 3) 54 540 µs Total Write Buffer Program Time (Note 4) 240 1200 µs Per Byte 7.5 38 µs Per Word 15 75 µs 200 1040 µs Per Byte 6.25 33 µs Per Word 12.5 65 µs 31.5 73 sec Effective Write Buffer Program Time (Note 5) Total Accelerated Write Buffer Program Time (Note 4) Effective Accelerated Write Buffer Program Time (Note 5) Chip Program Time Excludes system level overhead (Note 7) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, Programming specification assume that all bits are programmed to 00h. 2. Maximum values are measured at VCC = 3.0, worst case temperature. Maximum values are valid up to and including 100,000 program/erase cycles. 3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 4. For 1-16 words or 1-32 bytes programmed in a single write buffer programming operation. 5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation. 6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 7. System-level overhead is the time required to execute the command sequence (s) for the program command. See Tables 12 and 13 for further information on command definitions. 8. The device has a minimum erase and program cycle endurance of 100,000 cycles. LATCHUP CHARACTERISTICS Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V –100 mA +100 mA VCC Current Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. 52 Am29LV320MH/L December 14, 2005 D A T A S H E E T TSOP PIN AND BGA PACKAGE CAPACITANCE Parameter Symbol Parameter Description CIN Input Capacitance COUT Output Capacitance CIN2 Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ Max Unit TSOP 6 7.5 pF BGA 4.2 5 pF TSOP 8.5 12 pF BGA 5.4 6.5 pF TSOP 7.5 9 pF BGA 3.9 4.7 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Description Test Conditions Min Unit 150°C 10 Years 125°C 20 Years Minimum Pattern Data Retention Time December 14, 2005 Am29LV320MH/L 53 D A T A S H E E T PHYSICAL DIMENSIONS TS056/TSR056—56-Pin Standard and Reverse Pinout Thin Small Outline Package (TSOP) PACKAGE JEDEC SYMBOL MO-142 (B) EC MIN. NOM. MAX. 1 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.) A --- --- 1.20 2 PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP). A1 0.05 --- 0.15 3 PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK. A2 0.95 1.00 1.05 4 b1 0.17 0.20 0.23 b c1 0.17 0.10 0.22 --- 0.27 0.16 TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE. 5 DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS 0.15 mm PER SIDE. c 0.10 --- 0.21 6 D 19.90 20.00 20.20 D1 18.30 18.40 18.50 E 13.90 14.00 14.10 DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm. 7 THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 mm AND 0.25 mm FROM THE LEAD TIP. 8. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE SEATING PLANE. 9 DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS. 0.50 BASIC e L 0.50 0.60 0.70 O 0˚ 3˚ 5˚ R 0.08 --- 0.20 N 54 NOTES: TS/TSR 56 56 3160\38.10A Am29LV320MH/L December 14, 2005 D A T A S H E E T PHYSICAL DIMENSIONS LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm Package December 14, 2005 Am29LV320MH/L 55 D A T A S H E E T REVISION SUMMARY Revision A (May 30, 2002) Initial release as Advance Information data sheet. Revision A+1 (September 3, 2002) Byte/Word Program Command Sequence, Sector Erase Command Sequence, and Chip Erase Command Sequence Noted that the SecSi Sector, autoselect, and CFI functions are unavailable when a program or erase operation is in progress. Mirrorbit 32 Mbit Device Family Changed the 48-pin TSOP to 40-pin TSOP. Alternate CE# Controlled Erase and Program Operations Common Flash Memory Interface (CFI) Changed CFI website address. Added tRH parameter to table. CMOS Compatable Erase and Program Operations Added ILR parameter symbol to table. Added tBUSY parameter to table. Removed VIL, VIH, VOL, and VOH and replaced with VIL, VIH, VOL, VOH1 and VOH2. Figure 16. Program Operation Timings Clarified note #5. Added RY/BY# to waveform. Removed note #6. TSOP and BGA PIN Capacitance Read-Only Operations Added the FBGA package. Program Suspend/Program Resume Command Sequence Added note #3. Absolute Maximum Rating Changed 15 μs typical to maximum and added 5 μs typical. Changed the Ambient Temperature with Power Applied from –55°C to +125°C to –65°C to +125°C. Erase Suspend/Erase Resume Commands Revision A+3 (February 14, 2003) Changed typical from 20 μs to 5 μs and added a maximum of 20 μs. Distinctive Characteristics Corrected performance characteristics. Product Selector Guide AC Characteristics Added Note 2. Added Note Ordering Information Added 101R, 112R, and 120R to Valid Combinations Table. Added Note 1. Read-Only Operations Alternate CE# Controlled Erase and Program Operations Input values in the tWHWH1 and tWHWH2 parameters in the Erase and Program Options table that were previously TBD. Also added notes 5 and 6. Input values in the tWHWH1 and tWHWH2 parameters in the Alternate CE# Controlled Erase and Program Options table that were previously TBD. Also added notes 5 and 6. Erase and Programming Performance Erase and Program Operations Added 101R, 112R, and 120R to Speed Options. Input values into table that were previously TBD. Added note 3 and 4. Revision A+2 (November 15, 2002) Revision B (May 7, 2003) Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory Distinctive Characteristics Added second bullet and figure Added typical active read current Product Selector Guide and Read-Only Operations Global Added 30 ns to the 112R and 120R to Max page access time and Max OE# Access time. Converted to full datasheet version. Changed the Chip Enable to Output High Z and Output Enable to Output High Z to 16 ns. 56 Modified SecSi Sector Flash Memory Region section to include ESN references. Am29LV320MH/L December 14, 2005 D A T A S H E E T CMOS Compatible Corrected Typ and Max values for the ICC 1, 2, and 3. Erase and Program Operations and Alternate CE# Controlled Erase and Program Operations Changed Accelerated Effective Write Buffer Program Operation value. Erase and Programming Performance Input values into table that were previously TBD. Modified notes. AC Characteristics Figures - Program Operation Timings, Data# Polling Timings (During Embedded Algorithms, and Alternate CE# Controlled Write (Erase/Program) Operation Timings Updated with tPOLL information. AC Characteristics - Alternate CE# Controlled Erase and Program Operations Added tPOLL information and footnote. Erase and Programming Performance Added tPOLL information and footnote. Removed Word references. Trademarks Revision B +1 (February 12, 2004) Updated. Customer Lockable: SecSi Sector NOT Programmed or Protected at the Factory Cover sheet and Title page Removed second paragraph. Added notation referencing superseding documentation. Table 10 & Table 11: Command Definitions Revision B +2 (October 27, 2004) Replaced the Addr information for both Program/Erase Suspend and Program/Erase Resume from BA to XXX. Ordering Information Erase Suspend/Erase Resume Commands Revision B +3 (December 14, 2005) Added note on flash device performance during suspend/erase mode. Global EOL AC Characteristics - Erase and Program Operations Removed Byte information for tWHWH1 parameter. Added tPOLL information and footnote. Added Lead-free package options. This product has been retired and is not available for designs. For new and current designs, S29GL032A supersedes Am29LV320M H/L and is the factory-recommended migration path. Please refer to the S29GL032A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. Trademarks Copyright © 2004-2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. December 14, 2005 Am29LV320MH/L 57