CDP1823C/3 High-Reliability CMOS 128-Word x 8-Bit Static RAM March 1997 Features Description • For Applications in Aerospace, Military, and Critical Industrial Equipment The CDP1823C/3 is a 128 word x 8-bit CMOS/SOS static random access memory. It is compatible with the CDP1802, CDP1804, CDP1805, and CDP1806 microprocessors, and will interface directly without additional components. The CDP1823C has a recommended operating voltage range of 4V to 6.5V. • Compatible with CDP1800-Series Microprocessors at Maximum Speed • Interfaces with CDP1800-Series without Additional Components Microprocessors • Fast Access Time • At VDD = 5V, +25oC . . . . . . . . . . . . . . . . . . . . . . . . 275ns • Single Voltage Supply • Common Data Inputs and Outputs • Multiple Chip Select Inputs to Simplify Memory System Expansion • High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of VDD • Memory Retention for Standby Battery Voltage Down to 2V at 25oC • Latch-Up-Free Transient Radiation Tolerance Ordering Information PART NUMBER (5V) PACKAGE TEMP. RANGE SBDIP -55oC to +125oC CDP1823CD3 The CDP1823C memory has 8 common data input and data output terminals for direct connection to a bidirectional data bus and is operated from a single voltage supply. Five chip select inputs are provided to simplify memory system expansion. In order to enable the CDP1823C, the chip select inputs CS2, CS3, and CS5 require a low input signal, and the chip select inputs CS1 and CS4 require a high input signal. The MRD signal enables all 8 output drivers when in the low state and should be in a high state during a write cycle. After valid data appear at the output, the address inputs may be changed immediately. Output data will be valid until either the MRD signal goes high, the device is deselected, or tAA (access time) after address changes. PKG. NO. D24.6 Pinout CDP1823C/3 (SBDIP) TOP VIEW BUS 0 1 BUS 1 2 24 VDD 23 A0 BUS 2 3 22 A1 BUS 3 4 21 A2 BUS 4 5 20 A3 BUS 5 6 19 A4 BUS 6 7 18 A5 BUS 7 8 17 A6 CS1 9 16 MWR CS2 10 15 MRD CS3 11 14 CS5 VSS 12 13 CS4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 6-31 File Number 2982.1 CDP1823C/3 OPERATIONAL MODES FUNCTION MRD MWR CS1 CS2 CS3 CS4 CS5 Read 0 X 1 0 0 1 0 Storage State of Addressed Word Write 1 0 1 0 0 1 0 Input High Impedance Standby 1 1 1 0 0 1 0 High Impedance Not Selected X X X X X X X X X X 0 X X X X X 1 X X X X X 1 X X X X X 0 X X X X X 1 High Impedance NOTE: 1. Logic 1 = High, Logic 0 = Low, X = Don’t Care. 6-32 BUS TERMINAL STATE CDP1823C/3 Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1823C/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) SBDIP Package . . . . . . . . . . . . . . . . . . 60 17 Maximum Operating Temperature Range (TA) . . . .-55oC to +125oC Maximum Storage Temperature Range (TSTG) . . .-65oC to +150oC Maximum Lead Temperature (During Soldering) . . . . . . . . . +265oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150oC Recommended Operating Conditions At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: LIMITS PARAMETER MIN MAX UNITS 4 6.5 V VSS VDD V Supply Voltage Range Recommended Input Voltage Range Static Electrical Specifications VDD = 5V ±5% CONDITIONS LIMITS -55oC, +25oC PARAMETER +125oC VO (V) VIN (V) VDD (V) MIN MAX MIN MAX UNITS Quiescent Device Current (Note 1) IDD - 0, 5 5 - 270 - 1000 µA Output Low (Sink) Current (Note 1) IOL 0.4 0, 5 5 2.7 - 1.5 - mA Output High (Source) Current (Note 1) IOH 4.6 0, 5 5 - -1.3 - -0.7 mA Output Voltage Low-Level VOL - 0, 5 5 - 0.1 - 0.1 V Output Voltage High-Level VOH - 0, 5 5 VDD - 0.1 - VDD - 0.1 - V Input Low Voltage VIL 0.5, 4.5 - 5 - 0.3 VDD - 0.3 VDD V Input High Voltage VIH 0.5, 4.5 - 5 0.7 VDD - 0.7 VDD - V Input Leakage Current (Note 1) IIN - 0, 5 5 - ±2.6 - ±10 µA Operating Current (Note 1) IDD1 - 0, 5 5 - 5 - 10 mA Three-State Output Leakage Current IOUT 0, 5 0, 5 5 - ±2.6 - ±10 µA Input Capacitance CIN - - - - 7.5 - 7.5 pF Output Capacitance COUT - - - - 15 - 15 pF NOTE: 1. Limits designate 100% testing, all other limits are designer’s parameters under given test conditions and do not represent 100% testing. Read Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF LIMITS +25oC, -55oC +125oC SYMBOL VDD (V) MIN MAX MIN MAX UNITS Read Cycle tRC 5 360 - 505 - ns Access Time from Address Change (Note 1) tAA 5 - 360 - 505 ns Access Time from Chip Select tAC 5 - 360 - 505 ns PARAMETER 6-33 CDP1823C/3 Read Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF (Continued) LIMITS +25oC, -55oC +125oC SYMBOL VDD (V) MIN MAX MIN MAX UNITS Access Time from MRD (Note 1) tAM 5 - 310 - 435 ns Data Hold Time After Read tDH 5 50 - 70 - ns PARAMETER NOTE: 1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing. tRC tAA ADDRESS tAM (NOTE 1) MRD CS2, CS3, CS5 (NOTE 1) tAC CS1, CS4 tDH 90% VALID DATA HIGH IMPEDANCE 10% NOTES: 1. Minimum timing for valid data output. Longer times will initiate an earlier but invalid output. 2. MWR is high during read operation. Timing measurement reference is 0.5VDD. FIGURE 1. READ CYCLE TIMING DIAGRAM Write Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF LIMITS +25oC, -55oC +125oC SYMBOL VDD (V) (NOTE 2) MIN MAX (NOTE 2) MIN MAX UNITS Write Cycle tWC 5 280 - 400 - ns Address Setup Time (Note 1) tAS 5 70 - 100 - ns Address Hold Time tAH 5 70 - 100 - ns Write Pulse Width (Note 1) tWW 5 140 - 200 - ns Data to MWR Setup Time (Note 1) tDS 5 70 - 100 - ns PARAMETER 6-34 CDP1823C/3 Write Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF (Continued) LIMITS +25oC, -55oC +125oC SYMBOL VDD (V) (NOTE 2) MIN MAX (NOTE 2) MIN MAX UNITS Data Hold Time from MWR (Note 1) tDH 5 50 - 70 - ns Chip Select Setup tCS 5 210 - 300 - ns PARAMETER NOTES: 1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing. 2. Minimum timing to allow the indicated function to occur. tWC tAS ADDRESS tAH CS1, CS4 tCS CS2, CS3, CS5 tWW MWR tDS BUS 0-7 tDH VALID DATA NOTE: 1. MRD must be high during write operation. FIGURE 2. WRITE CYCLE TIMING WAVEFORMS Data Retention Specifications TEST CONDITIONS LIMITS +25oC, -55oC +125oC SYMBOL VDR (V) VDD (V) MIN MAX MIN MAX UNITS Minimum Data Retention Voltage (Note 1) VDR - - - 2 - 2.5 V Data Retention Quiescent Current IDD 2 - - 100 - 400 µA tCDR - 5 450 - 650 - ns tRC - 5 450 - 650 - ns PARAMETER Chip Deselect to Data Retention Time Recovery to Normal Operation Time NOTE: 1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing. 6-35 CDP1823C/3 DATA RETENTION MODE VDD 0.95 VDD 0.95 VDD VDR tCDR tf tr tRC CS VIH VIH VIL VIL FIGURE 3. LOW VDD DATA RETENTION WAVEFORMS 1 24 VDD 2 23 A0 3 22 A1 4 21 A2 5 20 A3 6 19 A4 7 18 A5 8 17 A6 A12 9 16 01 A11 10 15 A7 11 14 A8 12 13 A9 R A15 R A14 R A13 A10 R = 10kΩ ±20% PACKAGE TEMPERATURE DURATION VDD D 125oC 160 Hrs 7V 0 1.6 2.2 5.0 6.6 7.2 10.0 VDD 01 0 VDD 0 A0 VDD A1 0 NOTE: 1. A1 - A11 are division by 2 based on A0. FIGURE 4. DYNAMIC/OPERATING BURN-IN CIRCUIT AND TIMING DIAGRAM All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 6-36