Revised January 1999 CD4029BC Presettable Binary/Decade Up/Down Counter General Description The CD4029BC is a presettable up/down counter which counts in either binary or decade mode depending on the voltage level applied at binary/decade input. When binary/ decade is at logical “1”, the counter counts in binary, otherwise it counts in decade. Similarly, the counter counts up when the up/down input is at logical “1” and vice versa. A logical “1” preset enable signal allows information at the “jam” inputs to preset the counter to any state asynchronously with the clock. The counter is advanced one count at the positive-going edge of the clock if the carry in and preset enable inputs are at logical “0”. Advancement is inhibited when either or both of these two inputs is at logical “1”. The carry out signal is normally at logical “1” state and goes to logical “0” state when the counter reaches its maximum count in the “up” mode or the minimum count in the “down” mode provided the carry input is at logical “0” state. All inputs are protected against static discharge by diode clamps to both VDD and VSS. Features ■ Wide supply voltage range: ■ High noise immunity: 3V to 15V 0.45 VDD (typ.) ■ Low power TTL compatibility: or 1 driving 74LS fan out of 2 driving 74L ■ Parallel jam inputs ■ Binary or BCD decade up/down counting Ordering Code: Package Number Package Description CD4029BCWM Order Number M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide body CD4029BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4029BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC and SOP Top View © 1999 Fairchild Semiconductor Corporation DS005960.prf www.fairchildsemi.com CD4029BC Presettable Binary/Decade Up/Down Counter October 1987 CD4029BC Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) −0.5V to +18 VDC DC Supply Voltage (VDD) Input Voltage (VIN) DC Supply Voltage (VDD) −0.5V to VDD + 0.5 VDC −65°C to +150°C Storage Temperature Range (TS) 700 mW Small Outline 500 mW Symbol IDD VOL Parameter Quiescent Device Current LOW Level Output Voltage VOH HIGH Level Output Voltage VIL VIH IOL IIN (Note 2) −40°C Conditions Min Max +25°C Min Typ +85°C Max Min Max Units VDD = 5V 20 20 150 µA VDD = 10V 40 40 300 µA VDD = 15V 80 80 600 µA |IO| < 1 µA VDD = 5V 0.05 0 0.05 0.05 V VDD = 10V 0.05 0 0.05 0.05 V VDD = 15V 0.05 0 0.05 0.05 V |IO| < 1 µA VDD = 5V 4.95 4.95 5 4.95 V VDD = 10V 9.95 9.95 10 9.95 V VDD = 15V 14.95 14.95 15 14.95 V LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 1.5 1.5 V Input Voltage VDD = 10V, VO = 1V or 9V 3.0 3.0 3.0 V VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0 V HIGH Level VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5 V Input Voltage VDD = 10V, VO = 1V or 9V 7.0 7.0 7.0 V VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0 V VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA LOW Level Output VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA HIGH Level Output VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA Current (Note 3) VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.9 mA VDD = 15V, VO = 13.5V −3.6 Input Current VDD = 15V, VIN = 0V −0.3 −10−5 −0.3 −1.0 µA VDD = 15V, VIN = 15V 0.3 10−5 0.3 1.0 µA Current (Note 3) IOH Note 2: VSS = 0V unless otherwise specified. 260°C DC Electrical Characteristics −40°C to +85°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Lead Temperature (TL) (Soldering, 10 seconds) 0V to VDD VDC Operating Temperature Range (TA) Power Dissipation (PD) Dual-In-Line 3V to 15 VDC Input Voltage (VIN) −3.0 −8.8 −2.4 mA Note 3: IOH and IOL are tested one output at a time. 3 www.fairchildsemi.com CD4029BC Absolute Maximum Ratings(Note 1) (Note 2) CD4029BC AC Electrical Characteristics (Note 4) TA = 25°C, CL = 50 pF, RL = 200k, Input trCL = tfCL = 20 ns, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units CLOCKED OPERATION tPHL or tPLH tPHL or tPLH tPHL or tPLH Propagation Delay Time VDD = 5V 200 400 ns to Q Outputs VDD = 10V 85 170 ns VDD = 15V 70 140 ns Propagation Delay Time VDD = 5V 320 640 ns to Carry Output VDD = 10V 135 270 ns VDD = 15V 110 220 ns ns Propagation Delay Time VDD = 5V 285 570 VDD = 10V 120 240 ns VDD = 15V 95 190 ns Transition Time/Q VDD = 5V 100 200 ns or Carry Output VDD = 10V 50 100 ns VDD = 15V 40 80 ns Minimum Clock VDD = 5V 160 320 ns Pulse Width VDD = 10V 70 135 ns 55 110 to Carry Output tTHL or tTLH tWH or tWL CL = 15 pF VDD = 15V trCL or tfCL Maximum Clock Rise and Fall Time tSU Minimum Set-Up Time 15 µs VDD = 10V 10 µs VDD = 15V 5 Maximum Clock Frequency µs VDD = 5V 180 360 ns VDD = 10V 70 140 ns 55 110 VDD = 15V fCL ns VDD = 5V ns VDD = 5V 1.5 3.1 VDD = 10V 3.7 7.4 MHz VDD = 15V 4.5 9 MHz MHz CIN Average Input Capacitance Any Input 5 CPD Power Dissipation Capacitance Per Package (Note 5) 65 7.5 pF Propagation Delay Time VDD = 5V 285 570 to Q output VDD = 10V 115 230 ns VDD = 15V 95 195 ns Propagation Delay Time VDD = 5V 400 800 ns to Carry Output VDD = 10V 165 330 ns VDD = 15V 135 260 ns VDD = 5V 80 160 ns pF PRESET ENABLE OPERATION tPHL or tPLH tPHL or tPLH tWH Minimum Preset Enable VDD = 10V 30 60 ns VDD = 15V 25 50 ns Minimum Preset Enable VDD = 5V 150 300 ns Removal Time VDD = 10V 60 120 ns VDD = 15V 50 100 ns Propagation Delay Time VDD = 5V 265 530 ns to Carry Output VDD = 10V 110 220 ns VDD = 15V 90 180 ns Pulse Width tREM ns CARRY INPUT OPERATION tPHL or tPLH tPHL, tPLH Propagation Delay Time to Carry Output CL = 15 pF VDD = 5V 200 400 ns VDD = 10V 85 170 ns VDD = 15V 70 140 ns Note 4: *AC Parameters are guaranteed by DC correlated testing. Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application note, AN-90. www.fairchildsemi.com 4 CD4029BC Logic Waveforms Decade Mode Binary Mode 5 www.fairchildsemi.com CD4029BC Switching Time Waveforms Cascading Packages Parallel Clocking Ripple Clocking Carry out lines at the 2nd or later stages may have a negative-going spike due to differential internal delays. These spikes do not affect counter operation, but if the carry out is used to trigger external circuitry the carry out should be gated with the clock. www.fairchildsemi.com 6 CD4029BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M16B 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 7 www.fairchildsemi.com CD4029BC Presettable Binary/Decade Up/Down Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.