TI1 BQ33100PW Super capacitor manager capacitance learning esr measurement Datasheet

bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Super Capacitor Manager
Check for Samples: bq33100
FEATURES
1
•
•
•
•
•
•
•
•
•
Fully Integrated 2, 3, 4 and 5 Series Super
Capacitor Manager
Can Be Used With Up To 9 Series Capacitors
Without Individual Integrated Capacitor
Monitoring & Balancing
Active Capacitor Voltage Balancing
– Prevents Super Capacitor Overvoltage
during Charging
and Capacitor Health Monitoring
– Capacitance Learning
– ESR Measurement
– Operation Status
– State of Charge
– State of Health
– Charging Voltage and Current Reports
– Safety Alerts with Optional Pin Indication
Integrated Protection Monitoring and Control
– Over Voltage
– Short Circuit
– Excessive Temperature
– Excessive Capacitor Leakage
2 Wire SMBus Serial Communications
High-Accuracy 16-Bit Delta-Sigma ADC With a
16-Channel Multiplexer for Measurement
– Used for Voltage, Current and Temperature
Low Power Consumption
– <450uA in Normal Operating Mode
– <1uA in Shutdown Mode
Wide Operating Temperature: -40°C to +85°C
APPLICATIONS
•
•
•
•
•
•
•
Battery Backup Replacement
Cache Controllers
RAID Systems
Server Blade Cards
UPS
Medical and Test Equipment
Portable Instruments
DESCRIPTION
The Texas Instruments bq33100 Super Capacitor
Manager is a fully integrated, single-chip, solution that
provides a rich array of features for managing, charge
control, monitoring, and protection, for either 2, 3, 4
or 5 series Super Capacitors with individual capacitor
monitoring and balancing or up to 9 series capacitors
with only the stack voltage being measured. With a
small footprint of 7.8 x 6.4 mm in a compact 24-pin
TSSOP
package,
the
bq33100
maximizes
functionality and safety while dramatically increasing
ease of use and cutting the solution cost and size for
Super Capacitor applications.
Using its integrated high-performance analog
peripherals, the bq33100 measures and maintains an
accurate
record
of
available
capacitance,
state-of-health, voltage, current, temperature, and
other critical parameters in Super Capacitors, and
reports the information to the system host controller
over a 2-wire SMBus 1.1 compatible interface.
The bq33100 provides firmware controlled protection
on overvoltage, overtemperature, and overcharge
along with hardware controlled protection for
overcurrent in discharge and short circuit protection
during charge and discharge.
ORDERING INFORMATION
TA
AGE
24 PIN TSSOP (PW) Tube
–40°C to 85°C
(1)
(2)
bq33100PW
(1)
24 PIN TSSOP (PW) Tape & Reel
bq33100PWR (2)
A single tube quantity is 60 units.
A single reel quantity is 2000 units
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PIN DETAILS
TSSOP (PW)
(TOP VIEW)
VCCPACK
1
24
VCC
NC
2
23
CHG
VC1
3
22
NC
VC2
4
21
CHGOR
VC3
5
20
REG 27
VC4
6
19
GND
SRP
7
18
RBI
SRN
8
17
LLEN
TS
9
16
SCL
VC5
10
15
FAULT
CHGLVL0
11
14
SDA
CHGLVL1
12
13
VC5BAL
Table 1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
VCC
1
P
Power supply from power
NC
2
O
Not used and should be connected to VCC
VC1
3
IA
Sense voltage input terminal and external capacitor voltage balancing drive output for the 5th series
capacitor, and stack measurement input. See 'Series Capacitor Configuration' for systems with less than 5
series
VC2
4
IA
Sense voltage input terminal and external capacitor voltage balancing drive output for the 4th series
capacitor. See 'Series Capacitor Configuration' for systems with less than 5 series
VC3
5
IA
Sense voltage input terminal and external capacitor voltage balancing drive output for the 3rd series
capacitor. See 'Series Capacitor Configuration' for systems with less than 5 series
VC4
6
IA
Sense voltage input terminal and external capacitor voltage balancing drive output for the 2nd series
capacitor. See 'Series Capacitor Configuration' for systems with less than 5 series
SRP
7
IA
Analog input pin connected to the internal ADC peripheral for measuring a small voltage between SRP and
SRN where SRP is the top of the sense resistor.
SRN
8
IA
Analog input pin connected to the internal ADC peripheral for measuring a small voltage between SRP and
SRN where SRN is the bottom of the sense resistor.
TS
9
IA
Thermistor input
VC5
10
IA
Sense voltage input terminal and external capacitor voltage balancing drive output for the 1st capacitor. See
'Series Capacitor Configuration' for systems with less than 5 series
CHGLVL
0
11
O
Charge Control Output 0
CHGLVL
1
12
O
Charge Control Output 1
VC5BAL
13
O
Cell balance control output for the least positive capacitor
SDA
14
I/OD
FAULT
15
O
SCL
16
I/OD
LLEN
17
O
Learn Load Enable Output
RBI
18
P
RAM backup pin to provide backup potential to the internal DATA RAM if power is momentarily lost by using
a capacitor attached between RBI and GND
GND
19
P
Ground
REG27
20
P
Internal power supply 2.7V bias output
CHGOR
21
I
CHG Over Ride input. If not used connect to VSS
2
Serial Data: Transmits and Receives data
Active high output to indicate fault condition.
Serial clock input: Clocks data on SDA
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Table 1. Pin Functions (continued)
PIN
NAME
I/O
NO.
DESCRIPTION
NC
22
-
No connect, leave pin floating
CHG
23
O
P-Channel FET drive for controlling charge
VCC
24
P
Positive input from power supply
SYSTEM PARTITIONING DIAGRAM
Charger
Out +
Load+
Charge
Enable
ESR
Learning
Charger Voltage
Regulation
SDA
SCL
CHG
LVL1
CHG
LVL0
LLEN
CHG
REG27
CHGOR
VCC
VCCPACK
RBI
Regulator
Power Mode
Control
FET Drive
GND
SuperCap
Pack
Serial
Communications
VC1
AFE HW
Control
System Control
Watchdog
Oscillator
Data Flash
Memory
VC2
Voltage
Measurement
Cell Voltage Mux
& Translation
VC3
Charging
Algorithm
Over
Temperature
Protection
Temperature
Measurement
Over- &
UnderVoltage
Protection
Over
Current
Protection
SuperCap
Management
External Cell
Balancing Driver
VC4
Coloumb
Counter
HW Over
Current &
Short Circuit
Protection
VC5
VC5BAL
bq33100
SRN
TS
SRP
Pack Current
Sense
Load-
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
3
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted) (1)
VMAX
Supply voltage range
–0.3 to 34
V
V
VVC3–0.3 to VVC3+8.5
V
VC3
VVC4–0.3 to VVC4+8.5
V
VC4
VSRP–0.3 to VSRP+8.5
V
–0.3 to VREG27
V
SDA, SCL
–0.3 to 6.0
V
CHGOR
-0.3 to VCC
V
–0.3 to VREG27 + 0.3
V
–0.3 to VCC
V
-0.3 to VREG27+0.3
V
VC2
Input voltage range
SRP, SRN
TS, VC5, CHGLVL0, CHGLVL1, FAULT
CHG
VO
Output voltage range
UNIT
VVC2–0.3 to VVC2+8.5 or 34,
whichever is lower
VCC w.r.t. GND
VC1, VCC
VIN
VALUE
VC5BAL
RBI, REG27
–0.3 to 2.75
V
50
mA
ISS
Maximum combined sink current for input pins
TFUNC
Functional temperature
–40 to 110
°C
TSTG
Storage temperature range
–65 to 150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage
VCC
VCC
VSTARTUP
Start up voltage at VCC
VSHUTDOWN
VCC or VCC, whichever is higher
VIN
Input voltage range
5.2
3
Operating temperature
4
3.2
V
5.5
V
3.3
V
VVC2
VVC2+5
V
VC2
VVC3
VVC3+5
VC3
VVC4
VVC4+5
VC4
VSRP
VSRP+5
VCn – VC(n+1), (n=1, 2, 3, 4 )
0
5
VC5
0
1
0
VCC - 0.3
V
–0.3
1
V
SRP to SRN
External 2.7V REG capacitor
VVC2+5
UNIT
VC1, VCC
CHGOR
TOPR
MAX
25
3.8
VCC
CREG27
TYP
25
μF
1
–40
Submit Documentation Feedback
85
°C
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
GENERAL PURPOSE I/O
Typical values stated where TA = 25°C and VCC = VCC = 14.4V, Min/Max values stated where TA = -40°C to 85°C and VCC
= VCC = 3.8V to 25V (unless otherwise noted)
PARAMETER
TEST CONDITION
VIH
High-level input voltage
SDA, SCL, TS, VC5
VIL
Low-level input voltage
SDA, SCL, TS, VC5
VOH
Output voltage high
SDA, SCL, VC5BAL, CHGLVL0, CHGLVL1,
LLEN, FAULT, IL = –0.5 mA
VOL
Low-level output voltage
SDA, SCL, VC5BAL, CHGLVL0, CHGLVL1,
LLEN, FAULT, IL = 7 mA
CIN
Input capacitance
MIN
TYP
MAX
UNIT
2
V
0.8
V
VREG27–0.5
V
0.4
V
5
pF
SDA, SCL, TS, VC5, CHGLVL0, CHGLVL1,
LLEN, FAULT
SDA and SCL pull-down disabled
Ilkg
Input leakage current
VCHGOR
CHG Over Ride active high
RPD(SMBx)
SDA and SCL pull-down
TA = –40°C to 100°C
RPAD
Pad resistance
TS
μA
1
0.8
2.0
3.2
600
950
1300
kΩ
V
87
110
Ω
SUPPLY CURRENT
Typical values stated where TA = 25°C and VCC = VCC = 14.4V, Min/Max values stated where TA = -40°C to 85°C and VCC
= VCC = 3.8V to 25V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
ICC
Normal mode
Firmware running, no flash writes
450
ISHUTDOWN
Shutdown mode
TA = –40°C to 110°C
0.5
MAX
UNIT
μA
1
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
μA
5
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
REG27 LDO
Typical values stated where TA = 25°C and VCC = VCC = 14.4V, Min/Max values stated where TA = -40°C to 85°C and VCC
= VCC = 3.8V to 25V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.5
2.7
2.75
V
2.22
2.35
2.34
V
At REG27
2.25
2.5
2.6
V
Regulator output change
with temperature
IREG = 10 mA
TA = –40°C to 85°C
ΔV(REGLINE)
Line regulation
IREG = 10 mA
ΔV(REGLOAD)
Load regulation
IREG = 0.2 to 10 mA
I(REGMAX)
Current limit
VREG
Regulator output voltage
IREG27 = 10 mA
TA = –40°C to 85°C
VREG27IT–
Negative-going POR
voltage
At REG27
VREG27IT+
Positive-going POR
voltage
ΔV(REGTEMP)
±0.5%
25
±2
±4
mV
±20
±40
mV
50
mA
COULOMB COUNTER
Typical values stated where TA = 25°C and VCC = VCC = 14.4V, Min/Max values stated where TA = -40°C to 85°C and VCC
= VCC = 3.8V to 25V (unless otherwise noted)
PARAMETER
TEST CONDITION
Input voltage range
Conversion time
Single conversion
Effective resolution
Single conversion
Integral nonlinearity
TA = –25°C to 85°C
Offset error
MIN
TYP
-0.20
(1)
V
250
ms
Bits
±0.007
±0.034
%FSR
0.3
0.5
μV/°C
0.2%
0.8%
TA = –25°C to 85°C
μV
10
–0.8%
Full-scale error drift
150
Effective input resistance
(1)
(2)
UNIT
0.25
15
Offset error drift
Full-scale error (2)
MAX
2.5
PPM/°C
MΩ
Post Calibration Performance
Uncalibrated performance. This gain error can be eliminated with external calibration.
ADC
Typical values stated where TA = 25°C and VCC = VCC = 14.4V, Min/Max values stated where TA = -40°C to 85°C and VCC
= VCC = 3.8V to 25V (unless otherwise noted)
PARAMETER
Input voltage range
TEST CONDITION
MIN
TYP
–0.2
TS, VC5
Conversion time
31.5
Resolution (no missing codes)
16
Effective resolution
14
70
Offset error drift
Full-scale error
–0.8%
VIN = 1 V
6
160
±0.2%
8
%FSR
μV
μV/°C
0.4%
150
Effective input resistance
(1)
Bits
1
Full –scale error drift
V
Bits
±0.020
(1)
UNIT
ms
15
Integral nonlinearity
Offset error
MAX
0.8×VREG27
PPM/°C
MΩ
Channel to channel offset
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
EXTERNAL CAPACITOR VOLTAGE BALANCE DRIVE
Typical values stated where TA = 25°C and VCC = VCC = 14.4V, Min/Max values stated where TA = -40°C to 85°C and VCC
= VCC = 3.8V to 25V (unless otherwise noted)
PARAMETER
RBAL_drive
Internal pull-down
resistance for external
capacitor voltage
balance
TEST CONDITIONS
MIN
TYP
Capacitor voltage balance ON for VC1, VCi-VCi+1 = 4V,
where i = 1~4
5.7
Capacitor voltage balance ON for VC2, VCi-VCi+1 = 4V,
where = i = 1~4
3.7
Capacitor voltage balance ON for VC3, VCi-VCi+1 = 4V,
where = i = 1~4
1.75
Capacitor voltage balance ON for VC4, VCi-VCi+1 = 4V,
where = i = 1~4
0.85
MAX
UNIT
kΩ
CAPACITOR VOLTAGE MONITOR
Typical values stated where TA = 25°C and VCC = VCC = 14.4V, Min/Max values stated where TA = -40°C to 85°C and VCC
= VCC = 3.8V to 25V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
CAPACITOR Voltage Measurement Accuracy
TYP
MAX
UNIT
TA = –10°C to 60°C
MIN
±10
±20
mV
TA = –40°C to 85°C
±10
±35
INTERNAL TEMPERATURE SENSOR
Typical values stated where TA = 25°C and VCC = VCC = 14.4V, Min/Max values stated where TA = -40°C to 85°C and VCC
= VCC = 3.8V to 25V (unless otherwise noted)
PARAMETER
T(TEMP)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±3%
Temperature sensor accuracy
°C
THERMISTOR MEASUREMENT SUPPORT
Typical values stated where TA = 25°C and VCC = VCC = 14.4V, Min/Max values stated where TA = -40°C to 85°C and VCC
= VCC = 3.8V to 25V (unless otherwise noted)
PARAMETER
RERR
Internal resistor drift
R
Internal resistor
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–230
TS1, TS2
ppm/°C
17
20
kΩ
INTERNAL THERMAL SHUTDOWN
Typical values stated where TA = 25°C and VCC = VCC = 14.4V, Min/Max values stated where TA = -40°C to 85°C and VCC
= VCC = 3.8V to 25V (unless otherwise noted)
PARAMETER (1)
TMAX
Maximum REG27 temperature
TRECOVER
Recovery hysteresis temperature
(1)
TEST CONDITIONS
MIN
TYP
125
MAX
UNIT
175
°C
°C
10
Parameters assured by design. Not production tested.
HIGH FREQUENCY OSCILLATOR
Typical values stated where TA = 25°C and VCC = VCC = 14.4V, Min/Max values stated where TA = -40°C to 85°C and VCC
= VCC = 3.8V to 25V (unless otherwise noted)
PARAMETER
f(OSC)
MIN
TYP
TA = –20°C to 70°C
–2%
±0.25%
2%
TA = –40°C to 85°C
–3%
±0.25%
3%
3
6
Operating frequency of CPU clock
f(EIO)
Frequency error (1)
t(SXO)
Start-up time (2)
(1)
(2)
TEST CONDITIONS
MAX
UNIT
2.097
TA = –25°C to 85°C
MHz
ms
The frequency drift is included and measured from the trimmed frequency at VCC = VCC = 14.4 V, TA = 25°C
The startup time is defined as the time it takes for the oscillator output frequency to be ±3% when the device is already powered.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
7
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
LOW FREQUENCY OSCILLATOR
Typical values stated where TA = 25°C and VCC = VCC = 14.4V, Min/Max values stated where TA = -40°C to 85°C and VCC
= VCC = 3.8V to 25V (unless otherwise noted)
PARAMETER
f(LOSC)
Operating frequency
f(LEIO)
Frequency error (1)
t(LSXO)
Start-up time (2)
(1)
(2)
TEST CONDITIONS
MIN
TYP
MAX
32.768
MHz
TA = –20°C to 70°C
–1.5%
±0.25%
1.5%
TA = –40°C to 85°C
–2.5%
±0.25%
2.5%
TA = –25°C to 85°C
UNIT
100
ms
The frequency drift is included and measured from the trimmed frequency at VCC = VCC = 14.4 V, TA = 25°C.
The startup time is defined as the time it takes for the oscillator output frequency to be ±3%.
RAM BACKUP
Typical values stated where TA = 25°C and VCC = VCC = 14.4V, Min/Max values stated where TA = -40°C to 85°C and VCC
= VCC = 3.8V to 25V (unless otherwise noted)
I(RBI)
PARAMETER
TEST CONDITIONS
RBI data-retention input current
VRBI > V(RBI)MIN, VREG27 < VREG27IT-, TA =
70°C to 110°C
MIN
TYP
MAX
UNIT
20
1500
nA
VRBI > V(RBI)MIN, VREG27 < VREG27IT-, TA
= –40°C to 70°C
RBI data-retention voltage (1)
V(RBI)
(1)
500
1
V
Specified by design. Not production tested.
FLASH
Typical values stated where TA = 25°C and VCC = VCC = 14.4V, Min/Max values stated where TA = -40°C to 85°C and VCC
= VCC = 3.8V to 25V (unless otherwise noted)
PARAMETER (1)
TEST CONDITIONS
Data retention
Row programming time
t(MASSERASE)
Mass-erase time
t(PAGEERASE)
Page-erase time
ICC(PROG)
Flash-write supply current
ICC(ERASE)
Flash-erase supply current
(1)
8
TYP
MAX
10
Flash programming write-cycles
t(ROWPROG)
MIN
UNIT
Years
20k
Cycles
2
ms
250
ms
25
ms
4
6
mA
TA = –40°C to 0°C
8
22
TA = 0°C to 85°C
3
15
mA
Specified by design. Not production tested
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
CURRENT PROTECTION THRESHOLDS
Typical values stated where TA = 25°C and VCC = VCC = 14.4V, Min/Max values stated where TA = -40°C to 85°C and VCC
= VCC = 3.8V to 25V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(OCD)
OCD detection threshold voltage range, typical
ΔV(OCDT)
OCD detection threshold voltage program step
V(SCCT)
SCC detection threshold voltage range, typical
ΔV(SCCT)
SCC detection threshold voltage program step
V(SCDT)
SCD detection threshold voltage range, typical
ΔV(SCDT)
SCD detection threshold voltage program step
V(OFFSET)
SCD, SCC and OCD offset
V(Scale_Err)
SCD, SCC and OCD scale error
MIN
TYP
MAX
RSNS = 0
50
200
RSNS = 1
25
100
RSNS = 0
10
RSNS = 1
5
RSNS = 0
RSNS = 1
RSNS = 0
RSNS is set in
STATE_CTL
register
–300
–50
–225
-50
RSNS = 0
100
450
RSNS = 1
50
225
50
RSNS = 1
25
mV
mV
-25
RSNS = 0
mV
mV
–100
RSNS = 1
UNIT
mV
mV
–10
10
–10%
10%
mV
CURRENT PROTECTION TIMING
Typical values stated where TA = 25°C and VCC = VCC = 14.4V, Min/Max values stated where TA = -40°C to 85°C and VCC
= VCC = 3.8V to 25V (unless otherwise noted)
PARAMETER
t(OCDD)
Overcurrent in discharge delay
t(OCDD_STEP)
OCDD step options
t(SCDD)
Short circuit in discharge delay
t(SCDD_STEP)
SCDD step options
t(SCCD)
Short circuit in charge delay
t(SCCD_STEP)
SCCD step options
t(DETECT)
Current fault detect time
tACC
Overcurrent and short circuit
delay time accuracy
TEST CONDITIONS
MIN
TYP
1
MAX
31
2
0
915
AFE.STATE_CNTL[SCDDx2] = 1
0
1830
61
AFE.STATE_CNTL[SCDDx2] = 1
122
0
915
35
160
–20%
20%
Accuracy of typical delay time with no WDI
input
–50%
50%
Submit Documentation Feedback
Product Folder Link(s): bq33100
μs
μs
Accuracy of typical delay time with WDI active
Copyright © 2011, Texas Instruments Incorporated
μs
μs
61
VSRP-SRN = VTHRESH + 12.5 mV,
TA = –40°C to 85°C
ms
ms
AFE.STATE_CNTL[SCDDx2] = 0
AFE.STATE_CNTL[SCDDx2] = 0
UNIT
μs
9
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
SMBus
Typical values stated where TA = 25°C and VCC = VCC = 14.4V, Min/Max values stated where TA = -40°C to 85°C and VCC
= VCC = 3.8V to 25V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
UNIT
100
kHz
SMBus operating frequency
Slave mode, SCL 50% duty cycle
fMAS
SMBus master clock frequency
Master mode, no clock low slave extend
tBUF
Bus free time between start and stop
4.7
μs
tHD:STA
Hold time after (repeated) start
4.0
μs
tSU:STA
Repeated start setup time
4.7
μs
tSU:STO
Stop setup time
4.0
μs
tHD:DAT
Data hold time
tSU:DAT
Data setup time
tTIMEOUT
Error signal/detect
tLOW
Clock low period
10
MAX
fSMB
51.2
Receive mode
0
Transmit mode
300
kHz
ns
250
See
(1)
ns
25
35
ms
μs
4.7
tHIGH
Clock high period
See
(2)
50
μs
tLOW:SEXT
Cumulative clock low slave extend time
See
(3)
25
ms
tLOW:MEXT
Cumulative clock low master extend
time
See
(4)
10
ms
tF
Clock/data fall time
See
(5)
300
ns
tR
Clock/data rise time
See
(6)
1000
ns
(1)
(2)
(3)
(4)
(5)
(6)
4.0
The bq33100 times out when any clock low exceeds tTIMEOUT
tHIGH, Max, is the minimum bus idle time. SCL = SDA = 1 for t > 50 μs causes reset of any transaction involving bq33100 that is in
progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0). If NC_SMB is set then
the timeout is disabled.
tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
Rise time tR = VILMAX – 0.15) to (VIHMIN + 0.15)
Fall time tF = 0.9VDD to (VILMAX – 0.15)
SMBus Timing
t LOW
tR
tF
t HD:STA
SCL
t SU:STA
t HIGH
t HD:STA
t HD:DAT
t SU:STO
t SU:DAT
SDATA
t BUF
P
S
S
P
SMBus tTIMEOUT
Start
Stop
t LOW:SEXT
t LOW:MEXT
SCLACK
1
t LOW:MEXT
SCLACK
1
t LOW:MEXT
SCL
SDATA
(1)
10
SCLACK is the acknowledge-related clock pulse generated by the master.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
OVERVIEW
Super Capacitor Measurements
The bq33100 measures the series capacitor voltages or stack voltage, current and temperature using a
delta-sigma analog-to-digital converter (ADC). The bq33100 uses this measured data and advanced algorithms
to determine the State-of-Health and available capacitance of the Super Capacitor .
Voltage
The bq33100 has two separate modes, Normal mode and Stack mode, where measurements and taken and
managed differently. The setting of Operation Cfg [STACK] to 1 enables Stack mode otherwise the bq33100
operates in normal mode.
The bq33100 updates the individual series capacitor voltages at one (1) second intervals when in Normal mode
and measurers the stack voltage at one (1) second intervals when in Stack mode . The internal ADC of the
bq33100 measures the voltage, scales, and offsets, and calibrates it appropriately. To ensure an accurate
differential voltage sensing, the IC ground should be connected directly to the most negative terminal of the
Super Capacitor stack, not to the positive side of the sense resistor. This minimizes the voltage drop across the
PCB trace.
Current, Charge and Discharge Counting
The delta-sigma ADC measures the system current of the Super Capacitor by measuring the voltage drop across
a small-value sense resistor (typically 5 mΩ to 20 mΩ typ.) between the SRP and SRN pins. The ADC measures
bipolar signals from -0.20 V to 0.25 V.
Device Calibration
The bq33100 requires voltage calibration to maximize accuracy of the monitoring system, the bq33100
evaluation software can perform this calibration. The external filter resistors, connected from each capacitor to
the VCx input of the bq33100, are required to be 1kΩ.
The bq33100 can automatically calibrate its offset between the A to D converter and the input of the high voltage
translation circuit during normal operation for maximum capacitor voltage measurement accuracy.
Temperature
The bq33100 has an internal temperature sensor and input for an external temperature sensor input, TS. The
external input is used in conjunction with an NTC thermistor (default is Semitec 103AT) to sense the Super
Capacitor temperature. The bq33100 can be configured to use internal or external temperature sensors.
Series Capacitor Configuration
The bq33100 can be used to monitor 2, 3, 4 or 5 capacitors in series. The appropriate connectivity for the
different options are detailed in the following table.
Table 2. Series Capacitor Connectivity
bq33100 Pin
5-Series
4-Series
3-Series
2-Series
VC1
P of Top (5th) Cap
P of 4th Cap
Short to VC2
Short to VC2
VC2
P of 4th Cap, N of 5th Cap
P of 3rd Cap, N of 4th
Cap
P of 3rd Cap
Short to VC3
VC3
P of 3rd Cap, N of 4th Cap
P of 2nd Cap, N of 3rd
Cap
P of 2nd Cap, N of 3rd Cap
P of 2nd Cap
VC4
P of 2nd Cap, N of 3rd Cap
P of Bottom (1st) Cap, N P of Bottom (1st) Cap, N of 2nd
of 2nd Cap
Cap
P of Bottom (1st) Cap, N of 2nd
Cap
VC5
P of Bottom (1st) Cap, N of
2nd Cap
N of Bottom Cap (1st)
N of Bottom Cap (1st)
N of Bottom Cap (1st)
VSS
N of Bottom Cap (1st)
Short to VC5
Short to VC5
Short to VC5
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
11
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Note: The CC0...CC2 bits in Operation Cfg should be programmed to match the corresponding configuration.
When in Stack mode (Operation Cfg [STACK] =1) VC1 should be connected to VC2 and VC3 connected to VC4.
Additionally a 'divide by 2' resistor divider should be connected between the top and bottom of the capacitor
array with VC1,2 being the top and VC3,4 being the middle and VSS being the bottom. In this configuration pins
VC5 and VC5BAL are not used and should be connected to VSS.
Charge Control Features
The bq33100 charge control features can report the appropriate charging voltage and charging current via
communications bus if host or charge controller requires. The bq33100 can also report charging status and faults
through status registers and, optionally, the FAULT pin.
CHG Over Ride Control
The CHG output of the bq33100 is typically controlled automatically but can be over ridden through the CHGOR
pin (pin 21). On a low -to-high transition the CHG output is released turning off the external CHG FET and on a
high-to-low transition the CHG output is pulled low after a programmable delay.
Note: The CHG FET will remain OFF until OperationStatus [LTE] is set or through control via the SMBus
command FETControl. Once [LTE] is set then CHG will be controlled automatically.
Capacitor Voltage Balance Control
During charging and when in Normal mode, this feature reduces the voltage difference of the Super Capacitors
gradually using a voltage-based balancing algorithm. This prevents fully charged capacitors from overcharging
and causing excessive degradation and also increases the usable energy by preventing premature charge
termination.
If voltage balancing is required a voltage threshold can be set up for voltage balancing to be active. When
balancing the bq33100 control allows a weak, internal pull-down for VC1 to VC4 pin. The purpose of this weak
pull-down is to enable an external FET for current bypass. Series resistors placed between the input VC1 to VC4
pins and the positive Super Capacitor terminals, control the VGS of the external FET. The lowest capacitor is
slightly different and uses the VC5BAL output to enable the capacitor bypass
Lifetime Data Logging Features
The bq33100 offers limited lifetime data logging for the following critical Super Capacitor parameters for analysis
purposes:
• Lifetime maximum temperature
• Lifetime minimum temperature
• Lifetime maximum capacitor voltage
Safety Detection Features
The bq33100 supports a wide range of Super Capacitor and system safety features that can easily be configured
to act on the CHG output (pin 23) and/or the FAULT output (pin 15).
•
•
•
•
•
•
•
Overvoltage detection for individual series capacitors
Overcurrent detection during charging and discharging
Short circuit detection during charging and discharging
Overtemperature detection during charging
Voltage imbalance detection
Internal AFE clock and communication fault detections
State of Health degradation detection
Communications
The bq33100 uses SMBus v1.1 for host communications although an SMBus slave can be communicated with
via an I2C master.
12
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
SMBus On and Off State
The bq33100 detects a SMBus off state when SCL and SDA are logic-low for ≥ 2 seconds. Clearing this state
requires either SCL or SDA to transition high. Within 1 ms, the communication bus is available.
Power Modes
The bq33100 supports 2 different power modes:
•
•
In Normal Mode, the bq33100 performs measurements, calculations, protection decisions and data updates in
1 second intervals. Between these intervals, the bq33100 is in a reduced power mode.
In Shutdown mode the bq33100 is powered down with only a voltage based wake function operating
NOTATIONAL CONVENTIONS
The following notation is used in this document, if SBS commands and Data Flash values are mentioned within a
text block:
• SBS commands are set in italic, e.g., Voltage
• SBS bits and flags are capitalized, set in italic and enclosed with square brackets, e.g., [SS]
• Data Flash values are set in bold italic e.g., OV Threshold
• All Data Flash bits and flags are capitalized, set in bold italic and enclosed with square brackets, e.g., [OV]
All SBS commands, Data Flash values and flags mentioned in a chapter are listed at the beginning of each
chapter for reference.
The reference format for SBS commands is: SBS:Command Name(Command No.):Manufacturer Access(MA
No.)[Flag], for example:
SBS:Voltage(0x09), or SBS:ManufacterAccess(0x00):Seal Device(0x0020)
DETAILED DESCRIPTION
Capacitance Monitoring and Learning
Monitoring and Control Operational Overview
The bq33100 periodically determines the capacitance and equivalent series resistance (ESR) of the super
capacitor array during normal operation. The Learning Frequency is a register that sets the time between
automatic learning cycles of the Super Capacitor which can also be manually executed by issuing a Learn
command. The bq33100 uses the learning cycles to update the Capacitance and ESR registers accordingly and
both are accessible through the SMBus interface.
Learning process is a multi-step procedure fully controlled by the bq33100 that will perform the following
sequence to learn Capacitance and ESR:
1. Charge to V Learn Max
2. Discharge using constant current load to a minimum voltage of the present charging voltage and internally
record voltage and time
3. Charge to V Learn Max
4. Discharge using constant current load and internally record current and time
5. Calculate Capacitance and ESR based on recorded voltage and current
6. Determine new Charging Voltage
7. Discharge capacitors to Charging Voltage
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
13
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
V
Idle
Charging
Full Charge
Constant Current Discharge
A
Learning
ESR
Delta V
Vbat
B
Linear
Regression
C
Capacita
nce
Delta V
D
Charging
t
Capacita
nce
Delta T
Linear
Regressi
on Base
I
Current
500mA
t
-500mA
Figure 1. Voltage as Current During Learning
Where:
C = I ´ (t [D]- t [C]) (V [C]- V [D])
(1)
and
ESR = (V [A ]- V [B]) I
(2)
Main Monitoring Registers
Capacitance represents the total capacitance in the . The bq33100 computes capacitance in units of F (Farads).
On initialization, the bq33100 sets Capacitance to the data flash value stored in Initial Capacitance. During
subsequent learning cycles, the bq33100 updates Capacitance with the last measured capacitance of the . Once
updated, the bq33100 writes the new Capacitance value to data flash to Capacitance. Capacitance represents
the full Super Capacitor reference for relative state of charge calculations.
InitialCapacitance — The first updated value of Super Capacitor capacitance and represented in units of F.
RelativeStateOfCharge (RSOC) represents the % of available energy and is calculated by:
Capacitance * (Voltage - Vmin) / (Vcharging - Vmin)
Learning Frequency — The Learning Frequency register sets the time between automatic learning cycles of the
Super Capacitor which can also be manually executed by issuing a ManufacturerAccess Learn command. The
bq33100 uses the learning cycles to measure the Super Capacitor capacitance and update the Capacitance
register accordingly.
Initial Capacitance at Device Reset
The bq33100 estimates the initial capacitance of a at device reset, which is the case when the capacitors are first
attached to the application circuit. This gives a reasonably accurate Capacitance and RSOC value, however,
Super Capacitor capacitance learning is required in order to improve the accuracy of Capacitance and RSOC.
14
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Qualified Capacitance Learning
The bq33100 updates Capacitance with an amount based on the value learned during a qualified learning cycle.
Once updated, the bq33100 writes the new Capacitance value to data flash to Capacitance.
The bq33100 sets [CL] = 1 and clears [LPASS] in Operation Status when a qualified capacitance learning cycle
begins. The period of time that the learning takes is set by CL Time although the first learning cycle after a
device reset will not occur until after an elapsed time of Learning Frequency. When a qualified learn has
occurred [LPASS] in Operation Status is set.
During the learning process there are specific timeouts to protect from over charge or over discharge of the
super capacitor array. At the beginning of each phase of charge and discharge a timer is started. If the timer
exceeds Max Discharge Timeout during the discharging phase then Operation Status [LDTO] is set if the timer
exceeds Max Charge Timeout for the charging phase then Operation Status [LCTO] is set. the flags are cleared
upon the beginning of the next learning cycle.
During capacitance learning both capacitor voltage balancing operations and overvoltage detection are
suspended.
Health Determination
The bq33100 uses the following method to determine the relative health of the capacitor.
Health = (Capacitance / InitialCapacitance )
The bq33100 will determine a new ChargingVoltage at end of the learning cycle based on the newly learned
Capacitance. The following warnings will be set based on the changes in ChargingVoltage and the capacitors
ability to provide the minimum power needs.
ChargingVoltage = V Chg Nominal then SafetyStatus[HLOW], [HWARN] and [HFAIL] are cleared.
If ChargingVoltage is set to V Chg A or V Chg B then SafetyStatus[HLOW] is set.
If ChargingVoltage is set to V Chg Max then SafetyStatus [HWARN] is set.
If ChargingVoltage is set to V Chg Max and the bq33100 determines that the newly learned Capacitance cannot
provide the minimum power requirements then SafetyStatus [HFAIL] is set.
The minimum power requirements is determined by the Min Power, Required Time and Min Voltage data flash
values.
If the corresponding [HLOW], [HWARN] or [HFAIL] bits are set in FAULT when the SafetyStatus[HLOW] or
[HWARN] bit is set then the FAULT pin is set.
ESR Measurement
The bq33100 measures the voltage on the capacitor stack when the LLEN pin (pin 17) is high. The LLEN pin is
controlled by firmware to enable a circuit that presents a constant current load to the full capacitor stack. With the
known voltage and known current the ESR of the capacitor array can be determined. The final reported value of
ESR is also adjusted by the data flash value of ESR Offset
The final value of ESR can be read from the bq33100 via ESR which is in mΩ.
Monitor Operating Modes
Entry and exit of each mode is controlled by data flash parameters. In Discharge Mode, the [DSG] flag in
Operation Status is set. Discharge mode is entered when Current goes below (-)Dsg Current Threshold.
Discharge mode is exited when Current goes above Chg Current Threshold threshold for more than 1 second.
Charge mode is entered when Current goes above Chg Current Threshold. Charge mode is exited when
Current goes below Dsg Current Threshold for more than 1 second. .
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
15
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Capacitor Voltage Balancing
Capacitor voltage balancing in the bq33100 is accomplished by connecting an external parallel bypass load to
each capacitor, and enabling the bypass load depending on each individual capacitors voltage level. The bypass
load is typically formed by a P-ch MOSFET and a resistor connected in series across each capacitor. The filter
resistors that connect the capacitor tabs to VC1~VC4 pins of the bq33100 are required to be 1k ohms to support
this function on all capacitors other than the lowest. The lowest capacitor bypass is enabled via the VC5BAL pin.
Capacitor Voltage Balancing is only operational after the ManufacturerAccess Lifetime & Capacitor Balancing
Enable (0x21) command is sent to the bq33100.
Using this circuit, the bq33100 balances the capacitors during charge and after charge termination by
discharging those capacitors with voltage above the threshold set in CB Threshold and if the ΔV in capacitor
voltages exceeds the value programmed in CB Min. During capacitor voltage balancing, the bq33100 measures
the capacitor voltages periodically (during which time the voltage balancing circuit is turned off) and based on the
capacitor voltages, the bq33100 selects the appropriate capacitor to discharge. When ΔV of
CapacitorVoltage5...1 < CB Min then capacitor voltage balancing stops. Capacitor voltage balancing restarts
when ΔV of CapacitorVoltage5...1 ≥ CB Restart to avoid balancing start-stop oscillations.
Capacitor voltage balancing only occurs when:
•
•
•
Charging current is detected (Current > Chg Current Threshold OR
The [FC] flag in OperationStatus has been set AND
ΔCapacitorVoltage5...1 ≥ CB Restart
Capacitor voltage balancing stops when:
•
•
ΔCapacitorVoltage5...1 < CB Min
Discharging current detected (Current > Dsg Current Threshold)
This feature is disabled when in Stack mode, when Operation Cfg [STACK ] =1.
Charge Control
The bq33100 supports two main charge control architectures, discrete control and smart control. In a discrete
charge control implementation the CHGLVL0 and CHGLVL1 pins can be used to adjust the charging voltage of
an external supply (see reference schematic for example).
As the super capacitors age a higher charging voltage can be configured to offset the deteriorating super
capacitor ESR and Capacitance due to aging. With the discrete control method there are 4 levels of charging
voltages that can be chosen, V Chg Nominal, V Chg A, V Chg B and V Chg Max. The setting of the charging
voltage is determined by the value of the latest determined required Charging Voltage.
The CHGLVL0 and CHGLVL1 pin states are defined by the V Chg X parameters selected per the following table:
ChargingVoltage
CHGLVL1 (pin 12)
CHGLVL0 (pin11)
V Chg Nominal
0
0
V Chg A
0
1
V Chg B
1
0
V Chg Max
1
1
In a smart control architecture the bq33100 makes the appropriate maximum charging current and charging
voltage per the charging algorithm available via the ChargingCurrent and ChargingVoltage SMBus commands
respectively. This enables either an SMBus master or smart charger to manage the charging of the super
capacitor pack.
Primary Charge Termination
The bq33100 determines charge termination if:
•
•
16
The average charge current < Taper Current during 2 consecutive Current Taper Window time periods,
AND
Voltage + Taper Voltage ≥ ChargingVoltage
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
NOTE: To make sure that the charge terminates properly, it is recommend that Taper Current be set to a value
greater than the maximum charger voltage inaccuracy
The bq33100 sets the [FC] flag in Operation Status when a valid charge termination occurs and cleared when
RelativeStateOfCharge is less than 98%.
CHG Over Ride Control
During the normal operation of the bq33100 the CHG output of the bq33100 is typically controlled automatically
but can be over ridden through the CHGOR pin (pin 21). On a low -to-high transition the CHG output is released
turning off the external CHG FET and on a high-to-low transition the CHG output is pulled low after a
programmable delay CHG Enable Delay. If CHG Enable Delay is programmed to 0 the delay is a maximum of
250ms. If the CHG over ride function is not needed then the CHGOR pin should be connected to VSS.
Lifetime Data Gathering
Lifetime Maximum Temperature
During the operation lifetime of the bq33100 it gathers temperature data. During this time the bq33100 can be
enabled to record the Maximum value that the measured temperature reached. If the [LTE] flag is set in
OperationStatus, Lifetime Max Temp value is updated if one of the following conditions are met:
● internal measurement temperature - Lifetime Max Temp > 1 °C.
● internal measurement temperature > Lifetime Max Temp for a period > 60 seconds
● internal measurement temperature > Lifetime Max Temp AND any other lifetime value is updated.
Table 3. Lifetime Maximum Temperature
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
59
Lifetime Data
0
Lifetime Max
Temp
Integer
2
0
350
1400
Unit
0.1
degC
Lifetime Minimum Temperature
During the operation lifetime of the bq33100 it gathers temperature data. During this time the bq33100 can be
enabled to record the Minimum value that the measured temperature reached. If the [LTE] flag is set, Lifetime
Min Temp is updated if one of the following conditions are met:
● Lifetime Min Temp - internal measurement temperature > 1 °C.
● Lifetime Min Temp > internal measurement temperature for a period > 60 seconds
● Lifetime Min Temp > internal measurement temperature > AND any other lifetime value is updated.
Table 4. Lifetime Minimum Temperature
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
59
Lifetime Data
2
Lifetime Min
Temp
Integer
2
-600
50
1400
Unit
0.1
degC
Lifetime Maximum Capacitor Voltage
During the operation lifetime of the bq33100 it gathers voltage data and if in Single mode (Operation Cfg
[STACK ] =0). During this time the bq33100 can be enabled to record the Maximum value that the measured
voltage reached. If the [LTE] flag is set, Lifetime Max Capacitor Voltage is updated if one of the following
conditions are met:
● any internally measured capacitor voltage - Lifetime Max Capacitor Voltage > 25 mV
● any internally measured capacitor voltage > Lifetime Max Capacitor Voltage for a period > 60 seconds
● any internally measured capacitor voltage Lifetime Max Capacitor Voltage AND any other lifetime value is
updated.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
17
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Table 5. Lifetime Max Capacitor Voltage
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
59
Lifetime Data
4
Lifetime Max
Capacitor
Voltage
Integer
2
0
0
mV
32767
Safety Detection Features
The bq33100 supports a wide range of Super Capacitor and system safety detection and protection features that
are easily configured or enabled via the integrated data flash. These features are intended, through various
configuration options, to provide a level of safety from external influences causing damage to components with
the power path, eg: limiting the period of time the CHG FET is exposed to high current pulse charge conditions
Capacitor Overvoltage (OV)
The bq33100 can detect capacitor overvoltage condition and protect capacitors from damage.
When any CapacitorVoltage5...1 exceeds (ChargingVoltage / number of capacitors (see Operation Cfg
[CC2,1,0] ) + OV Threshold) the [OV] flag in SafetyAlert is set.
When any CapacitorVoltage5...1 exceeds (ChargingVoltage / number of capacitors (see Operation Cfg
[CC2,1,0] ) + OV Threshold) for a period greater than OV Time the [OV] flag in SafetyStatus is set.
When the bq33100 is configured for Pack Mode, when Operation Cfg [PACK ] =1, then a fault is detected when
Voltage exceeds (ChargingVoltage + OV Threshold) the [OV] flag in SafetyAlert is set.
When the bq33100 is configured for Pack Mode, when Operation Cfg [PACK ] =1, then a fault is detected when
Voltage exceeds (ChargingVoltage + OV Threshold) for a period greater than OV Time the [OV] flag in
SafetyStatus is set.
This function is disabled if OV Time is set to zero.
In an overvoltage condition charging is disabled and the CHG FET is turned off, ChargingCurrent and
ChargingVoltage are set to zero.
The bq33100 recovers from a capacitor overvoltage condition if all CapacitorVoltages5..1 are equal to or lower
than (ChargingVoltage / number of capacitors (see Operation Cfg [CC2,1,0] ) + OV Recovery. If the bq33100 is
configured for Pack Mode then the recover occurs when Voltage is equal to or lower than (ChargingVoltage + OV
Recovery.
On recovery the [OV] flag is reset, and ChargingCurrent and ChargingVoltage are set back to appropriate values
per the charging algorithm.
Note: When ChargingVoltage has been set to 0 due to a detected condition then the capacitor overvoltage
function is suspended.
Capacitor Voltage Imbalance (CIM)
The bq33100 starts capacitor voltage imbalance detection when Current is less than or equal to CIM Current
AND ALL CapacitorVoltage5..1 > Min CIM Check Voltage. This function only operates when the bq33100 is in
Normal mode, when Operation Cfg [PACK] =0.
When the difference between highest capacitor voltage and lowest capacitor voltage exceeds CIM Fail Voltage
the [CIM] flag in SafetyAlert is set.
When the difference between highest capacitor voltage and lowest capacitor voltage exceeds CIM Fail Voltage
for a period greater than CIM Time the [CIM] flag in SafetyStatus is set and ChargingCurrent and
ChargingVoltage are set to 0 and the CHG FET is turned off.
This function is disabled if CIM Time is set to zero.
The capacitor voltage imbalance detection is cleared when the difference between highest capacitor voltage and
lowest capacitor voltage is less than CIM Fail Voltage. When this is detected then the CHG FET is allowed to be
turned on, if other safety and configuration states permit, ChargingCurrent and ChargingVoltage are set to the
appropriate value per the charging algorithm, and the [CIM] flag in SafetyStatus is reset.
18
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Weak Capacitor (CLBAD)
When the capacitor array has been fully charged (indicated by OperationStatus [FC] being set) then it is
monitored for excessive leakage.
When Current exceeds CLBAD Current the [CLBAD] flag in SafetyAlert is set.
When Current exceeds CLBAD for a period greater than CLBAD Time the [CLBAD] flag in SafetyStatus is set.
This function is disabled if CLBAD Time is set to zero.
In a weak capacitor condition charging is disabled and the CHG FET is turned off, ChargingCurrent and
ChargingVoltage are set to zero.
The weak capacitor fault is cleared when Current falls equal to or below the CLBAD Recovery limit. When the
recovery condition is detected, then the CHG FET is allowed to be turned on, if other safety and configuration
states permit, ChargingCurrent and ChargingVoltage are set to the appropriate value per the charging algorithm,
and the [CLBAD] flag in SafetyStatus is reset.
Overtemperature (OT)
The bq33100 has overtemperature protection to prevent charging at excessive temperatures.
When Temperature exceeds OT the [OT] flag in SafetyAlert is set.
When Temperature exceeds OT for a period greater than OT Time the [OT] flag in SafetyStatus is set.
This function is disabled if OT Time is set to zero.
In an overtemperature condition charging is disabled and the CHG FET is turned off, ChargingCurrent and
ChargingVoltage are set to zero.
The overtemperature fault is cleared when Temperature falls equal to or below the OT Recovery limit. When the
recovery condition is detected, then the CHG FET is allowed to be turned on, if other safety and configuration
states permit, ChargingCurrent and ChargingVoltage are set to the appropriate value per the charging algorithm,
and the [OT] flag in SafetyStatus is reset.
Overcurrent During Charging (OC Chg)
The bq33100 has an independent level of recoverable overcurrent protection during charging.
When Current exceeds OC Chg the [OCC] flag in SafetyAlert is set.
When Current exceeds OC Chg for a period greater than OC Chg Time the [OCC] flag in SafetyStatus is set
and ChargingCurrent and ChargingVoltage are set to 0.
This function is disabled if OC Chg Time is set to zero.
The overcurrent fault is cleared when Current falls below OC Chg Recovery. When a charging-fault recovery
condition is detected, then the CHG FET is allowed to be turned on, if other safety and configuration states
permit, ChargingCurrent and ChargingVoltage are set to the appropriate value per the charging algorithm, and
the [OCC] flag in SafetyStatus is reset.
Overcurrent During Discharging (OC Dsg)
The bq33100 overcurrent is discharge detection executed by the integrated AFE is configured by the bq33100
data flash OC Dsg and OC Dsg Time registers.
When the integrated AFE detects a overcurrent in discharge condition the charge FET is turned off and the
[OCD] flag in SafetyStatus is set, the internal current recovery timer is reset and ChargingCurrent and
ChargingVoltage are set to 0.
The recovery is controlled by the bq33100 and requires that Current be ≤ OC Dsg Recovery threshold and that
the internal AFE current recovery timer ≥ Current Recovery Time.
When the recovery condition is detected, ChargingCurrent and ChargingVoltage are set to the appropriate value
per the charging algorithm, and the [OCD] flag inSafetyStatus is reset.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
19
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Short-Circuit During Charging (SC Chg)
The bq33100 short-circuit during charging protection is executed by the integrated AFE is configured by the
bq33100 data flash SC Chg Cfg register.
When the integrated AFE detects a short circuit fault the charge FET is turned off and the [SCC] flag in
SafetyStatus is set, the internal current recovery timer is reset and ChargingCurrent and ChargingVoltage are set
to 0.
The recovery is controlled by the bq33100 and requires that AverageCurrent be ≤ SC Recovery threshold and
that the internal AFE current recovery timer ≥ Current Recovery Time.
When the recovery condition is detected, ChargingCurrent and ChargingVoltage are set to the appropriate value
per the charging algorithm, and the [SCC] flag inSafetyStatus is reset.
Short-Circuit During Discharging (SC Dsg)
The bq33100 short-circuit during discharging detection is executed by the integrated AFE is configured by the
bq33100 data flash SC Dsg Cfg register.
When the integrated AFE detects a short circuit fault the charge FET is turned off and the [SCD] flag in
SafetyStatus is set, the internal current recovery timer is reset and ChargingCurrent and ChargingVoltage are set
to 0.
The recovery is controlled by the bq33100 and requires that Current be ≤ SC Recovery threshold and that the
internal AFE current recovery timer ≥ Current Recovery Time.
When the recovery condition is detected, ChargingCurrent and ChargingVoltage are set to the appropriate value
per the charging algorithm, and the [SCD] flag inSafetyStatus is reset.
AFE Watchdog (WDF)
The integrated AFE automatically turns off the CHG FET and sets the [WDF] flag in SafetyStatus if the integrated
AFE does not receive the appropriate frequency on the internal watchdog input (WDI) signal.
Integrated AFE Communication Fault (AFE_C)
The bq33100 periodically validates its read and write communications with the integrated AFE. If either a read or
write verify fails, an internal AFE_Fail_Counter is incremented. If the AFE_Fail_Counter reaches AFE Fail Limit,
the bq33100 sets the [AFE_C] flag in SafetyStatus. An AFE communication fault condition can also be declared
if, after a full reset, the initial gain and offset values read from the AFE cannot be verified. These values are A to
D readings of the integrated AFE VCx signal. The integrated AFE offset values are verified by reading the values
twice and confirming that the readings are within acceptable limits. The maximum number of read retries, if offset
and gain value verification fails and [AFE_C] fault is declared, is set in AFE Fail Limit
If the AFE Fail Limit is set to 0, this feature is disabled..
Data Flash Fault (DFF)
The bq33100 can detect if the data flash is not operating correctly. A permanent failure is reported when either:
(i) After a full reset the instruction flash checksum does not verify; (ii) if any data flash write does not verify; or (iii)
if any data flash erase does not verify
When a data flash fault is detected then the [DFF] flag in SafetyStatus is set.
FAULT Indication (FAULT Pin)
The bq33100 provides the status of the safety detection via SafetyStatus. To provide an extra indication of a fault
state ( SafetyStatus ≠ 0x00) the bq33100 will set the FAULT pin (pin 15) if the corresponding SafetyStatus bit is
set in Fault Cfg.
Operating Power Modes
The bq33100 has two operating power modes, Normal and Shutdown Mode.
20
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Normal Mode - During normal operation, the bq33100 takes Current, Voltage and Temperature measurements,
performs calculations, updates SBS data, and makes protection and status decisions at one-second intervals.
Between these periods of activity, the bq33100 is in a reduced power state.
Shutdown - The bq33100 enters Shutdown mode if the following conditions are met:
•
•
VVCCPACK ≤ Minimum Operating voltage
ManufacturerAccess: Shutdown command received AND Current = 0 AND Voltage < Shutdown Voltage
threshold.
Upon initial power up or a reset of the bq33100, application of a voltage > VSTARTUP must be applied to the
VCCPACK pin. The bq33100 will then power up and enter Normal Mode.
Security (Enables and Disables Features)
There are two levels of secured operation within the bq33100, Sealed and Unsealed. To switch between the
levels, different operations are needed with different codes.
1.Unsealed to Sealed — The use of the Seal command instructs the bq33100 to limit access to the SBS
functions and data flash space and sets the [SS] flag. In sealed mode, available standard SBS functions have
access per the Smart Battery Data Specification (SBS). Extended SBS Functions and data flash are not
accessible. Once in sealed mode, the part can never permanently return to Unsealed mode.
2. Sealed to Unsealed — Instructs the bq33100 to extend access to the SBS and data flash space and clears the
[SS] flag. In unsealed mode, all data, SBS, and DF have read/write access. Unsealing is a 2 step command
performed by writing the 1st word of the UnSealKey to ManufacturerAccess followed by the second word of the
UnSealKey to ManufacturerAccess. The unseal key can be read and changed via the extended SBS block
command UnSealKey when in Unsealed Mode. To return to the Sealed mode, either a hardware reset is needed,
or the ManufacturerAccess Seal command is needed.
Communications
The bq33100 uses SMBus v1.1 with optional packet error checking (PEC) per the SMBus specification.
bq33100 Slave Address
The bq33100 uses the address 0x16 on SMBus for communication.
SMBus On and Off State
The bq33100 detects an SMBus off state when SCL and SDA are logic-low for ≥ 2 seconds. Clearing this state
requires either SCL or SDA to transition high. Within 1 ms, the communication bus is available.
Packet Error Checking
The bq33100 can receive data with or without PEC.
In the write-word protocol, the bq33100 receives the PEC after the last byte of data from the host. If the host
does not support PEC, the last byte of data is followed by a stop condition. After receipt of the PEC, the bq33100
compares the value to its calculation. If the PEC is correct, the bq33100 responds with an ACKNOWLEDGE. If it
is not correct, the bq33100 responds with a NOT ACKNOWLEDGE. If the host supports PEC, the [HPE] bit in
Operation Cfg should be set to 1.
SBS COMMANDS
All SBS Values are updated in 1-second intervals. The extended SBS commands are only available when the
bq33100 device is in unsealed mode.
SBS Command Summary
Table 6. SBS COMMANDS
SBS Cmd
Mode
Name
Format
Size in
Bytes
Min
Value
Max
Value
Default Value
0x00
R/W
ManufacturerAccess
hex
2
0x0000
0xffff
—
Unit
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
21
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Table 6. SBS COMMANDS (continued)
SBS Cmd
Mode
Name
Format
Size in
Bytes
Min
Value
Max
Value
Default Value
Unit
0x08
R
Temperature
unsigned int
2
0
65535
—
0.1degK
0x09
R
Voltage
unsigned int
2
0
65535
—
mV
0x0a
R
Current
signed int
2
-32768
32767
—
mA
0x0b
R
ESR
unsigned int
2
0
65535
—
mΩ
0x0d
R
RelativeStateOfCharge
unsigned int
1
0
100
—
%
0x0e
R
Health
unsigned int
1
0
100
—
%
0x10
R
Capacitance
unsigned int
2
0
65535
—
F
0x14
R
ChargingCurrent
unsigned int
2
0
65534
—
mA
0x15
R
ChargingVoltage
unsigned int
2
0
65534
—
mV
0x3b
R
CapacitorVoltage5
unsigned int
2
0
65534
—
mV
0x3c
R
CapacitorVoltage4
unsigned int
2
0
65535
—
mV
0x3d
R
CapacitorVoltage3
unsigned int
2
0
65535
—
mV
0x3e
R
CapacitorVoltage2
unsigned int
2
0
65535
—
mV
0x3f
R
CapacitorVoltage1
unsigned int
2
0
65535
—
mV
Table 7. EXTENDED SBS COMMANDS
SBS Cmd
Mode
Name
Format
Size
in
Bytes
Min Value Max
Value
Default Value
0x50
R
SafetyAlert
Hex
2
0x0000
0xffff
—
0x51
R
SafetyStatus
Hex
2
0x0000
0xffff
—
0x54
R
OperationStatus
Hex
2
0x0000
0xf7f7
—
0x5a
R
SystemVoltage
unsigned int
2
0
65535
—
0x60
R/W
UnSealKey
Hex
4
0x000000
00
0xffffffff
—
0x70
R/W
ManufurerInfo
String
31+1
—
—
—
Unit
mV
SBS Command Details
The following provides detailed descriptions of the SBS Commands
ManufacturerAccess (0x00)
This read- or write-word function provides Super Capacitor data to system along with access to bq33100 controls
and security features.
Table 8. ManufacturerAccess
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
0x00
R/W
ManufacturerAccess
hex
2
0x0000
0xffff
-
Unit
Table 9. MAC Command Summary Table
SBS Cmd
Mode
0x0001
R
Device Type
0x0002
R
Firmware Version
Returns the firmware version.
0x0003
R
Hardware Version
Returns the hardware version
0x0004
R
DF Checksum
0x0020
W
Seal
22
Name
Description
Returns the IC part number.
Generates a checksum of the full Data Flash (DF) array
Enters Sealed mode with limited access to the extended SBS functions and data flash
space
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Table 9. MAC Command Summary Table (continued)
SBS Cmd
Mode
Name
Description
0 = Disables logging of lifetime data to non-volatile memory and disables capacitor
balancing
1 = Enables logging of lifetime data to non-volatile memory and enables capacitor
balancing
0x0021
R/W
Lifetime and Capacitor
Balancing Enable
0x0022
R
IF Checksum
0x0023
W
Learn
0x0024
W
Learn Value Reset
This write function instructs the bq33100 to reset the capacitance learned values
(Capacitance) to initial default values.
0x0025
W
Learn Initialization
This write function instructs the bq33100 to enter a capacitance learning
cycle(Capacitance Update) and update Initial values for Capacitance and ESR
0x0030
W
FAULT Activation
Drives the FAULT pin high
0x0031
W
FAULT Clear
0x0032
W
Charge Level Nominal
0x0033
W
Charge Level A
Drives the CHGLVL0,1 pins high, low
0x0034
W
Charge Level B
Drives the CHGLVL0,1 pins low, high
0x0035
W
Charge Level Max
Drives the CHGLVL0,1 pins high
0x0036
R
Read AD Current
Read A-to-D Converter Current Measurement
0x0037
W
Learn Load Activation
0x0038
W
Learn Load Clear
Sets the LLEN pin low
0x0040
W
Calibration Mode
Places bq33100 into calibration mode
0x0041
W
Reset
Unseal
Key
W
Unseal Device
Enables access to SBS and DF space
Extended
SBS
R/W
Extended SBS
Commands
Access to Extended SBS commands
Returns the value of the Instruction Flash (IF) checksum
This write function instructs the bq33100 to enter a capacitance learning
cycle(Capacitance Update).
Sets FAULT pin low
Drives the CHGLVL0,1 pins low
Drives the LLEN pin high (does not activate actual learning algorithm, see 0x0023)
bq33100 undergoes complete reset
Device Type (0x0001)
Returns the IC part number.
Table 10. Device Type
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
0x000
1
R
Device Type
Hex
2
-
-
-
Unit
Firmware Version (0x0002)
Returns the firmware version. The format is most-significant byte (MSB) = Decimal integer, and the
least-significant byte (LSB) = sub-decimal integer, e.g.: 0x0120 = version 01.20.
Table 11. Firmware Version
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
0x000
2
R
Firmware Version
Hex
2
-
-
-
Unit
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
23
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Hardware Version (0x0003)
Returns the hardware version stored in a single byte of reserved data flash. e.g.: 0x00a7 = Version A7.
Table 12. Hardware Version
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
0x00
R
Hardware Version
Hex
2
-
-
-
Unit
DF Checksum (0x0004)
This function is only available when the bq33100 is in unsealed mode, indicated by the [SS] OperationStatus
flag. A write to this command forces the bq33100 to generate a checksum of the full Data Flash (DF) array. The
generated checksum is then returned within 45 ms.
NOTE: If another SMBus command is received while the checksum is being generated, the DF Checksum is
generated but the response may time out.
Table 13. DF Checksum
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
0x000
4
R
DF Checksum
Hex
2
-
-
-
Unit
Seal Device (0x0020)
Instructs the bq33100 to limit access to the extended SBS functions and data flash space, sets the [SS] flag. This
command is only available when the bq33100 is in Unsealed mode. See "Security" chapter in this document for
detailed information.
Lifetime and Capacitor Balancing Enable (0x0021)
Enables/Disables the logging of Lifetime data to non-volatile memory and Capacitor balancing
FAULT Activation (0x0030)
This command drives the FAULT pin high. This command is only available when the bq33100 is in Unsealed
mode.
FAULT Clear (0x0031)
This command sets the FAULT pin back to low. This command is only available when the bq33100 is in
Unsealed mode.
CHGLVL0 Activation (0x0032)
This command drives the CHGLVL0 pin high. This command is only available when the bq33100 is in Unsealed
mode.
CHGLVL0 Clear (0x0033)
This command sets the CHGLVL0 pin back to low. This command is only available when the bq33100 is in
Unsealed mode.
CHGLVL1 Activation (0x0033)
This command drives the CHGLVL0 pin high. This command is only available when the bq33100 is in Unsealed
mode.
CHGLVL1 Clear (0x0034)
This command sets the CHGLVL0 pin back to low. This command is only available when the bq33100 is in
Unsealed mode.
24
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Learn Load Activation (0x0037)
This command drives the LLEN pin high. This command is only available when the bq33100 is in Unsealed
mode.
Learn Load Clear (0x0038)
This command sets the LLEN pin back to low. This command is only available when the bq33100 is in Unsealed
mode.
Calibration Mode (0x0040)
Places the bq33100 into calibration mode. This command is only available when the bq33100 is in Unsealed
mode
Reset (0x0041)
The bq33100 undergoes a full reset. The bq33100 holds the clock line down for a few milliseconds to complete
the reset. If ChargingVoltage < Voltage after a reset, then the pack is discharged using the capacitor voltage
balancing circuitry. This command is only available when the bq33100 is in Unsealed mode.
Unseal Device (UnsealKey)
Instructs the bq33100 to enable access to the SBS functions and data flash space and clear the [SS] flag. This 2
step command needs to be written to ManufacturerAccess in the following order: 1st word of the UnSealKey
followed by the 2nd word of the UnSealKey. If the command fails 4 seconds must pass before the command can
be reissued. This command is only available when the bq33100 is in Sealed mode. See "Security" chapter in this
document for detailed information.
Extended SBS Commands
Also available via ManufacturerAccess in sealed mode are some of the extended SBS commands. The result of
these commands need to be read from ManufacturerAccess after a write to ManufacturerAccess.
Temperature (0x08)
This read-word function returns an unsigned integer value of the temperature in units of 0.1°K, as measured by
the bq33100. It has a range of 0 to 6553.5°K. The source of the measured temperature is configured by the
[TEMP1] and [TEMP0] bits in the Operation Cfg register.
Table 14. Temperature
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
Unit
0x08
R
Temperature
Unsigned
Integer
2
0
65535
-
0.1°K
Voltage (0x09)
This read-word function returns an unsigned integer value of the sum of the individual Super Capacitor voltage
measurements in mV with a range of 0 to 20000 mV
Table 15. Voltage
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
Unit
0x09
R
Voltage
Unsigned
Integer
2
0
20000
-
mV
Current (0x0a)
This read-word function returns a signed integer value of the measured current being supplied (or accepted) by
the super capacitor pack in mA, with a range of –32,768 to 32,767. A positive value indicates charge current and
a negative value indicates discharge.
Any current value within the Deadband will be reported as 0 mA by the Current function.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
25
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Table 16. Current
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
Unit
0x0a
R
Current
Unsigned
Integer
2
-32768
32767
-
mA
ESR (0x0b)
This read-word function returns an unsigned integer value of the Super Capacitor array total ESR in mΩ with a
range of 0 to 65535mΩ
Table 17. ESR
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
Unit
0x0b
R
ESR
Unsigned
Integer
2
0
65535
-
mΩ
RelativeStateofCharge (0x0d)
This read-word function returns an unsigned integer value of the predicted remaining super capacitor
capacitance expressed as a percentage of Capacitance with a range of 0 to 100%, with fractions of % rounded
up.
If the [RSOCL] bit in Operation Cfg is set then RelativeStateofCharge is held at 99% until primary charge
termination occurs and only displays 100% upon entering primary charge termination.
If the [RSOCL] bit inOperation Cfg is cleared then RelativeStateofCharge is not held at 99% until primary
charge termination occurs. Fractions of % greater than 99% are rounded up to display 100%.
Table 18. RelativeStateofCharge
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
Unit
0x0d
R
RelativeStateofCh
arge
Unsigned
Integer
1
0
100
-
%
Health (0x0e)
This read-word function returns an unsigned integer value of the predicted health of the super capacitor pack
expressed as a percentage of Capacitance / InitialCapacitance with a range of 0 to 100%, with fractions of %
rounded up.
Table 19. Health
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
Unit
0x0e
R
Health
Unsigned
Integer
1
0
100
-
%
Capacitance (0x10)
This read- or write-word function returns an unsigned integer value, with a range of 0 to 65535, of the predicted
full charge capacitance in the super capacitor pack. This value is expressed in F.
Table 20. Capacitance
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
Unit
0x10
R/W
Capacitance
Unsigned
Integer
2
0
65534
-
F
26
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
ChargingCurrent (0x14)
This read-word function returns an unsigned integer value of the desired charging current, in mA, with a range of
0 to 65534.
Table 21. ChargingCurrent
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
Unit
0x14
R
ChargingCurrent
Unsigned
Integer
2
0
65534
-
mA
ChargingVoltage (0x15)
This read-word function returns an unsigned integer value of the desired charging voltage, in mV, where the
range is 0 to 65534.
Table 22. ChargingVoltage
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
Unit
0x15
R
ChargingVoltage
Unsigned
Integer
2
0
65534
-
mV
CapacitorVoltage5..1 (0x3b..0x3f)
These read-word functions return an unsigned value of the calculated individual capacitor voltages, in mV, with a
range of 0 to 65535. CapacitorVoltage1 corresponds to the bottom most series capacitor element, while
CapacitorVoltage5 corresponds to the top most series capacitor element.
Table 23. CapacitorVoltage5..1
SBS
Cmd
Mode
Name
0x3b
CapacitorVoltage
5
0x3c
CapacitorVoltage
4
0x3d
R
CapacitorVoltage
3
0x3e
CapacitorVoltage
2
0x3f
CapacitorVoltage
1
Format
Size in
Bytes
Min Value
Max Value
Default Value
Unit
Unsigned
Integer
2
0
65535
-
mV
Extended SBS Commands
Also available via ManufacturerAccess in sealed mode are some of the extended SBS commands. The
commands available are listed below. The result of these commands need to be read from ManufacturerAccess
after a write to ManufacturerAccess.
FETControl(0x46)
This write/read-word function allows direct control of the CHG FET for test purposes. The bq33100 overrides this
command unless in normal mode.
Table 24. FETControl
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
0x46
R
FETControl
hex
2
0x0000
0xffff
-
Unit
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
27
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
High
Byte
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
Low
Byte
RSVD
RSVD
RSVD
RSVD
RSVD
CHG
RSVD
RSVD
LEGEND: All Values Read-Only
CHG — Charge (CHG) FET Control
0 = CHG FET is turned OFF.
1 = CHG FET is turned ON.
SafetyAlert (0x50)
This read-word function returns indications of pending safety issues, such as running safety timers, or fail
counters that are nonzero but have not reached the required time or value to trigger a SafetyStatus failure.
These flags do not cause the FAULT pin to be set.
Table 25. SafetyAlert
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
0x50
R
SafetyAlert
hex
2
0x0000
0xffff
-
Unit
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
High
Byte
CLBAD
RSVD
RSVD
RSVD
RSVD
OTC
CIM
OV
Low
Byte
RSVD
RSVD
RSVD
RSVD
OCC
OCD
SCC
SCD
LEGEND: All Values Read-Only
CLBAD 1 = Excessive capacitor leakage alert
OTC 1 = Charge overtemperature alert
CIM
1 = Capacitor voltage Imbalance permanent failure alert
OV
1 = Capacitor overvoltage alert
OCC 1= Overcurrent during charge alert
OCD 1= AFE overcurrent during discharge alert
SCC 1= AFE short circuit during charge alert
SCD 1= AFE short circuit during discharge alert
SafetyStatus (0x51)
This read-word function returns the status of the safety features. These flags do not cause the FAULT pin to be
set unless the corresponding bit in FAULT Cfg is set.
Table 26. SafetyStatus
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
0x51
R
SafetyStatus
hex
2
0x0000
0xffff
-
28
Unit
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
High
Byte
CLBAD
HWARN
HLOW
RSVD
RSVD
OTC
CIM
OV
Low
Byte
DFF
RSVD
AFE_C
WDF
OCC
OCD
SCC
SCD
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
LEGEND: All Values Read-Only
CLBAD 1 = Excessive capacitor leakage fault
HWARN 1 = Health low warning
HLOW 1 = Health low indication
OTC 1 = Charge overtemperature fault
CIM
1 = Capacitor voltage Imbalance fault
OV
1 = Capacitor overvoltage fault
DFF
1 = Data Flash Fault permanent failure fault
AFE_C 1 = Permanent AFE Communications failure fault
WDF 1 = AFE Watchdog fault
OCC 1= Overcurrent during charge fault
OCD 1= AFE overcurrent during discharge fault
SCC 1= AFE short circuit during charge fault
SCD 1= AFE short circuit during discharge fault
OperationStatus (0x54)
This read-word function returns the current operation status
Table 27. OperationStatus
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
0x54
R
OperationStatus
hex
2
0x0000
0xf7f7
-
Unit
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
High
Byte
RSVD
DSG
SS
FC
LTE
RSVD
RSVD
CB
Low
Byte
LDTO
LCTO
LPASS
CL
RSVD
CFET
RSVD
RSVD
DSG Discharging
0 = bq33100 is in charging mode
1 = bq33100 is in discharging mode, relaxation mode, or valid charge termination has
occurred
SS
1 = Sealed security mode
FC
1 = Fully Charged
LTE
1 = Lifetime data and CHG FET operation enabled
CB
1 = Capacitor voltage balancing in progress
CL
1 = Capacitance learning in progress
LPASS 1 = Learning complete and successful
LCTO 1 = Learning charging phase time out
LDTO 1 = Learning discharging phase time out
SystemVoltage (0x5a)
This read-word function returns an unsigned integer value of the voltage at VCC (pin 24) in mV with a range of 0
to 20000 mV
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
29
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Table 28. SystemVoltage
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
Unit
0x5a
R
SystemVoltage
Unsigned
Integer
2
0
20000
-
mV
UnSealKey(0x60)
This read- or write-block command allows the user to change the Unseal key for the Sealed-to-Unsealed
security-state transition. This function is only available when the bq33100 is in the Unsealed mode, indicated by
a cleared [SS] flag.
The order of the bytes, when entered in ManufacturerAccess, is the reverse of what is written to or read from the
part. For example, if the 1st and 2nd word of the UnSealKey block read returns 0x1234 and 0x5678, then in
ManufacturerAccess, 0x3412 and 0x7856 should be entered to unseal the part.
Table 29. UnSealKey
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
0x60
R/W
UnSealKey
Hex
4
0x00000000
0xffffffff
-
Unit
ManufacturerInfo(0x70)
This read/write block function returns the data stored in Manuf. Info where byte 0 is the MSB with a maximum
length of 31 data + 1 length byte. When the bq33100 is in Unsealed mode, this block is read/write. When the
bq33100 is in Sealed mode, this block is read only.
Table 30. ManufacturerInfo
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default Value
0x70
R/W
ManufacturerInfo
String
31+1
-
-
-
Unit
DATA FLASH
CAUTION
Care should be taken when mass programming the data flash space using previous
versions of data flash memory map files (such as *.gg files) to make sure that all public
locations are updated correctly.
Data Flash can only be updated if Voltage ≥ Flash Update OK Voltage. Data flash reads and writes are verified
according to the method detailed in the "Data Flash Fault Detection" section of this data sheet.
Accessing Data Flash
In different security modes, the data flash access conditions change. See "Security" and "ManufacturerAccess"
sections for further details.
Data Flash Interface
The bq33100 data flash is organized into subclasses where each data flash variable is assigned an offset within
its numbered subclass. For example: the OT Time location is defined as:
•
•
•
Class = Safety
SubClass = Temperature = 2
Offset = 2
Note: Data Flash commands are NACKed if the bq33100 is in sealed mode ([SS] flag is set).
Each subclass can be addressed individually by using the DataFlashSubClassID (0x77) command and the data
within each subclass is accessed by using the DataFlashSubClassPage1..8 (0x78...0x7f) commands. Reading
30
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
and Writing subclass data are block operations which are each 32 Bytes long. Data can be written in shorter
block sizes, however. The final block in one subclass can be shorter than 32 bytes so care must be taken not to
write over the subclass boundary. None of the values written are bounded by the bq33100 and the values are not
rejected by the bq33100. Writing an incorrect value may result in hardware failure due to firmware program
interpretation of the invalid data. The data written is persistent, so a Power On Reset does resolve the fault.
Data Flash Summary
The following notation is used in the following table with regards to the Data Type column:
The Alpha Character
• H = Hexadecimal value
• I = Integer value
• S = String
• U = Unsigned Integer value
The Numeric Value following the Alpha Character is the length of the data in bytes, eg: OT Time Data Type =
U1 = Unsigned Integer of 1 byte in length
Table 31. DATA FLASH VALUES
Class
Subclass
ID
Subclass
Offset
Name
Data
Type
Min Value
Max
Value
Default Value Units
(EVSW
Units)*
Safety
0
Voltage
0
OV Threshold
I2
0
1000
100
mV
Safety
0
Voltage
2
OV Recovery
I2
-500
1000
0
mV
Safety
0
Voltage
4
OV Time
U1
0
255
2
s
Safety
0
Voltage
5
CIM Voltage
I2
0
5000
550
mV
Safety
0
Voltage
7
CIM Time
U1
0
240
10
s
Safety
0
Voltage
8
CIM Recovery
I2
0
5000
500
mV
Safety
0
Voltage
10
Min CIM Check Voltage
U2
0
65535
1000
mV
Safety
1
Current
0
OC Chg
I2
0
5000
1000
mA
Safety
1
Current
2
OC Chg Time
U1
0
240
5
s
Safety
1
Current
3
OC Chg Recovery
I2
-1000
5000
900
mA
Safety
1
Current
5
CLBAD Current
I2
0
30000
15
mA
Safety
1
Current
7
CLBAD Time
U1
0
240
60
s
Safety
1
Current
8
CLBad Recovery
I2
0
1000
10
mA
Safety
1
Current
10
Current Recovery Time
U1
0
240
5
s
Safety
1
Current
11
OC Dsg
H1
0
f
F
hex
Safety
1
Current
12
OC Dsg Time
H1
0
f
F
hex
Safety
1
Current
13
OC Dsg Recovery Time
I2
0
1000
5
mA
Safety
1
Current
15
SC Chg Cfg
H1
0
f7
F4
hex
Safety
1
Current
16
SC Dsg Cfg
H1
0
f7
f7
hex
Safety
1
Current
17
SC Recovery
I2
0
200
1
mA
Safety
2
Temperature
0
OT Chg
I2
0
1200
680
0.1 degC
(degC)
Safety
2
Temperature
2
OT Chg Time
U1
0
240
2
s
Safety
2
Temperature
3
OT Chg Recovery
I2
0
1200
630
0.1 degC
(degC)
Safety
3
AFE Verification
1
AFE Fail Limit
U1
0
255
100
num
Safety
3
AFE Verification
3
AFE Init Retry Limit
U1
0
255
6
num
Safety
3
AFE Verification
4
AFE Init Limit
U1
0
255
20
cnt
Charge
Control
34
Charge Cfg
0
Chg Voltage
I2
0
32767
8400
mV
Charge
Control
34
Charge Cfg
2
Chg Current
I2
0
20000
500
mA
Charge
Control
34
Charge Cfg
4
Chg Enable Delay
U2
0
65000
0
ms
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
31
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Table 31. DATA FLASH VALUES (continued)
Class
Subclass
ID
Subclass
Offset
Name
Data
Type
Min Value
Max
Value
Default Value Units
(EVSW
Units)*
Charge
Control
35
Full Charge Cfg
0
Taper Current
I2
0
1000
3
mA
Charge
Control
35
Full Charge Cfg
2
Taper Voltage
I2
0
1000
100
mV
Charge
Control
35
Full Charge Cfg
4
Current Taper Window
U1
0
240
2
s
Charge
Control
35
Full Charge Cfg
5
FC Set %
I1
-1
100
-1
%
Charge
Control
35
Full Charge Cfg
6
FC Clear %
I1
-1
100
98
%
Charge
Control
36
Capacitor Voltage
Balancing Cfg
0
CB Threshold
I2
0
5000
1500
mV
Charge
Control
36
Capacitor Voltage
Balancing Cfg
2
CB Min
U1
0
255
5
mV
Charge
Control
36
Capacitor Voltage
Balancing Cfg
3
CB Restart
U1
0
255
10
mV
System Data
48
Data
0
Design Voltage
I2
0
25000
10500
mV
System Data
48
Data
2
Manuf Date
U2
0
65535
0
Day +
Mo*32 + (Yr
-1980)*256
(date)
System Data
48
Data
4
Ser. Num.
H2
0
0xffff
1
hex
System Data
48
Data
6
Design Capacitance
I2
0
65535
250
F
System Data
48
Data
8
Init 1st Capacitance
I2
0
65535
250
F
System Data
48
Data
10
Capacitance
I2
0
65535
250
F
System Data
48
Data
12
Design ESR
I2
0
65535
320
mΩ
System Data
48
Data
14
Initial ESR
I2
0
65535
320
mΩ
System Data
48
Data
16
ESR
I2
0
65535
320
mΩ
System Data
48
Data
18
Manuf Name
S12
x
x
Texas inst.
-
System Data
48
Data
30
Device Name
S8
x
x
bq33100
-
System Data
48
Data
38
Init safety Status
H2
0
0xffff
0
hex
System Data
56
Manufacturer Data
0
Pack Lot Code
H2
0
0xffff
0
-
System Data
56
Manufacturer Data
2
PCB Lot Code
H2
0
0xffff
0
-
System Data
56
Manufacturer Data
4
Firmware Version
H2
0
0xffff
0
-
System Data
56
Manufacturer Data
6
Hardware Version
H2
0
0xffff
0
-
System Data
58
Manufacturer Info
0
Manu. Info
S32
x
x
0123456789A
BCDEF01234
56789ABCDE
-
System Data
59
Lifetime Data
0
Lifetime Max Temp
I2
0
1400
0
0.1 degC
(degC)
System Data
59
Lifetime Data
2
Lifetime Min Temp
I2
-600
1400
500
0.1 degC
(degC)
System Data
59
Lifetime Data
4
Lifetime Max Capacitor Vol
I2
0
32767
0
mV
Configuration
64
Registers
0
Operation Cfg
H2
0
0xFFFF
0x0408
flg
Configuration
64
Registers
4
FET Action
H2
0
0xFFFF
0
flg
Configuration
64
Registers
8
Fault
H2
0
0xFFFF
0
flg
Configuration
65
AFE
1
AFE State_CTL
H1
0
ff
0
flg
Configuration
67
Power
0
Flash Update OK Voltage
I2
0
20000
4000
mV
Configuration
67
Power
2
Shutdown Voltage
I2
0
5500
4000
mV
Monitoring
86
System
Requirement
0
Min Power
I2
0
16800
10
10mW
Monitoring
86
System
Requirement
2
Required Time
I2
0
32767
60
s
Monitoring
86
System
Requirement
4
Min Voltage
I2
0
10000
4000
mV
32
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Table 31. DATA FLASH VALUES (continued)
Class
Subclass
ID
Monitoring
Subclass
Offset
System
Requirement
Name
Data
Type
Min Value
Max
Value
Default Value Units
(EVSW
Units)*
Q Low Warning %
U1
0
100
100
%
Monitoring
87
Charging Voltage
0
V Chg Nominal
I2
0
25000
10400
mV
Monitoring
87
Charging Voltage
2
V Chg A
I2
0
25000
11125
mV
Monitoring
87
Charging Voltage
4
V Chg B
I2
0
25000
11875
mV
Monitoring
87
Charging Voltage
6
V Chg Max
I2
0
25000
12500
mV
Monitoring
87
Charging Voltage
8
V Learn Max
I2
0
25000
12500
mV
Monitoring
88
Learning
Configuration
0
Learning Frequency
U1
0
255
2
week
Monitoring
88
Learning
Configuration
1
Measurement Margin %
U1
0
100
10
%
Monitoring
88
Learning
Configuration
2
Max Charge Timeout
I2
0
32767
300
s
Monitoring
88
Learning
Configuration
4
Max Discharge Timeout
I2
0
32767
10
s
Monitoring
88
Learning
Configuration
6
Learn Delta Voltage
I2
0
2000
500
mV
Monitoring
88
Learning
Configuration
8
Cap Start Time
U2
0
65535
320
ms
Monitoring
81
Data
0
Dsg Current Threshold
I2
0
2000
10
mA
Monitoring
81
Data
2
Chg Current Threshold
I2
0
2000
0
mA
Calibration
104
Data
0
CC Offset
F4
1.00E-01
4.00E+0
0
0.47095
mΩ
Calibration
104
Data
4
CC Delta
F4
2.98E+04
1.19E+0
6
140466.3
mΩ
Calibration
104
Data
8
Cap 1 K-factor
I2
0
32767
20500
-
Calibration
104
Data
10
Cap 2 K-factor
I2
0
32767
20500
-
Calibration
104
Data
12
Cap 3 K-factor
I2
0
32767
20500
-
Calibration
104
Data
14
Cap 4 K-factor
I2
0
32767
20500
-
Calibration
104
Data
16
Cap 5 K-factor
I2
0
32767
20500
-
Calibration
104
Data
18
K-factor override flag
H2
0
0xFFFF
0
num
Calibration
104
Data
20
System Voltage K-factor
I2
0
32767
24500
-
Calibration
104
Data
22
Stack Voltage K-factor
I2
0
32767
24500
-
Calibration
104
Data
24
CC Offset
I2
-32768
32767
-7744
mV
Calibration
104
Data
26
Board Offset
I2
-32768
32767
0
µV
Calibration
104
Data
28
Int Temp Offset
I1
-128
127
0
0.1 °C
Calibration
104
Data
29
Ext Temp Offset
I1
-128
127
0
0.1 °C
Calibration
104
Data
31
ESR Offset
I1
-128
127
0
mΩ
Calibration
105
Config
0
CC Current
I2
0
32767
3000
mA
Calibration
105
Config
2
Voltage Signal
I2
0
32767
12600
mV
Calibration
105
Config
4
Temp Signal
I2
0
32767
298
°K
Calibration
105
Config
6
CC Offset Time
U2
0
65535
250
00DC
A
8
Config
105
Calibration
U2
ms
32
65535
OFFset
Time
Calibration
105
Config
10
Current Gain Time
U2
0
65535
250
ms
Calibration
105
Config
12
Voltage Time
U2
0
65535
1888
ms
Calibration
105
Config
14
Temperature Time
U2
0
65535
32
ms
Calibration
105
Config
17
Cal Mode Timeout
U2
0
65535
38400
s
Calibration
106
Temp Model
0
Ext Coef a1
I2
-32768
32767
-11130
-
Calibration
106
Temp Model
2
Ext Coef a2
I2
-32768
32767
19142
-
Calibration
106
Temp Model
4
Ext Coef a3
I2
-32768
32767
-19262
-
Calibration
106
Temp Model
6
Ext Coef a4
I2
-32768
32767
28203
-
Calibration
106
Temp Model
8
Ext Coef a5
I2
-32768
32767
892
-
Calibration
106
Temp Model
10
Ext Coef b1
I2
-32768
32767
328
-
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
33
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Table 31. DATA FLASH VALUES (continued)
Class
Subclass
ID
Subclass
Offset
Name
Data
Type
Min Value
Max
Value
Default Value Units
(EVSW
Units)*
Calibration
106
Temp Model
12
Ext Coef b2
I2
-32768
32767
-605
-
Calibration
106
Temp Model
14
Ext Coef b3
I2
-32768
32767
-2443
-
Calibration
106
Current
16
Ext Coef b4
I2
-32768
32767
4696
-
Calibration
106
Current
18
Ext rc0
I2
-32768
32767
11703
-
Calibration
106
Current
20
Ext adc0
I2
-32768
32767
11338
-
Calibration
106
Temp Model
22
Rpad
I2
-32768
32767
87
Ω
Calibration
106
Temp Model
24
Rint
I2
-32768
32767
17740
Ω
Calibration
106
Temp Model
26
Int Coef 1
I2
-32768
32767
0
-
Calibration
106
Temp Model
28
Int Coef 2
I2
-32768
32767
0
-
Calibration
106
Temp Model
30
Int Coef 3
I2
-32768
32767
-12263
-
Calibration
106
Temp Model
32
Int Coef 4
I2
-32768
32767
6106
-
Calibration
106
Temp Model
34
Int Min AD
I2
-32768
32767
0
cnt
Calibration
106
Temp Model
36
Int Max Temp
I2
-32768
32767
6106
0.1 degk
(degk)
Calibration
107
Current
0
Filter
U1
0
255
239
num
Calibration
107
Current
1
Dead Band
U1
0
255
5
mA
Calibration
107
Current
2
CC Deadband
U1
0
255
10
294 nV
Specific Data Flash Programming Details
In this section the data flash values that are not detailed elsewhere in this data sheet are shown in detail and
others are summarized for easy reference.
OC Dsg
The OC Dsg is programmed into the OCDV register of the integrated AFE device. The OC Dsg sets the
overcurrent in discharging voltage threshold. Changes to this data flash value requires a firmware full reset or a
power reset of the bq33100 to take effect.
Table 32. OC Dsg
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
1
Current
16
OC Dsg
Hex
1
0x00
0x0F
-
0x0F
Table 33. OCDV Register
AFE OCDV
Register
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit1
bit 0
—
—
—
—
OCDV3
OCDV2
OCDV1
OCDV0
0000 is the bq33100 power on reset default.
OCDV3, OCDV2, OCDV1, OCDV0 — Sets the overcurrent voltage threshold in discharging of the integrated
AFE.
0x0 - 0xf = sets the short circuit in discharging delay between 0ms - 915ms in 61ms steps.
[RSNS] = 0, 0x0 - 0xf sets the voltage threshold between 50mV and 200mV in 10mV steps.
[RSNS] = 1, 0x0 - 0xf sets the voltage threshold between 20mV and 100mV in 5mV steps.
OCDV (b7...b4) — Not used.
34
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Table 34. OCDV (b2-b0) Configuration Bits with Corresponding Voltage Threshold When
STATE_CTL[RSNS] = 0
Setting
Threshold
Setting
Threshold
0x00
0.050 V
0x08
0.130 V
0x01
0.060 V
0x09
0.140 V
0x02
0.070 V
0x0a
0.150 V
0x03
0.080 V
0x0b
0.160 V
0x04
0.090 V
0x0c
0.170 V
0x05
0.100 V
0x0d
0.180 V
0x06
0.110 V
0x0e
0.190 V
0x07
0.120 V
0x0f
0.200 V
Table 35. OCDV (b2-b0) Configuration Bits with Corresponding Voltage Threshold When
STATE_CTL[RSNS] = 1
Setting
Threshold
Setting
Threshold
0x00
0.025 V
0x08
0.065 V
0x01
0.050 V
0x09
0.070V
0x02
0.035 V
0x0a
0.075 V
0x03
0.040 V
0x0b
0.080 V
0x04
0.045 V
0x0c
0.085 V
0x05
0.050 V
0x0d
0.090 V
0x06
0.055 V
0x0e
0.095V
0x07
0.060 V
0x0f
0.100 V
OC Dsg Time
The OC Dsg Time is programmed into the OCDD register of the integtrated AFE device. The OC Dsg Time sets
the overcurrent in discharging delay. Changes to this data flash value requires a firmware full reset or a power
reset of the bq33100 to take effect.
Table 36. OC Dsg Time
Subclass
ID
Subclass
Name
Offset
Name
1
Current
17
OC Dsg Time Hex
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
1
0x00
0x0F
-
0x0F
Table 37. OCDD Register
AFE OCDD
Register
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit1
bit 0
—
—
—
—
OCDD3
OCDD2
OCDD1
OCDD0
0000 is the bq33100 power on reset default.
OCDD3, OCDD2, OCDD1, OCDD0 — Sets the overcurrent in discharging delay of the integrated AFE.
0x0 - 0xf = sets the overvoltage trip delay between 1ms - 31ms in 2ms steps
OCDD (b7...b4) — Not used.
Table 38. OCDD (b7-b4) Configuration Bits with Corresponding Delay Time
Setting
Delay
Setting
Delay
Setting
Delay
Setting
Delay
0x00
1 ms
0x04
9 ms
0x08
17 ms
0x0c
25 ms
0x01
3 ms
0x05
11 ms
0x09
19 ms
0x0d
27 ms
0x02
5 ms
0x06
13 ms
0x0a
21 ms
0x0e
29 ms
0x03
7 ms
0x07
15 ms
0x0b
23 ms
0x0f
31 ms
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
35
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
SC Dsg Cfg
The SC Dsg Cfg is programmed into the SCD register of the integtrated AFE device. The SC Dsg Cfg sets the
short circuit in discharging voltage threshold and the short circuit in discharging delay. Changes to this data flash
value requires a firmware full reset or a power reset of the bq33100 to take effect.
Table 39. SC Dsg Cfg
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
1
Current
21
SC Dsg Cfg
Hex
1
0x00
0x0F
-
0x0F
Table 40. SCD Register
AFE SCD
Register
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit1
bit 0
SCDD3
SCDD2
SCDD1
SCDD0
-
SCDV2
SCDV1
SCDV0
0000 is the bq33100 power on reset default.
SCDD3, SCDD2, SCDD1, SCDD0 — Sets the short circuit delay in discharging of the integrated AFE.
0x0 - 0xf = sets the short circuit in discharging delay between 0ms - 915ms in 61ms steps.
If STATE_CTL[SCDDx2] is set, the delay time is double of that programmed in this register.
SCDV2, SCDV1, SCDV0 — Sets the short circuit voltage threshold in discharging of the integrated AFE
[RSNS] = 0, 0x0 - 0x7 sets the short circuit voltage threshold between 100mV and 450mV in 50mV steps
[RSNS] = 1, 0x0 - 0x7 sets the short circuit voltage threshold between 50mV and 475mV in 25mV steps
SCD (b3)— Not used.
Table 41. SCDV (b2-b0) Configuration Bits with Corresponding Voltage Threshold When
STATE_CTL[RSNS] = 0
Setting
Threshold
Setting
Threshold
0x00
0.100 V
0x04
0.300 V
0x01
0.150 V
0x05
0.350 V
0x02
0.200 V
0x06
0.400 V
0x03
0.250 V
0x07
0.450 V
Table 42. SCDV (b2-b0) Configuration Bits with Corresponding Voltage Threshold When
STATE_CTL[RSNS] = 1
Setting
Threshold
Setting
Threshold
0x00
0.050 V
0x04
0.150 V
0x01
0.075 V
0x05
0.175 V
0x02
0.100 V
0x06
0.200 V
0x03
0.125 V
0x07
0.225 V
Table 43. SCDD (b7-b4) Configuration Bits with Corresponding Delay Time
Setting
36
Delay
Setting
Delay
Setting
Delay
Setting
Delay
0x00
0 us
0x04
244 us
0x08
0x01
61 us
0x05
305 us
0x09
488 us
0x0c
732 us
549 us
0x0d
0x02
112 us
0x06
366 us
793 us
0x0a
610 us
0x0e
854 us
0x03
183 us
0x07
427 us
0x0b
671 us
0x0f
915 us
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
SC Chg Cfg
The SC Chg Cfg is programmed into the SCC register of the integtrated AFE device. The SC Chg Cfg sets the
short circuit in charging voltage threshold and the short circuit in charging delay. Changes to this data flash value
requires a firmware full reset or a power reset of the bq33100 to take effect.
Table 44. SC Chg Cfg
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
1
Current
20
SC Chg Cfg
Hex
1
0x00
0xF7
-
0xF7
Table 45. SCC Register
AFE SCC
Register
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit1
bit 0
SCCD3
SCCD2
SCCD1
SCCD0
-
SCCV2
SCCV1
SCCV0
0000 is the bq33100 power on reset default.
SCCD3, SCCD2, SCCD1, SCCD0 — Sets the short circuit delay in charging of the integrated AFE.
0x0 - 0xf = sets the short circuit in charging delay between 0ms - 915ms in 61ms steps.
If STATE_CTL[SCDDx2] is set, the delay time is double of that programmed in this register.
SCCV2, SCCV1, SCCV0 — Sets the short circuit voltage threshold in charging of the integrated AFE
[RSNS] = 0, 0x0 - 0x7 sets the short circuit voltage threshold between 100mV and 450mV in 50mV steps
[RSNS] = 1, 0x0 - 0x7 sets the short circuit voltage threshold between 50mV and 475mV in 25mV steps
SCC (b3) — Not used.
Table 46. SCCV (b2-b0) Configuration Bits with Corresponding Voltage Threshold When
STATE_CTL[RSNS] = 0
Setting
Threshold
Setting
Threshold
0x00
–0.100 V
0x04
–0.300 V
0x01
–0.150 V
0x05
n/a
0x02
–0.200 V
0x06
n/a
0x03
–0.250 V
0x07
n/a
Table 47. SCCV (b2-b0) Configuration Bits with Corresponding Voltage Threshold When
STATE_CTL[RSNS] = 1
Setting
Threshold
Setting
Threshold
0x00
–0.050 V
0x04
–0.150 V
0x01
–0.075 V
0x05
–0.175 V
0x02
–0.100 V
0x06
–0.200 V
0x03
–0.125 V
0x07
–0.225 V
Table 48. SCCD (b7-b4) Configuration Bits with Corresponding Delay Time
Setting
Delay
Setting
Delay
Setting
Delay
Setting
Delay
0x00
0 us
0x04
244 us
0x08
0x01
61 us
0x05
305 us
0x09
488 us
0x0c
732 us
549 us
0x0d
0x02
112 us
0x06
366 us
793 us
0x0a
610 us
0x0e
854 us
0x03
183 us
0x07
427 us
0x0b
671 us
0x0f
915 us
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
37
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Initial Full Charge Capacitance
The value of Initial Full Charge Capacitance is used in the health and other calculations.
Table 49. Initial Full Charge Capacitance
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
48
Data
22
Initial Full
Charge
Capacitance
Integer
2
0
250
F
65535
Full Charge Capacitance
This value is used as the Full Charge Capacitance at device reset. This value is updated by the gauging
algorithm when a qualified learning cycle has completed.
Table 50. Full Charge Capacitance
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
48
Data
26
Full Charge
Capacitance
Integer
2
0
250
F
65535
Firmware Version
The ManufacturerAccess function reports Firmware Version as part of its return value.
Table 51. Firmware Version
Subclass
ID
Subclass
Name
56
Manufacturer
Data
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
4
Firmware
Version
Hex
2
0x0000
0x00000
-
0xffff
Hardware Revision
The ManufacturerAccess function reports Hardware Version as part of its return value.
Table 52. Hardware Revision
Subclass
ID
Subclass
Name
56
Manufacturer
Data
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
6
Hardware
Revision
Hex
2
0x0000
0x0000
-
0xffff
Manuf. Info
The ManufacturerInfo function returns the string stored in Manuf. Info. The maximum text length is 31
characters.
Table 53. Manuf. Info
Subclass
ID
Subclass
Name
58
Manufacturer
Info
38
Offset
Name
Format
Size in
Bytes
Min Value Max Value
0
Manuf. Info
String
32
-
Submit Documentation Feedback
-
Default
Value
Unit
012345678
9ABCDEF0
123456789
ABCDE
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Operation Cfg
This register enables, disables or configures various features of the bq33100.
Table 54. Operation Cfg
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
64
Registers
0
Operation
Cfg
Hex
2
0x0000
0x04a8
0xffff
Unit
Table 55. Operation Cfg Register
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
High Byte
RSVD
RSVD
RSVD
RSVD
RSVD
CC2
CC1
bit 0
CC0
Low Byte
RSVD
LT_EN
RSVD
TEMP1
TEMP0
RSVD
RSVD
STACK
LEGEND: RSVD = Reserved and must be programmed to 0 unless otherwise specified
CC2, CC1, CC0 —These bits configure the bq33100 for the number of series capacitors in the Super
Capacitor stack.
0,0,0 = Reserved
0,0,1 = 2 capacitors
0,1,0 = 3 capacitors (default)
0,1,1 = 4 capacitors
1,0,0 = 5 capacitors
LT_EN — Lifetime Data logging bit; this bit enables or disables Lifetime Data logging from occurring; This bit
can be directly set by the Lifetime Enable command.
0 = All Lifetime Data logging is prevented from occurring.
1 = All Lifetime Data logging are allowed
TEMP1, TEMP0 —These bits configure the source of the Temperature function
0,0 = Internal Temperature Sensor
0,1 = TS1 Input (default)
1,0 = Greater Value of TS1 or TS2 Inputs
1,1 = Average of TS1 and TS2 Inputs
STACK —This bit configure the bq33100 to measure all series voltages up to 5 series cells or just the stack
voltage.
0 = Each series cell is measured and can be balanced up to 5 series capacitors
1 = The capacitor stack is measured and Capacitor Balancing and Cell Imbalance Detection are disabled
FAULT Cfg
The FAULT Cfg register enables or disables the use of the FAULT pin when the corresponding bit in
SafetyStatus is set.
Table 56. FAULT Cfg
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
64
Registers
8
FAULT Cfg
Hex
2
0x0000
0xffff
0x0000
bit 2
bit 1
Unit
Table 57. FAULT Cfg Register
bit 7
bit 6
bit 5
bit 4
bit 3
High Byte
CLBAD
HFAIL
HWARN
HLOW
RSVD
OTC
CIM
OV
Low Byte
DFF
RSVD
AFE_C
WDF
OCC
OCD
SCC
SCD
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bit 0
39
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
CLBAD: Weak capacitor condition
HFAIL: Health fault condition
HWARN: Health warning condition
HLOW: Health low condition
AFE_C: AFE Communications failure condition
CIM: Capacitor voltage imbalance condition
DFF: Data Flash Fault failure condition
OTC: Charge overtemperature condition
OV: Capacitor overvoltage condition
WDF: AFE Watchdog fault condition
OCC: Charge overcurrent condition
OCD: AFE overcurrent on discharge condition
SCC: AFE short circuit on charge condition
SCD: AFE short circuit on discharge condition
AFE State_CTL
This register adjusts the AFE hardware overcurrent and short circuit detection thresholds and delay.
Table 58. AFE State_CTL
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
65
AFE
1
AFE
State_CTL
Hex
1
0x00
0x00
0xff
Unit
Table 59. AFE State_CTL Register
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RSVD
RSVD
SCDDX2
RSNS
RSVD
RSVD
RSVD
RSVD
LEGEND: RSVD = Reserved and must be programmed to 0
SCDDX2— Set this bit to double the SCD delay periods 0 (default) = Short Circuit current protection delay is as
programmed
1 = Short Circuit current protection delay is twice that programmed
RSNS— This bit, if set, configures the SCD threshold into a range suitable for a low sense resistor value by
dividing the SCDV selected voltage threshold by 2 0 (default) = Current protection voltage thresholds as
programmed
1 = Current protection voltage threshold divided by 2 as programmed
Measurement Margin %
Measurement Margin % provides any needed addition margin for measurement error or other error sources
Table 60. Measurement Margin %
Subclass
ID
Subclass
Name
86
Capacitance
Estimation
40
Offset
Name
Format
0
Measurement Unsigned
Margin %
Integer
Size in
Bytes
Min Value Max Value
Default
Value
Unit
1
0
10
%
Submit Documentation Feedback
100
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Timer
Timer provides the maximum amount of time for a learning cycle to complete
Table 61. Timer
Subclass
ID
Subclass
Name
86
Capacitance
Estimation
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
4
Timer
Integer
2
0
10
s
32767
V Chg Nominal
Nominal charging voltage(min) representing CHGLVL1 = Low (0) and CHGLVL0 = Low (0).
Table 62. V Chg Nominal
Subclass
ID
Subclass
Name
86
Capacitance
Estimation
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
6
V Chg
Nominal
Integer
2
0
10400
mV
25000
V Chg A
Charging voltage representing CHGLVL1 = Low (0) and CHGLVL0 = High (1).
Table 63. V Chg A
Subclass
ID
Subclass
Name
86
Capacitance
Estimation
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
8
V Chg A
Integer
2
0
11125
mV
25000
V Chg B
Charging voltage representing CHGLVL1 = High (1) and CHGLVL0 = Low (0).
Table 64. V Chg B
Subclass
ID
Subclass
Name
86
Capacitance
Estimation
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
10
V Chg B
Integer
2
0
11875
mV
25000
V Chg Max
Charging voltage(max) representing CHGLVL1 = High (1) and CHGLVL0 = High (1).
Table 65. V Chg Max
Subclass
ID
Subclass
Name
86
Capacitance
Estimation
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
12
V Chg Max
Integer
2
0
125000
mV
25000
Min Voltage
Min Voltage is the minimum voltage which the Super Capacitor should discharge. Min Voltage is used in
Capacitance estimation which defines the Super Capacitor usage range.
Table 66. Min Voltage
Subclass
ID
Subclass
Name
86
Capacitance
Estimation
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
16
Min Voltage
Integer
2
0
4000
mV
10000
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
41
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Learning Frequency
Learning Frequency is the amount of time elapsed between automatic learning cycles.
Table 67. Learning Frequency
Subclass
ID
Subclass
Name
86
Capacitance
Estimation
Offset
Name
Format
18
Learning
Frequency
Unsigned
Integer
Size in
Bytes
Min Value Max Value
Default
Value
Unit
1
0
2
week
255
Dsg Current Threshold
The bq33100 enters discharge mode from charge mode if Current < (-) Dsg Current Threshold.
Table 68. Dsg Current Threshold
Subclass
ID
Subclass
Name
81
Current
Thresholds
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
0
Dsg Current
Threshold
Integer
2
0
10
mA
2000
Chg Current Threshold
The bq33100 enters charge mode from discharge mode if Current > Chg Current Threshold.
Table 69. Chg Current Threshold
Subclass
ID
Subclass
Name
81
Current
Thresholds
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
2
Chg Current
Threshold
Integer
2
0
0
mA
2000
Quit Current
The bq33100 enters relaxation mode from charge mode if Current goes below Quit Current for 60 seconds. The
bq33100 enters relaxation mode from discharge mode if Current goes above (-)Quit Current for 60 seconds.
Table 70. Quit Current
Subclass
ID
Subclass
Name
81
Current
Thresholds
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
4
Quit Current
Integer
2
0
0
mA
1000
MEASUREMENT SYSTEM AND CALIBRATION CONFIGURATION
Calibration
The bq33100 does not require calibration but can be calibrated for improved measurement accuracy.
Coulomb Counter Deadband
The bq33100 does not accumulate charge or discharge for monitoring when the current input is below the
Deadband threshold which should be set sufficiently high to prevent false signal detection with no charge or
discharge flowing through the sense resistor.
Auto Calibration
The bq33100 provides an auto-calibration feature to cancel the voltage offset error across SRP and SRN for
maximum charge measurement accuracy. The bq33100 performs auto-calibration when the SMBus lines stay
low continuously for a minimum of 5 s and Temperature is within bounds of 5°C and 45°C.
Current Gain
Current Gain sets the mA current scale factor for the coulomb counter. Use calibration routines to set this value.
42
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Table 71. Current Gain
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
104
Data
0
Current Gain
Floating point
4
1.0E-01
0.9419
mOhm
4.0E+00
CC Delta
CC Delta sets the mF capacitance scale factor for the coulomb counter. Use calibration routines to set this value.
Table 72. CC Delta
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
104
Data
4
CC Delta
Floating point
4
Min Value Max Value
Default
Value
2.9826E+0 1.193046E+ 280932.825
4
06
Unit
mOhm
Cap1 K-factor
This register value stores the ADC voltage translation factor for the top capacitor (Capacitor 1), which is
connected between the VC1 and VC2 pins. By default, this value is not used and the factory calibration are in
effect. This value overrides the factory calibration when the K-factor Override Flag is set to 0x9669 by the
software calibration process.
Table 73. Cap1 K-factor
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
104
Data
8
Cap1
K-factor
Integer
2
0
20500
32767
Unit
Cap2 K-factor
This register value stores the ADC voltage translation factor for Capacitor 2, which is connected between the
VC2 and VC3 pins. By default, this value is not used and the factory calibration are in effect. This value
overrides the factory calibration when the K-factor Override Flag is set to 0x9669 by the software calibration
process.
Table 74. Cap2 K-factor
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
104
Data
10
Cap2
K-factor
Integer
2
0
20500
32767
Unit
Cap3 K-factor
This register value stores the ADC voltage translation factor for Capacitor 3, which is connected between the
VC3 and VC4 pins. By default, this value is not used and the factory calibration are in effect. This value
overrides the factory calibration when the K-factor Override Flag is set to 0x9669 by the software calibration
process.
Table 75. Cap3 K-factor
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
104
Data
12
Cap3
K-factor
Integer
2
0
20500
32767
Unit
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
43
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Cap4 K-factor
This register value stores the ADC voltage translation factor for Capacitor 4, which is connected between the
VC4 and VC5 pins. By default, this value is not used and the factory calibration are in effect. This value
overrides the factory calibration when the K-factor Override Flag is set to 0x9669 by the software calibration
process.
Table 76. Cap4 K-factor
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
104
Data
14
Cap4
K-factor
Integer
2
0
20500
32767
Unit
Cap5 K-factor
This register value stores the ADC voltage translation factor for the bottom capacitor (Capacitor 5), which is
connected between the VC5 and VSS pins.
Table 77. Cap5 K-factor
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
104
Data
16
Cap5
K-factor
Integer
2
0
20500
32767
Unit
K-factor Override Flag
This register value is by default 0, indicating that the factory calibrated K-factors are being used. If this register is
set to 0x9669, Cap1~Cap5 K-factors in the data flash are used for voltage translation.
Table 78. K-factor Override Flag
Subclass
ID
Subclass
Name
Offset
Name
104
Data
18
K-factor
Hex
Override Flag
Format
Size in
Bytes
Min Value Max Value
Default
Value
2
0x0
0x0
0xffff
Unit
System Voltage K-factor
This register value stores the scale factor for the PackVoltage, voltage measured at the VCCPACK pin of the
bq33100
Table 79. System Voltage K-factor
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
104
Data
20
System
Voltage
K-factor
Integer
2
0
24500
32767
Unit
Stack Voltage K-factor
This register value stores the scale factor for the Stack Voltage, voltage measured at the VCC pin of the
bq33100
Table 80. Stack Voltage K-factor
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
104
Data
22
Stack
Voltage
K-factor
Integer
2
0
24500
44
Submit Documentation Feedback
32767
Unit
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
CC Offset
This register value stores the coulomb counter offset compensation. It is set during CC Offset calibration, or by
automatic calibration of the bq33100 before the gauge enters shutdown. It is not recommended to manually
change this value.
Table 81. CC Offset
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
104
Data
20
CC Offset
Integer
2
-32768
-7744
(mV)
32767
Board Offset
This register value stores the compensation for the PCB dependant coulomb counter offset. It is recommended
to use characterization data of the actual PCB to set this value.
Table 82. Board Offset
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
104
Data
22
Board Offset
Integer
2
-32767
0
uV
32767
Int Temp Offset
This register value stores the internal temperature sensor offset compensation. Use calibration routines to set
this value
Table 83. Int Temp Offset
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
104
Data
24
Int Temp
Offset
Integer
1
-128
0
127
Unit
0.1
degC
Ext1 Temp Offset
This register value stores the temperature sensor offset compensation for the external temperature sensor 1
connected at the TS1 pin of the bq33100. Use calibration routines to set this value
Table 84. Ext1 Temp Offset
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
104
Data
25
Ext1 Temp
Offset
Integer
1
-128
0
127
Unit
0.1
degC
CC Current
This value sets the current used for the CC calibration when in calibration mode.
Table 85. CC Current
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
105
Config
0
CC Current
Integer
2
0
3000
mA
32767
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
45
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Voltage Signal
This value sets the voltage used for calibration when in calibration mode.
Table 86. Voltage Signal
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
105
Config
2
Voltage
Signal
Integer
2
0
12600
mV
Unit
32767
Temp Signal
This value sets the temperature used for the temperature calibration in calibration mode.
Table 87. Temp Signal
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
105
Config
4
Temp Signal
Integer
2
0
298
32767
0.1
degK
CC Offset Time
This value sets the time used for the CC Offset calibration in calibration mode. More time means more accuracy.
The legitimate values for this constant are integer multiples of 250. Numbers less than 250 will cause a CC
Offset calibration error. Numbers greater than 250 will be rounded down to the nearest multiple of 250.
Table 88. CC Offset Time
Subclass
ID
Subclass
Name
Offset
Name
Format
105
Config
6
CC Offset
Time
Unsigned
Integer
Size in
Bytes
Min Value Max Value
Default
Value
Unit
2
0
250
s (ms)
65535
ADC Offset Time
This constant defines the time for the ADC Offset calibration in calibration mode. More time means more
accuracy. The legitimate values for this constant are integer multiples of 32. Numbers less than 32 will cause an
ADC offset calibration error. Numbers greater than 32 will be rounded down to the nearest multiple of 32.
Table 89. ADC Offset Time
Subclass
ID
Subclass
Name
Offset
Name
Format
105
Config
8
ADC Offset
Time
Unsigned
Integer
Size in
Bytes
Min Value Max Value
Default
Value
Unit
2
0
32
ms
65535
Current Gain Time
This constant defines the time for the Current Gain calibration in calibration mode. More time means more
accuracy. The legitimate values for this constant are integer multiples of 250. Numbers less than 250 will cause a
Current gain calibration error. Numbers greater than 250 will be rounded down to the nearest multiple of 250.
Table 90. Current Gain Time
Subclass
ID
Subclass
Name
Offset
Name
Format
105
Config
10
Current Gain
Time
Unsigned
Integer
46
Size in
Bytes
Min Value Max Value
Default
Value
Unit
2
0
250
ms
Submit Documentation Feedback
65535
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Voltage Time
This constant defines the time for the voltage calibration in calibration mode. More time means more accuracy.
The legitimate values for this constant are integer multiples of 1984. Numbers less than 1984 will cause a
voltage calibration error. Numbers greater than 1984 will be rounded down to the nearest multiple of 1984.
Table 91. Voltage Time
Subclass
ID
Subclass
Name
Offset
Name
Format
105
Config
12
Voltage Time
Unsigned
Integer
Size in
Bytes
Min Value Max Value
Default
Value
Unit
2
0
1888
ms
65535
Temperature Time
This constant defines the time for the temperature calibration in calibration mode. More time means more
accuracy. The legitimate values for this constant are integer multiples of 32. Numbers less than 32 will cause a
temperature calibration error. Numbers greater than 32 will be rounded down to the nearest multiple of 32.
Table 92. Temperature Time
Subclass
ID
Subclass
Name
Offset
Name
Format
105
Config
14
Temperature
Time
Unsigned
Integer
Size in
Bytes
Min Value Max Value
Default
Value
Unit
2
0
32
ms
Unit
65535
Cal Mode Timeout
The bq33100 will exit calibration mode automatically after a Cal Mode Timeout period.
Table 93. Cal Mode Timeout
Subclass
ID
Subclass
Name
Offset
Name
Format
105
Config
17
Cal Mode
Timeout
Unsigned
Integer
Size in
Bytes
Min Value Max Value
Default
Value
2
0
38400
65535
1/128 s
(s)
Ext Coef a1..a5, b1..b4, Ext rc0, Ext adc0
These values characterize the external thermistor connected to the TS1 pin or the TS2 pin of the bq33100. The
default values characterize the Semitec 103AT NTC thermistor. Do not modify these values without consulting TI.
Table 94. Ext Coef a1..a5, b1..b4, Ext rc0, Ext adc0
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
106
Temp Model
0
Ext Coef a1
Integer
2
-32768
-11130
num
2
Ext Coef a2
19142
4
Ext Coef a3
-19262
6
Ext Coef a4
28203
8
Ext Coef a5
892
10
Ext Coef b1
328
12
Ext Coef b2
-605
14
Ext Coef b3
-2443
16
Ext Coef b4
4696
18
Ext rc0
11703
20
Ext adc0
11338
32767
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
47
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
Rpad
This value characterize the pad resistance of the bq33100. Do not modify without consulting TI.
Table 95. Rpad
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
106
Temp Model
22
Rpad
Integer
2
-32768
87
Ohm
32767
Rint
This value characterize the internal resistance of the bq3100. Do not modify without consulting TI.
Table 96. Rint
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
106
Temp Model
24
Rint
Integer
2
-32768
17740
Ohm
32767
Int Coef 1..4, Int Min AD, Int Max Temp
These values characterize the internal thermistor of the bq33100. Do not modify these values without consulting
TI.
Table 97. Int Coef 1..4, Int Min AD, Int Max Temp
Subclass
ID
Subclass
Name
Offset
Name
Format
Size in
Bytes
Min Value Max Value
Default
Value
Unit
106
Temp Model
26
Int Coef 1
Integer
2
-32768
0
s
28
Int Coef 2
0
30
Int Coef 3
-12263
32
Int Coef 4
6106
34
Int Min AD
0
36
Int Max Temp
6106
32767
0.1
degK
Filter
Filter defines the filter constant used in the AverageCurrent calculation:
AverageCurrent new = a x AverageCurrent old + (1 - a) x Current
with:
a = <Filter> / 256; the time constant = 1 sec/ln(1/a) (default 14.5 sec)
Table 98. Filter
Subclass
ID
Subclass
Name
Offset
Name
Format
107
Current
0
Filter
Unsigned
Integer
Size in
Bytes
Min Value Max Value
Default
Value
1
0
239
255
Unit
Deadband
Any current within ±DeadBand will be reported as 0 mA by the Current function
Table 99. Deadband
Subclass
ID
Subclass
Name
Offset
Name
Format
107
Current
1
Deadband
Unsigned
Integer
48
Size in
Bytes
Min Value Max Value
Default
Value
Unit
1
0
0
mA
Submit Documentation Feedback
255
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
CC Deadband
This constant defines the Deadband voltage for the measured voltage between the SR1 and SR2 pins used for
capacitance accumulation in units of 294 nV. Any voltages within ±CC Deadband do not contribute to
capacitance accumulation.
Table 100. CC Deadband
Subclass
ID
Subclass
Name
Offset
Name
Format
107
Current
2
Deadband
Unsigned
Integer
Size in
Bytes
Min Value Max Value
Default
Value
Unit
1
0
10
294 nV
255
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
49
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
APPLICATION INFORMATION
APPLICATION SCHEMATIC
Application Reference Schematic
50
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
bq33100
SLUS987A – JANUARY 2011 – REVISED MARCH 2011
www.ti.com
REVISION HISTORY
Changes from Original (January 2011) to Revision A
Page
•
Changed SYSTEM PARTITIONING DIAGRAM. .................................................................................................................. 3
•
Changed Voltage as Current During Learning graphic. ...................................................................................................... 14
•
Changed equation 1 denominator from (V[D] - [C]) to (V[C] - V[D]). .................................................................................. 14
•
Changed Application Reference Schematic. ...................................................................................................................... 50
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq33100
51
PACKAGE OPTION ADDENDUM
www.ti.com
1-Apr-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
BQ33100PW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
BQ33100PWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Mar-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
BQ33100PWR
Package Package Pins
Type Drawing
TSSOP
PW
24
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Mar-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ33100PWR
TSSOP
PW
24
2000
346.0
346.0
33.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
www.ti.com/audio
Communications and Telecom www.ti.com/communications
Amplifiers
amplifier.ti.com
Computers and Peripherals
www.ti.com/computers
Data Converters
dataconverter.ti.com
Consumer Electronics
www.ti.com/consumer-apps
DLP® Products
www.dlp.com
Energy and Lighting
www.ti.com/energy
DSP
dsp.ti.com
Industrial
www.ti.com/industrial
Clocks and Timers
www.ti.com/clocks
Medical
www.ti.com/medical
Interface
interface.ti.com
Security
www.ti.com/security
Logic
logic.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Power Mgmt
power.ti.com
Transportation and
Automotive
www.ti.com/automotive
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
Wireless
www.ti.com/wireless-apps
RF/IF and ZigBee® Solutions
www.ti.com/lprf
TI E2E Community Home Page
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2011, Texas Instruments Incorporated