ASAHI KASEI [AK93C45A/55A/65A/75A] AK93C45A / 55A / 65A / 75A 1K / 2K / 4K / 8Kbit Serial CMOS EEPROM Features ADVANCED CMOS EEPROM TECHNOLOGY READ/WRITE NON-VOLATILE MEMORY WIDE VCC OPERATION : VCC = 1.8V to 5.5V AK93C45A ・・1024 bits, 64 x 16 organization AK93C55A ・・2048 bits, 128 x 16 organization AK93C65A ・・4096 bits, 256 x 16 organization AK93C75A ・・8192 bits, 512 x 16 organization SERIAL INTERFACE - Interfaces with popular microcontrollers and standard microprocessors LOW POWER CONSUMPTION - 0.8µA Max. Standby High Reliability - Endurance : 100K cycles - Data Retention : 10 years Automatic address increment (READ) Automatic write cycle time-out with auto-ERASE Busy/Ready status signal Software controlled write protection IDEAL FOR LOW DENSITY DATA STORAGE - Low cost, space saving, 8-pin package (SOP, TSSOP) DO DATA REGISTER DI INSTRUCTION REGISTER INSTRUCTION DECODE, CONTROL AND CLOCK GENERATION 16 ADD. BUFFERS R/W AMPS AND AUTO ERASE DECODER 16 EEPROM 93C45A=1024bit 93C55A=2048bit 93C65A=4096bit 93C75A=8192bit CS VPP SW SK PE (AK93C55A/65A) VREF VPP GENERATOR Block Diagram DAM01E-02 2002/06 - 1 - ASAHI KASEI [AK93C45A/55A/65A/75A] General Description The AK93C45A/55A/65A/75A is a 1024/2048/4096/8192-bit serial CMOS EEPROM divided into 64/128/256/512 registers of 16 bits each. The AK93C45A/55A/65A/75A has 4 instructions such as READ, WRITE, EWEN and EWDS. Those instructions control the AK93C45A/55A/65A/75A. The AK93C45A/55A/65A/75A can operate full function under wide operating voltage range from 1.8V to 5.5V. The charge up circuit is integrated for high voltage generation that is used for write operation. A serial interface of AK93C45A/55A/65A/75A, consisting of chip select (CS), serial clock (SK), datain (DI) and data-out (DO), can easily be controlled by popular microcontrollers or standard microprocessors. AK93C45A/55A/65A/75A takes in the write data from data input pin (DI) to a register synchronously with rising edge of input pulse of serial clock pin (SK). And at read operation, AK93C45A/55A/65A/75A takes out the read data from a register to data output pin (DO) synchronously with rising edge of SK. The DO pin is usually in high impedance state. The DO pin outputs "L" or "H" in case of data output or Busy/Ready signal output. x Software controlled write protection When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable state. In the ERASE/WRITE disable state, execution of WRITE instruction is disabled. Before WRITE instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable state continues until EWDS instruction is executed or VCC is removed from the part. Execution of a read instruction is independent of both EWEN and EWDS instructions. The PE is internally pulled up to VCC. If the PE is left unconnected, the part will accept WRITE, EWEN and EWDS instructions. ・・AK93C55A/65A x Busy/Ready status signal After a write instruction, the DO output serves as a Busy/Ready status indicator. After the falling edge of the CS initiates the self-timed programming cycle, the DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of 250ns (Tcs). DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction. The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO output goes into a high impedance state. The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is given to the part. Type of Products Model AK93C45AF AK93C45AV AK93C55AF AK93C55AV AK93C65AF AK93C65AV AK93C75AV Memory size 1K bits 2K bits 4K bits 8K bits Temp. Range -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C DAM01E-02 VCC 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V Package 8pin Plastic SOP 8pin Plastic TSSOP 8pin Plastic SOP 8pin Plastic TSSOP 8pin Plastic SOP 8pin Plastic TSSOP 8pin Plastic TSSOP 2002/06 - 2 - ASAHI KASEI [AK93C45A/55A/65A/75A] Pin Arrangement AK93C45AF/55AF/65AF NC/PE(note) 1 8 NC VCC 2 7 GND CS 3 6 DO SK 4 5 DI AK93C45AV/55AV/65AV/75AV CS SK DI DO 8 7 6 5 1 2 3 4 8pin SOP VCC NC/PE(note) NC GND 8pin TSSOP (note) AK93C45A/75A・・NC, AK93C55A/65A・・PE Pin Name Function CS Chip Select SK Serial Data Clock DI Serial Data Input DO Serial Data Output GND Ground PE Program Enable VCC Power Supply NC Not Connected (note) The PE is internally pulled up to VCC ( R = typ.2.5MΩ, VCC=5V ). DAM01E-02 2002/06 - 3 - ASAHI KASEI [AK93C45A/55A/65A/75A] Functional Description The AK93C45A/55A/65A/75A has 4 instructions such as READ, WRITE, EWEN and EWDS. A valid instruction consists of a Start Bit (Logic"1"), the appropriate Op Code and the desired memory Address location. The CS pin must be brought low for a minimum of 250ns (Tcs) between each instruction when the instruction is continuously executed. Instruction READ WRITE EWEN EWDS WRAL Start Op Bit Code 1 10 1 01 1 00 1 00 1 00 Address A5-A0 A5-A0 11XXXX 00XXXX 01XXXX Data Comments D15-D0 D15-D0 Reads data stored in memory, at specified address. Writes register. Write enable must precede all programming modes. Disables all programming instructions. D15-D0 Writes all registers. X: Don't care table1. Instruction Set for the AK93C45A Instruction READ WRITE EWEN EWDS WRAL Start Op Bit Code 1 10 1 01 1 00 1 00 1 00 Address Data Comments X A6-A0 X A6-A0 11XXXXXX 00XXXXXX 01XXXXXX D15-D0 D15-D0 Reads data stored in memory, at specified address. Writes register. Write enable must precede all programming modes. Disables all programming instructions. D15-D0 Writes all registers. X: Don't care table2. Instruction Set for the AK93C55A Instruction READ WRITE EWEN EWDS WRAL Start Op Bit Code 1 10 1 01 1 00 1 00 1 00 Address Data Comments A7-A0 A7-A0 11XXXXXX 00XXXXXX 01XXXXXX D15-D0 D15-D0 Reads data stored in memory, at specified address. Writes register. Write enable must precede all programming modes. Disables all programming instructions. D15-D0 Writes all registers. X: Don't care table3. Instruction Set for the AK93C65A Instruction READ WRITE EWEN EWDS WRAL Start Op Address Bit Code 1 10 X A8-A0 1 01 X A8-A0 1 00 11XXXXXXXX 1 00 00XXXXXXXX 1 00 01XXXXXXXX Data Comments D15-D0 D15-D0 Reads data stored in memory, at specified address. Writes register. Write enable must precede all programming modes. Disables all programming instructions. D15-D0 Writes all registers. X: Don't care table4. Instruction Set for the AK93C75A (Note) x The WRAL instruction are used for factory function test only. User can't use the WRAL instruction. x The AK93C45A/55A/65A/75A perceives the start bit in the logic"1" and also "01". DAM01E-02 2002/06 - 4 - ASAHI KASEI [AK93C45A/55A/65A/75A] WRITE The write instruction is followed by 16 bits of data to be written into the specified address. After the last bit of data is put on the DI pin, the CS pin must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. The DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of 250ns (Tcs). DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction. CS SK DI 1 0 0 1 2 0 Start Bit 3 1 4 A5 5 A4 8 A1 9 A0 10 D15 11 D14 23 D2 24 D1 25 tCS D0 Op code Busy Hi-Z DO Ready AK93C45A output a logic "1" (Ready status), if previous instruction is WRITE. tE/W WRITE (AK93C45A) CS SK DI 1 0 0 1 2 0 Start Bit 3 4 X / A7 1 5 A6 10 A1 11 A0 12 D15 13 D14 25 D2 26 D1 27 tCS D0 Op code Busy Hi-Z DO Ready AK93C55A/65A output a logic "1" (Ready status), if previous instruction is WRITE. tE/W X: Don't care *Address bit A7 becomes a "don't care" for AK93C55A. WRITE (AK93C55A/65A) CS SK DI 1 0 0 1 Start Bit DO 2 0 3 1 4 X 5 A8 12 A1 13 A0 14 D15 15 D14 27 D2 28 D1 29 tCS D0 Op code Busy Hi-Z Ready AK93C75A output a logic "1" (Ready status), if previous instruction is WRITE. tE/W X: Don't care WRITE (AK93C75A) DAM01E-02 2002/06 - 5 - ASAHI KASEI [AK93C45A/55A/65A/75A] READ The read instruction is the only instruction which outputs serial data on the DO pin. Following the Start bit, first Op code and address are decoded, then the data from the selected memory location is available at the DO pin. A dummy bit (logical "0") precedes the 16-bit data from the selected memory location. The output data changes are synchronized with the rising edges of the serial clock (SK). The data in the next address can be read sequentially by continuing to provide clock. The address automatically cycles to the next higher address after the 16bit data shifted out. When the highest address is reached, the address counter rolls over to address $00 or $000 allowing the read cycle to be continued indefinitely. CS SK DI 1 0 0 1 2 1 Start bit 3 0 4 A5 5 A4 8 A1 9 10 11 25 26 40 41 A0 Op code Hi-Z DO 0 D15 D14 D0 Dummy address[A5–A0] Bit AK93C45A output a logic "1" (Ready status), if previous instruction is WRITE. D15 D1 D0 address[A5–A0]+1 READ (AK93C45A) CS SK DI 1 0 0 1 2 1 Start bit 3 4 X / A7 0 5 A6 10 A1 11 12 13 27 28 42 43 A0 Op code Hi-Z DO AK93C55A/65A output a logic "1" (Ready status), if previous instruction is WRITE. 0 D15 D14 D0 Dummy address[A6/A7–A0] Bit D15 D1 D0 address[A6/A7–A0]+1 X: Don't care *Address bit A7 becomes a "don't care" for AK93C55A. READ (AK93C55A/65A) CS SK DI 0 0 1 1 Start bit DO 2 1 3 0 4 X 5 A8 12 A1 13 14 15 29 30 44 45 A0 Op code Hi-Z AK93C75A output a logic "1" (Ready status), if previous instruction is WRITE. 0 D15 D14 D0 Dummy address[A8–A0] Bit D15 D1 D0 address[A8–A0]+1 X: Don't care READ (AK93C75A) DAM01E-02 2002/06 - 6 - ASAHI KASEI [AK93C45A/55A/65A/75A] EWEN / EWDS When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable state. In the ERASE/WRITE disable state, execution of WRITE instruction is disable. Before WRITE instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable state continues until EWDS instruction is executed or VCC is removed from the part. Execution of a read instruction is independent of both EWEN and EWDS instructions. CS SK DI 0 0 1 1 2 0 3 4 5 0 6 X 7 X 8 X 9 X EWEN=11 EWDS=00 Start bit Hi-Z DO AK93C45A output a logic "1" (Ready status), if previous instruction is WRITE. X: Don't care EWEN / EWDS (AK93C45A) CS SK DI 0 0 1 1 2 0 3 4 5 0 6 X 7 X 8 X 9 10 X X 11 X EWEN=11 EWDS=00 Start bit Hi-Z DO AK93C55A/65A output a logic "1" (Ready status), if previous instruction is WRITE. X: Don't care EWEN / EWDS (AK93C55A/65A) CS SK DI 0 0 1 1 Start bit DO 2 0 3 4 5 0 6 X 7 X 8 X 9 X 10 X 11 X 12 X 13 X EWEN=11 EWDS=00 Hi-Z AK93C75A output a logic "1" (Ready status), if previous instruction is WRITE. X: Don't care EWEN / EWDS (AK93C75A) DAM01E-02 2002/06 - 7 - ASAHI KASEI [AK93C45A/55A/65A/75A] Absolute Maximum Ratings Parameter Power Supply All Input Voltages with Respect to Ground Ambient storage temperature Symbol VCC VIO Min -0.6 -0.6 Max +7.0 VCC+0.6 Unit V V Tst -65 +150 °C Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability. Recommended Operating Condition Parameter Power Supply Ambient Operating Temperature Symbol VCC Ta DAM01E-02 Min 1.8 -40 Max 5.5 +85 Unit V °C 2002/06 - 8 - ASAHI KASEI [AK93C45A/55A/65A/75A] Electrical Characteristics (1) D.C. ELECTRICAL CHARACTERISTICS ◇AK93C45A/55A/65A ( 1.8V ≤ VCC ≤ 5.5V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified ) Paremeter Current Dissipation (WRITE) Symbol ICC1 Condition VCC=5.5V, tSKP=1.0µs, *1 ICC2 93C45A VCC=1.8V, tSKP=4µs,*1 93C55A/65A Min. Max. 4.0 Unit mA 1.5 mA 2.0 mA Current Dissipation ICC3 VCC=5.5V, tSKP=1.0µs, *1 0.5 mA (READ, EWEN, EWDS) ICC4 VCC=2.5V, tSKP=2.0µs, *1 0.2 mA ICC5 VCC=1.8V, tSKP=4.0µs, *1 0.1 mA Current Dissipation (Standby) ICCSB VCC=5.5V 0.8 µA Input High Voltage VIH1 VCC=5.0V±10% 2.0 VCC + 0.5 V VIH2 2.5V ≤ VCC ≤ 5.5V 0.8 x VCC VCC + 0.5 V VIH3 1.8V ≤ VCC < 2.5V 0.8 x VCC VCC + 0.5 V VIL1 VCC=5.0V±10% -0.1 0.8 V VIL2 2.5V ≤ VCC ≤ 5.5V -0.1 0.15 x VCC V VIL3 1.8V ≤ VCC < 2.5V -0.1 0.2 x VCC V VOH1 VCC=5.0V±10% IOH=-0.4mA VOH2 Input Low Voltage Output High Voltage *2 2.2 V 2.5V ≤ VCC ≤ 5.5V IOH=-0.1mA 0.8 x VCC V VOH3 1.8V ≤ VCC < 2.5V IOH=-0.1mA 0.8 x VCC V VOL1 VCC=5.0V±10% IOL=2.1mA 0.4 V VOL2 2.5V ≤ VCC ≤ 5.5V IOL=1.0mA 0.4 V VOL3 1.8V ≤ VCC < 2.5V IOL=0.1mA 0.4 V Input Leakage ILI VCC=5.5V, VIN=5.5V ±1.0 µA Output Leakage ILO VCC=5.5V, VOUT=5.5V, CS=GND ±1.0 µA Output Low Voltage *3 *1 : VIN=VIH/VIL, DO=Open *2 : VIN=VCC/GND, CS=GND, DO=Open *3 : CS, SK, DI pin DAM01E-02 2002/06 - 9 - ASAHI KASEI [AK93C45A/55A/65A/75A] ◇AK93C75A ( 1.8V ≤ VCC ≤ 5.5V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified ) Paremeter VCC=5.5V, tSKP=1.0µs, *4 Max. 4.0 Unit mA ICC2 VCC=1.8V, tSKP=4.0µs, *4 2.0 mA Current Dissipation ICC3 VCC=5.5V, tSKP=1.0µs, *4 0.4 mA (READ, EWEN, EWDS) ICC4 VCC=1.8V, tSKP=4.0µs, *4 0.1 mA Current Dissipation (Standby) ICCSB VCC=5.5V 0.8 µA Input High Voltage VIH VCC + 0.5 V Input Low Voltage VIL 0.2 x VCC V Output High Voltage VOH1 2.5V ≤ VCC ≤ 5.5V IOH=-0.1mA 0.8 x VCC V VOH2 1.8V ≤ VCC < 2.5V IOH=-0.1mA 0.8 x VCC V VOL1 2.5V ≤ VCC ≤ 5.5V IOL=1.0mA 0.4 V VOL2 1.8V ≤ VCC < 2.5V IOL=0.1mA 0.4 V Input Leakage ILI VCC=5.5V, VIN=5.5V ±1.0 µA Output Leakage ILO VCC=5.5V, VOUT=5.5V, CS=GND ±1.0 µA Current Dissipation (WRITE) Output Low Voltage Symbol ICC1 Condition Min. *5 0.8 x VCC -0.1 *4 : VIN=VIH/VIL, DO=Open *5 : VIN=VCC/GND, CS=GND, DO=Open DAM01E-02 2002/06 - 10 - ASAHI KASEI [AK93C45A/55A/65A/75A] (2) A.C. ELECTRICAL CHARACTERISTICS ( 1.8V ≤ VCC ≤ 5.5V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified ) Paremeter SK Cycle Time SK Pulse Width Symbol tSKP1 Condition 4.5V ≤ VCC ≤ 5.5V Min. 1.0 Max. Unit tSKP2 2.0V ≤ VCC < 4.5V 2.0 µs tSKP3 1.8V ≤ VCC < 2.0V 4.0 µs tSKW1 4.5V ≤ VCC ≤ 5.5V 500 ns tSKW2 2.0V ≤ VCC < 4.5V 1.0 µs tSKW3 1.8V ≤ VCC < 2.0V 2.0 µs µs CS Setup Time tCSS 100 ns CS Hold Time tCSH 0 ns Data Setup Time tDIS 200 ns Data Hold Time tDIH 200 ns Output delay *6 Selftimed Programming Time tPD1 4.5V ≤ VCC ≤ 5.5V 500 ns tPD2 2.0V ≤ VCC < 4.5V 1.0 µs tPD3 1.8V ≤ VCC < 2.0V 2.0 µs tE/W1 93C45A/55A/65A 10 ms tE/W2 93C75A 4.5V ≤ VCC ≤ 5.5V 8 ms 1.8V ≤ VCC < 4.5V 10 ms tE/W3 Min CS Low Time tCS 250 ns CS to Status Valid tSV CL=100pF 500 ns CS to Output High-Z tOZ1 2.0V ≤ VCC ≤ 5.5V 100 ns tOZ2 1.8V ≤ VCC < 2.0V 250 ns *6 : CL=100pF DAM01E-02 2002/06 - 11 - ASAHI KASEI [AK93C45A/55A/65A/75A] Synchronous Data timing CS tCSS tSKW tSKW tSKP SK tDIS DI 0 tDIH 1 tSV Hi-Z DO AK93C45A/55A/65A/75A output a logical "1" (Ready status), if previous instruction is WRITE. The Start of Instruction CS tCSH SK DI tPD DO D3 tPD D2 tPD D1 tOZ D0 Hi-Z The End of Instruction DAM01E-02 2002/06 - 12 - ASAHI KASEI [AK93C45A/55A/65A/75A] tCS CS tCSH SK tDIS DI tDIH D1 D0 tSV DO Hi-Z Busy Ready tE/W Busy/Ready Signal Output DAM01E-02 2002/06 - 13 - IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. 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