TI ADS8519IDBR 16-bit 250-ksps serial cmos sampling analog-to-digital converter Datasheet

 ADS8519
www.ti.com
SLAS462 – JUNE 2007
16-BIT 250-KSPS SERIAL CMOS SAMPLING ANALOG-TO-DIGITAL CONVERTER
FEATURES
1
•
•
•
•
•
•
•
0-V to 8.192-V, ±5-V, and ±10-V Input Ranges
90-dB SNR With 20-kHz Input
±2.0 LSB Max INL
±1 LSB Max DNL; 16-Bits No Missing Codes
SPI Compatible Serial Output with
Daisy-Chain (TAG) Feature and 3-State Bus
5-V Analog Supply, 5.25 V ~ 1.65 V I/O Supply
Pinout Similar to ADS7809 (Low Speed) and
12-Bit ADS7808/8508
No External Precision Resistors Required
Uses Internal or External Reference
100-mW Typ Power Dissipation at 250 KSPS
32-Pin 5x5 QFN and 28-Pin SSOP Packages
Simple DSP Interface
The ADS8519 is a complete 16-bit sampling
analog-to-digital (A/D) converter using state-of-the-art
CMOS structures. It contains a complete 16-bit,
capacitor- based, successive approximation register
(SAR) A/D converter with sample-and-hold,
reference, clock, and a serial data interface. Data can
be output using the internal clock or can be
synchronized to an external data clock. The ADS8519
also provides an output synchronization pulse for
ease of use with standard DSP processors.
The ADS8519 is specified at a 250-kHz sampling rate
over the full temperature range. Precision resistors
provide various input ranges including ±10 V and 0 V
to 5 V, while the innovative design allows operation
from a single 5-V supply with power dissipation under
100 mW.
The ADS8519 is available in 32-pin 5x5 QFN and
28-pin SSOP packages, both fully specified for
operation over the industrial -40°C to 85°C
temperature range.
APPLICATIONS
•
•
•
•
•
DESCRIPTION
Industrial Process Control
Data Acquisition Systems
Digital Signal Processing
Medical Equipment
Instrumentation
Successive Approximation Register
Clock
CDAC
7 kΩ
R1IN
7 kΩ
EXT/INT
BUSY
25.67 kΩ
R2IN
2.87 kΩ
R3IN
Comparator
CAP
Buffer
4 kΩ
REF
Internal
+4.096 V Ref
Serial
Data
Out
&
Control
DATACLK
TAG
DATA
R/C
SB/BTC
CS
PWRD
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2007, Texas Instruments Incorporated
PRODUCT PREVIEW
•
•
•
•
•
ADS8519
www.ti.com
SLAS462 – JUNE 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION (1)
MINIMUM
INL
(LSB)
PRODUCT
ADS8519IB
NO
MISSING
CODE
±2
MINIMUM
SINAD
(dB)
16
SPECIFICATION
TEMPERATURE
RANGE
90
PACKAGE
LEAD
PACKAGE
DESIGNATOR
5x5 QFN-32
RHB
–40°C to 85°C
SSOP-28
5x5 QFN-32
ADS8519I
±3
15
87
(1)
ADS8519IBRHB
ADS8519IBRHBR
ADS8519IBDB
DB
ADS8519IBDBR
RHB
–40°C to 85°C
SSOP-28
ORDERING
NUMBER
ADS8519IRHB
ADS8519IRHBR
ADS8519IDB
DB
ADS8519IDBR
TRANSPORT
MEDIA, QTY
Tube, 50
Tape and Reel, 2000
Tube, 50
Tape and Reel, 2000
Tube, 50
Tape and Reel, 2000
Tube, 50
Tape and Reel, 2000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
PRODUCT PREVIEW
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
Analog inputs
R1IN
±25 V
R2IN
±25 V
R3IN
±25 V
REF
+VANA + 0.3 V to AGND2 - 0.3 V
DGND, AGND2
Ground voltage differences
±0.3 V
VANA
6V
VDIG to VANA
0.3 V
VDIG
6V
Digital inputs
–0.3 V to +VDIG + 0.3 V
Maximum junction temperature
165°C
Internal power dissipation
700 mW
Lead temperature (soldering, 10s)
(1)
300°C
All voltage values are with respect to network ground terminal.
ELECTRICAL CHARACTERISTICS
At TA = –40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise specified)
ADS8519I
PARAMETER
ADS8519IB
TEST CONDITIONS
UNIT
MIN
TYP
Resolution
MAX
MIN
TYP
16
MAX
16
Bits
ANALOG INPUT
Voltage ranges (1)
Impedance (1)
Capacitance
50
50
pF
THROUGHPUT SPEED
Conversion cycle time
Acquire and convert
Throughput rate
4
250
4
250
μs
kHz
DC ACCURACY
INL
Integral linearity error
–3
3
–2
2
LSB (2)
DNL
Differential linearity error
–2
2
–1
1
LSB
(1)
(2)
2
±10 V, ±5 V, 0 V to 8.192 V, etc. (see Table 3)
LSB means least significant bit. For the ±10-V input range, one LSB is 305 μV.
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ELECTRICAL CHARACTERISTICS (continued)
At TA = –40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise specified)
ADS8519I
PARAMETER
UNIT
MIN
No missing codes
MIN
TYP
MAX
16
Bits
0.67
LSB
–0.05
±0.5
0.05
–0.05
±0.5
0.05
–0.5
TBD
0.5
–0.5
TBD
0.5
–0.05
0.05
–0.05
0.05
–0.5
0.5
–0.5
0.5
4
–2
Int. Ref.
All other ranges
%FSR
Int. Ref.
±10 V range
±7
±7
ppm/°C
Ext. Ref.
All other ranges
Full-scale error drift
%FSR
Ext. Ref.
Bipolar zero error (4)
±2
–4
Bipolar zero error drift
Unipolar zero
error (4)
MAX
0.67
±10 V range
Full-scale error drift
Full-scale
error (4) (5)
TYP
15
Transition noise (3)
Full-scale
error (4) (5)
ADS8519IB
TEST CONDITIONS
±2
±2
8.192 V
–20
Unipolar zero error drift
Recovery to rated accuracy after
power down
1-μF Capacitor to CAP
Power supply sensitivity
(VDIG = VANA = VD)
+4.75 V < VD < +5.25 V
–8
95
ppm/°C
2
±2
20
–20
20
±0.4
±0.4
1
1
8
–8
mV
ppm/°C
mV
ppm/°C
ms
8
LSB
SFDR
Spurious-free dynamic range
fI = 20 kHz
THD
Total harmonic distortion
fI = 20 kHz
SINAD
Signal-to-(noise+distortion)
fI = 20 kHz
–100
87
–60-dB Input
SNR
Signal-to-noise ratio
fI = 20 kHz
102
97
–94
91
30
88
Full-power bandwidth (7)
92
90
500
dB (6)
102
–100
89
PRODUCT PREVIEW
AC ACCURACY
–96
dB
91
dB
32
dB
92
dB
500
kHz
SAMPLING DYNAMICS
Aperture delay
Transient response
5
FS Step
5
2
Overvoltage recovery (8)
ns
2
150
150
μs
ns
REFERENCE
Internal reference voltage
No load
4.076
4.096
4.116
4.076
4.096
4.116
V
Internal reference source current
(must use external buffer)
1
1
μA
Internal reference drift
8
8
ppm/°C
External reference voltage range
for specified linearity
External reference current drain
2.5
Ext. 4.096-V Ref.
4.096
4.1
2.5
100
4.096
4.1
V
100
μA
V
DIGITAL INPUTS
Logic levels
VIL
Low-level input voltage
VDIG = 1.65 V ~ 5.25 V
–0.3
0.8, 0.35 xVDIG
–0.3
0.8, 0.35 xVDIG
VIH
High-level input voltage
VDIG = 1.65 V ~ 5.25 V
2.0, 0.65 xVDIG
VDIG +0.3 V
2.0, 0.65 xVDIG
VDIG +0.3 V
V
IIL
Low-level input current
VIL = 0 V
±10
±10
μA
IIH
High-level input current
VIH = 5 V
±10
±10
μA
DIGITAL OUTPUTS
Data format (Serial 16-bits)
Data coding (Binary 2's
complement or straight binary)
Pipeline delay (Conversion results
only available after completed
conversion.)
(3)
(4)
(5)
(6)
(7)
(8)
Typical rms noise at worst case transitions and temperatures.
As measured with circuit shown in Figure 25 and Figure 26.
For bipolar input ranges, full-scale error is the worst case of –full-scale or +full-scale uncalibrated deviation from ideal first and last code
transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. For unipolar input
ranges, full-scale error is the deviation of the last code transition divided by the transition voltage. It also includes the effect of offset
error.
All specifications in dB are referred to a full-scale ±10-V input.
Full-power bandwidth is defined as the full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB.
Recovers to specified performance after 2 x FS input overvoltage.
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ELECTRICAL CHARACTERISTICS (continued)
At TA = –40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise specified)
ADS8519I
PARAMETER
ADS8519IB
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
Data clock (Selectable for internal
or external data clock)
Internal clock (output only when
transmitting data)
External clock (can run continually
but not recommended for optimum
performance)
EXT/INT Low
9
9
MHz
EXT/INT High
0.1
26
0.1
26
MHz
VOL
Low-level output voltage
ISINK = 1.6 mA,
VDIG = 1.65 V ~ 5.25 V
VOH
High-level output voltage
ISOURCE = 500 μA,
VDIG = 1.65 V ~ 5.25 V
Leakage current
Hi-Z state,
VOUT = 0 V to VDIG
±5
±5
μA
Output capacitance
Hi-Z state
15
15
pF
5.25
V
0.45
VDIG-0.45
0.45
VDIG-0.45
V
V
POWER SUPPLIES
PRODUCT PREVIEW
VDIG
Digital input voltage
1.65
VANA
Analog input voltage
4.75
IDIG
Digital input current
IANA
Analog input current
Must be ≤ VANA
5.25
1.65
5
5.25
4.75
0.1
5
5.25
1
0.1
1
mA
V
20
25
20
25
mA
100
125
100
125
mW
POWER DISSIPATION
PWRD Low
fS = 250 kHz
PWRD High
50
μW
50
TEMPERATURE RANGE
Specified performance
–40
85
–40
85
°C
Derated performance (9)
–55
125
–55
125
°C
Storage
–65
150
–65
150
°C
THERMAL RESISTANCE (ΘJA)
67
67
°C/W
35.861
35.861
°C/W
SSOP
QFN
(9)
4
The internal reference may not be started correctly beyond the industrial temperature range (–40°C to 85°C), therefore use of an
external reference is recommended.
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SLAS462 – JUNE 2007
TIMING REQUIREMENTS, TA = –40°C to 85°C
MIN
TYP
MAX
6
20
ns
2.2
μs
tw1
Pulse duration, convert
td1
Delay time, BUSY from R/C low
tw2
Pulse duration, BUSY low
td2
Delay time, BUSY, after end of conversion
5
td3
Delay time, aperture
5
tconv
Conversion time
tacq
Acquisition time
tconv + tacq
40
UNIT
ns
ns
ns
2.2
μs
μs
1.8
Cycle time
4
μs
td4
Delay time, R/C Low to internal DATACLK output
270
ns
tc1
Cycle time, internal DATACLK
110
ns
td5
Delay time, data valid to internal DATACLK high
15
35
ns
td6
Delay time, data valid after internal DATACLK low
20
35
ns
tc2
Cycle time, external DATACLK
35
ns
tw3
Pulse duration, external DATACLK high
15
ns
tw4
Pulse duration, external DATACLK low
15
ns
tsu1
Setup time, R/C rise/fall to external DATACLK high
15
ns
tsu2
Setup time, R/C transition to CS transition
10
td7
Delay time, SYNC, after external DATACLK high
3
35
ns
td8
Delay time, data valid from external DATACLK high
2
20
ns
td9
Delay time, CS rising edge to external DATACLK rising edge
td10
tsu3
td11
Delay time, final external DATACLK to BUSY rising edge
tsu3
Setup time, TAG valid
0
ns
th1
Hold time, TAG valid
2
ns
ns
10
ns
Delay time, previous data available after CS, R/C low
2
μs
Setup time, BUSY transition to first external DATACLK
5
TAG
NC
NC
DATACLK
23 NC
VANA
28
13
SYNC
22 NC
R1IN
29
12
DGND
AGND1
30
11
EXT/INT
R2IN
31
10
SB/BTC
R3IN
32
1
9
21 R/C
20 NC
18 NC
17 DATA
16 DATACLK
Note:
15 SYNC
Thermal Pad
2
3
4
5
6
7
8
NC
24 CS
NC 11
DGND 14
CS
NC
R/C
14
19 TAG
EXT/INT 13
NC
27
NC 10
SB/BTC 12
NC
DATA
VDIG
25 BUSY
NC
AGND2 9
PWRD
15
AGND2
NC 8
NC
26
BUSY
NC
REF 7
24 23 22 21 20 19 18 17
25
16
26 PWRD
REF
CAP 6
27 VANA
NC
R3IN 4
NC 5
28 VDIG
CAP
R2IN 3
μs
RHB PACKAGE
(TOP VIEW)
NC
R1IN 1
AGND1 2
ns
1
DB PACKAGE
(TOP VIEW)
PRODUCT PREVIEW
PARAMETER
NC
The package thermal pad must be soldered
to the printed circuit board for thermal and
mechanical performance.
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Terminal Functions
TERMINAL
NAME
DESCRIPTION
SSOP
NO.
QFN NO.
I/O
AGND1
2
30
–
Analog ground. Used internally as ground reference point. Minimal current flow.
AGND2
9
6
–
Analog ground
BUSY
25
25
O
Busy output. Falls when a conversion is started, and remains low until the conversion is completed
and the data is latched into the output shift register.
CS
24
22
–
Chip select. Internally ORed with R/C.
PRODUCT PREVIEW
CAP
6
3
DATA
17
15
O
Serial data output. Data is synchronized to DATACLK, with the format determined by the level of
SB/BTC. In the external clock mode, after 16 bits of data, the ADS8519 outputs the level input on
TAG as long as CS is low and R/C is high (see Figure 8 and Figure 9). If EXT/INT is low, data is
valid on both the rising and falling edges of DATACLK, and between conversions DATA stays at
the level of the TAG input when the conversion was started.
DATACLK
16
14
I/O
Either an input or an output depending on the EXT/INT level. Output data is synchronized to this
clock. If EXT/INT is low, DATACLK transmits 16 pulses after each conversion, and then remains
low between conversions.
DGND
14
12
–
Digital ground
EXT/INT
13
11
–
Selects external or internal clock for transmitting data. If high, data is output synchronized to the
clock input on DATACLK. If low, a convert command initiates the transmission of the data from the
previous conversion, along with 16-clock pulses output on DATACLK.
–
No connect
NC
5, 8, 10, 1, 2, 5, 7,
11, 18, 8, 9, 16,
20, 22,
17, 19,
23
21, 23,
24
PWRD
26
26
I
Power down input. If high, conversions are inhibited and power consumption is significantly
reduced. Results from the previous conversion are maintained in the output shift register.
R/C
21
20
I
Read/convert input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the
hold state and starts a conversion. When EXT/INT is low, this also initiates the transmission of the
data results from the previous conversion. If EXT/INT is high, a rising edge on R/C with CS low, or
a falling edge on CS with R/C high, transmits a pulse on SYNC and initiates the transmission of
data from the previous conversion.
REF
7
4
I/O
Reference input/output. Outputs internal 4.096-V reference. Can also be driven by external system
reference. In both cases, bypass to ground with a 2.2-μF tantalum capacitor.
R1IN
1
29
I
Analog input. See Table 3 for input range connections.
R2IN
3
31
I
Analog input. See Table 3 for input range connections.
R3IN
4
32
I
Analog input. See Table 3 for input range connections.
SB/BTC
12
10
O
Select straight binary or binary 2's complement data output format. If high, data is output in a
straight binary format. If low, data is output in a binary 2's complement format.
SYNC
15
13
O
Sync output. This pin is used to supply a data synchronization pulse when the EXT level is high
and at least one external clock pulse has occured when not in the read mode. See the external
clock modes desciptions.
TAG
19
18
I
Tag input for use in the external clock mode. If EXT is high, digital data input from TAG is output
on DATA with a delay that is dependent on the external clock mode. See Figure 8 and Figure 9.
VANA
27
28
I
Analog supply input. Nominally +5 V. Connect directly to pin 20, and decouple to ground with
0.1-μF ceramic and 10-μF tantalum capacitors.
VDIG
28
27
I
Digital supply input. Connect directly to pin 19. Must be ≤ VANA.
6
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PARAMETER MEASUREMENT INFORMATION
CS
R/C
R/C
CS
tsu1
tsu1
tsu1
External
DATACLK
tsu1
External
DATACLK
CS Set Low, Discontinuous Ext DATACLK
R/C Set Low, Discontinuous Ext DATACLK
BUSY
CS
tsu2
tsu2
tsu3
1
External
DATACLK
R/C
2
CS Set Low, Discontinuous Ext DATACLK
tw1
PRODUCT PREVIEW
Figure 1. Critical Timing
tw1
R/C
td1
td1
tw2
tw2
BUSY
td2
td3
STATUS
Nth Conversion
Error
Correction
tconv
td4
td2
td11
td3
td11
Error
(N+1)th Conversion Correction
(N+1)th Accquisition
tconv
tacq
tc1
(N+2)th Accquisition
tacq
td4
Internal
1
DATACLK
TAG = 0
16
1
2
16
td6
td5
DATA
2
D15
D0
(N−1)th Conversion Data
CS, EXT/INT, and TAG are tied low
TAG = 0
D15
D0
TAG = 0
Nth Conversion Data
8 starts READ
Figure 2. Basic Conversion Timing - Internal DATACLK (Read Previous Data During Conversion)
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PARAMETER MEASUREMENT INFORMATION (continued)
tw1
tw1
R/C
td1
td1
tw2
tw2
BUSY
td2
td3
STATUS
Error
Correction
Nth Conversion
td2
td3
td11
td11
(N+1)th Accquisition
(N+1)th Conversion
tacq
tconv
(N+2)th Accquisition
tacq
tconv
tsu3
tsu1
Error
Correction
tsu3
tsu1
External
1
DATACLK
DATA TAG = 0
16
2
1
No more
data to
shift out
TAG = 0
1
16
Nth Data
PRODUCT PREVIEW
EXT/INT tied high, CS and TAG are tied low
TAG = 0
16
2
1
No more
data to
shift out
TAG = 0
16
(N+1)th Data
TAG = 0
tw1 + tsu1 starts READ
Figure 3. Basic Conversion Timing - External DATACLK
tw1
R/C
td1
tsu1
tw2
td1
BUSY
td2
td3
STATUS
td3
td11
Nth Conversion
Error
Correction
(N+1) th Accquisition
tsu3
tconv
tacq
tc2
tw3
External
DATACLK
tsu1
tw4
0
1
2
3
4
5
10
11
12
13
14
15
16
SYNC = 0
td8
T00
EXT/INT tied high, CS tied low
D14
D13
D12
D11
D10
D05
D04
D03
D02
D01
D00
Null
T00
Txx
T02
T03
T04
T05
T06
T11
T12
T13
T14
T15
T16
Null
T17
Tyy
th1
tsu3
TAG
td8
Nth Conversion Data
D15
DATA
T01
tw1 + tsu1 starts READ
Figure 4. Read After Conversion (Discontinuous External DATACLK)
8
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PARAMETER MEASUREMENT INFORMATION (continued)
tw1
R/C
td1
tw2
BUSY
td10
td3
td2
Error
Correction
Nth Conversion
STATUS
tsu3
tconv
tc2
tsu1
External
tw3
td11
tw4
1
0
DATACLK
2
3
4
5
10
11
12
13
14
15
16
SYNC = 0
Nth Conversion Data
D15
D14
D13
D12
D11
D10
D05
D04
D03
td8
D02
D01
D00
PRODUCT PREVIEW
td8
DATA
Rising DATACLK change DATA, tw1 + tsu1 Starts READ
TAG is not recommended for this mode. There is not enough
time to do so without violating td11.
EXT/INT tied high, CS and TAG tied low
Figure 5. Read During Conversion (Discontinuous External DATACLK)
tw1
R/C
td1
tsu1
td1
tsu1
tw2
BUSY
td2
td3
Error
Nth Conversion Correction
STATUS
td3
td11
(N+1)th Accquisition
tconv
tacq
tc2
tsu3
tsu1
External
DATACLK
0
1
tsu1
tw4
tw3
2
3
4
5
6
7
12
13
14
15
16
17
18
tc2
td7
SYNC =0
td8
Nth Conversion Data
D15
DATA
D13
D12
D11
D10
D05
D04
D03
D02
D01
D00
Null
T02
T03
T04
T05
T06
T11
T12
T13
T14
T15
T16
T17
T00
Txx
th1
tsu3
TAG
td8
D14
T00
EXT/INT tied high, CS tied low
T01
Tyy
tw1 + tsu1 starts READ
Figure 6. Read After Conversion With SYNC (Discontinuous External DATACLK)
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PARAMETER MEASUREMENT INFORMATION (continued)
tw1
R/C
td1
tw2
BUSY
td3
td10
td2
Error
Correction
Nth Conversion
STATUS
tsu3
tconv
tsu1
tsu1
External
tw3
tsu1
0
DATACLK
tc2
tw4
1
2
3
td11
4
5
6
7
12
13
14
15
16
17
18
td7
tc2
SYNC = 0
td8
PRODUCT PREVIEW
DATA
EXT/INT tied high, CS and TAG tied low
td8
Nth Conversion Data
D15
D14
D13
D12
D11
D10
D05
D04
D03
D02
D01
D00
tw1 + tsu1 Starts READ
TAG is not recommended for this mode. There is not enough
time to do so without violating td11.
Figure 7. Read During Conversion With SYNC (Discontinuous External DATACLK)
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Tag 18
Tag 17
Tag 16
PRODUCT PREVIEW
Tag 15
Tag 2
Tag 0
Tag 1
Bit 15 (MSB)
t c2
t su2
t su1
0
TAG
DATA
SYNC
BUSY
R/C
CS
External
DATACLK
t w1
t su2
t d1
t w3
t d7
1
t c2
t w4
2
t d8
3
Bit 14
4
Bit 1
17
18
Bit 0 (LSB)
Tag 0
t d9
Tag 1
Tag 19
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. Conversion and Read Timing with Continuous External DATACLK (EXT/INT Tied High) Read
After Conversions (Not Recommended)
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Tag 18
Tag 17
Tag 16
Tag 1
TAG
DATA
SYNC
t d1
BUSY
R/C
CS
External
DATACLK
t su2
t w3
t c2
t w1
t w4
t su1
t su1
Tag 0
t c2
t d8
t d10
PRODUCT PREVIEW
Bit 15 (MSB)
Bit 0 (LSB)
Tag 0
t d8
Tag 1
Tag 19
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 9. Conversion and Read Timing with Continous External DATACLK (EXT/INT Tied High) Read
Previous Conversion Results During Conversion (Not Recommended)
12
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POSITIVE INL DISTRIBUTION
NEGATIVE INL DISTRIBUTION
Figure 10.
Figure 11.
POSITIVE DNL DISTRIBUTION
NEGATIVE DNL DISTRIBUTION
Figure 12.
Figure 13.
AC
vs
FREE-AIR TEMPERATURE
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY
Figure 14.
Figure 15.
DC CODE
REFERENCE DRIFT
Figure 16.
Figure 17.
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PRODUCT PREVIEW
TYPICAL CHARACTERISTICS
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TYPICAL CHARACTERISTICS (continued)
INL
Figure 18.
DNL
PRODUCT PREVIEW
Figure 19.
FFT (100 kHz Input)
Figure 20.
FFT (10 kHz Input)
Figure 21.
14
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BASIC OPERATION
Two signals control conversion in the ADS8519: CS and R/C. These two signals are internally ORed together. To
start a conversion the chip must be selected, CS low, and the conversion signal must be active, R/C low. Either
signal can be brought low first. Conversion starts on the falling edge of the second signal. BUSY goes low when
conversion starts and returns high after the data from that conversion is shifted into the internal storage register.
Sampling begins when BUSY goes high.
To reduce the number of control pins CS can be tied low permanently. The R/C pin now controls conversion and
data reading exclusively. In the external clock mode this means that the ADS8519 will clock out data whenever
R/C is brought high and the external clock is active. In the internal clock mode data is clocked out every convert
cycle regardless of the states of CS and R/C. The ADS8519 provides a TAG input for cascading multiple
converters together.
READING DATA
Data can be clocked out with either the internally generated clock or with an external clock. The EXT/INT pin
controls this function. If external clock is used the TAG input can be used to daisy-chain multiple ADS8519 data
pins together.
INTERNAL DATACLK
In the internal clock mode data for the previous conversion is clocked out during each conversion period. The
internal data clock is synchronized to the internal conversion clock so that is does not interfere with the
conversion process.
The DATACLK pin becomes an output when EXT/INT is low. 16 clock pulses are generated at the beginning of
each conversion after timing t8 is satisfied, i.e. you can only read previous conversion result during conversion.
DATACLK returns to low when it is inactive. The 16 bits of serial data are shifted out the DATA pin synchronous
to this clock with each bit available on a rising and then a falling edge. DATA pin returns to the state of TAG pin
input sensed at the start of transmission.
EXTERNAL DATACLK
The external clock mode offers several ways to retrieve conversion results. However, since the external clock
cannot be synchronized to the internal conversion clock care must be taken to avoid corrupting the data.
When EXT/INT is set high, the R/C and CS signals control the read state. When the read state is initiated the
result from the previously completed conversion is shifted out the DATA pin synchronous to the external clock
that is connected to the DATACLK pin. Each bit is available on a falling and then a rising edge. The maximum
external clock speed of 28.5 MHz allows data shifted out quickly either at the beginning of conversion or the
beginning of sampling.
There are several modes of operation available when using an external clock. It is recommended that the
external clock run only while reading data. This is the discontinuous clock mode. Since the external clock is not
synchronized to the internal clock that controls conversion slight changes in the external clock can cause
conflicts that can corrupt the conversion process. Specifications with a continuously running external clock
cannot be guaranteed. It is especially important that the external clock does not run during the second half of the
conversion cycle (approximately the time period specified by td11, see timing table).
In the discontinuous clock mode data can be read during conversion or during sampling, with or without a SYNC
pulse. Data read during a conversion must meet the td11 timing specification. Data read during sampling must be
complete before starting a conversion.
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PRODUCT PREVIEW
The conversion result is available as soon as BUSY returns to high therefore, data always represents the
conversion previously completed even when it is read during a conversion. The ADS8519 outputs serial data in
either straight binary or binary two’s compliment format. The SB/BTC pin controls the format. Data is shifted out
MSB first. The first conversion immediately following a power-up will not produce a valid conversion result.
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Whether reading during sampling or during conversion a SYNC pulse is generated whenever at least one rising
edge of the external clock occurs while the part is not in the read state. In the discontinuous external clock with
SYNC mode a SYNC pulse follows the first rising edge after the read command. The data is shifted out after the
SYNC pulse. The first rising clock edge after the read command generates a SYNC pulse. The SYNC pulse can
be detected on the next falling edge and then the next rising edge. Successively, each bit can be read first on the
falling edge and then on the next rising edge. Thus 17 clock pulses after the read command are required to read
on the falling edge. 18 clock pulses are necessary to read on the rising edge.
Table 2. DATACLK Pulses
DATACLK PULSES REQUIRED
DESCRIPTION
WITH SYNC
WITHOUT SYNC
Read on falling edge of DATACLK
17
16
Read on rising edge of DATACLK
18
17
If the clock is entirely inactive when not in the read state no SYNC, pulse is generated. In this case the first rising
clock edge shifts out the MSB. The MSB can be read on the first falling edge or on the next rising edge. In this
discontinuous external clock mode with no SYNC 16 clocks are necessary to read the data on the falling edge
and 17 clocks for reading on the rising edge. Data always represents the conversion already completed.
PRODUCT PREVIEW
TAG FEATURE
The TAG feature allows the data from multiple ADS8519 converters to be read on a single serial line. The
converters are cascaded together using the DATA pins as outputs and the TAG pins as inputs as illustrated in
Figure 22. The DATA pin of the last converter drives the processor's serial data input. Data is then shifted
through each converter, synchronous to the externally supplied data clock, onto the serial data line. The internal
clock cannot be used for this configuration.
The preferred timing uses the discontinuous, external, data clock during the sampling period. Data must be read
during the sampling period because there is not sufficient time to read data from multiple converters during a
conversion period without violating the td11 constraint (see the EXTERNAL DATACLOCK section). The sampling
period must be sufficiently long to allow all data words to be read before starting a new conversion.
Note, in Figure 22, that a NULL bit separates the data word from each converter. The state of the DATA pin at
the end of a READ cycle reflects the state of the TAG pin at the start of the cycle. This is true in all READ
modes, including the internal clock mode. For example, when a single converter is used in the internal clock
mode the state of the TAG pin determines the state of the DATA pin after all 16 bits have shifted out. When
multiple converters are cascaded together this state forms the NULL bit that separates the words. Thus, with the
TAG pin of the first converter grounded as shown in Figure 22 the NULL bit becomes a zero between each data
word.
16
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ADS8519A
DATA
CS
R/C
DATACLK
TAG
SCLK
ADS 8519B
TAG(A)
DATA
CS
R/C
DATACLK
TAG
TAG(B)
GPIO
GPIO
SDI
Null
D
A00
Q
D
Q
D
Null
D
A15
Q
D
Q
D
B00
DATA (A)
A16
Q
D
Q
D
B15
Q
B16
DATA (B)
Q
DATACLK
R/C
(both A & B)
BUSY
(both A & B)
SYNC
(both A & B)
1
2
3
4
16
17
DATA ( A )
A15
A14
A13
A01
A00
DATA ( B )
B15
B14
B13
B01
B00
EXT/INT tied high, CS of both converter A and B, TAG input of converter A are tied low.
18
19
20
21
Null
TAG(A) = 0
A
Nth Conversion Data
Null A15
A14 A13
B
34
A01
35
36
A00
Null
A
TAG(A) = 0
.
Figure 22. Timing of TAG Feature With Single Conversion (Using External DATACLK)
ANALOG INPUTS
The ADS8519 has three analog input ranges as shown in Table 3. The offset specification is factory calibrated
with internal resistors. The gain specification is factory calibrated with 0.1%, 0.25-W, external resistors as shown
in Figure 25 and Figure 26. The external resistors can be omitted if a larger gain error is acceptable or if using
software calibration. The hardware trim circuitry shown in Figure 25 and Figure 26 can reduce the error to zero.
The analog input pins R1IN, R2IN, and R3IN have ±25-V overvoltage protection. The input signal must be
referenced to AGND1. This will minimized the ground loop problem typical to analog designs. The analog input
should be driven by a low impedance source. A typical driving circuit using OPA627 or OPA132 is shown in
Figure 26.
The ADS8519 can operate with its internal 4.096-V reference or an external reference. An external reference
connected to pin 6 (REF) bypasses the internal reference. The external reference must drive the 4-kΩ resistor
that separates pin 6 from the internal reference (see the illustration on page 1). The load will vary with the
difference between the internal and external reference voltages. The external reference voltage can vary from
3.9 V to 4.2 V. The internal reference will be approximately 4.096 V. The reference, whether internal or external,
is buffered internally with a buffer with its output on pin 5 (CAP).
The ADS8519 is factory tested with 2.2-μF capacitors connected to pins 5 and 6 (CAP and REF). Each capacitor
should be placed as close as possible to its pin. The capacitor on pin 6 band limits the internal reference noise. A
smaller capacitor can be used but it may degrade SNR and SINAD The capacitor on pin 5 stabilizes the
reference buffer and provides switching charge to the CDAC during conversion. Capacitors smaller than 1 μF
can cause the buffer to become unstable may not hold sufficient charge for the CDAC. The parts are tested to
specifications with 2.2 μF so larger capacitors are not necessary. The ESR (equivalent series resistance) of
these compensation capacitors is also critical. Keep the total ESR under 3 Ω. See the TYPICAL
CHARACTERISTICS section concerning how ESR affects performance.
Neither the internal reference nor the buffer should be used to drive an external load. Such loading can degrade
performance. Any load on the internal reference causes a voltage drop across the 4-kΩ resistor and will affect
gain. The internal buffer is capable of driving ±2-mA loads but any load can cause perturbations of the reference
at the CDAC, degrading performance. It should be pointed out that, unlike other competitor’s parts with similar
input structure, the ADS8519 does not require a second high speed amplifier used as buffer to isolate the CAP
pin from the signal dependent current in the R3IN pin but can tolerate it if one do exist.
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PRODUCT PREVIEW
External
DATACLK
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The external reference voltage can vary from 3.9 V to 4.2 V. The reference voltage determines the size of the
least significant bit (LSB). The larger reference voltages produce a larger LSB, which can improve SNR. Smaller
reference voltages can degrade SNR.
+15V
2.2 mF
22 pF
ADS8519
100 nF
R1IN
GND
2 kW
Pin 7
2 kW
Pin 2
Vin
22 pF
Pin3
AGND
Pin 1
−
OPA627
or OPA132
+
R2IN
Pin6
R3IN
Pin4
CAP
2.2 mF
GND
AGND2
2.2 mF
GND
100 nF
2.2 mF
PRODUCT PREVIEW
−15 V
GND
Figure 23. Typical Driving Circuitry (±10 V, No Trim)
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Table 3. Input Range Connections (see Figure 25 and Figure 26 for complete
information)
ANALOG
INPUT RANGE
CONNECT R1IN TO
CONNECT R2IN TO
CONNECT
R3 TO
IMPEDANCE
±10 V
VIN
AGND
CAP
8.88 kΩ
±10 V
AGND
VIN
CAP
8.88 kΩ
±5 V
VIN
VIN
CAP
6.08 kΩ
0 V to 8.192 V
AGND
AGND
VIN
5.95 kΩ
Table 4. Control Truth Table
Initiate conversion and
output data using external
clock
No actions
Power down
CS
R/C
BUSY
EXT/INT
DATACLK
PWRD
SB/BTC
OPERATION
1>0
0
1
0
Output
0
x
0
1>0
1
0
Output
0
x
Initiates conversion n. Data from conversion n - 1
clocked out on DATA synchronized to 16 clock
pulses output on DATACLK.
1>0
0
1
1
Input
0
x
Initiates conversion n.
0
1>0
1
1
Input
0
x
Initiates conversion n.
1>0
1
1
1
Input
x
x
Outputs data with or without SYNC pulse. See
section Reading Data.
1>0
1
0
1
Input
0
x
0
0>1
0
1
Input
0
x
Outputs data with or without SYNC pulse. See
section Reading Data.
0
0
0>1
x
x
0
x
This is an acceptable condition.
x
x
x
x
x
0
x
Analog circuitry powered. Conversion can
proceed..
x
x
x
x
x
1
x
Analog circuitry disabled. Data from previous
conversion maintained in output registers.
x
x
x
x
x
x
0
Serial data is output in binary 2s complement
format.
x
x
x
x
x
x
1
Serial data is output in straight binary format.
Selecting output format
PRODUCT PREVIEW
SPECIFIC FUNCTION
Initiate conversion and
output data using internal
clock
Table 5. Output Codes and Ideal Input Voltages
DIGITAL OUTPUT
DESCRIPTION
BINARY 2's
COMPLEMENTS
(SB/BTC LOW)
ANALOG INPUT
STRAIGHT
BINARY
(SB/BTC HIGH)
BINARY CODE
HEX CODE
BINARY CODE
HEX CODE
8.191875 V
0111 1111 1111 1111
7FFF
1111 1111 1111 1111
FFFF
4.096 V
0000 0000 0000 0000
0000
1000 0000 0000 0000
8000
153 μV
4.095975 V
1111 1111 1111 1111
FFFF
0111 1111 1111 1111
7FFF
-5 V
0V
1000 0000 0000 0000
8000
0000 0000 0000 0000
0000
Full-scale range
±10
±5
0 V to 8.192 V
Least significant
bit (LSB)
305 μV
153 μV
125 μV
Full scale
(FS - 1LSB)
9.999695 V
4.999847 V
Midscale
0V
0V
One LSB below
midscale
-305 μV
-Full scale
-10 V
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1
±10 V
2
+5 V
2.2 µF +
175 kΩ
20 kΩ
4
+
Gain
2.2 µF
30 kΩ
3
5
1
±10 V
VIN
2
AGND1
2.2 µF +
REF
3
4
CAP
2.2 µF
AGND1
REF
CAP
+
5
AGND2
(a) ±10 V With Hardware Trim
VIN
AGND2
(b) ±10 V Without Hardware Trim
Note: Use 1% metal film resistors.
Figure 24. Gain Adjust Trim
PRODUCT PREVIEW
Input Range
With Trim
(Adjust Gain)
Without Trim
0 V − 8.192 V
R1IN
AGND1
AGND1
R2IN
R2IN
R3IN
VIN
2.2 µF
R1IN
CAP
+
2.2 µF
+
REF
R3IN
VIN
2.2 µF
+
CAP
+5V
576 kΩ
50 kΩ
2.2 µF
AGND2
+
REF
AGND2
Figure 25. Offset/Gain Circuits for Unipolar Input Ranges
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With Trim
(Adjust Gain)
Without Trim
VIN
R1IN
±10 V
+
2.2 µF
AGND1
AGND1
R2IN
R2IN
R3IN
R3IN
+5 V
CAP
2.2 µF
+
R1IN
VIN
2.2 µF
576 kΩ
+
2.2 µF
+
CAP
REF
REF
50 kΩ
AGND2
VIN
AGND2
R1IN
R1IN
AGND1
AGND1
VIN
R2IN
±5V
R3IN
+
R2IN
2.2 µF
+5 V
CAP
PRODUCT PREVIEW
Input Range
R3IN
+
CAP
576 kΩ
2.2 µF
2.2 µF
+
50 kΩ
REF
REF
+
AGND2
2.2 µF
AGND2
Figure 26. Offset/Gain Circuits for Bipolar Input Ranges
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PACKAGE OPTION ADDENDUM
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29-Jun-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
ADS8519IBDB
PREVIEW
SSOP
DB
28
50
TBD
Call TI
Call TI
ADS8519IBDBR
PREVIEW
SSOP
DB
28
2000
TBD
Call TI
Call TI
ADS8519IDB
PREVIEW
SSOP
DB
28
50
TBD
Call TI
Call TI
ADS8519IDBR
PREVIEW
SSOP
DB
28
2000
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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representatives against any damages arising out of the use of TI products in such safety-critical applications.
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Telephony
www.ti.com/telephony
Low Power
Wireless
www.ti.com/lpw
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
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