EMD5DXV6T1, EMD5DXV6T5 Preferred Devices Product Preview Dual Bias Resistor Transistors http://onsemi.com NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network (3) R1 The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base−emitter resistor. These digital transistors are designed to replace a single device and its external resistor bias network. The BRT eliminates these individual components by integrating them into a single device. In the EMD5DXV6T1 series, two complementary BRT devices are housed in the SOT−563 package which is ideal for low power surface mount applications where board space is at a premium. • • • • • (2) R2 Q1 Q2 R2 R1 (4) (5) 6 (6) 54 1 Simplifies Circuit Design Reduces Board Space Reduces Component Count Available in 8 mm, 7 inch Tape and Reel Lead Free Solder Plating (1) 23 SOT−563 CASE 463A PLASTIC MARKING DIAGRAM U5 D U5 = Specific Device Code D = Date Code ORDERING INFORMATION Device This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2003 July, 2003 − Rev. P1 1 Package Shipping EMD5DXV6T1 SOT−563 4 mm pitch 4000/Tape & Reel EMD5DXV6T5 SOT−563 2 mm pitch 8000/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Publication Order Number: EMD5DXV6/D EMD5DXV6T1, EMD5DXV6T5 MAXIMUM RATINGS (TA = 25°C unless otherwise noted, common for Q1 and Q2, − minus sign for Q1 (PNP) omitted) Rating Symbol Value Unit Collector-Base Voltage VCBO 50 Vdc Collector-Emitter Voltage VCEO 50 Vdc IC 100 mAdc Symbol Max Unit PD 357 (Note 1) 2.9 (Note 1) mW Collector Current THERMAL CHARACTERISTICS Characteristic (One Junction Heated) Total Device Dissipation TA = 25°C Derate above 25°C Thermal Resistance Junction-to-Ambient Characteristic (Both Junctions Heated) Total Device Dissipation TA = 25°C RJA 350 (Note 1) °C/W Symbol Max Unit PD 500 (Note 1) 4.0 (Note 1) mW Derate above 25°C Thermal Resistance Junction-to-Ambient Junction and Storage Temperature 1. FR−4 @ Minimum Pad http://onsemi.com 2 mW/°C mW/°C RJA 250 (Note 1) °C/W TJ, Tstg −55 to +150 °C EMD5DXV6T1, EMD5DXV6T5 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Min Typ Max Unit Collector-Base Cutoff Current (VCB = 50 V, IE = 0) ICBO − − 100 nAdc Collector-Emitter Cutoff Current (VCB = 50 V, IB = 0) ICEO − − 500 nAdc Emitter-Base Cutoff Current (VEB = 6.0, IC = 5.0 mA) IEBO − − 1.0 mAdc Collector-Base Breakdown Voltage (IC = 10 A, IE = 0) V(BR)CBO 50 − − Vdc Collector-Emitter Breakdown Voltage (IC = 2.0 mA, IB = 0) V(BR)CEO 50 − − Vdc hFE 20 35 − VCE(SAT) − − 0.25 Vdc Characteristic Q1 TRANSISTOR: PNP OFF CHARACTERISTICS ON CHARACTERISTICS DC Current Gain (VCE = 10 V, IC = 5.0 mA) Collector−Emitter Saturation Voltage (IC = 10 mA, IB = 0.3 mA) Output Voltage (on) (VCC = 5.0 V, VB = 2.5 V, RL = 1.0 k) VOL − − 0.2 Vdc Output Voltage (off) (VCC = 5.0 V, VB = 0.5 V, RL = 1.0 k) VOH 4.9 − − Vdc Input Resistor R1 3.3 4.7 6.1 k Resistor Ratio R1/R2 0.38 0.47 0.56 Collector-Base Cutoff Current (VCB = 50 V, IE = 0) ICBO − − 100 nAdc Collector-Emitter Cutoff Current (VCB = 50 V, IB = 0) ICEO − − 500 nAdc Emitter-Base Cutoff Current (VEB = 6.0, IC = 5.0 mA) IEBO − − 0.1 mAdc Collector-Base Breakdown Voltage (IC = 10 A, IE = 0) V(BR)CBO 50 − − Vdc Collector-Emitter Breakdown Voltage (IC = 2.0 mA, IB = 0) V(BR)CEO 50 − − Vdc hFE 80 140 − VCE(SAT) − − 0.25 Vdc Output Voltage (on) (VCC = 5.0 V, VB = 2.5 V, RL = 1.0 k) VOL − − 0.2 Vdc Output Voltage (off) (VCC = 5.0 V, VB = 0.5 V, RL = 1.0 k) VOH 4.9 − − Vdc Input Resistor R1 33 47 61 k Resistor Ratio R1/R2 0.8 1.0 1.2 Q2 TRANSISTOR: NPN OFF CHARACTERISTICS ON CHARACTERISTICS DC Current Gain (VCE = 10 V, IC = 5.0 mA) Collector−Emitter Saturation Voltage (IC = 10 mA, IB = 0.3 mA) http://onsemi.com 3 EMD5DXV6T1, EMD5DXV6T5 PD , POWER DISSIPATION (MILLIWATTS) 250 200 150 100 50 0 −50 RJA = 833°C/W 0 50 100 TA, AMBIENT TEMPERATURE (°C) Figure 1. Derating Curve http://onsemi.com 4 150 EMD5DXV6T1, EMD5DXV6T5 1000 1 VCE = 10 V IC/IB = 10 TA=75°C 0.1 0.01 hFE, DC CURRENT GAIN VCE(sat) , MAXIMUM COLLECTOR VOLTAGE (VOLTS) TYPICAL ELECTRICAL CHARACTERISTICS — EMD5DXV6T1 PNP TRANSISTOR 25°C −25°C 0 10 20 30 50 40 100 1 60 1 10 100 IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA) Figure 2. VCE(sat) versus IC Figure 3. DC Current Gain 1000 100 IC, COLLECTOR CURRENT (mA) f = 1 MHz IE = 0 mA TA = 25°C 10 Cob , CAPACITANCE (pF) 25°C −25°C 10 12 8 6 4 SERIES 1 2 0 TA=75°C 0 5 10 20 30 15 25 35 VR, REVERSE BIAS VOLTAGE (VOLTS) 40 1 VO = 5 V 0.1 0.01 45 75°C 10 TA=−25°C 25°C 0 Figure 4. Output Capacitance 2 4 6 8 Vin, INPUT VOLTAGE (VOLTS) 10 Figure 5. Output Current versus Input Voltage http://onsemi.com 5 12 EMD5DXV6T1, EMD5DXV6T5 10 1000 VCE = 10 V IC/IB = 10 hFE, DC CURRENT GAIN VCE(sat) , MAXIMUM COLLECTOR VOLTAGE (VOLTS) TYPICAL ELECTRICAL CHARACTERISTICS — EMD5DXV6T1 NPN TRANSISTOR 1 25°C TA=−25°C 75°C 0.1 0.01 0 TA=75°C 25°C −25°C 100 10 50 20 40 IC, COLLECTOR CURRENT (mA) 10 IC, COLLECTOR CURRENT (mA) 1 Figure 6. VCE(sat) versus IC 1 100 IC, COLLECTOR CURRENT (mA) 0.4 0.2 0 0 25°C 75°C 0.6 TA=−25°C 10 1 0.1 0.01 0.001 50 10 20 30 40 VR, REVERSE BIAS VOLTAGE (VOLTS) VO = 5 V 0 2 4 6 Vin, INPUT VOLTAGE (VOLTS) 100 VO = 0.2 V TA=−25°C 10 25°C 75°C 1 0.1 0 10 8 Figure 9. Output Current versus Input Voltage Figure 8. Output Capacitance V in , INPUT VOLTAGE (VOLTS) Cob , CAPACITANCE (pF) Figure 7. DC Current Gain f = 1 MHz IE = 0 mA TA = 25°C 0.8 100 20 30 40 50 IC, COLLECTOR CURRENT (mA) Figure 10. Input Voltage versus Output Current http://onsemi.com 6 10 EMD5DXV6T1, EMD5DXV6T5 INFORMATION FOR USING THE SOT−563 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.3 0.0118 0.45 0.0177 1.35 0.0531 1.0 0.0394 0.5 0.5 0.0197 0.0197 SCALE 20:1 mm inches SOT−563 SOT−563 POWER DISSIPATION SOLDERING PRECAUTIONS The power dissipation of the SOT−563 is a function of The melting temperature of solder is higher than the the pad size. This can vary from the minimum pad size for rated temperature of the device. When the entire device is soldering to a pad size given for maximum power dissipaheated to a high temperature, failure to complete soldering tion. Power dissipation for a surface mount device is deterwithin a short time could result in device failure. Theremined by TJ(max), the maximum rated junction temperature fore, the following items should always be observed in orof the die, RJA, the thermal resistance from the device der to minimize the thermal stress to which the devices are junction to ambient, and the operating temperature, TA. Ussubjected. ing the values provided on the data sheet for the SOT−563 package, PD can be calculated as follows: • Always preheat the device. • The delta temperature between the preheat and solderTJ(max) − TA ing should be 100°C or less.* PD = RJA • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temThe values for the equation are found in the maximum perature ratings as shown on the data sheet. When ratings table on the data sheet. Substituting these values using infrared heating with the reflow soldering methinto the equation for an ambient temperature TA of 25°C, od, the difference shall be a maximum of 10°C. one can calculate the power dissipation of the device which in this case is 150 milliwatts. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. 150°C − 25°C PD = = 150 milliwatts • When shifting from preheating to soldering, the maxi833°C/W mum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should The 833°C/W for the SOT−563 package assumes the use be allowed to cool naturally for at least three minutes. of the recommended footprint on a glass epoxy printed cirGradual cooling should be used as the use of forced cuit board to achieve a power dissipation of 150 milliwatts. cooling will increase the temperature gradient and There are other alternatives to achieving higher power disresult in latent failure due to mechanical stress. sipation from the SOT−563 package. Another alternative • Mechanical stress or shock should not be applied durwould be to use a ceramic substrate or an aluminum core ing cooling. board such as Thermal Clad . Using a board material such as Thermal Clad, an aluminum core board, the power dis* Soldering a device without preheating can cause excessipation can be doubled using the same footprint. sive thermal shock and stress which can result in damage to the device. http://onsemi.com 7 EMD5DXV6T1, EMD5DXV6T5 PACKAGE DIMENSIONS SOT−563, 6 LEAD CASE 463A−01 ISSUE O A −X− 5 6 1 2 C K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4 B −Y− 3 D G STYLE 1: PIN 1. 2. 3. 4. 5. 6. J 5 PL 6 0.08 (0.003) EMITTER 1 BASE 1 COLLECTOR 2 EMITTER 2 BASE 2 COLLECTOR 1 DIM A B C D G J K S S M X Y STYLE 2: PIN 1. 2. 3. 4. 5. 6. STYLE 3: PIN 1. 2. 3. 4. 5. 6. EMITTER 1 EMITTER2 BASE 2 COLLECTOR 2 BASE 1 COLLECTOR 1 CATHODE 1 CATHODE 1 ANODE/ANODE 2 CATHODE 2 CATHODE 2 ANODE/ANODE 1 STYLE 4: PIN 1. 2. 3. 4. 5. 6. MILLIMETERS MIN MAX 1.50 1.70 1.10 1.30 0.50 0.60 0.17 0.27 0.50 BSC 0.08 0.18 0.10 0.30 1.50 1.70 INCHES MIN MAX 0.059 0.067 0.043 0.051 0.020 0.024 0.007 0.011 0.020 BSC 0.003 0.007 0.004 0.012 0.059 0.067 COLLECTOR COLLECTOR BASE EMITTER COLLECTOR COLLECTOR Thermal Clad is a trademark of the Bergquist Company. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800−282−9855 Toll Free USA/Canada http://onsemi.com 8 EMD5DXV6/D