TI CV215-10PAGG4 512 x 18, 1024 x 18, 2048 x 18, 4096 x 18 dsp-sync first-in, first-out memory Datasheet

SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
D
D
D
D
D
D
D
D
D
512 × 18-Bit Organization Array (SN74V215)
1024 × 18-Bit Organization Array
(SN74V225)
2048 × 18-Bit Organization Array
(SN74V235)
4096 × 18-Bit Organization Array
(SN74V245)
7.5-ns Read/Write Cycle Time
3.3-V VCC, 5-V Input Tolerant
First-Word or Standard Fall-Through
Timing
Single or Double Register-Buffered Empty
and Full Flags
Easily Expandable in Depth and Width
D
D
D
D
D
D
D
D
Asynchronous or Coincident Read and
Write Clocks
Asynchronous or Synchronous
Programmable Almost-Empty and
Almost-Full Flags With Default Settings
Half-Full Flag Capability
Output Enable Puts Output Data Bus in
High-Impedance State
High-Performance Submicron CMOS
Technology
Packaged in 64-Pin Thin Quad Flat Package
DSP and Microprocessor Interface Control
Logic
Provide a DSP Glueless Interface to Texas
Instruments TMS320 DSPs
description
The SN74V215, SN74V225, SN74V235, and SN74V245 are very high-speed, low-power CMOS clocked first-in
first-out (FIFO) memories. They support clock frequencies up to 133 MHz and have read-access times as fast
as 5 ns. These DSP-Sync FIFO memories feature read and write controls for use in applications such as
DSP-to-processor communication, DSP-to-analog front end (AFE) buffering, network, video, and data
communications.
These are synchronous FIFOs, which means each port employs a synchronous interface. All data transfers
through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals.
The continuous clocks for each port are independent of one another and can be asynchronous or coincident.
The enables for each port are arranged to provide a simple interface between DSPs, microprocessors, and/or
buses controlled by a synchronous interface. An output-enable (OE) input controls the 3-state output.
The synchronous FIFOs have two fixed flags, empty flag/output ready (EF/OR) and full flag/input ready (FF/IR),
and two programmable flags, almost-empty (PAE) and almost-full (PAF). The offset loading of the
programmable flags is controlled by a simple state machine, and is initiated by asserting the load pin (LD). A
half-full flag (HF) is available when the FIFO is used in a single-device configuration.
Two timing modes of operation are possible with these devices: first-word fall-through (FWFT) mode and
standard mode.
In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three
transitions of the RCLK signal. A read enable (REN) does not have to be asserted for accessing the first word.
In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a
specific read operation is performed. A read operation, which consists of activating REN and enabling a rising
RCLK edge, shifts the word from internal memory to the data output lines.
These devices are depth expandable, using a daisy-chain technique or FWFT mode. The XI and XO pins are
used to expand the FIFOs. In depth-expansion configuration, first load (FL) is grounded on the first device and
set to high for all other devices in the daisy chain.
The SN74V215, SN74V225, SN74V235, and SN74V245 are characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DSP-SYNC and TMS320 are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
D16
D17
GND
RCLK
REN
LD
OE
RS
VCC
GND
EF/OR
Q17
Q16
GND
Q15
VCC
PAG PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PAE
FL
WCLK
WEN
WXI
VCC
PAF
RXI
FF/IR
WXO/HF
RXO
Q0
Q1
GND
Q2
Q3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
2
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Q14
Q13
GND
Q12
Q11
VCC
Q10
Q9
GND
Q8
Q7
Q6
Q5
GND
Q4
VCC
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
functional block diagram
D0–D17
LD
59
WCLK
WEN
19
Input
Register
20
Offset
Register
Write-Control
Logic
25
23
54
17
26
Flag
Logic
RAM ARRAY
512 × 18, 1024 × 18,
2048 × 18, 4096 × 18
Write
Pointer
FL
WXI
(HF)/WXO
RXI
RXO
RS
18
21
26
24
27
Expansion
Logic
57
Reset
Logic
FF/IR
PAF
EF/OR
PAE
HF/(WXO)
Read
Pointer
Read-Control
Logic
Output
Register
58
61
RCLK
OE
60
REN
Q0–Q17
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512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
Terminal Functions
TERMINAL
DESCRIPTION
NO.
D0–D17
1–16, 63,
64
I
Data inputs. Data inputs for an 18-bit bus.
EF/OR
54
O
Memory-empty/valid-data-available flag. In the standard mode, the EF function is selected. EF indicates
whether the FIFO memory is empty. In FWFT mode, the OR function is selected. OR indicates whether
there is valid data available at the outputs.
FF/IR
25
O
Memory-full/space-available flag. In the standard mode, the FF function is selected. FF indicates whether
the FIFO memory is full. In the FWFT mode, the IR function is selected. IR indicates whether there is space
available for writing to the FIFO memory.
I
Mode selection. In the single-device or width-expansion configuration, FL, together with WXI and RXI,
determines if the mode is standard mode or first-word fall-through (FWFT) mode, as well as whether the
PAE/PAF flags are synchronous or asynchronous (see Table 4). In the daisy-chain depth-expansion
configuration, FL is grounded on the first device (first-load device) and set to high for all other devices in
the daisy chain.
FL
GND
18
30, 35, 40,
46, 51, 55,
62
Ground
LD
59
I
Read/write control. When LD is low, data on the inputs D0–D11 is written to the offset and depth registers
on the low-to-high transition of the WCLK, when WEN is low. When LD is low, data on the outputs Q0–Q11
is read from the offset and depth registers on the low-to-high transition of RCLK when REN is low.
OE
58
I
Output enable. When OE is low, the data output bus is active. If OE is high, the output data bus is in the
high-impedance state.
PAE
17
O
Programable almost-empty flag. When PAE is low, the FIFO is almost empty, based on the offset
programmed into the FIFO. The default offset at reset is 63 from empty for SN74V215, and 127 from empty
for SN74V225, SN74V235, and SN74V245.
PAF
23
O
Programable almost-full flag. When PAF is low, the FIFO is almost full, based on the offset programmed
into the FIFO. The default offset at reset is 63 from full for SN74V215, and 127 from full for SN74V225,
SN74V235, and SN74V245.
28, 29, 31,
32, 34,
36–39, 41,
42, 44, 45,
47, 48, 50,
52, 53
O
Data outputs. Data outputs for an 18-bit bus.
RCLK
61
I
Read clock. When REN is low, data is read from the FIFO on a low-to-high transition of RCLK, if the FIFO
is not empty.
REN
60
I
Read enable. When REN is low, data is read from the FIFO on every low-to-high transition of RCLK. When
REN is high, the output register holds the previous data. Data is not read from the FIFO if EF is low.
RS
57
I
Reset. When RS is set low, internal read and write pointers are set to the first location of the RAM array,
FF and PAF go high, and PAE and EF go low. A reset is required before an initial write after power up.
Q0–Q17
RXI
24
I
Read expansion. In the single-device or width-expansion configuration, RXI, together with FL and WXI,
determines if the mode is standard mode or FWFT mode, as well as whether the PAE/PAF flags are
synchronous or asynchronous (see Table 4). In the daisy-chain depth-expansion configuration, RXI is
connected to RXO (read expansion out) of the previous device.
RXO
27
O
Last-location-read flag. In the depth-expansion configuration, a pulse is sent from RXO to RXI of the next
device when the last location in the FIFO is read.
VCC
22, 33, 43,
49, 56
WCLK
4
I/O
NAME
19
Supply voltage. +3.3-V power-supply pins.
I
Write clock. When WEN is low, data is written into the FIFO on a low-to-high transition of WCLK if the FIFO
is not full.
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512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
Terminal Functions (Continued)
TERMINAL
NAME
WEN
NO.
I/O
DESCRIPTION
I
Write enable. When WEN is low, data is written into the FIFO on every low-to-high transition of WCLK.
When WEN is high, the FIFO holds the previous data. Data is not written into the FIFO if FF is low.
20
WXI
21
I
Width expansion. In the single-device or width-expansion configuration, WXI, together with FL and RXI,
determines if the mode is standard mode or FWFT mode, as well as whether the PAE/PAF flags are
synchronous or asynchronous (see Table 4). In the daisy-chain depth-expansion configuration, WXI is
connected to WXO (write expansion out) of the previous device.
WXO/HF
26
O
Half-full flag. In the single-device or width-expansion configuration, the device is more than half full when
HF is low. In the depth-expansion configuration, a pulse is sent from WXO to WXI of the next device when
the last location in the FIFO is written.
detailed description
INPUTS:
DATA IN (D0–D17)
Data inputs for 18-bit-wide data.
CONTROLS:
RESET (RS)
Reset is accomplished when RS is taken low. During reset, both internal read and write pointers are set to the
first location. A reset is required after power up before a write operation can take place. The half-full flag (HF)
and programmable almost-full flag (PAF) is reset to high after tRSF. The programmable almost-empty flag (PAE)
is reset to low after tRSF. The full flag (FF) resets to high. The empty flag (EF) resets to low in standard mode,
but resets to high in FWFT mode. During reset, the output register is initialized to all zeros, and the offset
registers are initialized to their default values.
WRITE CLOCK (WCLK)
A write cycle is initiated on the low-to-high transition of WCLK. Data setup and hold times must be met with
respect to the low-to-high transition of WCLK.
The write and read clocks can be asynchronous or coincident.
WRITE ENABLE (WEN)
When WEN is low, data can be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the
device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation.
When WEN is high, no new data is written in the RAM array on each WCLK cycle.
To prevent data overflow in the standard mode, FF goes low, inhibiting further write operations. Upon completion
of a valid read cycle, FF goes high, allowing a write to occur. The FF flag is updated on the rising edge of WCLK.
To prevent data overflow in the FWFT mode, IR goes high, inhibiting further write operations. Upon completion
of a valid read cycle, IR goes low, allowing a write to occur. The IR flag is updated on the rising edge of WCLK.
WEN is ignored when the FIFO is full in either FWFT or standard mode.
READ CLOCK (RCLK)
Data can be read on the outputs on the low-to-high transition of RCLK when OE is low.
The write and read clocks can be asynchronous or coincident.
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512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
detailed description (continued)
READ ENABLE (REN)
When REN is low, data is loaded from the RAM array into the output register on the rising edge of every RCLK
cycle if the device is not empty.
When REN is high, the output register holds the previous data and no new data is loaded into the output register.
Data outputs Q0–Qn maintain the previous data value.
In the standard mode, every word accessed at Qn, including the first word written to an empty FIFO, must be
requested using REN. When the last word has been read from the FIFO, the empty flag (EF) goes low, inhibiting
further read operations. REN is ignored when the FIFO is empty. After a write is performed, EF goes high,
allowing a read to occur. The EF flag is updated on the rising edge of RCLK.
In the FWFT mode, the first word written to an empty FIFO automatically goes to the outputs Qn, on the third
valid low-to-high transition of RCLK + tSKEW after the first write. REN need not be asserted low. To access all
other words, a read must be executed using REN. The RCLK low-to-high transition after the last word has been
read from the FIFO, output ready (OR) goes high with a true read (RCLK with REN low), inhibiting further read
operations. REN is ignored when the FIFO is empty.
OUTPUT ENABLE (OE)
When OE is low, the parallel output buffers transmit data from the output register. When OE is high, the Q-output
data bus is in the high-impedance state.
LOAD (LD)
The SN74V215, SN74V225, SN74V235, and SN74V245 devices contain two 12-bit offset registers with data
on the inputs, or read on the outputs. When LD is low and WEN is low, data on the inputs D0–D11 is written into
the empty offset register on the first low-to-high transition of the write clock (WCLK). When LD and WEN are
held low, data is written into the full offset register on the second low-to-high transition of WCLK (see Tables 1
and 2). The third transition of WCLK again writes to the empty-offset register.
However, writing to all offset registers need not occur at one time. One or two offset registers can be written and
then, by bringing LD high, the FIFO is returned to normal read/write operation. When LD is low, and WEN is low,
the next offset register in sequence is written.
Table 1. Writing to Offset Registers
SELECTION†
LD
WEN
WCLK
L
L
↑
Writing to offset registers:
Empty offset
Full offset
L
H
↑
No operation
H
L
↑
Write into FIFO
H
H
↑
No operation
† The same selection sequence applies to reading from the
registers. REN is enabled and read is performed on the
low-to-high transition of RCLK.
6
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detailed description (continued)
Table 2. Offset Register Location and Default Values†
17
12
11
0
Empty Offset Register
Default Value
003FH (74V215):
007FH (74V225/74V235/74V245)
Not used
17
12
11
0
Full Offset Register
Not used
Default Value
003FH (74V215):
007FH (74V225/74V235/74V245)
† Any bits of the offset register not being programmed should be set to zero.
When LD is low and WEN is high, the WCLK input is disabled; then, a signal at this input can neither increment
the write-offset-register pointer, nor execute a write.
The contents of the offset registers can be read on the output lines when LD is low and REN is low; then, data
can be read on the low-to-high transition of RCLK. Reading the control registers employs a dedicated
read-offset-register pointer. (The read and write pointers operate independently.) Offset register content can be
read out in the standard mode only. It is inhibited in the FWFT mode.
A read from and a write to the offset registers should not be performed simultaneously.
FIRST LOAD (FL)
For the single-device mode, see Table 5 for additional information. In the daisy-chain depth-expansion
configuration, FL is grounded to indicate it is the first device loaded and is set high for all other devices in the
daisy chain (see Operating Configurations for further details).
WRITE EXPANSION INPUT (WXI)
This is a dual-purpose pin. For single-device mode, see Table 5 for additional information. WXI is connected
to write expansion out (WXO) of the previous device in the daisy-chain depth-expansion mode.
READ EXPANSION INPUT (RXI)
This is a dual-purpose pin. For single-device mode, see Table 5 for additional information. RXI is connected to
read expansion out (RXO) of the previous device in the daisy-chain depth-expansion mode.
OUTPUTS:
FULL FLAG/INPUT READY (FF/IR)
This is a dual-purpose pin. In FWFT mode, the input ready (IR) function is selected. IR goes low when memory
space is available for writing data. When there is no free space left, IR goes high, inhibiting further write
operations.
In standard mode, the FF function is selected. When the FIFO is full, FF goes low, inhibiting further write
operations. When FF is high, the FIFO is not full. If no reads are performed after a reset, FF goes low after
D writes to the FIFO. D = 512 for the SN74V215, 1024 for the SN74V225, 2048 for the SN74V235, and 4096
for the SN74V245.
IR goes high after D writes to the FIFO. D = 513 for the SN74V215, 1025 for the SN74V225, 2049 for the
SN74V235, and 4097 for the SN74V245. The additional word in FWFT mode is due to the capacity of the
memory plus output register.
FF/IR is synchronous and updated on the rising edge of WCLK.
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SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
detailed description (continued)
EMPTY FLAG/OUTPUT READY (EF/OR)
This is a dual-purpose pin. In FWFT mode, the OR function is selected. OR goes low at the same time the first
word written to an empty FIFO appears valid on the outputs. OR stays low after the RCLK low-to-high transition
that shifts the last word from the FIFO memory to the outputs. OR goes high only with a true read (RCLK with
REN low). The previous data stays at the outputs, indicating that the last word was read. Further data reads
are inhibited until OR goes low again.
In the standard mode, the EF function is selected. When the FIFO is empty, EF goes low, inhibiting further read
operations. When EF is high, the FIFO is not empty.
EF/OR is synchronous and updated on the rising edge of RCLK.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
PAF goes low when the FIFO reaches the almost-full condition. In FWFT mode, if no reads are performed, PAF
goes low after 513 – m for the SN74V215, 1025 for the SN74V225, 2049 for the SN74V235, and 4097 for the
SN74V245. Default values for m are in Table 3 and Table 4.
In standard mode, if no reads are performed after reset (RS), PAF goes low after (512 – m) writes for the
SN74V215, (1024 – m) writes for the SN74V225, (2048 – m) writes for the SN74V235, and (4096 – m) writes
for the SN74V245. The offset m is defined in the full offset register.
If asynchronous PAF configuration is selected, PAF is asserted low on the low-to-high transition of WCLK. PAF
is reset to high on the low-to-high transition of RCLK. If synchronous PAF configuration is selected (see Table 5),
PAF is updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
PAE goes low when the FIFO reaches the almost-empty condition. In FWFT mode, PAE goes low when there
are n + 1 words, or fewer, in the FIFO. In standard mode, PAE goes low when there are n words or fewer in the
FIFO. The offset n is defined as the empty offset. The default values for n are noted in Table 3 and Table 4.
If there is no empty offset specified, PAE is low when the device is 63 away from completely empty for
SN74V215, and 127 away from completely empty for SN74V225, SN74V235, and SN74V245.
If asynchronous PAE configuration is selected, PAE is asserted low on the low-to-high transition of the read clock
(RCLK). PAE is reset to high on the low-to-high transition of the write clock (WCLK). If synchronous PAE
configuration is selected (see Table 5), PAE is updated on the rising edge of RCLK.
WRITE EXPANSION OUT/HALF-FULL FLAG (WXO/HF)
This is a dual-purpose output. In the single-device and width-expansion mode, when write expansion in (WXI)
and/or read expansion in (RXI) are grounded, this output acts as an indication of a half-full memory.
After one-half of the memory is filled, and at the low-to-high transition of the next write cycle, the half-full flag
(HF) goes low and remains set until the difference between the write pointer and read pointer is less than or
equal to one-half of the total memory of the device. HF is then reset to high by the low-to-high transition of the
read clock (RCLK). HF is asynchronous.
In the daisy-chain depth-expansion mode, WXI is connected to WXO of the previous device. This output acts
as a signal to the next device in the daisy chain by providing a pulse when the previous device writes to the last
location of memory.
READ EXPANSION OUT (RXO)
In the daisy-chain depth-expansion configuration, read expansion in (RXI) is connected to read expansion out
(RXO) of the previous device. This output acts as a signal to the next device in the daisy chain by providing a
pulse when the previous device reads from the last location of memory.
8
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detailed description (continued)
DATA OUTPUTS (Q0–Q17)
Q0–Q17 are data outputs for 18-bit-wide data.
functional description
TIMING MODES:
STANDARD vs FIRST-WORD FALL-THROUGH (FWFT) MODE
The SN74V215, SN74V225, SN74V235, and SN74V245 support two different timing modes. The selection of
the mode of operation is determined during configuration at reset (RS). During an RS operation, the first load
(FL), read expansion input ( RXI), and write-expansion input (WXI) pins are used to select the timing mode as
shown in the truth table (see Table 5). In standard mode, the first word written to an empty FIFO does not appear
on the data output lines unless a specific read operation is performed. A read operation, which consists of
activating read enable (REN) and enabling a rising read clock (RCLK) edge, shifts the word from internal
memory to the data output lines. In FWFT mode, the first word written to an empty FIFO is clocked directly to
the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted to access
the first word.
Various signals, both input and output signals, operate differently, depending on which timing mode is in effect.
FIRST-WORD FALL-THROUGH MODE (FWFT)
In this mode, status flags IR, PAF, HF, PAE, and OR operate in the manner outlined in Table 3. To write data
into the FIFO, WEN must be low. Data presented to the data-in lines is clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the output ready (OR) flag goes low. Subsequent writes
continue to fill the FIFO. PAE goes high after n + 2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for this value is stated in the footnote of Table 3. This parameter also is user
programmable. See the Programmable Flag Offset Loading section.
If data continues to be written into the FIFO, and no read operations are taking place, HF switches to low when
the 258th (SN74V215), 514th (SN74V225), 1026th (SN74V235), and 2050th (SN74V245) word, respectively,
is written into the FIFO. Continuing to write data into the FIFO causes PAF to go low. Again, if no reads are
performed, PAF goes low after (513 – m) writes for the SN74V215, (1025 – m) writes for the SN74V225,
(2049 – m) writes for the SN74V235, and (4097 – m) writes for the SN74V245, where m is the full offset value.
The default setting for this value is stated in the footnote of Table 3.
When the FIFO is full, the input ready (IR) flag goes high, inhibiting further write operations. If no reads are
performed after a reset, IR goes high after D writes to the FIFO. D = 513 for the SN74V215, 1025 for the
SN74V225, 2049 for the SN74V235, and 4097 for the SN74V245. The additional word in FWFT mode is due
to the capacity of the memory plus output register.
If the FIFO is full, the first read operation causes the IR flag to go low. Subsequent read operations cause PAF
and HF to go high at the conditions described in Table 3. If further read operations occur without write
operations, PAE goes low when there are n + 1 words in the FIFO, where n is the empty offset value. If there
is no empty offset specified, PAE is low when the device is 64 away from empty for SN74V215, and 128 away
from empty for SN74V225, SN74V235, and SN74V245. Continuing read operations cause the FIFO to be
empty. When the last word has been read from the FIFO, OR goes high, inhibiting further read operations. REN
is ignored when the FIFO is empty.
POST OFFICE BOX 655303
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9
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
functional description (continued)
Table 3. Status Flags for FWFT Mode
NUMBER OF WORDS IN FIFO
IR
PAF
HF
PAE
OR
0
L
H
H
L
H
1 to (n+1)†
L
H
H
L
L
(n+2) to 1025
(n+2) to 2049
L
H
H
H
L
514 to [1025–(m+1)]‡
1026 to [2049–(m+1)]‡
2050 to [4097–(m+1)]‡
L
H
L
H
L
(513–m) to 512
(1025–m) to 1024
(2049–m) to 2048
(4097–m) to 4096
L
L
L
H
L
513
1025
2049
4097
H
L
L
H
L
SN74V215
SN74V225
SN74V235
SN74V245
0
0
0
1 to (n+1)†
1 to (n+1)†
1 to (n+1)†
(n+2) to 257
(n+2) to 513
258 to [513–(m+1)]‡
† n = Empty offset (SN74V215 n = 63; SN74V225, SN74V235, and SN74V245 n = 127)
‡ m = Full offset (SN74V215 m = 63; SN74V225, SN74V235, and SN74V245 m = 127)
STANDARD MODE
In this mode, status flags FF, PAF, HF, PAE, and EF operate in the manner outlined in Table 4. To write data into
the FIFO, write enable (WEN) must be low. Data presented to the data-in lines is clocked into the FIFO on
subsequent transitions of the write clock (WCLK). After the first write is performed, the empty flag (EF) goes
high. Subsequent writes continue to fill the FIFO. The programmable almost-empty flag (PAE) goes high after
n + 1 words have been loaded into the FIFO, where n is the empty offset value. The default setting for this value
is stated in the footnote of Table 4. This parameter also is user programmable. See the Programmable Flag
Offset Loading section.
If data continues to be written into the FIFO, and no read operations are taking place, the half-full flag (HF)
switches to low when the 257th (SN74V215), 513th (SN74V225), 1025th (SN74V235), and 2049th (SN74V245)
word, is written into the FIFO. Continuing to write data into the FIFO causes the programmable almost-full flag
(PAF) to go low. Again, if no reads are performed, PAF goes low after (512 – m) writes for the SN74V215, (1024
– m) writes for the SN74V225, (2048 – m) writes for the SN74V235 and (4096 – m) writes for the SN74V245.
Offset m is the full offset value. This parameter also is user programmable. See the Programmable Flag Offset
Loading section. If there is no full offset specified, PAF is low when the device is 63 away from full for SN74V215,
and 127 away from full for the SN74V225, SN74V235, and SN74V245.
When the FIFO is full, the full flag (FF) goes low, inhibiting further write operations. If no reads are performed
after a reset, FF goes low after D writes to the FIFO. D = 512 for the SN74V215, 1024 for the SN74V225, 2048
for the SN74V235, and 4096 for the SN74V245.
If the FIFO is full, the first read operation causes FF to go high. Subsequent read operations cause PAF and
the half-full flag (HF) to go high under the conditions described in Table 4. If further read operations occur,
without write operations, the programmable almost-empty flag (PAE) goes low when there are n words in the
FIFO, where n is the empty offset value. If there is no empty offset specified, PAE is low when the device is 63
away from completely empty for SN74V215, and 127 away from completely empty for SN74V225, SN74V235,
and SN74V245. Continuing read operations cause the FIFO to be empty. When the last word has been read
from the FIFO, EF goes low, inhibiting further read operations. REN is ignored when the FIFO is empty.
10
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SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
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SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
functional description (continued)
Table 4. Status Flags for Standard Mode
NUMBER OF WORDS IN FIFO
FF
PAF
HF
PAE
EF
0
H
H
H
L
L
1 to n†
H
H
H
L
H
(n+1) to 1024
(n+1) to 2048
H
H
H
H
H
513 to [1025–(m+1)]‡
1025 to [2048–(m+1)]‡
2049 to [4096–(m+1)]‡
H
H
L
H
H
(512–m) to 511
(1024–m) to 1023
(2048–m) to 2047
(4096–m) to 4095
H
L
L
H
H
512
1024
2048
4096
L
L
L
H
H
SN74V215
SN74V225
SN74V235
SN74V245
0
0
0
1 to n†
1 to n†
1 to n†
(n+1) to 256
(n+1) to 512
257 to [512–(m+1)]‡
† n = Empty offset (SN74V215 n = 63; SN74V225, SN74V235, and SN74V245 n = 127)
‡ m = Full offset (SN74V215 m = 63; SN74V225, SN74V235, and SN74V245 m = 127)
PROGRAMMABLE FLAG LOADING
Full- and empty-flag offset values can be user programmable. The SN74V215, SN74V225, SN74V235, and
SN74V245 have internal registers for these offsets. Default settings are stated in the footnotes of Table 3 and
Table 4. Offset values are loaded into the FIFO using the data input lines D0–D11. To load the offset registers,
the load (LD) pin and WEN pin must be held low. Data present on D0–D11 is transferred to the empty offset
register on the first low-to-high transition of WCLK. By continuing to hold the LD and WEN pins low, data present
on D0–D11 is transferred into the full offset register on the next transition of the WCLK. The third transition again
writes to the empty offset register. Writing to all offset registers does not have to occur at the same time. One
or two offset registers can be written and, then, by bringing the LD pin high, the FIFO is returned to normal
read/write operation. When the LD pin and WEN again are set low, the next offset register in sequence is written.
The contents of the offset registers can be read on the data output lines Q0–Q11 when the LD pin is set low,
and REN is set low. Data then can be read on the next low-to-high transition of RCLK. The first transition of RCLK
presents the empty offset value to the data output lines. The next transition of RCLK presents the full offset
value. Offset register content can be read in the standard mode only. It cannot be read in the FWFT mode.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIMING SELECTION
The SN74V215, SN74V225, SN74V235, and SN74V245 can be configured during the configuration-at-reset
cycle (see Table 5) with either asynchronous or synchronous timing for PAE and PAF flags.
If asynchronous PAE/PAF configuration is selected (see Table 5), the PAE is asserted low on the low-to-high
transition of RCLK. PAE is reset to high on the low-to-high transition of WCLK. Similarly, the PAF is asserted
low on the low-to-high transition of WCLK, and PAF is reset to high on the low-to-high transition of RCLK. For
detailed timing diagrams, see Figure 9 for asynchronous PAE timing and Figure 10 for asynchronous PAF
timing.
If synchronous PAE/PAF configuration is selected, PAE is asserted and updated on the rising edge of RCLK
only, but not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only, but not RCLK.
For detailed timing diagrams, see Figure 18 for synchronous PAE timing and Figure 19 for synchronous PAF
timing.
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SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
functional description (continued)
Table 5. Truth Table for Configuration at Reset
FL
RXI
WXI
EF/OR
FF/IR
PAE, PAF
FIFO TIMING MODE
0
0
0
Single register-buffered
empty flag
Single register-buffered
full flag
Asynchronous
Standard
0
0
1
Triple register-buffered
output-ready flag
Double register-buffered
input ready flag
Asynchronous
FWFT
0
1
0
Double register-buffered
empty flag
Double register-buffered
full flag
Asynchronous
Standard
0†
1
1
Single register-buffered
empty flag
Single register-buffered
full flag
Asynchronous
Standard
1
0
0
Single register-buffered
empty flag
Single register-buffered
full flag
Synchronous
Standard
1
0
1
Triple register-buffered
output-ready flag
Double register-buffered
input ready flag
Synchronous
FWFT
1
1
0
Double register-buffered
empty flag
Double register-buffered
full flag
Synchronous
Standard
1‡
1
1
Single register-buffered
empty flag
Single register-buffered
full flag
Asynchronous
Standard
† In daisy-chain depth expansion, FL is held low for the first-load device. The RXI and WXI inputs are driven by the
corresponding RXO and WXO outputs of the preceding device.
‡ In daisy-chain depth expansion, FL is held high for members of the expansion other than the first-load device. The RXI and
WXI inputs are driven by the corresponding RXO and WXO outputs of the preceding device.
REGISTER-BUFFERED FLAG OUTPUT SELECTION
The SN74V215, SN74V225, SN74V235, and SN74V245 can be configured during the configuration-at-reset
cycle (see Table 7) with single, double, or triple register-buffered flag output signals. The various combinations
available are described in Table 6 and Table 7. In general, going from single to double or triple register-buffered
flag outputs removes the possibility of metastable flag indications on boundary states (empty or full conditions).
The tradeoff is the addition of clock-cycle delays for the respective flag to be asserted. Not all combinations of
register-buffered flag outputs are supported. Register-buffered outputs apply to the empty flag and full flag only.
Partial flags are not affected. Table 6 and Table 7 summarize the options available.
Table 6. Register-Buffered Flag Output Options, FWFT Mode
PROGRAMMING
AT RESET
FLAG TIMING
DIAGRAMS
OUTPUT READY
(OR)
INPUT READY
(IR)
PARTIAL
FLAGS
FL
RXI
WXI
Triple
Double
Asynchronous
0
0
1
Figure 23
Triple
Double
Synchronous
1
0
1
Figure 16, Figure 17
Table 7. Register-Buffered Flag Output Options, Standard Mode
12
EMPTY FLAG
(EF)
BUFFERED OUTPUT
FULL FLAG
(FF)
BUFFERED OUTPUT
PARTIAL
FLAGS
TIMING MODE
Single
Single
Single
Single
Double
Double
PROGRAMMING AT
RESET
FLAG TIMING
DIAGRAMS
FL
RXI
WXI
Asynchronous
0
0
0
Synchronous
1
0
0
Figure 5, Figure 6
Double
Asynchronous
0
1
0
Figure 20, Figure 22
Double
Synchronous
1
1
0
Figure 20, Figure 22
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Figure 5, Figure 6
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
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SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
tRS
RS
tRSR
REN, WEN, LD
FL, RXI, WXI
(see Note A)
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
tRSS
tRSR
Configuration Setting
(see Note C)
RCLK, WCLK
(see Note B)
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
tRSF
FF/IR
tRSF
EF/OR
Standard Mode
FWFT Mode
FWFT Mode
Standard Mode
tRSF
PAF,
WXO/HF, RXO
tRSF
PAE
tRSF
Q0–Q17
OE = 1
(see Note D)
OE = 0
NOTES: A. Single-device mode (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). FL, RXI, WXI should be static (tied to VCC
or GND).
B. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.
C. In FWFT mode, IR goes low based on the WCLK edge after reset.
D. After reset, the outputs are low if OE = 0 and 3-state if OE = 1.
Figure 1. Reset Timing
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tCLK
tCLKH
tCLKL
WCLK
tDS
D0–D17
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÌÌÌ
ÌÌÌ
tENS
WEN
tWFF
tDH
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÏÏÏÏ
ÏÏÏÏ
Data
Invalid
tENH
No Operation
tWFF
ÎÎÎ
ÎÎÎ
ÌÌ
ÌÌ
FF
tSKEW1 (see Note A)
RCLK
REN
NOTES: A. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high during the current
clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, FF might not change
state until the next WCLK edge.
B. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.
Figure 2. Write-Cycle Timing With Single Register-Buffered FF (Standard Mode)
14
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tCLK
tCLKH
tCLKL
RCLK
ÌÌÌ
ÌÌÌ
ÌÌÌ
tENS
REN
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÌÌÌ
ÌÌÌ
ÌÌÌ
tENH
No Operation
tREF
tREF
EF
ÎÎÎÎÎ
ÎÎÎÎÎ
tA
Q0–D17
tOLZ
tOHZ
tOE
OE
tSKEW1
(see Note A)
WCLK
WEN
NOTES: A. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that EF goes high during the current
clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, EF might not change
state until the next RCLK edge.
B. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.
Figure 3. Read-Cycle Timing With Single Register-Buffered EF (Standard Mode)
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WCLK
D0–D17
WEN
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÌÌÌ
ÌÌÌ
ÌÌÌ
tDS
D0 (First Valid Write)
D1
D2
D3
D4
tENS
tFRL
(see Note A)
tSKEW1
RCLK
tREF
EF
REN
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
Q0–Q17
tOLZ
tENS
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
tA
tA
D0
D1
tOE
OE
NOTES: A. When tSKEW1 is at the minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 is less than the
minimum specification, tFRL (maximum) = either (2 × tCLK) + tSKEW1 or tCLK + tSKEW1. The latency timing applies only at the
empty boundary (EF is low).
B. The first word always is available the cycle after EF goes high.
C. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.
Figure 4. First-Data-Word Latency with Single Register-Buffered EF (Standard Mode)
16
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No Write
No Write
WCLK
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
tSKEW1
(see Note A)
D0–D17
tWFF
tDS
Data Write
tWFF
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
tSKEW1
(see Note A)
tDS
Data
Write
tWFF
FF
WEN
RCLK
tENS
tENS
tENH
tENH
tA
tA
REN
OE
Q0–Q17
Low
Data In Output Register
Data Read
Next Data Read
NOTES: A. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high during the current
clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, FF might not change
state until the next WCLK edge.
B. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.
Figure 5. Single Register-Buffered Full-Flag Timing (Standard Mode)
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512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
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WCLK
ÎÎÎ
ÎÎÎ
D0–D17
tDS
Data Write 1
tENS
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
tDS
Data Write 2
tENS
ÌÌÌ
ÌÌÌ
tENH
WEN
tFRL
(see Note A)
tSKEW1
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
tENH
tFRL
(see Note A)
tSKEW1
RCLK
tREF
tREF
tREF
EF
REN
OE
Low
tA
Q0–Q17
Data In Output Register
Data Read
NOTES: A. When tSKEW1 is at the minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 is less than the minimum
specification, tFRL (maximum) = either (2 × tCLK) + tSKEW1 or tCLK + tSKEW1. The latency timing applies only at the empty
boundary (EF is low).
B. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.
Figure 6. Single Register-Buffered Empty Flag Timing (Standard Mode)
18
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tCLK
tCLKH
tCLKL
WCLK
ÌÌÌÌÏÏÏÏÏ
ÌÌÌÌÏÏÏÏÏ
ÌÌÌÌÏÏÏÏÏ
ÌÌÌÌ
ÌÌÌÌ
tENS
LD
tENH
tENS
WEN
tDS
tDH
PAE Offset
ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
D0–D15
D0–D11
PAE Offset
PAF Offset
Figure 7. Write Programmable Registers (Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
RCLK
ÌÌÌÌÏÏÏÏÏ
ÌÌÌÌÏÏÏÏÏ
ÌÌÌÌ
ÌÌÌÌ
tENS
LD
tENH
tENS
REN
Q0–Q15
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
tA
Unknown
PAE Offset
PAF Offset
Figure 8. Read Programmable Registers (Standard Mode)
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PAE Offset
ÎÎÎ
ÎÎÎ
19
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
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tCLKH
tCLKL
WCLK
tENS
WEN
PAE
tENH
ÌÌÌÌÏÏÏÏ
ÌÌÌÌÏÏÏÏ
n Words in FIFO
(see Note B)
n + 1 Words in FIFO
(see Note C)
tPAEA
n + 1 Words in FIFO
(see Note B)
n + 2 Words in FIFO
(see Note C)
n Words in FIFO
(see Note B)
n + 1 Words in FIFO
(see Note C)
tPAEA
RCLK
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
tENS
REN
NOTES: A.
B.
C.
D.
E.
n = PAE offset
For standard mode
For FWFT mode
PAE is asserted low on RCLK transition and reset to high on WCLK transition.
Select the asynchronous modes by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during reset.
Figure 9. Asynchronous Programmable Almost-Empty-Flag Timing (Standard and FWFT Modes)
20
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tCLKH
tCLKL
WCLK
tENS
WEN
tENH
ÌÌÌ ÏÏÏ
ÌÌÌ ÏÏÏ
tPAFA
PAF
D – m Words
in FIFO
D – (m + 1) Words in FIFO
(see Notes A and B)
D – (m + 1) Words
in FIFO
tPAFA
RCLK
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
tENS
REN
NOTES: A. m = PAF offset
B. D = maximum FIFO depth
In FWFT mode: D = 513 for the SN74V215, 1025 for the SN74V225, 2049 for the SN74V235 and 4097 for the SN74V245
In standard mode: D = 512 for the SN74V215, 1024 for the SN74V225, 2048 for the SN74V235 and 4096 for the SN74V245
C. PAF is asserted to low on WCLK transition and reset to high on RCLK transition.
D. Select asynchronous modes by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during reset.
Figure 10. Asynchronous Programmable Almost-Full-Flag Timing (Standard and FWFT Modes)
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tCLKH
tCLKL
WCLK
tENS
tENH
ÌÌÌÌÏÏÏÏ
ÌÌÌÌÏÏÏÏ
WEN
D/2+1 Words in FIFO,
(see Notes A and B)
tHF
D/2 Words in FIFO,
(see Notes A and B)
HF
Words in FIFO
D – 1 + 2 (see Notes A
D/2 Words in FIFO,
2
and C)
(see Notes A and B)
D – 1 + 1 Words in FIFO
(see Notes A and C)
2
D–1 +1
2
tHF
Words in FIFO
(see Notes A
and C)
RCLK
ÌÌÌÌ
ÌÌÌÌ
tENS
REN
NOTES: A. D = maximum FIFO depth
In FWFT mode: D = 513 for the SN74V215, 1025 for the SN74V225, 2049 for the SN74V235 and 4097 for the SN74V245
In standard mode: D = 512 for the SN74V215, 1024 for the SN74V225, 2048 for the SN74V235 and 4096 for the SN74V245
B. For standard mode
C. For FWFT mode
D. Select single-device mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset.
Figure 11. Half-Full-Flag Timing (Standard and FWFT Modes)
tCLKH
See
Note A
WCLK
tXO
WXO
tENS
WEN
ÌÌÌ
ÌÌÌ
NOTE A: Write to last physical location.
ÏÏÏ
ÏÏÏ
Figure 12. Write-Expansion-Out Timing
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
tCLKH
RCLK
See
Note A
tXO
RXO
ÌÌÌÌ ÏÏÏÏ
ÌÌÌÌ ÏÏÏÏ
tENS
REN
NOTE A: Read from last physical location.
Figure 13. Read-Expansion-Out Timing
tXI
WXI
tXIS
WCLK
Figure 14. Write-Expansion-In Timing
tXI
RXI
tXIS
RCLK
Figure 15. Read-Expansion-In Timing
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
1
WEN
ÎÎ ÎÎÎÎÎÎ Î Î Î Î ÎÎÎÎÎÎ Î Î Î Î Î Î ÎÎÎ
ÎÎ ÎÎÎÎÎÎ Î Î Î Î ÎÎÎÎÎÎ Î Î Î Î Î Î ÎÎÎ
tDH
tDS
D0–D17
W1
W2
tDS
W3
W[n+2]
W4
tSKEW1
RCLK
1
2
W[n+3]
tDS
W[n+4]
W
D – 1+ 1
2
W
D – 1+ 2
2
W
tDS
D – 1+ 3
2
W[D-m-2]
W[D-m-1]
W[D-m]
tENH
W[D-m+1]
W[D-m+2]
W[D]
W[D+1]
tSKEW2 (see Note B)
3
REN
tA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Q0–Q17
Data in Output Register
W1
tREF
OR
tPAES
PAE
tHF
HF
tPAFS
PAF
tWFF
IR
NOTES: A. t SKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go low after two RCLK cycles plus tREF . If the time between the rising
edge of WLCK and the rising edge of RCLK is less than t SKEW1, the OR deassertion might be delayed one extra RCLK cycle.
B. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go high during the current clock cycle. If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW2, the PAE deassertion might be delayed one extra RCLK cycle.
C. LD is high, OE is low.
D. n = PAE offset, m = PAF offset, D = maximum FIFO depth = 513 words for the SN74V215, 1025 words for the SN74V225, 2049 words for the SN74V235, and 4097 words
for the SN74V245.
E. Select synchronous FWFT mode by setting ( FL , RXI , WXI ) = (1,0,1) during reset.
Figure 16. Write Timing With Synchronous Programmable Flags (FWFT Mode)
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNCTM FIRST-IN, FIRST-OUT MEMORIES
1
tENS
SCAS636E -– APRIL 2000 -– REVISED SEPTEMBER 2002
24
WCLK
WCLK
1
tENH
2
tSKEW2
(see Note B)
tSKEW1
(see Note A)
tENS
WEN
ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tDH
tDS
D0–D17
WD
RCLK
tENS
tENS
REN
OE
tA
tA
tA
tOHZ
Q0–Q17
W1
tA
W1
W2
W3
Wm+2
W[m+3]
tA
tA
W[m+4]
W
D – 1+ 1
2
W
D – 1+ 2
2
W[D-n-1]
W[D-n]
W[D-n+1]
W[D-n+2]
W[D-1]
WD
tREF
OR
tPAES
PAE
tHF
HF
tWFF
tWFF
IR
NOTES: A. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that IR goes low after one WCLK plus tWFF. If the time between the rising
edge of RLCK and the rising edge of WCLK is less than tSKEW1, the IR assertion might be delayed an extra WCLK cycle.
B. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go high during the current clock cycle. If the time between the rising edge
of RCLK and the rising edge of WCLK is less than tSKEW2, the PAF deassertion time may be delayed an extra WCLK cycle.
C. LD is high.
D. n = PAE offset, m = PAF offset, D = maximum FIFO depth = 513 words for the SN74V215, 1025 words for the SN74V225, 2049 words for SN74V235, and 4097 words
for SN74V245.
E. Select synchronous FWFT mode by setting ( FL , RXI , WXI ) = (1,0,1) during reset.
Figure 17. Read Timing With Synchronous Programmable Flags (FWFT Mode)
25
SCAS636E -– APRIL 2000 -– REVISED SEPTEMBER 2002
tPAFS
PAF
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNCTM FIRST-IN, FIRST-OUT MEMORIES
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
tOE
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
tCLKH
tCLKL
WCLK
ÎÎÎÎÏÏÏ
ÎÎÎÎÏÏÏ
tENS
WEN
PAE
tENH
n Words in FIFO,
(see Note B)
n + 1 Words in FIFO
(see Note C)
tSKEW2
(see Note D)
tPAES
(see Note C)
n + 1 Words in FIFO,
(see Note B)
n + 2 Words in FIFO
(see Note C)
n Words in FIFO
(see Note B),
n + 1 Words in FIFO
(see Note C)
tPAES
RCLK
tENS
tENH
ÎÎ ÏÏÏ
REN
NOTES: A.
B.
C.
D.
n = PAE offset
For standard mode
For FWFT mode
tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go high during the current clock cycle.
If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, the PAE deassertion might be delayed
one extra RCLK cycle.
E. PAE is asserted and updated on the rising edge of RCLK only.
F. Select synchronous modes by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during reset.
Figure 18. Synchronous Programmable Almost-Empty-Flag Timing (Standard and FWFT Modes)
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
tCLKH
tCLKL
WCLK
ÎÎÎÎÏÏÏ
ÎÎÎÎÏÏÏ
tENS
WEN
PAF
tENH
tPAFS
D – (m + 1) Words
in FIFO
D – m Words in FIFO
D – (m + 1) Words in FIFO
tSKEW2
(see Note C)
tPAFS
RCLK
tENS
tENH
ÎÎ ÏÏÏ
ÎÎ ÏÏÏ
REN
NOTES: A. m = PAF offset
B. D = maximum FIFO depth
In FWFT mode: D = 513 for the SN74V215, 1025 for the SN74V225, 2049 for the SN74V235, and 4097 for the SN74V245.
In standard mode: D = 512 for the SN74V215, 1024 for the SN74V225, 2048 for the SN74V235, and 4096 for the SN74V245.
C. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go high during the current clock cycle.
If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, the PAF deassertion time might
be delayed an extra WCLK cycle.
D. PAF is asserted and updated on the rising edge of WCLK only.
E. Select synchronous modes by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during reset.
Figure 19. Synchronous Programmable Almost-Full-Flag Timing (Standard and FWFT Modes)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
No
Write
No
Write
WCLK
1
2
tSKEW1
(see Note A)
1
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
tDS
D0–D17
tWFF
2
tSKEW1
(see Note A)
Wd
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
tDS
Data Write
tWFF
tWFF
FF
WEN
RCLK
tENS
tENS
tENH
tENH
REN
OE
Low
tA
Q0–Q17
tA
Data in Output Register
Data Read
Next Data Read
NOTES: A. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high after one WCLK
cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, the FF deassertion
time might be delayed an extra WCLK cycle.
B. LD is high.
C. Select double register-buffered standard mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during reset.
Figure 20. Double Register-Buffered Full-Flag Timing (Standard Mode)
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
tCLK
tCLKH
tCLKL
WCLK
1
2
tDS
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌ
ÎÎÎ ÏÏÏ
ÎÎ
ÎÎÎ ÏÏÏ
ÎÎ
tDH
D0–D17
Data in
Valid
tENS
WEN
tENH
No Operation
tWFF
tWFF
FF
tSKEW1
(see Note A)
RCLK
REN
NOTES: A. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high after one WCLK
cycle plus tRFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, the FF deassertion
might be delayed an extra WCLK cycle.
B. LD is high.
C. Select double register-buffered standard mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during reset.
Figure 21. Write-Cycle Timing With Double Register-Buffered FF (Standard Mode)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
tCLK
tCLKH
tCLKL
RCLK
1
2
tENS
ÎÎÎÎÏÏÏ
ÎÎÎÎÏÏÏ
tENH
No Operation
REN
tREF
tREF
EF
ÌÌÌÌ
ÌÌÌÌ
tA
Q0–Q17
tOLZ
Last Word
tOHZ
tOE
OE
tSKEW1
(see Note A)
WCLK
tENS
tENH
WEN
tDS
tDH
D0–D17
First Word
NOTES: A. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that EF goes high after one RCLK
cycle plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, the EF deassertion
might be delayed an extra RCLK cycle.
B. LD is high.
C. Select double register-buffered standard mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during reset.
Figure 22. Read-Cycle Timing With Double Register-Buffered EF (Standard Timing)
30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
WCLK
tENS
tENH
WEN
tDS
D0–D17
RCLK
REN
ÌÌÌ
ÌÌÌ
ÌÌ
ÌÌ
tDH
W1
W2
ÌÌ
ÌÌ
W3
tSKEW1
(see Note A)
1
ÌÌ
ÌÌ
2
W4
3
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
tA
Q0–Q17
ÌÌÌ
Ì
ÌÌ
tDS
W[n+2]
ÌÌ
ÌÌ
ÌÌ
ÌÌ
W[n+3]
ÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌ
Data In Output Register
W1
tREF
tREF
OR
NOTES: A. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go high during the current cycle. If
the time between the rising edge of WLCK and the rising edge of RCLK is less than tSKEW1, the OR deassertion might be delayed
one extra RCLK cycle.
B. LD is high, OE is low.
C. Select FWFT mode by setting (FL, RXI, WXI) = (0,0,1) or (1,0,1) during reset.
Figure 23. OR-Flag Timing and First Word Fall Through When FIFO is Empty (FWFT mode)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
operating configurations
SINGLE-DEVICE CONFIGURATION
A single SN74V215, SN74V225, SN74V235, or SN74V245 can be used when the application requirements are
for 512/1024/2048/4096 words or fewer, respectively. These FIFOs are in a single-device configuration when
the first load (FL), write expansion in (WXI) and read expansion in (RXI) control inputs are configured as
(FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset (see Figure 24).
Reset (RS)
Write Clock (WCLK)
Read Clock (RCLK)
Write Enable (WEN)
Read Enable (REN)
Load (LD)
Output Enable (OE)
74V215
74V225
74V235
74V245
Data In (D0–D17)
Data Out (Q0–Q17)
Empty Flag/Output Ready (EF/OR)
Full Flag/Input Ready (FF/IR)
Programmable (PAF)
Programmable (PAE)
Half-Full Flag (HF)
FL
RXI
WXI
Figure 24. Block Diagram of Single 512 × 18, 1024 × 18, 2048 × 18, or 4096 × 18 Synchronous FIFO
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
operating configurations (continued)
WIDTH-EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control signals of multiple devices. Status flags
can be detected from any one device. The exceptions are the empty flag/output ready and full flag/input ready.
Because of variations in skew between RCLK and WCLK, it is possible for flag assertion and deassertion to vary
by one cycle between FIFOs. To avoid problems, the user must create composite flags by gating the empty
flags/output ready of every FIFO, and separately gating all full flags/input ready. Figure 25 demonstrates a
36-word width by using two SN74V215, SN74V225, SN74V235, or SN74V245 memories. Any word width can
be attained by adding additional SN74V215, SN74V225, SN74V235, or SN74V245 memories. These FIFOs
are in a single-device configuration when the first load (FL), write expansion in (WXI), and read expansion in
(RXI) control inputs are configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during
reset (see Figure 25).
Reset (RS)
Reset (RS)
Data In (D)
36
18
18
Read Clock (RCLK)
Write Clock (WCLK)
Read Enable (REN)
Write Enable (WEN)
Output Enable (OE)
Load (LD)
74V215
74V225
74V235
74V245
Programmable (PAE)
Half-Full Flag (HF)
Full Flag/
Input Ready
(FF/IR)
FF/IR
Programmable (PAF)
74V215
74V225
74V235
74V245
FF/IR
EF/OR
Empty Flag/
Output Ready
(EF/OR)
EF/OR
18
FL
WXI
RXI
18
FL WXI
Data Out (Q)
36
RXI
NOTE A: Do not connect any output control signals directly together.
Figure 25. Block Diagram of 512 × 36, 1024 × 36, 2048 × 36, or 4096 × 36
Synchronous FIFO Memory Used in a Width-Expansion Configuration
DEPTH-EXPANSION CONFIGURATION, DAISY-CHAIN TECHNIQUE (WITH PROGRAMMABLE FLAGS)
These devices can be adapted easily to applications requiring more than 512, 1024, 2048, or 4096 words of
buffering. Figure 26 shows depth expansion using three SN74V215, SN74V225, SN74V235, or SN74V245
memories. Maximum depth is limited only by signal loading.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
WXO RXO
WCLK RCLK
WEN
REN
RS
OE
LD
74V215
74V225
Dn
74V235
VCC
74V245
FL
FF/IR
Data In
Qn
EF/OR
PAE
PAF
WXI
RXI
WXO
WCLK
WEN
RS
LD
RXO
RCLK
REN
OE
Data Out
74V215
VCC
Dn 74V225 Qn
74V235
74V245
FL
FF/IR
PAF
WXI
WXO
WCLK
Write Clock
Write Enable
EF/OR
PAE
RXI
RXO
RCLK
WEN
Reset
Read Clock
Read Enable
REN
OE
Output Enable
RS
Dn 74V215
Qn
LD 74V225
Load
74V235
74V245
FF/IR
PAF
EF/OR
FF/IR
EF/OR
PAF
WXI
PAE
RXI
PAE
First Load (FL)
NOTES: A.
B.
C.
D.
E.
F.
G.
The first device must be designated by grounding the first load (FL) control input.
All other devices must have FL in the high state.
The write expansion out (WXO) pin of each device must be tied to the write expansion in (WXI) pin of the next device.
The read expansion out (RXO) pin of each device must be tied to the read expansion in (RXI) pin of the next device.
All load (LD) pins are tied together.
The half-full flag (HF) is not available in this depth-expansion configuration.
EF, FF, PAE, and PAF are created with composite flags by ORing together every respective flag for monitoring. The composite
PAE and PAF flags are not precise.
H. In daisy-chain mode, the flag outputs are single-register buffered and the partial flags are in asynchronous timing mode.
Figure 26. Block Diagram of 1536 × 18, 3072 × 18, 6144 × 18, 12288 × 18
Synchronous FIFO Memory With Programmable Flags Used in Depth-Expansion Configuration
34
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
operating configurations (continued)
DEPTH-EXPANSION CONFIGURATION (FWFT MODE)
In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs
of the next) with no external logic necessary. The resulting configuration provides a total depth equivalent to
the sum of the depths associated with each single FIFO. NO TAG shows a depth expansion using two
SN74V215, SN74V225, SN74V235, or SN74V245 memories.
Care should be taken to select FWFT mode during master reset for all FIFOs in the depth expansion
configuration. The first word written to an empty configuration passes from one FIFO to the next (ripple down)
until it finally appears at the outputs of the last FIFO in the chain. No read operation is necessary, but the RCLK
of each FIFO must be free running. Each time the data word appears at the outputs of one FIFO, that device’s
OR line goes low, enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for OR of the last FIFO in the chain to go low
(i.e., valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO is the sum
of the delays for each individual FIFO:
(N – 1) × (4 × transfer clock) + 3 × TRCLK
Where: N is the number of FIFOs in the expansion and TRCLK is the RCLK period. Extra cycles should be added
for the possibility that the tSKEW1 specification is not met between WCLK and transfer clock, or RCLK and
transfer clock, for the OR flag.
The ripple-down delay is noticeable only for the first word written to an empty depth-expansion configuration.
There is no delay evident for subsequent words written to the configuration.
The first free location created by reading from a full depth-expansion configuration bubbles up from the last FIFO
to the previous one until finally it moves into the first FIFO of the chain. Each time a free location is created in
one FIFO of the chain, that FIFO’s IR line goes low, enabling the preceding FIFO to write a word to fill it.
For a full expansion configuration, the amount of time it takes for IR of the first FIFO in the chain to go low after
a word has been read from the last FIFO is the sum of the delays for each individual FIFO:
(N – 1) × (3 × transfer clock) + 2TWCLK
Where: N is the number of FIFOs in the expansion and TWCLK is the WCLK period. Extra cycles should be added
for the possibility that the tSKEW1 specification is not met between RCLK and transfer clock, or WCLK and
transfer clock, for the IR flag.
The transfer clock line should be tied to either WCLK or RCLK, whichever is faster. Both these actions result
in data moving, as quickly as possible, to the end of the chain and free locations to the beginning of the chain.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
35
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
HF
HF
PAF
Write Clock
Write Enable
Input Ready
Data In n
PAE
Transfer Clock
WCLK
RCLK
WEN 74V215
74V225
IR
74V235
74V245
OR
WEN
REN
OE
Dn FL RXI WXI Qn
(0,1)
WCLK
IR
GND
n
VCC
GND
Read Clock
RCLK
74V215
74V225
74V235
74V245
Output Ready
OR
Output Enable
OE
Dn FL RXI WXI Qn
(0,1)
Read Enable
REN
n
Data Out
VCC
GND
Figure 27. Block Diagram of 1024 × 18, 2048 × 18, 4096 × 18, 8192 × 18
Synchronous FIFO Memory With Programmable Flags Used in Depth-Expansion Configuration
36
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 5 V
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
TYP
MAX
UNIT
VCC
GND
Supply voltage
3.0
3.3
3.6
V
Supply voltage
0
0
0
V
VIH
VIL
High-level input voltage
2
5
V
TA
Operating free-air temperature
Low-level input voltage
0
0.8
V
70
°C
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VOH
VOL
VCC = 3.0 V,
VCC = 3.0 V,
IOH = – 2 mA
IOL = 8 mA
II
IOZ
VCC = 3.6 V,
VCC = 3.6 V,
VI = VCC to 0.4 V
OE ≥ VIH,
ICC1
ICC2
VCC = 3.3 V,
VCC = 3.6 V,
See Notes 1, 2, and 3
CIN
VI = 0, TA = 25°C,
VO = 0, TA = 25°C,
f = 1 MHz
10
pF
f = 1 MHz, Output deselected, (OE ≥ VIH)
10
pF
COUT
2.4
UNIT
V
VO = VCC to 0.4 V
See Notes 1 and 4
0.4
V
±1
µA
± 10
µA
35
mA
5
mA
NOTES: 1. Tested with outputs disabled (IOUT = 0)
2. RCLK and WCLK switch at 20 MHz and data inputs switch at 10 MHz.
3. Typical ICC1 = 2.04 + 0.88 × fS + 0.02 × CL × fS (in mA). These equations are valid under the following conditions:
VCC = 3.3 V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive
load (in pF).
4. All inputs = (VCC – 0.2 V) or (GND + 0.2 V), except RCLK and WCLK, which switch at 20 MHz.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
37
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figure 28 through Figure 23)
’74V215-7
’74V225-7
’74V235-7
’74V245-7
’74V215-10
’74V225-10
’74V235-10
’74V245-10
’74V215-15
’74V225-15
’74V235-15
’74V245-15
’74V215-20
’74V225-20
’74V235-20
’74V245-20
MIN
MIN
MIN
MIN
MAX
133
MAX
MAX
Clock cycle frequency
tCLK
tCLKH
Clock cycle time
7.5
10
15
20
ns
Clock high time
3.5
4.5
6
8
ns
tCLKL
tDS
Clock low time
3.5
4.5
6
8
ns
Data setup time
2.5
3
4
5
ns
tDH
tENS
Data hold time
0.5
0.5
1
1
ns
Enable setup time
2.5
3
4
5
ns
tENH
tLDS
Enable hold time
0.5
0.5
1
1
ns
Load setup time
3.5
3.5
4
4
ns
tLDH
tRS
Load hold time
0.5
0.5
1
1
ns
Reset pulse width†
10
10
15
20
ns
tRSS
tRSR
Reset setup time
8
8
10
12
ns
Reset recovery time
8
8
10
12
tRSF
tOLZ
Reset to flag and output time
tOE
tOHZ
Output enable to output valid
tWFF
tREF
Write clock to Full flag
5
6.5
10
Read clock to Empty flag
5
6.5
12.5
2
5
2
15
Output enable to output in low Z
0
1
tPAFA
Clock to asynchronous programmable
Almost-Full flag
tPAFS
Write clock to synchronous programmable
Almost-Full flag
tPAEA
Clock to asynchronous programmable
Almost-Empty flag
tPAES
Read clock to synchronous programmable
Almost-Empty flag
2
15
0
6
Output enable to output in high Z
6.5
66.7
MAX
fclock
tA
Data access time
100
UNIT
10
2
15
0
6
3
ns
ns
20
0
ns
ns
3
10
ns
8
3
10
ns
12
ns
10
12
ns
17
20
22
ns
5
8
10
12
ns
12.5
17
20
22
ns
5
8
10
12
ns
12.5
17
20
22
ns
5
6.5
10
12
ns
1
3
MHz
12
8
6
6
50
tHF
tXO
Clock to Half-Full flag
tXI
tXIS
Expansion in pulse duration
2.5
3
6.5
8
ns
Expansion in setup time
2.5
3
5
8
ns
tSKEW1
Skew time between read clock and write clock for
FF/IR and EF/OR
5
5
6
8
ns
tSKEW2
Skew time between read clock and write clock for
PAE and PAF (synchronous only)
7
14
18
20
ns
Clock to expansion out
† Pulse durations less than minimum values are not allowed.
38
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
AC TEST CONDITIONS
VCC/2
GND to 3.0 V
3 ns
1.5 V
1.5 V
See A
See B and C
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load for tCLK = 10 ns, 15 ns
Output Load for tCLK = 7.5 ns
50 Ω
ZO = 50 Ω
I/O
B. AC TEST LOAD FOR 7.5 SPEED GRADE
3.3 V
From Output
Under Test
510 Ω
30 pF
(see Note A)
Typical – ∆t CD – ns
6
330 Ω
5
4
3
2
1
0
0
20
40
60
80 100 120 140 160 180 200
Capacitance – pF
A. OUTPUT LOAD CIRCUIT
FOR 10, 15, AND 20 SPEED GRADES
C. LUMPED CAPACITIVE LOAD, TYPICAL DERATING
NOTE A: Includes probe and jig capacitance
Figure 28. Load Circuits
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
39
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CV215-10PAGG4
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
CV235-7PAGG4
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
CV245-10PAGG4
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
CV245-7PAGG4
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74V215-10PAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74V215-15PAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74V215-20PAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74V215-7PAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74V225-10PAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74V225-15PAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74V225-20PAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74V225-7PAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74V235-10PAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74V235-15PAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74V235-20PAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74V235-7PAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74V245-10PAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74V245-15PAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74V245-20PAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74V245-7PAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
0,08 M
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
1,05
0,95
0°– 7°
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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