EM621FU16BU Series Low Power, 128Kx16 SRAM Document Title 128K x16 bit Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date 0.0 Initial Draft Oct. 31, 2007 0.1 0.1 Revision Nov. 16, 2007 Remark Emerging Memory & Logic Solutions Inc. 4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com Zip Code : 690-719 The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1 EM621FU16BU Series Low Power, 128Kx16 SRAM 128K x16 Bit Low Power and Low Voltage CMOS Static RAM FEATURES GENERAL DESCRIPTION - Process Technology : 0.15mm Full CMOS - Organization : 128K x16 - Power Supply Voltage => EM621FU16BU Series : 2.7V~3.3V - Low Data Retention Voltage : 1.5V (MIN) - Three state output and TTL Compatible - Packaged product designed for 45/55/70ns - Package Type: 44-TSOP2 The EM621FU16BU series are fabricated by EMLSI’s advanced full CMOS process technology. The families support industrial temperature range and Chip Scale Package for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current. The EM621FU16BU series are available in KGD, JEDEC standard 44 pin 400 mil TSOP2 package. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed Standby (ISB1, Typ.) Operating (ICC1.Max) PKG Type EM621FU16BU-45LF Industrial (-40 ~ 85oC) 2.7V~3.3V 45ns 1 µA 3mA 44-TSOP2 EM621FU16BU-55LF Industrial (-40 ~ 85oC) 2.7V~3.3V 55ns 1 µA 3mA 44-TSOP2 EM621FU16BU-70LF Industrial (-40 ~ 85oC) 2.7V~3.3V 70ns 1 µA 3mA 44-TSOP2 FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O 15 I/O 14 I/O 13 I/O 12 VSS VCC I/O 11 I/O 10 I/O 9 I/O 8 NC A8 A9 A10 A11 NC Name Function Name Function CS Chip select inputs Vcc Power Supply OE Output Enable input Vss Ground WE Write Enable input UB Upper Byte (I/O8~15) A0~A16 Address Inputs LB Lower Byte (I/O0~7) I/O0~I/O15 Data Inputs/Outputs NC No Connection Pre-charge Circuit A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 VCC VSS Row Select 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 EM621FU16BU-45LF A4 A3 A2 A1 A0 CS I/O 0 I/O 1 I/O 2 I/O 3 VCC VSS I/O 4 I/O 5 I/O 6 I/O 7 WE A16 A15 A14 A13 A12 I/O0 ~ I/O7 I/O8 ~ I/O15 Data Cont Data Cont Memory Array 1024 x 2048 I/O Circuit Column Select A10 A11 A12 A13 A14 A15 A16 WE OE UB LB CS 2 Control Logic EM621FU16BU Series Low Power, 128Kx16 SRAM ABSOLUTE MAXIMUM RATINGS * Parameter Symbol Voltage on Any Pin Relative to Vss Minimum Unit VIN, VOUT -0.2 to 4.0V V Voltage on Vcc supply relative to Vss VCC -0.2 to 4.0V V Power Dissipation PD 1.0 W Operating Temperature TA -40 to 85 o C * Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL DESCRIPTION CS OE WE LB UB I/O0-7 I/O8-15 Mode Power H X X X X High-Z High-Z Deselected Stand by X X X H H High-Z High-Z Deselected Stand by L H H L X High-Z High-Z Output Disabled Active L H H X L High-Z High-Z Output Disabled Active L L H L H Data Out High-Z Lower Byte Read Active L L H H L High-Z Data Out Upper Byte Read Active L L H L L Data Out Data Out Word Read Active L X L L H Data In High-Z Lower Byte Write Active L X L H L High-Z Data In Upper Byte Write Active L X L L L Data In Data In Word Write Active Note: X means don’t care. (Must be low or high state) 3 EM621FU16BU Series Low Power, 128Kx16 SRAM RECOMMENDED DC OPERATING CONDITIONS 1) Parameter Symbol Min Typ Max Unit Supply voltage VCC 2.7 3.0 3.3 V Ground VSS 0 0 0 V Input high voltage VIH 2.0 - VCC + 0.22) V Input low voltage VIL -0.23) - 0.6 V 1. 2. 3. 4. TA= -40 to 85oC, otherwise specified Overshoot: VCC +2.0 V in case of pulse width < 20ns Undershoot: -2.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f =1MHz, TA=25oC) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Ouput capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested. DC AND OPERATING CHARACTERISTICS Parameter Symbol Test Conditions Min Typ Max Unit Input leakage current ILI VIN=VSS to VCC -1 - 1 uA Output leakage current ILO CS=VIH or OE=VIH or WE=VIL or LB=UB=VIH VIO=VSS to VCC -1 - 1 uA Operating power supply ICC IIO=0mA, CS=VIL, VIN=VIH or VIL - - 3 mA ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS<0.2V, LB<0.2V or/and UB<0.2V, VIN<0.2V or VIN>VCC-0.2V - - 3 mA 45ns - - 35 ICC2 Cycle time = Min, IIO=0mA, 100% duty, CS=VIL, LB=VIL or/and UB=VIL , VIN=VIL or VIH 55ns - - 30 70ns - - 25 Average operating current mA Output low voltage VOL IOL = 2.1mA - - 0.4 V Output high voltage VOH IOH = -1.0mA 2.4 - - V Standby Current (TTL) ISB CS=VIH, Other inputs=VIH or VIL - - 0.3 mA - 11) 10 uA Standby Current (CMOS) ISB1 CS>VCC-0.2V, (CS controlled) Other inputs = 0~VCC (Typ. condition : VCC=3.0V @ 25oC) (Max. condition : VCC=3.3V @ 85oC) NOTES 1. Typical values are measured at Vcc=3.0V, TA=25oC and not 100% tested. 4 LF EM621FU16BU Series Low Power, 128Kx16 SRAM AC OPERATING CONDITIONS VTM3) Test Conditions (Test Load and Test Input/Output Reference) R12) Input Pulse Level : 0.4V to 2.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : 1.5V Output Load (See right) : CL1) = 100pF + 1 TTL (70ns) CL1) = 30pF + 1 TTL (45ns/55ns) 1. Including scope and Jig capacitance R2=3150 ohm 2. R1=3070 ohm, 3. VTM=2.8V 4. CL = 5pF + 1 TTL (measurement with tLZ, tHZ, tOLZ, tOHZ, tWHZ) R22) CL1) READ CYCLE (Vcc =2.7V to 3.3V, Gnd = 0V, TA = -40oC to +85oC) Parameter Symbol 45ns 55ns 70ns Min Max Min Max Min Max Unit Read cycle time tRC 45 - 55 - 70 - ns Address access time tAA - 45 - 55 - 70 ns Chip select to output tCO - 45 - 55 - 70 ns Output enable to valid output tOE - 25 - 25 - 35 ns UB, LB access time tBA 70 ns Chip select to low-Z output tLZ 10 - 10 - 10 - ns UB, LB enable to low-Z output tBLZ 5 - 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - 5 - ns Chip disable to high-Z output tHZ 0 20 0 20 0 25 ns UB, LB disable to high-Z output tBHZ 0 15 0 20 0 25 ns Output disable to high-Z output tOHZ 0 15 0 20 0 25 ns Output hold from address change tOH 10 - 10 - 10 - ns 45 55 WRITE CYCLE (Vcc =2.7V to 3.3V, Gnd = 0V, TA = -40oC to +85oC) Parameter Symbol 45ns 55ns 70ns Min Max Min Max Min Max Unit Write cycle time tWC 45 - 55 - 70 - ns Chip select to end of write tCW 45 - 45 - 60 - ns Address setup time tAS 0 - 0 - 0 - ns Address valid to end of write tAW 45 - 45 - 60 - ns UB, LB valid to end of write tBW 45 - 45 - 60 - ns Write pulse width tWP 35 - 40 - 50 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to ouput high-Z tWHZ 0 15 0 20 0 20 ns Data to write time overlap tDW 25 Data hold from write time tDH 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 5 - 5 - ns 5 25 30 ns EM621FU16BU Series Low Power, 128Kx16 SRAM TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS=OE=VIL, UB or/and LB=VIL) tRC Address tAA tOH Data Out Previous Data Valid Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH) tRC Address tAA tOH tCO CS tHZ tBA UB,LB tBHZ tOE OE Data Out High-Z tOHZ tOLZ Data Valid tBLZ tLZ NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 EM621FU16BU Series Low Power, 128Kx16 SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED) tWC Address tCW(2) tWR(4) CS tAW tBW UB,LB tWP(1) WE tAS(3) Data in tDH tDW High-Z High-Z Data Valid tWHZ Data out tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS CONTROLLED) tWC Address tAS(3) tCW(2) tWR(4) CS tAW tBW UB,LB tWP(1) WE tDW Data in Data out Data Valid High-Z High-Z 7 tDH EM621FU16BU Series Low Power, 128Kx16 SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED) tWC Address tCW(2) tWR(4) CS tAW tBW UB,LB tWP(1) tAS(3) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high. 8 EM621FU16BU Series Low Power, 128Kx16 SRAM DATA RETENTION CHARACTERISTICS Parameter Symbol VCC for Data Retention VDR Data Retention Current IDR Chip Deselect to Data Retention Time tSDR Operation Recovery Time tRDR Test Condition ISB1 Test Condition (Chip Disabled) 1) VCC=1.5V, ISB1 Test Condition (Chip Disabled) 1) See data retention wave form Min Typ2) Max Unit 1.5 - 3.3 V - 0.5 5.0 µA 0 - - tRC - - NOTES 1. See the ISB1 measurement condition of data sheet page 4. 2. Typical value is measured at TA=25oC and not 100% tested. DATA RETENTION WAVE FORM tSDR Data Retention Mode Vcc 3.0V 2.2V VDR CS > Vcc-0.2V CS GND 9 tRDR ns EM621FU16BU Series Low Power, 128Kx16 SRAM PACKAGE DIMENSIONS 44Pin - TSOP Type2 Unit : millimeters/Inches 10 EM621FU16BU Series Low Power, 128Kx16 SRAM SRAM PART CODING SYSTEM EM X XX X X X XX X X - XX XX 1. EMLSI Memory 11. Power 2. Product Type 10. Speed 3. Density 4. Function 9. Package 8. Generation 5. Technology 7. Organization 6. Operating Voltage 7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 1. Memory Component EM --------------------- Memory 2. Product Type 6 ------------------------ SRAM 8. Generation Blank ----------------- 1st generation A ----------------------- 2nd generation B ----------------------- 3rd generation C ----------------------- 4th generation D ----------------------- 5th generation E ----------------------- 6th generation F ----------------------- 7th generation G ---------------------- 8th generation 3. Density 1 ------------------------- 1M 2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 4. Function 0 ----------------------- Dual CS 1 ----------------------- Single CS 2 ----------------------- Multiplexed 3 ------------- Single CS / LBB, UBB(tBA=tOE) 4 ------------- Single CS / LBB, UBB(tBA=tCO) 5 ------------- Dual CS / LBB, UBB(tBA=tOE) 6 ------------- Dual CS / LBB, UBB(tBA=tCO) 9. Package Blank ---------------- KGD, 48&36FpBGA S ---------------------- 32 sTSOP1 T ---------------------- 32 TSOP1 U ---------------------- 44 TSOP2 V ---------------------- 32 SOP 10. Speed 45 ---------------------55 ---------------------70 ---------------------85 ---------------------10 ---------------------12 ---------------------- 5. Technology F ------------------------- Full CMOS 6. Operating Voltage T ------------------------- 5.0V V ------------------------- 3.3V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V 45ns 55ns 70ns 85ns 100ns 120ns 11. Power LL ---------------------- Low Low Power LF ---------------------- Low Low Power(Pb-Free & Green) L ---------------------- Low Power S ---------------------- Standard Power 11