Austin AS8FLC2M32BQ-100/IT Hermetic, multi-chip module (mcm) 64mb, 2m x 32, 3.3volt boot block flash array Datasheet

FLASH
AUSTIN SEMICONDUCTOR, INC.
AS8FLC2M32
Austin Semiconductor, Inc.
FIGURE 1: PIN ASSIGNMENT
(Top View)
•
•
•
•
•
•
•
OPTION
Access Speed
70ns
90ns
100ns
120ns
MARKING
-70
-90
-100
-120
61
62
63
64
65
66
67
68
01
02
03
04
05
06
76
15
55
16
54
17
53
18
52
19
51
20
50
DQ14
I/O14
DQ15
I/O15
25
45
26
44
21
I/O19
DQ19
I/O20
DQ20
I/O21
DQ21
I/O22
DQ22
DQ23
I/O23
GND
I/O24
DQ24
I/O25
DQ25
I/O26
DQ26
I/O27
DQ27
49
[Package Designator QT]
22
48
I/O28
DQ28
DQ29
I/O29
DQ30
I/O30
DQ31
I/O31
43
42
41
40
39
38
37
36
35
34
46
33
47
24
32
23
Pin Assignment
(Top View)
DQ8
I/O8
Reset\
I/O15
DQ15
I/O24
DQ24
VCC
I/O31
DQ31
DQ9
I/O9
CS2\
DQ14
I/O14
I/O25
DQ25
CS4\
DQ30
I/O30
DQ10
I/O10
GND
I/O13
DQ13
I/O26
DQ26
NC
DQ29
I/O29
A14
DQ11
I/O11
DQ12
I/O12
A7
DQ27
I/O27
DQ28
I/O28
A16
A10
OE\
A12
A4
A1
A11
A9
A17
A20
NC
A5
A2
A0
A15
WE\
A13
A6
A3
A18
VCC
I/O7
DQ7
A8
NC
I/O23
DQ23
DQ0
I/O0
CS1\
DQ6
I/O6
I/O16
DQ16
CS3\
DQ22
I/O22
66 HIP
DQ1
I/O1
A19
I/O5
DQ5
I/O17
DQ17
GND
I/O21
DQ21
DQ2
I/O2
I/O3
DQ3
I/O4
DQ4
I/O18
DQ18
DQ19
I/O19
DQ20
I/O20
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8FLC2M32B is a 64Mb
FLASH Multi-Chip Module organized as 2M x 32 bits. The
module achieves high speed access, low power consumption
and high reliability by employing advanced CMOS memory
technology. The military grade product is manufactured in
compliance to the MIL-PRF-38534 specifications, making the
AS8FLC2M32B ideally suited for military or space applications.
The module is offered in a 68-lead 0.990 inch square ceramic
quad flat pack or 66-lead 1.185inch square ceramic Hex In-line
Package (HIP). The CQFP package design is targeted for those
applications, which require low profile SMT Packaging.
Q
P
Temperature Range
Full Mil (MIL-PRF-38534, Class H) /Q
Military Temp (-55oC to +125oC)
/XT
Industrial (-40oC to +85oC) /IT
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS8FLC2M32B
Rev. 1.2 5/09
57
14
I/O16
DQ16
I/O17
DQ17
I/O18
DQ18
[Package Designator P
H]
Package
Ceramic Quad Flat Pack
Ceramic Hex Inline Pack
13
31
•
•
•
•
•
•
64Mb device, total density, organized as 2M x 32
Bottom Boot Block (Sector) Architecture
(Contact factory for top boot)
Operation with single 3.0V Supply
Available in multiple Access time variations
Individual byte control via individual byte selects (CSx\)
Low Power CMOS
1,000,000 Erase/Program Cycles
Minimum 1,000,000 Program/Erase Cycles per sector
guaranteed
Sector Architecture:
• One 16K byte, two 8K byte, one 32K byte and
thirty-one 64Kbyte sectors (byte mode)
Any combination of sectors can be concurrently erased
MCM supports full array (multi-chip) Erase
Embedded Erase and Program Algorithms
Erase Suspend/Resume; Supports reading data from or
programming data to a sector not being Erased
TTL Compatible Inputs and Outputs
Military and Industrial operating temperature ranges
78
30
•
•
59
12
29
FEATURES
60
11
28
MIL-PRF-38534, Class H
10
27
•
I/O0
DQ0
I/O1
DQ1
DQ2
I/02
I/O3
DQ3
I/O4
DQ4
I/O5
DQ5
I/O6
DQ6
DQ7
I/O7
GND
DQ8
I/O8
DQ9
I/O9
DQ10
I/O10
DQ11
I/O11
DQ12
I/012
DQ13
I/O13
VCC
A11
A12
A13
A14
A15
A16
CS1\
OE\
CS2\
A17
WE2\
WE3\
WE4\
A18
A19
NC
A20
Available via Applicable Specifications:
07
09
64Mb, 2M x 32, 3.3Volt Boot Block FLASH
Array
08
RESET\
A0
A1
A2
A3
A4
A5
CS3\
GND
CS4\
WE1\
A6
A7
A8
A9
A10
VCC
Hermetic, Multi-Chip Module
(MCM)
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
FLASH
AUSTIN SEMICONDUCTOR, INC.
AS8FLC2M32
Austin Semiconductor, Inc.
before executing the erase operation. During erasure, the
device automatically times the erase pulse widths and verifies
proper cell margin.
BLOCK DIAGRAM
68-Ld. CQFP, Package "QT"
WE1\ CS1\
WE2\ CS2\
WE3\ CS3\
WE4\ CS4\
RESET\
OE\
A0-Ax
21M x 8
DQ
I/O0-7
21M x 8
21M x 8
21M x 8
DQ
I/O8-15
DQ
I/O16-23
DQ
I/O24-31
The host system can detect whether a program or erase
operation is complete by observing the RY/BY\ pin, or by
reading the DQ7 (Data\ Polling) and DQ6 (toggle) STATUS
BITS. After a program or erase cycle has been completed, the
device is ready to read array data or accept another command.
The SECTOR ERASE ARCHITECTURE allows memory
sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully erased
when shipped from ASI.
BLOCK DIAGRAM
P
66-Ld. HIP, Package "H"
CS2\
CS3\
Hardware data protection measures include a low VCC
detector that automatically inhibits WRITE operations during
power transitions. The hardware sector protection features
disables both program and erase operation in any combination
of the sectors of memory. This can be achieved in-system or
via specially adapted commercial programming equipment.
CS4\
WE\
RESET\
OE\
A0-Ax
21M x 8
DQ
I/O0-7
21M x 8
DQ
I/O8-15
21M x 8
DQ
DQ
I/O16-23
2
1M x 8
The ERASE SUSPEND feature enables the user to put erase on
hold for any period of time to read data from, or program data
to, any sector which is not selected for erasure. True
BACKGROUND ERASE can thus be achieved.
DQ
I/O24-31
The device requires only a single 3.3volt power supply for
both READ and WRITE operations. Internally generated and
regulated voltages are provided for the program and erase
functions.
The device is entirely command set compatible with the
JEDEC SINGLE POWER FASH STANDARD. Commands are
written to the command register using standard
microprocessor write timings. Register contents serve as
input to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch
addresses and data required for the programming or erase
function(s). Reading data out of the array is similar to reading
from other electrically programmable devices.
Device programming occurs by executing the program command
sequence. This initiates the EMBEDDED PROGRAM algorithm
that automatically times the WRITE PULSE widths and cycle
and verifies each cell for proper cell margins. The UNLOCK
BYPASS mode facilitates faster programming times by requiring
only two WRITE cycles to program data instead of four.
The HARDWARE RESET\ PIN terminates any operation in
progress and resets the internal state machine to a READ
operation. The RESET\ pin may be tied to the system reset
circuitry.
LOGIC DIAGRAM (Byte)
VCC
GND
DQ (byte)
RY/BY\
RESET\
WEx\
I/O Buffers
State
Control
Command
Register
Erase Voltage
Generator
PGM Voltage
Generator
Data Latch
Chip Enable
Output Enable
Logic
CSx\
OE\
Sector
Switches
VCC Detector
Timer
Address Latch
CS1\
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0-Ax
Device erasure occurs by executing the erase command
sequence. This initiates the Embedded Erase algorithm, an
internal algorithm that automatically pre-programs the array
AS8FLC2M32B
Rev. 1.2 5/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
FLASH
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
A system reset would then also reset the FLASH device,
enabling the system microprocessor to read the boot-up
firmware from the FLASH memory array. The device offers two
power-saving features. When addresses have been stable for
a specified amount of time, the device enters the AUTOMATIC
SLEEP MODE. The system can also place the device into the
STANDBY mode. Power consumption is greatly reduced in
both these modes.
AS8FLC2M32
the power transition. No command is necessary in this mode
to obtain array data. Standard microprocessor read cycles
that
assert valid data on the device address inputs produce valid
data on the data outputs. The device remains enabled for read
access until the command register contents are altered.
See READING ARRAY DATA for more information. Refer to
AC Read Operations table data for timing specifications
relevant to this operational mode.
Device Bus Operations
Writing Commands/Command Sequences
This section describes the use of the command register for
setting and controlling the bus operations. The command
register itself does not occupy any addressable memory
locations. The register is composed of a series of latches that
store the commands, addresses and data information needed
to execute the indicated command. The contents of the register
serve as the input to the internal state machine. The state
machine output dictates the function of the device. Table 1
lists the device bus operations, the inputs and control/stimulus
levels they require, and the resulting output. The following
subsections describe each of these operations in further detail.
To WRITE a command or command sequence, the system must
drive CSx\, WEx\ to VIL and OE\ to VIH.
An ERASE command operation can erase one sector, multiple
sectors, or the entire array. Table 2 indicates the address space
contained within each sector within the array. A sector address
consists of the address bits required to uniquely select a sector.
The “Command Definitions” section has details on erasure of
a single, multiple sectors, the entire array or suspending/
resuming the erase operation.
Requirements for Reading Array Data
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on each of the Data input/
output bits within each byte of the MCM FLASH array.
Standard read cycle timings apply in this mode. Refer to the
Autoselect Mode and Autoselect Command Sequence sections
for more information.
To read array data from the outputs, the system must drive the
CSx\ and OE\ pins to VIL. Chip Select CSx\ is the power and
chip select control of the byte or bytes targeted by the system
(user). Output Enable [OE\] is the output control and gates
array data to the output pins. Write (byte) Enables [WEx\]
should remain at VIH levels.
The internal state machine is set for reading array data upon
device power-up, or after a HARDWARE RESET. This ensures
that no spurious alteration of the memory content occurs during
ICC2 in the DC Characteristics table represents that active
current specification for the WRITE mode. The AC
Characteristics section contains timing specifications for Write
Operations.
Table 1
RESET\
CS1\
CS2\
CS3\
CS4\
L
H
H
H
D0-D7 Out
H
L
H
H
D8-D15 Out
H
H
L
H
H
H
H
L
L
L
L
L
L
H
H
H
L
H
H
H
D0-D7 In
H
L
H
H
H
L
H
H
D8-D15 In
H
H
L
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
L
L
L
VCC +/- 0.3V
VCC +/- 0.3V
VCC +/- 0.3V
VCC +/- 0.3V
X
X
X
X
X
Standby
H
H
VCC +/- 0.3V
WE1\ WE2\ WE3\ WE4\ OE\
H
H
H
H
L
OPERATION
READ
H
WRITE
D16-D31 In
D0-D31 In
L
L
L
L
H
H
H
H
H
Output Diable
X
X
X
X
X
X
X
X
Reset
L
L
L
L
L
L
L
L
H
Sector Protect
L
L
L
L
L
L
L
L
H
Sector Unprotect
X
X
X
X
X
X
X
X
X
Temporary Sector Unprotect
L=Logic=VIL, H=Logic High=VIH, VID=12.0 +/-0.5V, X= Don't Care, AIN=Address In, DOUT=Data Out
AS8FLC2M32B
Rev. 1.2 5/09
A0-Ax In
D24-D31 In
X
VID
Legend
Notes
D16-D31 Out
D0-D31 Out
L
VID
A0-Ax In
DATA BUS (DQ0-DQX)
D24-D31 Out
X
VID
ADDRESSES
X
X
X
SECTOR ADDRESS
A7=L, A2=H, A1=L
SECTOR ADDRESS
A7=L, A2=H, A1=L
AIN
DIN, DOUT
DIN, DOUT
DIN
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
FLASH
AS8FLC2M32
Program and Erase Operation Status
During an ERASE or PROGRAM operation, the system may
check the status of the operation by reading the status bits on
each of the seven data I/O bits within each byte of the MCM
FLASH array. Standard READ cycle timings and ICC read
specifications apply. Refer to “Write Operation Status” for
more information, and to “AC Characteristics” for timing
specifications.
The AUTOMATIC SLEEP mode is independent of the CSx\,
WEx\ and OE\ control signals. Standard address access timings
provide new data when addresses are changed. While in sleep
mode, output data is latched and always available to the system.
ICC5 in the “DC Characteristics Table represents the
AUTOMATIC SLEEP mode current usage.
RESET\: Hardware Reset Pin
Standby Mode
The RESET\ pin provides a hardware method of resetting the
When the system is not READING or WRITING to the device, device to reading array data. When the RESET\ pin is driven
it can place the device in the standby mode to save on power low for at least a period of tRP, the device immediately terminates
any operation in progress, tristates all output pins, and ignores
consumption.
all READ/WRITE commands for the duration of the RESET\
The device enters the CMOS STANDBY mode when the CSx\ pulse. The device also resets the internal state machine to
and RESET\ pins are held at VCC+/-0.3v. If CSx\ and RESET\ reading array data. The operation that was interrupted should
are held at VIH, but not within VCC+/-0.3v, the device will be in be reinitiated once the device is ready to accept another
STANDBY mode but at levels higher than achievable in full command sequence, to ensure data integrity.
CMOS STANDBY. The device requires standard access time
(tCE) for read access when the device is in either of these Current is reduced for the duration of the RESET\ pulse. When
RESET\ is held at VSS+/-0.3v, the device draws CMOS
STANDBY modes, before it is ready to READ data.
STANDBY current (ICC4). If RESET\ is held at VIL but not
If the device is deselected during ERASURE or within the limits of VCC +/- 0.3v, the MCM Array will be in
PROGRAMMING, the device draws active current until the STANDBY, but current limits will be higher than those listed
under ICC4.
operation is completed.
In the DC Characteristics table, ICC3 and ICC4 represent the The RESET\ pin may be tied to the system reset circuitry. A
system reset would thus also reset the FLASH array, enabling
STANDBY MODE currents.
the system to read the boot-up firmware code from the boot
block area of the memory.
Automatic Sleep Mode
The AUTOMATIC SLEEP mode minimizes FLASH device
energy consumption. The device automatically enables this
mode when addresses remain stable for tACC + 30ns.
AS8FLC2M32B
Rev. 1.2 5/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
If RESET\ is asserted during a PROGRAM or ERASE operation, the RY/BY\ pin remains a “0” (busy) until the internal
reset operation is complete, which requires a time of tREADY.
The system can thus monitor RY/BY\ to determine whether the
RESET operation is complete. If RESET\ is asserted when a
Autoselect Code Table
PROGRAM or ERASE operation is not executing (RY/BY\ pin
is “1”), the RESET operation is completed within a time of
tREADY. The system can read data tRH after the RESET\ pin
returns to VIH.
Refer to the “AC Characteristics” tables for RESET\ parameters.
Output Disable Mode
When the OE\ input is at VIH, output from the device is disabled.
The output pins are placed in the high Impedance State.
Autoselect Mode
AS8FLC2M32
identification, and sector protection verification through
identifier codes output via the appropriate Byte DQ’s. This
mode is primarily intended for programming equipment to
automatically match a device to be programmed with its
corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the
command register.
When using programming equipment (modified to support
multi-byte devices, or supplied from the programming
equipment provider as such), the autoselect mode requires
VID (11.5v to 12.5v) on address pin A9. Address pins A6, A1,
and A0 must be as shown in the Autoselect Table below. In
addtion, when verifying sector protection, the sector address
must appear on the appropriate highest order address bits.
When all necessary bits have been set as required, the
programming equipment may then read the corresponding
identifier code on the appropriate Byte DQ’s.
To access the autoselect codes in-system, the host system
can issue the autoselect command via the command register.
The autoselect mode provides manufacturer and device
AS8FLC2M32B
Rev. 1.2 5/09
FLASH
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
FLASH
AS8FLC2M32
Sector Address Table
Sector A20 A19 A18 A17 A16 A15 A14 A13
Sector Size
(Kbytes / Kwords)
Address Range (in
hexadecimal)
SA0
0
0
0
0
0
0
0
X
16/8
000000-003FFF
SA1
0
0
0
0
0
0
1
0
8/4
004000-005FFF
SA2
0
0
0
0
0
0
1
1
8/4
006000-007FFF
SA3
0
0
0
0
0
1
X
X
32/16
008000-00FFFF
SA4
0
0
0
0
1
X
X
X
64/32
010000-01FFFF
SA5
0
0
0
1
0
X
X
X
64/32
020000-02FFFF
SA6
0
0
0
1
1
X
X
X
64/32
030000-03FFFF
SA7
0
0
1
0
0
X
X
X
64/32
040000-04FFFF
SA8
0
0
1
0
1
X
X
X
64/32
050000-05FFFF
SA9
0
0
1
1
0
X
X
X
64/32
060000-06FFFF
SA10
0
0
1
1
1
X
X
X
64/32
070000-07FFFF
SA11
0
1
0
0
0
X
X
X
64/32
080000-08FFFF
SA12
0
1
0
0
1
X
X
X
64/32
090000-09FFFF
SA13
0
1
0
1
0
X
X
X
64/32
0A0000-0AFFFF
SA14
0
1
0
1
1
X
X
X
64/32
0B0000-0BFFFF
SA15
SA16
SA17
SA18
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
64/32
64/32
64/32
64/32
0C0000-0CFFFF
0D0000-0DFFFF
0E0000-0EFFFF
0F0000-0FFFFF
SA19
1
0
0
0
0
X
X
X
64/32
100000-10FFFF
SA20
1
0
0
0
1
X
X
X
64/32
110000-11FFFF
SA21
1
0
0
1
0
X
X
X
64/32
120000-12FFFF
SA22
1
0
0
1
1
X
X
X
64/32
130000-13FFFF
SA23
1
0
1
0
0
X
X
X
64/32
140000-14FFFF
SA24
1
0
1
0
1
X
X
X
64/32
150000-15FFFF
SA25
1
0
1
1
0
X
X
X
64/32
160000-16FFFF
SA26
1
0
1
1
1
X
X
X
64/32
170000-17FFFF
SA27
1
1
0
0
0
X
X
X
64/32
180000-18FFFF
SA28
1
1
0
0
1
X
X
X
64/32
190000-19FFFF
SA29
1
1
0
1
0
X
X
X
64/32
1A0000-1AFFFF
SA30
1
1
0
1
1
X
X
X
64/32
1B0000-1BFFFF
SA31
1
1
1
0
0
X
X
X
64/32
1C0000-1CFFFF
SA32
1
1
1
0
1
X
X
X
64/32
1D0000-1DFFFF
SA33
1
1
1
1
0
X
X
X
64/32
1E0000-1EFFFF
SA34
1
1
1
1
1
X
X
X
64/32
1F0000-1FFFFF
Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode
AS8FLC2M32B
Rev. 1.2 5/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
FLASH
AS8FLC2M32
Sector Protect Algorithm Flow
START
PLSCNT = 1
RESET# = VID
Wait 1 ms
Temporary Sector
Unprotect Mode
No
First Write
Cycle = 60h?
Yes
Set up sector
address
Sector Protect:
Write 60h to sector
address with
A7 = 0, A2 = 1,
A1 = 0
Wait 150 µs
Increment
PLSCNT
Verify Sector
Protect: Write 40h
to sector address
with A7 = 0,
A2 = 1, A1 = 0
Reset
PLSCNT = 1
Read from
sector address
with A7 = 0,
A2 = 1, A1 = 0
No
No
PLSCNT
= 25?
Data = 01h?
Yes
Yes
Yes
Device failed
Protect another
sector?
No
Remove VID
from RESET#
Write reset
command
Sector Protect
Algorithm
AS8FLC2M32B
Rev. 1.2 5/09
Sector Protect
complete
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
FLASH
AS8FLC2M32
Sector Un-Protect Algorithm Flow
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
PLSCNT = 1
RESET# = VID
Wait 1 ms
First Write
Cycle = 60h?
No
Temporary Sector
Unprotect Mode
Yes
No
All sectors
protected?
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with
A7 = 1, A2 = 1,
A1 = 0
Wait 15 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A7 = 1, A2 = 1,
A1 = 0
Increment
PLSCNT
Read from
sector address
with A7 = 1,
A2 = 1, A1 = 0
No
PLSCNT
= 1000?
Data = 00h?
Yes
Yes
Device failed
Set up
next sector
address
No
Last sector
verified?
No
Yes
Sector Unprotect
Algorithm
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
AS8FLC2M32B
Rev. 1.2 5/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
FLASH
AS8FLC2M32
Temporary Sector Unprotect
Write Pulse “GLITCH” Protection
This feature allows temporary un-protection of previously
protected sectors to change data in-system. Setting the RESET\
pin to VID activates the sector Unprotect mode. During this
mode, formerly protected sectors can be programmed or erased
by selecting the sector addresses. Once VID is removed from
the RESET\ pin, all the previously protected sectors are
protected again. The diagram below depicts the algorithm
flow for this operation.
Noise pulses of less than 5ns (typical) on OE\, CSx\ or WEx\ do
not initiate a WRITE cycle.
Logical Inhibit
WRITE cycles are inhibited by holding any one of OE\=VIL,
CSx\=VIH or WEx\=VIH. To initiate a WRITE cycle, CSx\ and
WEx\ must be a logical zero while OE\ is a logical one.
Power-Up WRITE Inhibit
If WEx\=CSx\=VIL and OE\=VIH during power-up, the device
does not accept commands on the rising edge of WEx\. The
internal state machine is automatically reset to READING array
data on power-up.
Temporary Sector Unprotect Diagram
Start
Command Definitions
RESET\ = VID
(Note 1)
Writing specific address and data commands or sequences
into the command register initiates device operations. The
COMMAND REGISTER TABLE defines the valid register
command sequences for this device Module. WRITING
incorrect address and data values or WRITING them in the
improper sequence resets the device to READING array data.
Perform Erase or
Program
Operations
RESET\ = VIH
All addresses are latched on the falling edge of WEx\ or CSx\,
whichever happens later. All data is latched on the rising edge
of WEx\ or CSx\, whichever happens first. Refer to the AC
timing references for correct timings of the appropriate signals.
Temporary Sector
Unprotect
Completed
(Note 2)
Reading Array Data
The device is automatically set to READING Array data after
device power-up. No commands are required to retrieve data.
The device is also ready to READ data after completing an
Embedded Program or Embedded Erase operation.
NOTES:
1. All protected sectors unprotected
2. All previously protected sectors are
protected once again
Hardware Data Protection
The command sequence requirements of UNLOCK cycles for
PROGRAMMING or ERASING provides data protection
against inadvertent WRITES. In addition, the following
hardware data protection measures prevent accidental
ERASURE or PROGRAMMING, which might otherwise be
caused by spurious system level signals during VCC powerup and power-down transitions, or from system noise.
After the device accepts an ERASE Suspend command, the
device enters the ERASE Suspend Mode. The system can
read array data using the standard READ timings, except that
if it READS at an address within Erase-Suspended sectors, the
device outputs status data. After completing a programming
operation in the Erase Suspend Mode, the system may once
again READ array data with the same exception.
Low VCC WRITE Inhibit
The system must issue the reset command to re-enable the
device for reading array data if DQ5, DQ13, DQ21 and DQ29
goes high, or while in the autoselect mode.
When VCC is less than VLKO, the device does not accept any
WRITE cycles. This protects data during VCC power-up and
power-down. The system must provide the proper signals to
the control pins to prevent unintentional WRITES when VCC
is greater than VLKO.
AS8FLC2M32B
Rev. 1.2 5/09
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9
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
Reset Command
WRITING the reset command to the device resets the device
to reading array data. Address bits are don’t care for this
command.
The RESET command may be WRITTEN between the sequence
cycles in an ERASE command sequence before ERASING
begins. This resets the device to READING array data. Once
ERASURE begins, the device ignores RESET command
requests until the first initiation of the operation has completed.
The RESET command may be WRITTEN between the sequence
cycles in a program command sequence and before
programming begins. This RESETS the device to READING
Array data. Once programming begins, the device ignores
additional RESET command requests until the current operation
has completed.
The RESET command may be written between the sequence
cycles in an Autoselect command sequence. Once in the
Autoselect Mode, the reset command must be WRITTEN to
return to READING Array data.
Autoselect Command Sequence
The Autoselect command sequence allows the host system to
access the manufacturer and device codes, allowing the user
determination as to whether or not a Sector is protected. This
method is an alternative to DEVICE PROGRAMMERS but
requires VID on Address bit 9 (A9).
The Autoselect command sequence is initiated by WRITING
two UNLOCK cycles, followed by the AUTOSELECT
COMMAMD. The device then enters the AUTOSELECT
mode, and the system may read at any address, any number of
times, without initiating another command.
A READ cycle at Address XX00h retrieves the manufacturer
code. A READ cycle at Address XX01h returns the device
code. A READ cycle containing a Sector Address (SA) and
the address 02h returns 01h if that sector is protected, or 00h if
it is un-protected.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock WRITE
cycles, followed by the PROGRAM set-up command. The
program address and data are WRITTEN next, which in turn
initiates the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device
automatically provides internally generated PROGRAM pulses
and verifies the programmed cell margin.
AS8FLC2M32B
Rev. 1.2 5/09
FLASH
AS8FLC2M32
When the Embedded Program algorithm is complete, the device
then returns to READING array data and addresses are no
longer latched. The system can determine the status of the
program operation by using DQ31, DQ30, DQ23, DQ22, DQ15.
DQ14, DQ7, DQ6, or RY/BY\.
Any commands WRITTEN to the device during the Embedded
Program algorithm are ignored. Note that a HARDWARE
RESET immediately terminates the programming operation. The
Byte Program command sequence should be reinitiated once
the device has reset to READING Array data, to ensure data
integrity.
PROGRAMMING is allowed in any sequence and across
Sector Boundaries. A bit cannot be PROGRAMMED from a
“0” back to a “1”, this can only be accomplished via an ERASE
operation.
Unlock Bypass Command Sequence
The UNLOCK BYPASS feature allows the system to program
bytes or words to the device faster than using the standard
program command sequence. The UNLOCK BYPASS command
sequence is initiated by first WRITING two UNLOCK cycles.
This is followed by a third WRITE cycle containing the
UNLOCK BYPASS command, 20h. The device then enters the
UNLOCK BYPASS mode. A two-cycle UNLOCK BYPASS
command operation is all that is required to PROGRAM in this
mode. The first cycle in this sequence contains the UNLOCK
BYPASS program command, A0h; the second cycle contains
the program address and data. Additional data is
PROGRAMMED in the same manner. This mode dispenses
with the initial two UNLOCK cycles required in the standard
PROGRAM command sequence. The first cycle must contain
the data 90h; the second cycle the data 00h. Addresses are
don’t care fore both cycles. The device then returns to
READING Array data.
Chip Erase Command Sequence
CHIP ERASE is a six-bus cycle operation. The CHIP ERASE
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional UNLOCK
WRITE cycles are then followed by the chip ERASE command,
which in turn invokes the Embedded ERASE algorithm. The
device does not require the system to PRE-PROGRAM prior to
ERASE. The Embedded ERASE algorithm automatically PREPROGRAMS and VERIFIES the entire Array for an all Zero
data pattern prior to electrical ERASE. The system is not
required to provide any controls or timing during these
operations.
Any commands WRITTEN to the chip during the Embedded
ERASE operation are ignored. Note that a HARDWARE RESET
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AUSTIN SEMICONDUCTOR, INC.
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Any commands WRITTEN to the chip during the Embedded
ERASE operation are ignored. Note that a HARDWARE RESET
during the chip erase operation immediately terminates the
operation. The CHIP ERASE command sequence should be
reinitiated once the device has returned to READING Array
data, to ensure data integrity.
The system can determine the status of the erase operation by
using byte data from each of the four bytes or the RY/BY\ pin.
When the Embedded ERASE Algorithm is complete, the device
returns to READING Array data and Addresses are no longer
latched.
Sector Erase Command Sequence
SECTOR ERASE is a six-bus cycle operation. The SECTOR
ERASE command sequence is initiated by WRITING two
UNLOCK cycles, followed by a SET-UP command. Two
additional UNLOCK WRITE cycles are then followed by the
address of the sector to be ERASED, and the SECTOR ERASE
command.
The device does not require the system to PREPROGRAM the
memory prior to ERASE. The Embedded ERASE Algorithm
automatically PROGRAMS and verifies the sector for an all
zero data pattern prior to electrical ERASE. The system is not
required to provide any controls or timings during these
operations.
After the command sequence is WRITTEN, a SECTOR ERASE
time-out of 50uS begins. During the time-out period, additional
Sector Addresses and SECTOR ERASE commands may be
WRITTEN. Loading the SECTOR ERASE buffer may be done
in any sequence and the number of sectors may be from one
sector to all sectors. The time between these additional cycles
must be less than 50uS, otherwise the last address and command
might not be accepted, and erasure may begin. It is
recommended that processor interrupts be disabled during this
time to ensure all commands are accepted. The interrupts can
be re-enabled after the last SECTOR ERASE command is
WRITTEN. If the time between additional SECTOR ERASE
commands can be assumed to be less than 50uS, the system
need not monitor DQ3, DQ11, DQ19 or DQ27 to determine if
the SECTOR ERASE has timed out. The time-out begins from
the rising edge of the final WEx\ pulse in the command
sequence.
Once the SECTOR ERASE operation has begun, only the
ERASE SUSPEND command is valid. All other commands are
ignored. Note that a HARDWARE RESET during the SECTOR
ERASE operation immediately terminates the operation. The
SECTOR ERASE command sequence should be reinitiated
once
AS8FLC2M32B
Rev. 1.2 5/09
FLASH
AS8FLC2M32
When the Embedded Erase Algorithm is complete, the device
returns to READING Array data and addresses are no longer
latched. The system can determine the status of the ERASE
operation by using DQ2, DQ6, and DQ7 of Byte 1; DQ10, DQ14
and DQ15 of Byte 2; DQ18, DQ22 and DQ23 of Byte 3 as well as
DQ26, DQ30 and DQ31 of Byte 4. In addition to the Data IO
indicators, the system/user my monitor RY/BY\ for the status
of the operation.
Erase Suspend/Erase Resume Commands
The ERASE SUSPEND command allows the system to interrupt
a SECTOR ERASE operation and then READ data from, or
PROGRAM data to, any sector not selected for ERASURE.
This command is valid only during the SECTOR ERASE
command sequence. The ERASE SUSPEND command is
ignored if WRITTEN during the CHIP ERASE operation or
Embedded Program algorithm. WRITING the ERASE
SUSPEND command during the SECTOR ERASE time-out
immediately terminates the time-out period and SUSPENDS
the ERASE operation. Addresses are “don’t-cares” when
WRITING the ERASE SUSPEND command.
When the ERASE command is WRITTEN during a SECTOR
ERASE operation, the device requires a maximum of 20us to
SUSPEND the ERASE operation. However, when the ERASE
SUSPEND command is WRITTEN during the SECTOR ERASE
time-out, the device immediately terminates the time-out period
and SUSPENDS the ERASE operation.
After the ERASE operation has been SUSPENDED, the system
can READ Array data from or PROGRAM data to any sector
not selected for ERASURE. Normal READ and WRITE timings
and command definitions apply. READING at any Address
within ERASE-SUSPENDED sectors produces status data on
three DQ pins within each Byte. DQ2, DQ6, and DQ7 of Byte 1;
DQ10, DQ14 and DQ15 of Byte 2; DQ18, DQ22 and DQ23 of
Byte 3 as well as DQ26, DQ30 and DQ31 of Byte 4 to determine
if a sector is actively ERASING or is ERASE-SUSPENDED.
After and ERASE-SUSPENDED program operation is complete,
the system can once again READ from or WRITE to within
non-suspended sectors. The system can determine the status
of the PROGRAM operation using the DQ6, 7 bits of Byte 1;
DQ14, 15 of Byte 2; DQ22, 23 of Byte 3 and DQ30, 31 of Byte 4;
just as in the standard PROGRAM operation.
The system may also write the auto select command sequence
when the device is in the ERASE SUSPEND mode. The device
allows READING autoselect codes even at addresses within
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11
FLASH
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
ERASING sectors, since the codes are not stored in the memory
Array. When the device exits the Autoselect mode, the device
reverts to the ERASE SUSPEND mode, and is ready for another
valid operation.
AS8FLC2M32
Data\ Polling Algorithm Diagram
Start
The system must WRITE the ERASE RESUME command to
exit the ERASE SUSPEND mode and continue the SECTOR
ERASE operation. Further WRITES of the RESUME command
are ignored. Another ERASE SUSPEND command can be
WRITTEN after the device has resumed ERASING.
READ Byte Data
Address = VA
Erase Operation Diagram
READ Byte Data
Address = VA
DQ7, DQ15, YES
DQ23, DQ31=
Data?
DQ7, DQ15, YES
DQ23, DQ31=
Data?
NO
NO
Start
Write ERASE
Command
Sequence
FAIL
NO
PASS
DQ5, DQ13,
DQ21,
DQ29=1?
YES
Data Poll from
System
NO
Algorithm is complete, the device outputs the datum
PROGRAMMED into each of these status bits. The system
must provide the PROGRAM address to READ valid status
information. If a PROGRAM address fails within a protected
sector, Data\ Polling is active for approximately 1uS, then the
device returns to reading array data.
Data = FFh?
YES
ERASURE
Completed
Write Operation Status
The device provides several bits to determine the status of a
write operation: DQ2, DQ3, DQ5, DQ6 and DQ7 of Byte 1;
DQ10, DQ11, DQ13, DQ14 and DQ15 of Byte 2; DQ18, DQ19,
DQ21, DQ22 and DQ23 of Byte 3; as well as, DQ26, DQ27,
DQ29, DQ30 and DQ31 of Byte 4. In addition, the RY/BY\ pin
is also used in the monitoring of this operation.
During the Embedded Erase Algorithm, Data\ Polling produces
a “0” on the Data\ Polling Status bits. When the Embedded
ERASE Algorithm is complete, or if the device enters the ERASE
SUSPEND mode, Data\ Polling produces a “1” on each of the
Data\ Polling status bits. This is analogous to the complement/
true data output described for the Embedded Program
Algorithm: the ERASE function changes all the bits in a sector
to “1”; prior to this, the device outputs the “compliment”, or
“0”. The system must provide an address within any of the
sectors selected for ERASURE to READ valid status
information.
DQ7, DQ15, DQ23 and DQ31: Data\ Polling
The Data\ Polling bit per byte, indicates to the host system
whether an Embedded Algorithm is in progress or completed,
or whether the device is in ERASE SUSPEND. Data\ Polling is
valid after the rising edge of the final WEx\ pulse in the
PROGRAM or ERASE command sequence.
During the Embedded Program Algorithm, the device outputs
on DQ7 for Byte 1, DQ15 for Byte 2, DQ23 for Byte 3, and DQ31
for Byte 4, the complement of the datum programmed to each
of these bits. This status also applies to the PROGRAMMING
during ERASE SUSPEND. When the Embedded Program
AS8FLC2M32B
Rev. 1.2 5/09
After an ERASE Command sequence is WRITTEN, if all s4ctors
selected for erasing are protected, Data\ Polling is active for
approximately 100uS, then the device returns to READING
array data. If not all selected sectors are protected, the
Embedded ERASE Algorithm ERASES the unprotected sectors,
and ignores the selected sectors that are protected.
When the system detects a Data\ Polling status bit has changed
from the complement to true data, it can READ valid data at
each of the Bytes on the following READ cycles. This is
because
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12
FLASH
AUSTIN SEMICONDUCTOR, INC.
AS8FLC2M32
Austin Semiconductor, Inc.
Command Sequence
(Note 1)
Read (Note 5)
Reset (Note 6)
Manufacturer ID
Auto-Select
Device ID, Btm. Boot
(Note 7)
Sector Protect Verify
(Note 8)
Program
Unlock Bypass
Unlock Bypass Program
(Note 9)
Unlock Bypass Reset
(Note 10)
Chip Erase
Sector Erase
Erase Suspend (Note 11)
Erase Resume (Note 12)
Cycles
Command Definition Table
First
1
1
4
Addr
RA
XXX
AAA
Data
RD
F0
AA
4
4
AAA
AAA
4
3
2
Second
Addr
Data
Bus Cycles (Notes 2-4)
Third
Fourth
Addr
Data
Addr
Data
555
55
AAA
90
X00
1
AA
AA
555
555
55
55
AAA
AAA
90
90
AAA
AAA
XXX
AA
AA
A0
555
555
PA
55
55
PD
AAA
AAA
A0
20
X01
(SA)
X04
PA
37
0
1
PD
2
XXX
90
XXX
0
6
6
1
1
AAA
AAA
XXX
XXX
AA
AA
B0
30
555
555
55
55
AAA
AAA
80
80
AAA
AAA
AA
AA
Fifth
Sixth
Addr
Data
Addr
Data
555
555
55
55
AAA
SA
10
30
Legend:
X= Don't Care
RA = Address of the memory location to be read
RD = Data read from location RA during read operation
PA = Address of the memory location to be programmed. Addresses latched on the falling edge of the Wex\ or Cex\ pulse, whichever occurs later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever occurs later.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20-A13 uniquely select any sector.
Notes:
1.See Table 1 for Valid Bus Operations.
2.All values in hexadecimal.
3.Except when reading array or autoselect data, all bus cycles are write operations
4.Data bits A20-A11 are don’t cares for unlock and command cycles
5.No unlock or command cycles required when reading array data.
6.The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ% goes high (while the device is providing status data).
7.The fourth cycle of the autoselect command sequence is a read cycle
8.The data is 00h for an unprotected sector and 01h for a protected sector.
9.The Unlock Bypass command is required prior to the Unlock Bypass Program command.
10.The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.
11. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase operation.
12. The Erase Resume command is valid only during the Erase Suspend mode.
*Data is for single byte.
BYTE 1 = DQ0 - DQ7
BYTE 2 = DQ8 - DQ15
BYTE 3 = DQ16 - DQ23
BYTE 4 = DQ24 - DQ31
AS8FLC2M32B
Rev. 1.2 5/09
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13
AUSTIN SEMICONDUCTOR, INC.
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DQ7, DQ15, DQ23 and DQ31 may change asynchronously with
the 7 lower order bits within each Byte, while the OEx\ pins are
asserted Low.
FLASH
AS8FLC2M32
If a program address falls within a protected sector, DQ6, 14,
22, and or DQ30 will toggle for approximately 1us after the
PROGRAM command sequence is WRITTEN, then returns to
READING Array data.
RY/BY\: Ready/Busy\
The RY/BY\ pin is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in the progress or
complete. The RY/BY\ status is valid after the rising edge of
the final WEx\ pulse in the command sequence has terminated.
Since the RY/BY\ is an open-drain output, the Byte Ready/
Busy pins are wire-or’d together, indicating the Ready/Busy
status of the Four-Byte module.
If the output is low (BUSY), the device is actively ERASING or
PROGRAMMING. If the output is high (READY), the device is
ready to READ array data, or is in the STANDBY mode.
DQ6, DQ14, DQ22 and DQ30: Toggle Bit 1
Toggle Bit 1 indicates whether an Embedded Program or Erase
Algorithm is in progress, complete, or has entered the ERASE
SUSPEND mode. Toggle Bit 1 may be read at any address and
is valid after the rising edge of the final WEx\ pulse in the
command sequence as well as during the sector ERASE timeout.
During an Embedded Program or Erase Algorithm operation,
successive READ cycles that access any address will cause
this status indicator to toggle. When the operation is complete,
the status bit will stop toggling.
After an ERASE command sequence is WRITTEN, if all sectors
selected for ERASING are protected, the toggle bit(s) will toggle
for approximately 100uS, then will become steady state as the
device returns to READING array data. If not all selected sectors
are protected, the Embedded Erase Algorithm will cause
ERASURE of unprotected sectors, ignoring the selected sectors
that are protected.
The System can use DQ2, DQ6 of Byte 1; DQ10, DQ14 of Byte
2; DQ18, DQ22 of Byte 3; DQ26, DQ30 of Byte 4 together to
determine whether a sector is actively ERASING or is ERASE
SUSPENDED. When the device is actively ERASING the DQ6
of Byte 1; DQ14 of Byte 2; DQ22 of Byte 3 and DQ30 of Byte 4
toggles and when the devices enters ERASE SUSPEND, the
status bit returns to a steady state. However, the system must
also use DQ2 of Byte 1; DQ10 of Byte 2, DQ18 of Byte 3 and
DQ26 of Byte 4 to determine which sectors are ERASING or
ERASE SUSPENDED in each of the Bytes contained in the
Module. Alternatively DQ7, DQ15, DQ23 and DQ31 can be used
(see DQ7, DQ15, DQ23, DQ31 Data\ Polling).
AS8FLC2M32B
Rev. 1.2 5/09
DQ6, 14, 22, and or DQ30 also toggles during the ERASE
SUSPEND program mode, stops toggling once the operation
is complete.
DQ2, DQ10, DQ18 and DQ26: Toggle Bit II
The “Toggle Bit II” on each of the Bytes, when used with DQ6,
14, 22, and DQ30 indicates whether a particular sector is actively
ERASING or whether that sector is ERASE-SUSPENDED.
Toggle Bit II is valid after the rising edge of the final WEx\
pulse in the command sequence.
DQ2, 10, 18 and or DQ26 toggles when the system READS at
addresses within those sectors that have been selected for
ERASURE, but does not indicate when a sector is being
ERASED. DQ6, 14, 22 and DQ30 by comparison indicates that
a device is actively ERASING or in ERASE SUSPEND, but
cannot distinguish which sectors are selected for the operation,
therefore both status bits are required for sector and mode
information.
Reading Toggle Bits I/II
Whenever the system initially begins READING toggle bit
statuses, it must READ Byte data (ie…DQ0-7, DQ8-15, DQ1623 and or DQ24-31) at least twice in a row to determine whether
a Toggle Bit is toggling. Typically, the system would note and
store the value of the toggle bit after the first READ. After the
second READ, the system would compare the new value of
the Toggle Bit with the first. If the toggle bit is not toggling the
device has completed the PROGRAM or ERASE operation.
The system can READ array data on each Byte during the next
READ cycle.
If after the initial two READ cycles, the system determines that
the toggle bit is still toggling, the system also should note
whether the value of DQ5, 13, 21 and or DQ29 is High. If High,
the system should then determine again whether the toggle
bit(s) are again toggling, since the toggle bit may have indeed
stop toggling just as DQ5, 13, 21 and or DQ29 went High. If the
toggle bit is no longer toggling, the device has successfully
completed the operation. If the toggle bit is still active
(toggling), the device has not successfully completed the
operation and the system must WRITE the RESET command
to return to READING array data.
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14
AUSTIN SEMICONDUCTOR, INC.
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The remaining scenario is that the system initially determines
that the toggle bit is toggling and DQ5, 13, 21, and or DQ29 has
not gone High. The system may continue to monitor the toggle
bit and DQ5, 13, 21, and or DQ29 through successive READ
cycles, determining the status as described in the previous
paragraph. Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the beginning of
the Algorithm when it returns to determine the status of the
operation.
Toggle Bit Algorithm Diagram
Start
READ(#1) Byte
Data from Byte1, 2,
3 and or 4
DQ5, 13, 21, and or DQ29 indicates whether the PROGRAM or
ERASE time has exceeded a specified internal pulse count limit.
Under these conditions this will produce a logic level “1” High.
This is a failure condition that indicates the PROGRAM or
ERASE cycle was not successfully completed.
The DQ5, 13, 21 and or DQ29 failure condition may appear if
the system tries to PROGRAM a “1” to a location that was
previously PROGRAMMED to a logic level “0” Low. Only an
ERASE operation can change a logic level “0” back to a Logic
Level “1”. Under this condition, the device halts operation
and when the operation has exceeded the timing limits, DQ5,
13, 21, and or DQ29 will produce a logic level “1”.
After WRITING a Sector Erase command sequence, the system
may read this status bit or bits to determine whether or not an
ERASE operation has begun. If additional sectors are selected
for ERASURE, the entire time-out also applies after each
additional Sector Erase command. When the time-out is
complete, this status bit or bits changes from a logic level “0”
to “1”. The system may ignore this status bit if the system can
guarantee that the time between additional Sector Erase
command will always be less than 50us.
NO
DQ5, 13, 21
and or DQ29 =
"1"
After the Sector Erase command sequence is WRITTEN, the
system should read the status on DQ7, 15, 23 and or DQ31
(Data\ Polling) or DQ6, 14, 22, and or DQ30 (Toggle Bit I) to
ensure the device has accepted the command sequence. Then
READ DQ3, 11, 19 and or DQ27, looking for this bit or bits to be
a logic level “1”. If this bit is a logic level “1”, the internally
controlled ERASE cycle has begun; all further commands are
ignored until the ERASE operation is complete. If this bit is a
logic level “0”, the device will accept additional Sector Erase
commands. To ensure the command has been accepted, the
system software should check the status of DQ3, 11, 19 and or
DQ27 prior to and following each subsequent Sector Erase
command. If this bit or bits is a logic level “1” on the second
status check, the last command might not have been accepted.
YES
READ(#1) Byte
Data from Byte1, 2,
3 and or 4
READ(#2) Byte
Data from Byte1, 2,
3 and or 4
Toggle Bit =
Toggle?
DQ5,13,21,and or DQ29: Exceeding Timing Limits
DQ3, 11, 19, and or DQ27: Sector Erase Timer
YES
NO
AS8FLC2M32
Under both of these conditions, the system must issue the
RESET command to return to reading array data.
READ(#2) Byte
Data from Byte1, 2,
3 and or 4
Toggle Bit =
Toggle?
FLASH
NO
YES
Operation Not
Complete, WRITE
RESET Command
AS8FLC2M32B
Rev. 1.2 5/09
PROGRAM/
ERASE Complete
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
15
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AUSTIN SEMICONDUCTOR, INC.
AS8FLC2M32
Austin Semiconductor, Inc.
Pin Description/Assignment Table
Signal Name
Address
Type
Input
Output Enable
Symbol
A0, A1, A2. A3,
A4, A5, A6, A7
A8, A9, A10, A11
A12,A13,A14,A15
A16,A17,A18,A19
CS1\, CS2\
CS3\, CS4\
WE1\, WE2\
WE3\, WE4\
OE\
Reset
RESET\
Input
Power Supply
VCC
Ground [Core]
VSS
Data Input, Output
I/O0,I/O1,I/O2
Input/
Output
I/O3,I/O4,I/O5
I/O6,I/O7,1/O8
I/O9,I/O10,I/O11
I/O12,I/O13,I/O14
I/O15,I/O16,I/O17
I/O18,I/O19,I/O20
I/O21,I/O22,I/O23
I/O24,I/O25,I/O26
I/O27,I/O28,I/O29
I/O30,I/O31
NC
OPEN
Chip Selects
Write Enables
No Connection
Input
Input
Input
Pin DEF/Package=QT
8, 7, 6, 5,
4, 3, 66, 65,
64, 63, 62, 28,
29,30,31,32,
33,37,41,42
34, 36,
2, 68
67, 38,
39, 40
35
Symbol
Pin DEF/Package=H
A0, A1, A2. A3,
7, 60, 61, 62, 49, 50,
A4, A5, A6, A7
51, 37, 41, 17, 16, 6,
A8, A9, A10, A11
38, 40, 4, 18, 5, 28,
A12,A13,A14,A15
8, 21
A16,A17,A18,A19
CS1\, CS2\
20, 13, 53, 46
CS3\, CS4\
WE\
29
3.
Active Low True Output Enable (x32)
9
RESET\
12
Active Low True Reset
Input
61,27
VCC
19, 45
Power for Core and I/O
Input
1,52,18
VSS
14, 54
Digital GND
10,11,12,13,14,15,
16,17,19,20,21,22,
23,24,25,26,60,59,
58,57,56,55,54,53,
51,50,49,48,47,46,
45,44
I/O0,I/O1,I/O2
I/O3,I/O4,I/O5
I/O6,I/O7,1/O8
I/O9,I/O10,I/O11
I/O12,I/O13,I/O14
I/O15,I/O16,I/O17
I/O18,I/O19,I/O20
I/O21,I/O22,I/O23
I/O24,I/O25,I/O26
I/O27,I/O28,I/O29
I/O30,I/O31
NC
43
9, 10, 11, 22, 33, 32, Data Input, Output
31, 30, 1, 2, 3, 15
26, 25, 24, 23, 42, 43
44, 55, 66, 65, 65, 63
34, 35, 36, 42, 43, 44,
55, 66, 65, 64, 63,
34, 35, 48, 59, 58,
57, 56
47, 52, 39
No internal connection
Test Conditions
Max.
Units
4
V
12.5
V
VCC+0.5
V
VDDQ+0.5
V
200
mA
150
85
125
ο
C
ο
C
C
Test Specifications
Parameter
-70/-90 -100/-120
Output Load
1 TTL Gate
Output Load Capacitance,
30
100
CL (including Jig)
5
Input Rise and Fall Times
0.0-3.0
Input Pulse Levels
Input timing measurement
1.5
reference levels
Output timing measurement
1.5
reference levels
Units
pF
ns
V
V
V
ο
Minimum DC voltage on any Input or Input/Output pin is
–0.5v. During voltage transitions, input or input/output
pins may undershoot VSS to –2.0v for periods of up to
20ns.
Minimum DC input/output voltage on pins A9, OE\, and
RESET\ is-0.5v. During voltage transitions, A9, OE\, and
RESET\ may undershoot VSS to –2.0v for periods of up to
20ns. Maximum DC input voltage on pin A9 is +12.5v
which may overshoot to 14.0v for periods up to 20ns.
No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one (1) second.
*Stress greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum conditions for any duration or segment of time
may affect device reliability.
AS8FLC2M32B
Rev. 1.2 5/09
Active Low True Write Enable(s)
27
Absolute Maximum Ratings
Parameter
Symbol
Min.
-0.5
Voltage on VDD Pin (Note 1)
VCC
-0.5
Voltage on A9, OE\,
VCNTL
and RESET\ (Note 2)
-0.5
Voltage on Input Pins
VIN
-0.5
Voltage on I/O Pins
VIO
Output Short Circuit Current
ISC
(Note 3)
-65
Storage Temperature
tSTG
-40
Operating Temperatures
/IT
-55
[Screening Levels]
/XT
2.
Active Low True Chip Selects (Enables)
OE\
Absolute Maximum Ratings*
1.
Description
Address Inputs
Test Set-Up
3.3v
Device
Under
Test
1N3064
CL
6.2K
ohm
1N3064
1N3064
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16
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AUSTIN SEMICONDUCTOR, INC.
AS8FLC2M32
Austin Semiconductor, Inc.
DC Electrical Characteristics
Symbol
ILI
ILIT
ILO
Parameter
Input Load Current
A9 Input Load Current
Output Leakage Current
ICC1
Vcc Active Read Current
CE\=VIL, OE\=VIH
ICC2
VCC Active Write Current
ICC3
ICC4
ICC5
Automatic Sleep Mode
VIH=VCC +/- 0.3v, VIL=VSS +/- 0.3v
VIL
VIH
Input Low Voltage
Input High Voltage
Voltage for Autoselect and
Temporary Sector Unprotect
Output Low Voltage
VID
VOL
VOH1
VOH2
VLKO
Max
+/- 5.0
160.0
+/-5.0
120
70
Units
uA
uA
uA
mA
mA
Notes
CE\=VIL, OE\=VIH
140
mA
2,3,5
VCC Standby Current
CE\, RESET\=VCC +/- 0.3V
150
uA
2
VCC Standby Current During
Reset
RESET\=VCC +/- 0.3v
150
uA
2
150
uA
2,4
Ouput High Voltage
Test Conditions
Min
Vin=Vss to Vcc, Vcc=Vcc MAX
Vcc=Vcc Ma,; A9=12.5v
VOUT=VSS to VCC, VCC=VCC MAX
14Mhz
8Mhz
-0.5
0.8
0.7xVCC VCC+0.3
11.5
VCC=3.3v
IOL=4.0mA, VCC=VCC MIN
IOH=-2.0mA, VCC=VCC MIN
IOH=-100uA, VCC=VCC MIN
Low VCC Lock-Out Voltage
2.4
VCC-0.4
2.3
1,2
1,2
V
V
12.5
V
0.45
V
V
2.5
V
4
Notes:
[1]
[2]
[3]
[4]
[5]
AS8FLC2M32B
Rev. 1.2 5/09
The ICC current listed is typically less than 8mA/Mhz, with OE\ at VIH
Maximum ICC specifications are tested with VCC=VCC MAX
ICC active while Embedded Program or Embedded Erase Algorithm is in progress
Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns
Not 100% Tested
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17
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AS8FLC2M32
Austin Semiconductor, Inc.
AC Switching Characteristics
Parameter
Symbol
JEDEC Standard
Hardware Reset
RESET\ Low to READ or WRITE (Embedded Algorithms)
RESET\ Low to READ or WRITE (Not Embedded)
RESET\ Pulse Width
RESET\ High time before READ
RESET\ Low to Standby Mode
RY/BY\ Recovery time
Erase/Program Operations
WRITE cycle time
Address Setup time
Address Hold time
Data Setup time
Data Hold time
Output Enable Setup time
READ Recovery time before WRITE (OE\ High to WEx\ Low)
CSx\ Setup time
CSx\ Hold time
WRITE Pulse width
WRITE Pulse Width High
Programming Operation
Sector Erase Operation
VCC Setup time
Recovery time from RY/BY\
Program/Erase Valid to RY/BY\ delay
-70
Min.
-90
Max.
Min.
tREADY
tREADY
tRP
tRH
tRPD
tRB
tAVAV
tAVWL
tWLAX
tDVWH
tWHDX
tWC
tAS
tAH
tDS
tDH
tOES
tGHWL
tGHWL
tELWL
tCS
tWHEH
tCH
tWLWH
tWP
tWHWL
tWPH
tWHWH1 tWHWH1
tWHWH2 tWHWH2
tVCS
tRB
tBUSY
Read Operations
READ Cycle time
Address to Output delay
CSx\ Low to Output delay
OE\ Low to Output delay
CSx\ Low to Output High-Z
OE\ Low to Output High-Z
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGLQZ
READ
OE\ Low Hold time
Toggle and Data Polling
Output Hold time from Addresses, CSx\ or OE\
tAXQX
tRC
tACC
tCE
tOE
tDF
tDF
-100
Max.
Min.
-120
Max.
Min.
Max.
All Speeds, Max. 20
All Speeds, Max. 500
All Speeds Max. 500
All Speeds Max. 50
All Speeds Max. 20
All Speeds 0
70
90
45
35
45
45
35
35
100
120
All Speeds, Min. 0
70
90
70
70
30
25
25
tOEH
tOH
50
50
All Speeds, Min. 0
All Speeds, Min. 0
All Speeds, Min. 0
All Speeds, Min. 0
All Speeds, Min. 0
40
All Speeds, Min. 30
All Speeds, Typ. 9
All Speeds, Typ. 0.7
All Speeds, Min. 50
All Speeds, Min. 0
All Speeds, Min. 90
100
90
90
35
30
30
All Speeds, Min. 0
All Speeds, Min. 10
All Speeds, Min 0
50
50
50
120
100
100
40
30
30
120
120
50
35
35
Units
Notes
us
ns
ns
ns
us
ns
1
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
sec
us
ns
ns
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
Notes to Switching Specifications:
1.
AS8FLC2M32B
Rev. 1.2 5/09
Not 100% tested
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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READ Operations
Parameter
JEDEC
Std
tAVAV
tRC
tAVQV
Description
Test Setup
Read Cycle Time1
tACC
Address to Output Delay
CE# = VIL
OE# = VIL
OE# = VIL
70
Speed Options
90
100 120
Min
70
90
100
120
Max
70
90
100
120
tELQV
tCE
Chip Enable to Output Delay
Max
70
90
100
120
tGLQV
tOE
Output Enable to Output Delay
Max
30
35
35
40
tEHQZ
tDF
Chip Enable to Output High Z1
Max
16
tGHQZ
tDF
Output Enable to Output High Z1
Max
16
Latency Between Read and Write Operations
tSR/W
tAXQX
Min
20
Read
Min
0
Toggle and Data# Polling
Min
10
Min
0
tOEH
Output Enable Hold Time1
tOH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First1
Unit
ns
Notes:
1. Not 100% Tested
READ Operations Timing
tRC
Addresses Stable
Addresses
tACC
CE#
tDF
OE#
tOE
tSR/W
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
AS8FLC2M32B
Rev. 1.2 5/09
0V
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Word / Byte Configuration (BYTE#)
Parameter
JEDEC
Std
tELFL / tELFH
70
Description
Speed Options
90
100 120
CE# to BYTE# Switching Low or High
Max
5
tFLQZ
BYTE# Switching Low to Output HIGH Z
Max
16
tFHQV
BYTE# Switching High to Output Active
Min
70
90
Unit
ns
100
120
BYTE# Timings for Read Operations
CE#
OE#
BYTE#
tELFL
BYTE#
Switching
from word
to byte
mode
Data Output
(DQ0–DQ14)
DQ0–DQ14
Data Output
(DQ0–DQ7)
Address
Input
DQ15
Output
DQ15/A-1
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte to
word mode
Data Output
(DQ0–DQ7)
DQ0–DQ14
Address
Input
DQ15/A-1
Data Output
(DQ0–DQ14)
DQ15
Output
tFHQV
BYTE# Timings for Write Operations
Figure 15.4 BYTE# Timings for Write Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
AS8FLC2M32B
Rev. 1.2 5/09
tSET
(tAS)
tHOLD (tAH)
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AUSTIN SEMICONDUCTOR, INC.
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AS8FLC2M32
Erase / Program Operations
Parameter
JEDEC
Std
tAVAV
tWC
70
Description
Write Cycle Time1
tAVWL
tAS
Address Setup Time
tWLAX
tAH
Address Hold Time
tDVWH
tDS
Data Setup Time
tWHDX
tDH
Data Hold Time
tOES
70
Speed Options
90
100 120
90
40
tELWL
tCS
tWHEH
tCH
CE# Hold Time
0
tWLWH
tWP
Write Pulse Width
tWHWL
tWPH
Write Pulse Width High
35
30
tSR/W
Latency Between Read and Write Operations
20
tWHWH2
0
Min
0
Byte
Programming Operation2
ns
0
Word
5
µs
7
0.7
sec
50
µs
Sector Erase Operation2
1
ns
Typ
tVCS
Vcc Setup Time
Min
tRB
Recovery Time from RY/BY#
Min
0
Program / Erase Valid to RY / BY# Delay
Max
90
tBUSY
45
0
tGHWL
tWHWH2
45
Unit
45
35
tGHWL
tWHWH1
120
0
Output Enable Setup Time
Read Recovery Time Before Write
(OE# High to WE# Low)
CE# Setup Time
tWHWH1
100
ns
Notes:
1.
Not 100% Tested
2.
See Erase and Programming Performance for more information
Program Operation Timings
Program Command Sequence (last two cycles)
Addresses
Read Status Data (last two cycles)
tAS
tWC
555h
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tD
A0h
Data
PD
Status
tBUSY
DOUT
tRB
RY/BY#
VCC
tVCS
Notes
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode
AS8FLC2M32B
Rev. 1.2 5/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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AUSTIN SEMICONDUCTOR, INC.
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Austin Semiconductor, Inc.
Chip / Sector Erase Operation Timings
Erase Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data
2AAh
SA
VA
555h for chip erase
VA
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
In
Progress
30h
55h
Complete
10 for Chip Erase
tRB
tBUSY
RY/BY#
tVCS
VCC
Notes:
1.
SA=Sector Address (for Sector Erase), VA= Valid Address for reading status data.
2.
Illustration shows device in word mode.
Back to Back Read / Write Cycle Timing
tWC
Addresses
tRC
PA
RA
PA
tACC
tAH
tCPH
tCE
CE#
tCP
tOE
tSR/W
OE#
tWDH
AS8FLC2M32B
Rev. 1.2 5/09
tGHWL
tWP
WE#
Data
PA
tDS
tDF
tOH
tDH
Valid In
Valid Out
Valid In
Valid Out
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Austin Semiconductor, Inc.
Data# Polling TImings (During Embedded Algorithms)
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
High Z
Valid Data
True
High Z
Valid Data
True
tBUS
RY/BY#
Note
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle
Toggle Bit Timings (During Embedded Algorithms)
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ6/DQ2
tBUS
Valid Status
Valid Status
(first read)
(second read)
Valid Status
Valid Data
(stops toggling)
RY/BY#
Note
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array
data read cycle.
AS8FLC2M32B
Rev. 1.2 5/09
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Austin Semiconductor, Inc.
DQ2 vs. DQ6
Enter
Embedded
Erasing
Erase
Suspend
Erase
Resume
Erase
Suspend
Program
Erase Suspend
Read
Erase
WE#
Enter Erase
Suspend Program
Erase
Erase Suspend
Read
Erase
Complete
DQ6
DQ2
Note
The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.
Temporary Sector Unprotect
Parameter
JEDEC
Std
tVIDR
tRSP
Description
VID Rise and Fall Time 1
All Speed Options
RESET# Setup Time for
Temporary Sector Unprotect
Min
500
Unit
ns
Min
4
µs
Temporary Sector Unprotect Timing Diagram
g
p
y
p
g
g
12 V
RESET#
0 or 3 V
0 or 3 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
AS8FLC2M32B
Rev. 1.2 5/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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AUSTIN SEMICONDUCTOR, INC.
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Austin Semiconductor, Inc.
Sector Protect / Unprotect Timing Diagram
VID
VIH
RESET#
SA, A6,
Valid*
Valid*
Valid*
A1, A0
Sector Protect/Unprotect
Data
60h
Verify
60h
40h
Status
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
CE#
WE#
OE#
Note
For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Alternate CE# Controlled Erase/Program Operations
Parameter
JEDEC
Std
tAVAV
tWC
Speed Options
70
90 100 120 Unit
70
90 100 120 ns
tAVEL
tAS
Description
Write Cycle Time1
Address Setup Time
tELAX
tAH
Address Hold Time
tDVEH
tDS
Data Setup Time
tDH
Data Hold Time
0
ns
tOES
0
ns
0
ns
0
ns
tEHDX
0
ns
45
35
40
ns
45
45
ns
tGHEL
tGHEL
tWLEL
tWS
Output Enable Setup Time
Read Recovery Time Before Write
High to WE# Low)
WE# Setup Time
tEHWH
tWH
WE# Hold Time
0
ns
tELEH
tCP
CE# Pulse Width
35
ns
tEHEL
tCPH
CE# Pulse Width High
30
ns
tSR/W
Latency Between Read and Write Operations
20
ns
tWHWH1
tWHWH1
Programming Operation2
tWHWH2
tWHWH2
Sector Erase Operation2
Min
(OE#
Byte
Typ
5
µs
0.7
sec
Notes:
1. Not 100% Tested
2. See Erase and Programming Performance
AS8FLC2M32B
Rev. 1.2 5/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
25
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
FLASH
AS8FLC2M32
Mechanical Drawings
b
Detail A
e
Austin Semiconductor
[Package Designator Q]
R
B
L1
Austin Semi Package Specifications
Min
Max
Symbol
0.120
0.140
A
0.005
0.015
A2
0.010 REF
B
0.013
0.017
b
0.800 BSC
D
0.870
0.890
D1
0.980
1.000
D2
0.936
0.956
E
0.050 BSC
e
0.010 TYP
R
0.035
0.045
L1
D
D1
D2
Detail A
E
A2
AS8FLC2M32B
Rev. 1.2 5/09
A
Dimensions in Inches
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AUSTIN SEMICONDUCTOR, INC.
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FLASH
AS8FLC2M32
Mechanical Drawings
Austin Semiconductor
[Package Designator H]
E
E1
e
A
A1
e
L
66 x ob
D
D1
D2
4 x ob1
Pin 1: SQ. Pad
65 x ob2
Austin Semi Package Specifications
Min
Max
Symbol
A
0.210
0.245
A1
0.025
0.035
A2
0.135
0.145
ob
0.016
0.020
ob1
0.045
0.055
ob2
0.065
0.075
D/E
1.170
1.200
1.000 BSC
D1/E1
D2
0.600 BSC
1.150
D3
1.140
e
0.100 BSC
L
0.145
0.155
Dimensions in Inches
AS8FLC2M32B
Rev. 1.2 5/09
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27
FLASH
AUSTIN SEMICONDUCTOR, INC.
AS8FLC2M32
Austin Semiconductor, Inc.
Ordering Information
Ceramic Quad Flat Pack
ASI Part Number
Configuration
Speed
(ns)
Pkg.
70
90
100
120
CQFP-68
CQFP-68
CQFP-68
CQFP-68
70
90
100
120
CQFP-68
CQFP-68
CQFP-68
CQFP-68
70
90
100
120
CQFP-68
CQFP-68
CQFP-68
CQFP-68
Speed
(ns)
Pkg.
70
90
100
120
HIP-66
HIP-66
HIP-66
HIP-66
70
90
100
120
HIP-66
HIP-66
HIP-66
HIP-66
70
90
100
120
HIP-66
HIP-66
HIP-66
HIP-66
0
0
Industrial Operating Range (-40 C to +85 C)
AS8FLC2M32BQ-70/IT
AS8FLC2M32BQ-90/IT
AS8FLC2M32BQ-100/IT
AS8FLC2M32BQ-120/IT
2Mx32, 3.3v,Flash Bottom Boot Block
2Mx32, 3.3v,Flash Bottom Boot Block
2Mx32, 3.3v,Flash Bottom Boot Block
2Mx32, 3.3v,Flash Bottom Boot Block
0
0
Extended Operating Range (-55 C to +125 C)
AS8FLC2M32BQ-70/XT
AS8FLC2M32BQ-90/XT
AS8FLC2M32BQ-100/XT
AS8FLC2M32BQ-120/XT
2Mx32, 3.3v,Flash Bottom Boot Block
2Mx32, 3.3v,Flash Bottom Boot Block
2Mx32, 3.3v,Flash Bottom Boot Block
2Mx32, 3.3v,Flash Bottom Boot Block
MIL-PRF-38534, CLASS H
AS8FLC2M32BQ-70/Q
AS8FLC2M32BQ-90/Q
AS8FLC2M32BQ-100/Q
AS8FLC2M32BQ-120/Q
2Mx32, 3.3v,Flash Bottom Boot Block
2Mx32, 3.3v,Flash Bottom Boot Block
2Mx32, 3.3v,Flash Bottom Boot Block
2Mx32, 3.3v,Flash Bottom Boot Block
Hex Inline Package
ASI Part Number
Configuration
0
0
Industrial Operating Range (-40 C to +85 C)
AS8FLC2M32BP-70/IT
AS8FLC2M32BP-90/IT
AS8FLC2M32BP-100/IT
AS8FLC2M32BP-120/IT
2Mx32, 3.3v,Flash Bottom Boot Block
2Mx32, 3.3v,Flash Bottom Boot Block
2Mx32, 3.3v,Flash Bottom Boot Block
2Mx32, 3.3v,Flash Bottom Boot Block
0
0
Extended Operating Range (-55 C to +125 C)
AS8FLC2M32BP-70/XT
AS8FLC2M32BP-90/XT
AS8FLC2M32BP-100/XT
AS8FLC2M32BP-120/XT
2Mx32, 3.3v,Flash Bottom Boot Block
2Mx32, 3.3v,Flash Bottom Boot Block
2Mx32, 3.3v,Flash Bottom Boot Block
2Mx32, 3.3v,Flash Bottom Boot Block
MIL-PRF-38534, CLASS H
AS8FLC2M32BP-70/Q
AS8FLC2M32BP-90/Q
AS8FLC2M32BP-100/Q
AS8FLC2M32BP-120/Q
2Mx32, 3.3v,Flash Bottom Boot Block
2Mx32, 3.3v,Flash Bottom Boot Block
2Mx32, 3.3v,Flash Bottom Boot Block
2Mx32, 3.3v,Flash Bottom Boot Block
*Consult Factory for Top Boot
AS8FLC2M32B
Rev. 1.2 5/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
28
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
FLASH
AS8FLC2M32
DOCUMENT TITLE
64Mb, 2M x 32, 3.3Volt Boot Block FLASH Array
REVISION HISTORY
Rev #
1.1
1.2
AS8FLC2M32B
Rev. 1.2 5/09
History
Updated Package Information
Updated Order Chart (QT to Q)
Release Date
May 2008
May 2009
Status
Release
Release
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
29