DM54S194/DM74S194 4-Bit Bidirectional Universal Shift Registers General Description These bidirectional shift registers are designed to incorporate virtually all of the features a system designer may want in a shift register; they feature parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-modecontrol inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely: Parallel (broadside) load Shift right (in the direction QA toward QD) Shift left (in the direction QD toward QA) Inhibit clock (do nothing) Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flipflops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial input. Clocking of the flip-flop is inhibited when both mode control inputs are low. Features Y Y Y Y Y Y Parallel inputs and outputs Four operating modes: Synchronous parallel load Right shift Left shift Do nothing Positive edge-triggered clocking Direct overriding clear Typical clock frequency 105 MHz Typical power dissipation 425 mW Connection Diagram Dual-In-Line Package TL/F/6475 – 1 Order Number DM54S194J or DM74S194N See NS Package Number J16A or N16E C1995 National Semiconductor Corporation TL/F/6475 RRD-B30M105/Printed in U. S. A. DM54S194/DM74S194 4-Bit Bidirectional Universal Shift Registers June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54S DM74S 0§ C to a 70§ C b 65§ C to a 150§ C Storage Temperature Range Recommended Operating Conditions Symbol DM54S194 Parameter DM74S194 Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage 0.8 0.8 V IOH High Level Output Current b1 b1 mA IOL Low Level Output Current fCLK Clock Frequency (Note 1) fCLK tW tSU 2 2 V 20 20 mA 0 105 70 MHz 0 90 60 MHz 0 105 70 Clock Frequency (Note 2) 0 90 60 Pulse Width (Note 3) Clock 7 7 Clear 12 12 Mode 11 11 Data 5 5 3 3 Setup Time (Note 3) tH Hold Time (Note 3) tREL Clear Release Time (Note 3) TA Free Air Operating Temperature 9 ns ns ns 9 b 55 125 V ns 0 70 §C Note 1: CL e 15 pF, RL e 280X, TA e 25§ C and VCC e 5V. Note 2: CL e 50 pF, RL e 280X, TA e 25§ C and VCC e 5V. Note 3: TA e 25§ C and VCC e 5V. Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Symbol Parameter Min Typ (Note 4) DM54 2.5 3.4 DM74 2.7 3.4 Conditions Max Units b 1.2 V VI Input Clamp Voltage VCC e Min, II e b18 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max VIH e Min, VIL e Max II Input Current @ Max Input Voltage VCC e Max, VI e 5.5V IIH High Level Input Current VCC e Max, VI e 2.7V 50 mA IIL Low Level Input Current VCC e Max, VI e 0.5V b2 mA IOS Short Circuit Output Current VCC e Max (Note 5) Supply Current VCC e Max (Note 6) ICC V 0.5 V 1 mA DM54 b 40 b 100 DM74 b 40 b 100 85 135 mA mA Note 4: All typicals are at VCC e 5V, TA e 25§ C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 6: With all outputs open, inputs A through D grounded, and 4.5V applied to S0, S1, CLEAR, and the SERIAL inputs, ICC is tested with a momentary ground, then 4.5V applied to CLOCK. 2 Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) Symbol RL e 280X From (Input) To (Output) Parameter CL e 15 pF Min CL e 50 pF Max Min 70 Units Max fMAX Maximum Clock Frequency tPLH Propagation Delay Time Low to High Level Output Clock to Q 60 MHz 12 15 ns tPHL Propagation Delay Time High to Low Level Output Clock to Q 16.5 20 ns tPHL Propagation Delay Time High to Low Level Output Clear to Q 18.5 23 ns Function Table Inputs Mode Clear L H H H H H H H Clock S1 S0 X X H L L H H L X X H H H L L L X L u u u u u X Outputs Serial Parallel Left Right A B C D X X X X X H L X X X X H L X X X X X a X X X X X X X b X X X X X X X c X X X X X X X d X X X X X QA QB QC QD L QA0 a H L QBn QBn QA0 L QB0 b QAn QAn QCn QCn QB0 L QC0 c QBn QBn QDn QDn QC0 L QD0 d QCn QCn H L QD0 H e High Level (steady state). L e Low Level (steady state). X e Don’t Care (any input, including transitions). u e Transition from low to high level. a, b, c, d e The level of steady state input at inputs A, B, C, or D, respectively. QA0, QB0, QC0, QD0 e The level of QA, QB, QC, or QD, respectively, before the indicated steady state input conditions were established. QAn, QBn, QCn, QDn e The level of QA, QB, QC respectively, before the most recent u transition of the clock. Logic Diagram S194 TL/F/6475 – 2 3 Timing Diagram Typical Clear, Load, Right-Shift, Left-Shift, Inhibit, and Clear Sequences TL/F/6475 – 3 4 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number DM54S194J NS Package Number J16A 5 DM54S194/DM74S194 4-Bit Bidirectional Universal Shift Registers Physical Dimensions inches (millimeters) (Continued) 16-Lead Molded Dual-In-Line Package (N) Order Number DM74S194N NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.