TI1 BQ24187YFFR 1a usb-otg support Datasheet

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bq24187
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bq24187 2A, 30V Host-Controlled Single-Input, Single Cell Switchmode Li-Ion Battery
Charger with Integrated Sense Element and 1A USB-OTG Support
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
Charge Time Optimizer (Enhanced CC/CV
Transition) for Faster Charging
Integrated FETs for Up to 2A Charge Rate at 5%
Accuracy and 93% Peak Efficiency
Boost Capability to Supply 5V at 1A at IN for USB
OTG Supply
Integrated Current Sense Resistor for Smallest
Size and Cost
30V Input Rating with Over-Voltage Protection
Supports 5V USB2.0/3.0 with 6.5V OVP
Small Solution Size In a 2,4mm x 2,4mm 36-ball
WCSP or 4mm x 4mm QFN-24 Package
Safe and Accurate Battery Management
Functions Programmed Using I2C Interface
– Charge Voltage, Current, Termination
Threshold, Input Current Limit, VIN_DPM
Threshold
– Voltage-based, JEITA Compatible NTC
Monitoring Input
– Thermal Regulation Protection for Input
Current Control
– Thermal Shutdown and Protection
Smartphones and Tablets
Handheld Products
Power Banks and External Battery Packs
Small Power Tools
Portable Media Players and Gaming
3 Description
The bq24187 is a highly integrated single cell Li-Ion
battery charger targeted for space-limited, portable
applications with high capacity batteries. The single
cell charger has a single input that supports operation
from either a USB port or wall adapter supply for a
versatile solution. The integrated sense element
reduces solution size and external component count.
The charge parameters are programmable using the
I2C interface. To Support USB OTG applications, the
bq24187 is configurable to boost the battery voltage
to 5V at the input. In this mode, the bq24187 supplies
up to 1A and operates with battery voltages down to
3.3V. A voltage-based, JEITA compatible battery
pack thermistor monitoring input (TS) is included that
monitors battery temperature for safe charging.
Device Information
ORDER NUMBER (1)
PACKAGE
BODY SIZE
bq24187YFFR
DSBGA (36)
2,4mm × 2,4mm
bq24187RGER (2)
VQFN (24)
4mm × 4mm
(1)
(2)
For ordering information see the addendums at the end of the
data sheet.
PREVIEW
4 Typical Application
IN
SW
VBUS
D+
DGND
BOOT
PGND
CS+
DRV
BAT
USB PHY
PSEL
HOST
GPIO1
System
Load
bq24187
PACK+
TEMP
TS
INT
SDA
SDA
SCL
SCL
VDRV
PACK-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
Not Recommended for New Designs
bq24187
SLUSBM0 – APRIL 2014
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Typical Application ................................................
Revision History.....................................................
Terminal Configuration and Functions................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
8.2
8.3
8.4
8.5
8.6
1
1
1
1
2
3
5
9
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
12
14
14
23
26
Applications and Implementation ...................... 31
9.1 Application Information............................................ 31
9.2 Typical Application .................................................. 31
Absolute Maximum Ratings ...................................... 5
Handling Ratings....................................................... 5
Recommended Operating Conditions....................... 5
Thermal Information ................................................. 5
Electrical Characteristics........................................... 6
Timing Requirements ................................................ 9
Switching Characteristics .......................................... 9
Typical Characteristics ............................................ 10
10 Layout................................................................... 34
10.1 Layout Guidelines ................................................. 34
10.2 Layout Example .................................................... 35
11 Device and Documentation Support ................. 36
11.1
11.2
11.3
11.4
Detailed Description ............................................ 11
Documentation Support .......................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
36
36
36
12 Mechanical, Packaging, and Orderable
Information ........................................................... 36
8.1 Overview ................................................................. 11
5 Revision History
2
DATE
REVISION
NOTES
April 2014
*
Initial release.
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6 Terminal Configuration and Functions
SW
SW
PGND
PGND
AGND
IN
RGE Package
(24-Terminal 4 mm X 4 mm QFN)
Top View
24
23
22
21
20
19
PMID
1
18 IN
BOOT
2
17 SDA
DRV
3
16 SCL
bq24187
11
12
10
8
9
7
AGND
13 STAT
N.C.
CS+ 6
INT
14 PSEL
BAT
TS 5
BAT
15 N.C.
CS+
CD 4
YFF Package
(36-Ball 2,6 mm X 2,6 mm DSBGA)
Top View
1
2
3
4
5
6
A
PGND
PGND
PGND
PGND
PGND
PGND
B
PMID
SW
SW
SW
SW
SW
C
IN
IN
IN
IN
CD
BOOT
D
SDA
SCL
N.C.
PSEL
TS
DRV
E
STAT
INT
CS+
CS+
CS+
CS+
F
AGND
N.C.
BAT
BAT
BAT
BAT
Terminal Functions
TERMINAL
NAME
YFF
AGND
F1
BAT
F3-F6
BOOT
CD
RGE
I/O
12, 20
DESCRIPTION
Analog Ground. Connect to the PGND TERMINALs and the ground plane of the circuit.
8, 9
I/O
Battery Connection. Connect to the positive terminal of the battery. Additionally, bypass BAT to GND
with a 1μF capacitor.
C6
2
I
High Side MOSFET Gate Driver Supply. Connect a 0.033µF ceramic capacitor (voltage rating > 10V)
from BOOT to SW to supply the gate drive for the high side MOSFETs.
C5
4
I
IC Hardware Disable Input. Drive CD high to place the bq24187 in Hi-Z mode. Drive CD low for
normal operation.
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Terminal Functions (continued)
TERMINAL
NAME
YFF
DRV
D6
IN
C1-C4
I/O
DESCRIPTION
3
O
Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. Bypass DRV
to PGND with a 1μF ceramic capacitor. DRV may be used to drive external loads up to 10mA. DRV is
active whenever the input is connected and VIN > VUVLO and VIN > (VBAT + VSLP).
18, 19
I
DC Input Power Supply. IN is connected to the external DC supply (AC adapter or USB port). Bypass
IN to PGND with at least a 4.7μF ceramic capacitor.
10
O
Status Output. INT is an open-drain output that signals charging status and fault interrupts. INT pulls
low during charging. INT is high impedance when charging is complete or the charger is disabled.
When a fault occurs, a 128μs pulse is sent out as an interrupt for the host. INT is enabled /disabled
using the EN_STAT bit in the control register. Connect INT to a logic rail through a 100kΩ resistor to
communicate with the host processor.
RGE
INT
E2
N.C.
D3, F2
11, 15
--
Connect to the ground plane of the circuit.
PGND
A1-A6
21, 22
--
Ground terminal. Connect to the the ground plane of the circuit.
PMID
B1
1
I
High Side Bypass Connection. Connect a 1µF capacitor from PMID to PGND as close to the PMID
and PGND TERMINALs as possible.
PSEL
D4
14
I
Hardware Input Current Limit. In DEFAULT mode, PSEL selects the input current limit during
DEFAULT mode. Drive PSEL high to select USB100 mode, drive PSEL low to select 1.5A mode.
SCL
D2
16
I
I2C Interface Clock. Connect SCL to the logic rail through a 10kΩ resistor.
SDA
D1
17
I/O
I2C Interface Data. Connect SDA to the logic rail through a 10kΩ resistor.
13
O
Status Output. STAT is an open-drain output that signals charging status and fault interrupts. STAT
pulls low during charging. STAT is high impedance when charging is complete or the charger is
disabled. When a fault occurs, a 128μs pulse is sent out as an interrupt for the host. STAT is enabled
/disabled using the EN_STAT bit in the control register. Connect STAT to a logic rail using an LED for
visual indication or through a 10kΩ resistor to communicate with the host processor.
STAT
E1
SW
B2-B6
23, 24
O
Inductor Connection. Connect to the switched side of the external inductor.
CS+
E3-E6
6, 7
I
System Voltage Sense and Charger FET Connection. Connect CS+ to the inductor. Bypass CS+
locally with 20μF.
TS
D5
5
I
Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from DRV to GND. The
NTC is connected from TS to GND. The TS function provides 4 thresholds for JEITA compatibility. TS
faults are reported by the I2C interface. Pull TS high to VDRV to disable the TS function. See the NTC
Monitor section for more details on operation and selecting the resistor values.
Thermal
PAD
–
–
–
There is an internal electrical connection between the exposed thermal pad and the PGND
TERMINAL of the device. The thermal pad must be connected to the same potential as the PGND
TERMINAL on the printed circuit board. Do not use the thermal pad as the primary ground input for
the device. PGND TERMINAL must be connected to ground at all times.
4
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
IN
Terminal voltage range (with
respect to PGND)
MIN
MAX
–1.3
30
BOOT
–0.3
30
V
–0.7
20
V
SDA, SCL, CS+, BAT, STAT, DRV, TS, PSEL, INT
–0.3
5
V
–0.3
5
V
SW
4.5
A
CS+, BAT (charging)
3.5
A
Input Current (Continuous)
Output Sink Current
V
SW
BOOT to SW
Output Current (Continuous)
UNIT
2.75
STAT, INT
A
10
mA
Operating free-air temperature range
–40
85
°C
Junction temperature, TJ
–40
125
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
TSTG
Storage temperature range
MIN
MAX
UNIT
–65
150
°C
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
MIN
MAX
UNIT
IN voltage
4.2
28 (1)
V
IN operating voltage
4.2
6.0
IIN
Input current, IN input
ISW
Ouput Current from SW, DC
IBAT
Charge Current
TJ
Operating junction temperature, TJ
(1)
0
2.5
A
2
A
2
A
125
°C
The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOST or SW terminals. A
tight layout minimizes switching noise.
7.4 Thermal Information
bq24187
THERMAL METRIC
(1)
YFF
RGE
36 TERMINALS
24 TERMINALS
RθJA
Junction-to-ambient thermal resistance
55.8
32.6
RθJCtop
Junction-to-case (top) thermal resistance
0.5
30.5
RθJB
Junction-to-board thermal resistance
10
3.3
ψJT
Junction-to-top characterization parameter
2.6
0.4
ψJB
Junction-to-board characterization parameter
9.9
9.3
RθJCbot
Junction-to-case (bottom) thermal resistance
N/A
2.6
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
Circuit of Figure 6, VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = –40°C–125°C and TJ=25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENTS
VUVLO < VIN < VOVP AND VIN>VBAT+VSLP, PWM
switching
IIN
Supply current for control
Battery discharge current in high
impedance mode, (BAT, SW,
CS+)
IBAT_HIZ
15
mA
VUVLO < VIN < VOVP AND VIN>VBAT+VSLP, PWM
NOT switching
6.5
0°C< TJ < 85°C, VIN = 5V, High-Z Mode
250
μA
0°C< TJ < 85°C, VBAT = 4.2 V, VIN = 5V, SCL, SDA
= 0V or 1.8V, High-Z Mode
15
μA
0°C< TJ < 85°C, VBAT = 4.2 V, VIN = 0V, SCL, SDA
= 0V or 1.8V
80
μA
CHARGER PARAMETERS
RSENSE
Internal Sense Element
Resistance
Measured from BAT to
CS+, VBAT = 4.2V, High-Z
mode
YFF
17
25
mΩ
RGE
32
47
mΩ
Charge voltage
Operating in voltage regulation, Programmable
range
TJ = 25°C, RGE Package
VBATREG
Voltage Regulation Accuracy
TJ = 0°C to 85°C, RGE and YFF Package
Fast charge current range
VLOWV ≤ VBAT < VBAT(REG)
TJ = 0°C to 125°C, RGE and YFF Package
ICHARGE
Fast charge current accuracy
500 mA ≤ ICHARGE ≤ 1A
ICHARGE ≥ 1000mA
3.5
4.44
–0.5%
0.5%
–0.75%
0.75%
-1.0%
1.0%
500
2000
–10%
10%
–5%
5%
VBATSHRT
Battery short circuit threshold
VBATSHRT(hys)
Hysteresis for VLOWV
Battery voltage falling
1.9
IBATSHRT
Battery short circuit charge
current
VBAT < VLOWV
33.5
≤ 50mA
–30%
30%
ITERM
Termination charge current
50mA < ITERM < 200mA
–15%
15%
ITERM ≥ 200mA
–15%
ITERM
VRCH
Recharge threshold voltage
VDET(SRC1)
VDET(SRC2)
Battery detection voltage
threshold (TE = 1)
VDET(SNK)
IDETECT
6
Below VOREG
100
50
VRCH
During current source (Turn IBATSHRT on)
VRCH –
200mV
Termination enabled (TE = 1)
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2.1
mA
V
mV
66.5
mA
10%
120
During current source (Turn IBATSHRT off)
During current sink
Battery detection current before
charge done (sink current)
2
100
V
150
mV
V
VBATSHRT
7
mA
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Electrical Characteristics (continued)
Circuit of Figure 6, VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = –40°C–125°C and TJ=25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENT LIMITING
IIN_USB
VIN_DPM
Input current limiting threshold
Input based DPM threshold
range
USB charge mode,
VIN = 5V,
Current pulled from SW
IINLIM = USB100
90
95
100
IINLIM = USB500
450
475
500
IINLIM = USB150
125
140
150
IINLIJM = USB900
800
850
900
IINLIM = 1.5A
1425
1500
1575
IINLIM = 2.0A
1850
2000
2200
Charge mode, programmable via I2C
VIN_DPM threshold Accuracy
4.2
4.76
–3%
3%
mA
V
VDRV BIAS REGULATOR
VDRV
Internal bias regulator voltage
IDRV
DRV Output current
VDO_DRV
DRV Dropout voltage (VIN –
VDRV)
VIN>5V
4.3
4.8
5.3
V
10
mA
IIN = 1A, VIN = 4.2V, IDRV = 10mA
450
mV
0.4
V
1
µA
0
STATUS OUTPUT (STAT, INT)
VOL
Low-level output saturation
voltage
IO = 5 mA, sink current
IIH
High-level leakage current
V/CHG = V/PG = 5V
INPUT TERMINALS (CD, PSEL)
VIL
Input low threshold
VIH
Input high threshold
0.4
RPULLDOWN
CD pull-down resistance
CD only
VUVLO
IC active threshold voltage
VIN rising
VUVLO_HYS
IC active hysteresis
VIN falling from above VUVLO
VSLP
Sleep-mode entry threshold, VINVBAT
2.0 V ≤ VBAT ≤ VBATREG, VIN falling
VSLP_HYS
Sleep-mode exit hysteresis
VOVP
Input supply OVP threshold
voltage
IN rising, 100mV hysteresis
VBOVP
Battery OVP threshold voltage
VBAT threshold over VOREG to turn off charger
during charge
VBOVP_HYS
VBOVP hysteresis
Lower limit for VBAT falling from above VBOVP
ICbCLIMIT
Cycle-by-cycle current limit
VCS+ shorted
TSHTDWN
Thermal trip
V
1.4
V
100
kΩ
PROTECTION
3.2
Thermal regulation threshold
3.4
V
mV
0
40
120
mV
40
100
190
mV
6.25
6.5
6.75
V
1.03 ×
VBATREG
1.05 ×
VBATREG
1.07 ×
VBATREG
V
% of
VBATREG
1
4.1
4.5
4.9
150
Thermal hysteresis
TREG
3.3
300
A
°C
10
Charge current begins to cut off
Safety Timer Accuracy
125
–20%
°C
20%
PWM
RDSON_Q1
RDSON_Q2
Internal top MOSFET onresistance
YFF Package: Measured from IN to SW
75
120
mΩ
RGE Package: Measured from IN to SW
80
135
mΩ
Internal bottom N-channel
MOSFET on-resistance
YFF Package: Measured from SW to PGND
75
115
mΩ
RGE Package: Measured from SW to PGND
80
135
mΩ
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Electrical Characteristics (continued)
Circuit of Figure 6, VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = –40°C–125°C and TJ=25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BATTERY-PACK NTC MONITOR
VHOT
High temperature threshold
VTS falling, 2% VDRV Hysteresis
27.3
30
32.6
%VDRV
VWARM
Warm temperature threshold
VTS falling, 2% VDRV Hysteresis
36.0
38.3
41.2
%VDRV
VCOOL
Cool temperature threshold
VTS rising, 2% VDRV Hysteresis
54.7
56.4
58.1
%VDRV
VCOLD
Low temperature threshold
VTS rising, 2% VDRV Hysteresis
58.2
60
61.8
%VDRV
TSOFF
TS Disable threshold
VTS rising, 4% VDRV Hysteresis
80
85
%VDRV
1.3
I2C COMPATIBLE INTERFACE
VIH
Input low threshold level
VPULL-UP=1.8V, SDA and SCL
VIL
Input low threshold level
VPULL-UP=1.8V, SDA and SCL
0.4
V
V
VOL
Output low threshold level
IL=5mA, sink current
0.4
V
IBIAS
High-Level leakage current
VPULL-UP=1.8V, SDA and SCL
1
μA
2.7V<VBAT<4.5V, no switching
100
µA
4.5
V
5.2
V
OTG BOOST SUPPLY
IQBAT_ BOOST
Quiescent current during boost
mode (BAT TERMINAL)
Boost voltage range for specified
boost operation
3.3
VIN_BOOST
Boost output voltage (to terminal
VBUS)
2.7V<VBAT<4.5V over line and load
IBO
Maximum output current for
boost
2.7V<VBAT<4.5V
IBLIMIT
Cycle by cycle current limit for
boost (measured at lowside FET)
2.7V<VBAT<4.5V
VBOOSTOVP
Over voltage protection threshold
for boost (IN terminal)
Signals fault and exits boost mode
VBURST(ENT)
VBURST(EXIT)
8
4.95
BOOST_ILIM=1
1000
BOOST_ILIM=0
500
5.05
mA
BOOST_ILIM=1
4
BOOST_ILIM=0
2
A
5.8
6
6.2
V
Upper VIN voltage threshold to
enter burst mode (stop switching)
5.1
5.2
5.3
V
Lower VBUS voltage threshold to
exit burst mode (start switching)
4.9
5
5.1
V
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7.6 Timing Requirements
Circuit of Figure 6, VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = –40°C–125°C and TJ=25ºC for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CHARGER PARAMETERS
Deglitch time for battery short to
fast charge transition
VBAT rising or falling
Deglitch time for charge
termination
tDGL(RCH)
1
ms
Both rising and falling, 2-mV over-drive, tRISE,
tFALL=100ns
32
ms
Deglitch time
VBAT falling below VRCH, tFALL=100ns
32
ms
tDETECT(SRC)
Battery detection time (sourcing
current)
Termination enabled (TE = 1)
2
s
tDETECT(SNK)
Battery detection time (sinking
current)
Termination enabled (TE = 1)
250
ms
Deglitch for CD and PSEL
CD or PSEL rising/falling
100
µs
tDGL(VSLP)
Deglitch time for supply rising
above VSLP+VSLP_EXIT
Rising voltage, 2-mV over drive, tRISE=100ns
30
ms
tDGL(BOVP)
BOVP Deglitch
Battery entering/exiting BOVP
tDGL(TERM)
INPUT TERMINALS (CD, PSEL)
PROTECTION
Safety Timer Accuracy
8
–20%
ms
20%
BATTERY-PACK NTC MONITOR
tDGL(TS)
Deglitch time on TS change
Applies to VHOT , VWARM , VCOOL , and VCOLD
50
ms
2
I C COMPATIBLE INTERFACE
tWATCHDOG
30
tI2CRESET
50
s
700
ms
7.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
fOSC
Oscillator frequency
DMAX
Maximum duty cycle
DMIN
Minimum duty cycle
TEST CONDITIONS
MIN
1.35
TYP
MAX
UNIT
1.5
1.65
MHz
95%
0%
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7.8 Typical Characteristics
10
100
90
6
4
80
Efficiency (%)
Charge Current Accuracy (%)
8
2
0
-2
TA=25ºC
-4
70
60
TA=0ºC
-6
TA=85ºC
-8
TA=60ºC
-10
2.9
3.1
3.3
VIN = 5 V
3.5
3.7
3.9
VBAT (V)
50
4.1
4.3
40
4.5
2
2.5
3
3.5
4
4.5
VBAT (V)
ICHG = 1.2 A
ICHG = 2 A
VIN = 5 V
Figure 1. Current Charge vs Battery Voltage
VREG = 4.44 V
TA = 25°C
Figure 2. Efficiency vs Batter`y Charge
16
0.0
14
12
Input Current - mA
VBAT Accuracy (%)
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
10
8
6
4
TA=25ºC
2
TA=60ºC
TA=0ºC
0
-2
0
0.5
1
IBAT (A)
1.5
2
0
Figure 3. VBAT Accuracy vs IBAT – 4.2 V Setting
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2
4
6
8
10
Input Voltage - V
TA = 25°C
12
14
16
Figure 4. Input IQ - No Battery, No System
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8 Detailed Description
8.1 Overview
The bq24187 is a highly integrated single cell Li-Ion battery charger targeted for space-limited, portable
applications with high capacity batteries. The single cell charger has a single input that supports operation from
either a USB port or wall adapter supply for a versatile solution. The integrated sense element reduces solution
size and external component count. The charge parameters are programmable using the I2C interface. To
Support USB OTG applications, the bq24187 is configurable to boost the battery voltage to 5V at the input. In
this mode, the bq24187 supplies up to 1A and operates with battery voltages down to 3.3V. The battery is
charged in three phases: precharge, fast charge constant current and constant voltage. In all charge phases, an
internal control loop monitors the IC junction temperature and reduces the charge current if the internal
temperature threshold is exceeded. Additionally, a voltage-based, JEITA compatible battery pack thermistor
monitoring input (TS) is included that monitors battery temperature for safe charging.
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8.2 Functional Block Diagrams
PMID
4.8–V
reference
DRV
IN
5A
+
BOOT
CbC current
limit
IINLIM
Q1
DC-DC converter PWM logic,
compensation and battery
FET control
VINDPM
VSYS(REG)
IBAT(REG)
SW
VBAT(REG)
DIE temp
regulation
Q3
PGND
VSUPPLY
CS+
References
OVP
comparator
VIN
Termination
reference
+
VINOVP
+
Termination
comparator
Sleep
Comparator
VIN
+
SDA
BAT
Recharge comparator
VBAT +VSLP
CD
IBAT
Start Recharge
cycle
Hi-Z
mode
Enable Linear
charge
+
VBATREG – 0.12 V
VBAT
VSYSREG comparator
+
VSYS
VMINSYS
+
Good Battery
circuit
VBATGD
2
I C
interface
VBATSC Comparator
Enable
IBATSHRT
SCL
+
VBAT
VBATSHRT
Supplement COMPARATOR
+
VSYS
VBAT
VBSUP
VDRV
VBOVP Comparator
PSEL
+
1.5 A /
USB100
VBAT
VBATOVP
+
DISABLE
TS COLD
INT
1 C/
0.5 C
+
TS COOL
+
VBATREG
– 0.14 V
TS WARM
STAT
+
DISABLE
Charge
controller
with timer
TS HOT
TS
Figure 5. Block Diagram In Charging Mode
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Functional Block Diagrams (continued)
PMID
4.8-V
reference
DRV
IN
BOOT
VBOOST amp
Q1
+
VIN_BOOST
VBURST_ENT
Burst mode enter
comparator
Low side current
limit comparator
IBLIMIT
VDRV
+
VBURST_EXT
SW
+
DC-DC
converter
PWM logic
and
compensation
+
Q2
Burst mode exit
comparator
PGND
Boost short circuit
comparator
VBOOSTSHRT
+
VBOOSTOVP
+
VBOOST
OVP comparator
CS+
Battery SC comparator
VBAT
VBIAS
Battery short
circuit
+
ILIM(SUPP)
BAT
CD
SDA
I2C
Interface
SCL
Digital control
STAT
INT
TS
Figure 6. Block Diagram In Boost Mode
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8.3 Feature Description
The bq24187 is a highly integrated single cell Li-Ion battery charger targeted for space-limited, portable
applications with high capacity batteries. The single cell charger has a single input that supports operation from
either a USB port or wall adapter supply for a versatile solution. The integrated sense element reduces solution
size and external component count. The charge parameters are programmable using the I2C interface. To
Support USB OTG applications, the bq24187 is configurable to boost the battery voltage to 5V at the input. In
this mode, the bq24187 supplies up to 1A and operates with battery voltages down to 3.3V. The battery is
charged in three phases: precharge, fast charge constant current and constant voltage. In all charge phases, an
internal control loop monitors the IC junction temperature and reduces the charge current if the internal
temperature threshold is exceeded. Additionally, a voltage-based, JEITA compatible battery pack thermistor
monitoring input (TS) is included that monitors battery temperature for safe charging.
The Device Functional Modes section explains these features in detail.
8.4 Device Functional Modes
8.4.1 High Impedance Mode (Hi-Z Mode)
High Impedance mode (Hi-Z mode) is the low quiescent current state for the bq24187. During Hi-Z mode, the
buck converter is off. The bq24187 is in Hi-Z mode when VIN < VUVLO, the HZ_MODE bit in the I2C is '1' or the
CD terminal is driven high. Hi-Z mode resets the safety timer.
The bq24187 contains a CD input that is used to disable the IC and place the bq24187 into high-impedance
mode. Drive CD low to enable the bq24187 and enter normal operation. Drive CD high to disable charge and
place the bq24187 into high-impedance mode. CD is internally pulled down to PGND with a 100kΩ resistor.
When exiting Hi-Z mode, charging resumes in approximately 110ms.
8.4.1.1 Input Connected
8.4.1.1.1 Input Voltage Protection In Charge Mode
8.4.1.1.1.1 Sleep Mode
The bq24187 enters the low-power sleep mode if the voltage on VIN falls below sleep-mode entry threshold,
VBAT+VSLP, and VIN is higher than the undervoltage lockout threshold, VUVLO. This feature prevents draining the
battery during the absence of VIN. When VIN < VBAT+ VSLP, the bq24187 turns off the PWM converter, sends a
single 128μs pulse is sent on the STAT and INT outputs and the STATx and FAULT_x bits of the status registers
are updated in the I2C. Once VIN > VBAT+ VSLP, the STATx and FAULT_x bits are cleared and the device initiates
a new charge cycle. The FAULT_x bits are not cleared until they are read in the I2C and the sleep condition no
longer exists.
8.4.1.1.1.2 Input Voltage Based DPM (VIN-DPM)
During normal charging process, if the input power source is not able to support the programmed or default
charging current, the supply voltage deceases. Once the supply drops to VIN_DPM (default 4.2V), the charge
current limit is reduced down to prevent the further drop of the supply. When the IC enters this mode, the charge
current is lower than the set value and the DPM_STATUS bit is set. This feature ensures IC compatibility with
adapters with different current capabilities without a hardware change. Figure 7 shows the VIN-DPM behavior to
a current limited source. In this figure the input source has a 750mA current limit and the device charge current is
increased until the input current limit of the adapter is reached and the supply collapses. If the 2X timer is set, the
safety timer is extended while VIN-DPM is active. Additionally, termination is disabled.
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Device Functional Modes (continued)
Adapter Voltage Falls due to Adapter Current Limit
Input Current Reduced by VINDPM function to Prevent
Adapter from Crashing
Charge Current is Reduced by VINDPM Response
Sum of Charge Current and Load Current is limited to the
Adapter Current Limit of 750mA
Figure 7. bq24187 VINDPM
8.4.1.1.1.3 Input Over-Voltage Protection
The bq24187 provides over-voltage protection on the input that protects downstream circuitry. The built-in input
over-voltage protection to protect the device and other components against damage from overvoltage on the
input supply (Voltage from VIN to PGND). When VIN > VOVP, the bq24187 turns off the PWM converter, sends a
single 128μs pulse is sent on the STAT and INT outputs and the STATx and FAULT_x bits of the status registers
and the battery/supply status registers are updated in the I2C. Once the OVP fault is removed, the STATx and
FAULT_x bits are cleared and the device returns to normal operation.
8.4.1.1.2 Charge Mode Operation
8.4.1.1.2.1 Charge Profile
When a valid input source is connected, the CE bit in the control register determines whether a charge cycle is
initiated. By default, the bq24187 enables the charge cycle when a valid input source is connected (VIN>VUVLO
and VBAT+VSLP<VIN<VOVP). There are 4 loops that influence the charge current; constant current loop (CC),
constant voltage loop (CV), thermal regulation loop and input voltage dynamic power management loop (VINDPM). During the charging process, all four loops are enabled and the one that is dominant takes control. The
bq24187 supports a precision Li-Ion or Li-Polymer charging system for single-cell applications. Figure 8 shows a
typical charge.
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Device Functional Modes (continued)
Current regulation
phase
Precharge
phase
Voltage regulation
phase
Regulation
voltage
Regulation
current
VBATSHRT
(2.0 V)
Battery
voltage
Charge current
Termination
IBATSHRT
Figure 8. Typical Charging Profile Of Bq24187
8.4.1.1.3 Battery Charging Process
When the battery is deeply discharged or shorted, the bq24187 applies IBATSHORT to the battery to close the
battery protector switch and bring the battery voltage up to acceptable charging levels. Once the battery rises
above VBATSHRT, the charge current is regulated to the value set in the I2C register by the ICHARGE bits. The
charge current is regulated to ICHARGE until the voltage between BAT and PGND reaches the regulation voltage.
The voltage between BAT and PGND is regulated to VBATREG (CV mode) while the charge current naturally
tapers down as shown in Figure 8. During the CC or CV modes, if the die temperature heats up, the thermal
regulation loop reduces the input current to maintain a die temperature at 125°C.
When termination is enabled (TE bit is '1'), the bq24187 monitors the charging current during the CV mode. Once
the charge current tapers down to the termination threshold, ITERM, and the battery voltage is above the recharge
threshold, the bq24187 terminates charge and enters battery detection (see Battery Detection section for more
details). The termination current level is programmable. To disable the charge current termination, the host sets
the charge termination bit (TE) of charge control register to 0. Refer to I2C section for details. When termination
is disabled, VBAT is continuously regulated to VBATREG. Termination is also disabled when any loop is active other
than CC or CV. This includes VINDPM, input current limit, or thermal regulation. Termination is also disabled during
TS WARM/COOL conditions and when the LOW_CHG bit is set to '1'. A charge cycle is initiated when one of the
following conditions is detected:
• The battery voltage falls below the VBATREG-VRCH threshold
• IN Power-on reset (POR)
• CE bit toggle or RESET bit is set (Host controlled)
• CD terminal is toggled
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Device Functional Modes (continued)
8.4.1.1.3.1 Charge Time Optimizer
The CC to CV transition is enhanced in the bq24187 architecture. The "knee" between CC and CV is very sharp.
This enables the charger to remain in CC mode as long as possible before beginning to taper the charge current
(CV mode). This provides a decrease in charge time as compared to older topologies.
8.4.1.1.4 Battery Detection
When termination conditions are met, a battery detection cycle is started. During battery detection, IDETECT is
pulled from VBAT for tDETECT(SNK) to verify there is a battery. If the battery voltage remains above VDETECT for the
full duration of tDETECT(SNK), a battery is determined to be present and the IC enters “Charge Done”. If VBAT falls
below VDETECT, a “Battery Not Present” fault is signaled, the charge parameters are reset (VBATREG, ICHARGE and
ITERM) and battery detection continues. The next cycle of battery detection, the bq24187 turns on IBATSHRT for
tDETECT(SRC). If VBAT rises to VDET(SRC1), the current source is turned off and a “No Battery” condition is registered.
In order to keep VBAT high enough to close the battery protector, the current source turns on if VBAT falls to
VDET(SRC2). The source cycle continues for tDETECT(SRC). After tDETECT(SRC), the battery detection continues through
another current sink cycle. Battery detection continues until charge is disabled or a battery is detected. Once a
battery is detected, the fault status clears and a new charge cycle begins. Battery detection is not performed
when termination is disabled.
8.4.1.1.5 Battery Overvoltage Protection (BOVP)
If the battery is ever above the battery OVP threshold (VBOVP), the battery OVP circuit shuts the PWM converter
off to discharge the battery to safe operating levels. A battery OVP most commonly occurs when the bq24187
returns to DEFAULT mode after a watchdog timer expiration or RESET bit written to '1'. In this condition, the
VBATREG is reset and may be below the battery voltage. Other conditions may be when the input is initially
plugged in before I2C communication is established or TS WARM conditions or when writing the VBATREG to
less than the battery voltage. The battery OVP condition is cleared when the battery voltage falls below the
hysteresis of VBOVP either by the battery discharging or writing the VBATREG to a higher value. When a battery
OVP event exists for tDGL(BOVP), the bq24187 sends a single 128μs pulse on the STAT/ INT outputs and the
STATx and FAULT_x bits are updated in the I2C. Once the BOVP fault is removed, the STATx bits are cleared
and the device returns to normal operation. The FAULT_x bits are not cleared until they are read in the I2C after
the BOVP condition no longer exists.
8.4.1.1.6 Default Mode
DEFAULT mode is used when I2C communication is not available. DEFAULT mode is entered in the following
situations:
1. When the charger is enabled before I2C communication is established
2. When the watchdog timer expires without a reset from the I2C interface
3. The RESET bit is written in the I2C register
In DEFAULT mode, the I2C registers are reset to the default values. The 1.25 min safety timer is reset and starts
when DEFAULT mode is entered if a charge cycle is underway. The default value for VBATREG is 3.6V, and the
default value for ICHARGE is 1A. The input current limit in DEFAULT mode is set by PSEL. (See Power Source
Selector Input section) DEFAULT mode is exited by writing to the I2C interface. Note that if termination is
enabled and charging has terminated, a new charge cycle is NOT initiated when entering DEFAULT mode.
8.4.1.1.7 Power Source Selector Input (PSEL)
The bq24187 contains a PSEL input that is used to program the input current limit during DEFAULT mode. Drive
PSEL high to indicate a USB source is connected to the input and program the 100mA current limit for IN. Drive
PSEL low to indicate that an AC Adapter is connected to the input. When PSEL is low, the IC starts up with a
1.5A input current limit. Once an I2C write is done and the device is in HOST mode, the PSEL has no effect on
the input current limit until the watchdog timer expires and returns the bq24187 to DEFAULT mode.
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Device Functional Modes (continued)
8.4.1.1.8 Safety Timer and Watchdog Timer In Charge Mode
At the beginning of charging process, the bq24187 starts the safety timer. This timer is active during the entire
charging process. If charging has not terminated before the safety timer expires, the IC enters suspend mode
where charging is disabled. The safety timer time is selectable using the I2C interface. When a safety timer fault
occurs, a single 128μs pulse is sent on the STAT and INT outputs and the STATx bits of the status registers are
updated in the I2C. The CE bit, HZ_MODE bit, CD terminal or input power must be toggled in order to clear the
safety timer fault. The safety timer duration is selectable using the TMR_X bits in the Safety Timer Register/ NTC
Monitor register. Changing the safety timer duration resets the safety timer.
In addition to the safety timer, the bq24187 contains a 30-second (tWATCHDOG) watchdog timer that monitors the
host through the I2C interface. Once a write is performed on the I2C interface, a watchdog timer is started. The
watchdog timer is reset by the host using the I2C interface. This is done by writing a “1” to the reset bit
(TMR_RST) in the control register. The TMR_RST bit is automatically set to “0” when the watchdog timer is
reset. This process continues until battery is fully charged or the safety timer expires. If the watchdog timer
expires, the IC enters DEFAULT mode where the default charge parameters are loaded, the safety timer restarts
at 1.25 minutes and charging continues. The I2C may be accessed again to reinitialize the desired values and
restart the watchdog timer as long as the safety timer has not expired. Once the safety timer expires, charging is
disabled. This function prevents continuous charging of a defective battery if the host fails to reset the safety
timer. In the event the watchdog timer expires, the I2C circuit is reset as well. This prevents the I2C from
indefinitely hanging if the I2C master loses control during a read/write. The watchdog timer flow chart is shown in
Figure 9.
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Device Functional Modes (continued)
Start Safety Timer
Yes
Safety timer expired?
Safety timer
fault
No
Charging suspended
Enter suspended
mode
Fault indicated in
STAT registers
STAT = Hi
Update STAT
bits
Yes
Charge Done?
ICHG < ITERM
No
No
I2C Read/Write
performed?
Yes
Start watchdog timer
Charge Done?
ICHG < ITERM
Reset watchdog timer
STAT = Hi
Update STAT
bits
Yes
No
Yes
Safety timer expired?
Safety timer
fault
No
Charging suspended
Enter suspended
mode
Fault indicated in
STAT registers
WD timer expired?
Yes
No
Yes
Received
software watchdog
RESET?
No
Reset to default
2
values in I C
register
Restart 40 min
safety timer
Figure 9. The Watchdog Timer Flow Chart For Bq24187
8.4.1.1.9 LDO Output (DRV)
The bq24187 contains a linear regulator (DRV) that is used to supply the internal MOSFET drivers and other
circuitry. Additionally, DRV supplies up to 10mA external loads to power the STAT LED or the USB transceiver
circuitry. The maximum value of the DRV output is 5.3V so it ideal to protect voltage sensitive USB circuits. The
LDO is on whenever a supply is connected to the input of the bq24187. The LDO is on whenever a supply is
connected to the input of the bq24187. The DRV is disabled under the following conditions:
1. VSUPPLY < UVLO
2. VSUPPLY < VBAT + VSLP
3. Thermal Shutdown
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Device Functional Modes (continued)
8.4.1.1.10 External NTC Monitoring (TS)
The I2C interface allows the user to easily implement the JEITA standard for systems where the battery pack
thermistor is monitored by the host. Additionally, the bq24187 provides a flexible, voltage based TS input for
monitoring the battery pack NTC thermistor. The voltage at TS is monitored to determine that the battery is at a
safe temperature during charging. The JEITA specification is shown in Figure 10.
1.0 C
Charging Current 0.5 C
Portion of spec not covered by TS
Implementation on bq24187
4.25 V
VBAT 4.15 V
4.1 V
T1
(0°C)
T2
(10°C)
T3
T4
(45°C) (50°C)
Cold
Cool
Warm
T5
(60°C)
Hot
Figure 10. Charge Current During TS Conditions
To satisfy the JEITA requirements, four temperature thresholds are monitored; the cold battery threshold (TNTC <
0°C), the cool battery threshold (0°C < TNTC < 10°C), the warm battery threshold (45°C < TNTC < 60°C) and the
hot battery threshold (TNTC > 60°C). These temperatures correspond to the VCOLD, VCOOL, VWARM, and VHOT
thresholds in the EC table. Charging is suspended and timers are suspended when VTS < VHOT or VTS > VCOLD.
When VCOOL < VTS < VCOLD, the charging current is reduced to half of the programmed charge current. When
VHOT < VTS < VWARM, the battery regulation voltage is reduced by 140mV from the programmed regulation
threshold. The TS function is disabled by connecting TS directly to DRV (VTS > VTSOFF).
The TS function is voltage based for maximum flexibility. Connect a resistor divider from DRV to GND with TS
connected to the center tap to set the threshold. The connections are shown in Figure 11. The resistor values are
calculated using the following equations:
é 1
1 ù
VDRV ´ RCOLD ´ RHOT ´ ê
ú
V
V
HOT û
ë COLD
RLO =
éV
ù
é V
ù
RHOT ´ ê DRV - 1ú - RCOLD ´ ê DRV - 1ú
ë VHOT
û
ë VCOLD
û
(1)
VDRV
-1
VCOLD
RHI =
1
1
+
RLO RCOLD
(2)
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Device Functional Modes (continued)
Where:
VCOLD = 0.60 × VDRV
VHOT = 0.30 × VDRV
RLO ´ RHI ´ 0.564
RCOOL =
RLO - RLO ´ 0.564 - RHI ´ 0.564
RLO ´ RHI ´ 0.383
RWARM =
RLO - RLO ´ 0.383 - RHI ´ 0.383
(3)
(4)
Where RHOT is the NTC resistance at the hot temperature and RCOLD is the NTC resistance at cold
temperature.
The WARM and COOL thresholds are not independently programmable. The COOL and WARM NTC
resistances for a selected resistor divider are calculated using Equation 3 and Equation 4.
DISABLE
VBAT(REG)
– 100 mV
1 x Charge/
0.5 x Charge
TS COLD
TS COOL
TS WARM
VDRV
+
+
+
VDRV
TS HOT
RHI
+
TS
TEMP
PACK+
bq24187
+
–
RLO
PACK–
Figure 11. TS Circuit
8.4.1.1.11 Thermal Regulation and Protection
During the charging process, to prevent overheating in the chip, bq24187 monitors the junction temperature, TJ,
of the die and reduces the input current once TJ reaches the thermal regulation threshold, TREG. The input
current is reduced to zero when the junction temperature increases about 10°C above TREG. Once the input
current is reduced to 0, the system current is reduced while the battery supplements the load to supply the
system. When the input current is completely reduced to 0 and TJ>125°C, this is may cause a thermal shutdown
of the bq24187 if the die temperature rises too high. At any state, if TJ exceeds TSHTDWN, bq24187 stops charging
and disables the buck converter. During thermal shutdown mode, PWM is turned off, all timers are suspended,
and a single 128μs pulse is sent on the STAT and INT outputs and the STATx and FAULT_x bits of the status
registers are updated in the I2C. The charge cycle resumes when TJ falls below TSHTDWN by approximately 10°C.
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Device Functional Modes (continued)
8.4.1.1.12 Charge Status Outputs (STAT, INT)
The STAT/INT output is used to indicate operation conditions for bq24187. STAT/INT is pulled low during
charging when EN_STAT bit in the control register is set to “1”. When charge is complete or disabled, STAT/INT
is high impedance. When a fault occurs, a 128-µs pulse (interrupt) is sent out to notify the host. The status of
STAT/INT during different operation conditions is summarized in Table 1. STAT/INT drives an LED for visual
indication or can be connected to the logic rail for host communication. The EN_STAT bit in the control register is
used to enable/disable the charge status for STAT/INT. The interrupt pulses are unaffected by EN_STAT and will
always be shown.
Table 1. STAT Terminal Summary
CHARGE STATE
Charge in progress and EN_STAT=1
STAT
Low
Other normal conditions
High-Impedance
Charge mode faults: Timer fault, sleep mode, VIN over voltage, VIN < UVLO, thermal shutdown
128-μs pulse, then High Impedance
8.4.2 Boost Mode Operation
In HOST mode, when the operation mode bit (BOOST_EN) in the control register (bit 6 in register 0x00h) is set
to 1, bq24187 operates in boost mode and delivers 5V to IN to supply USB OTG devices connected to the USB
connector. Boost operation can start with VBAT between 3.45V to 4.5V, and will maintain boost output until
VBAT falls to 3.3V. IN supplies up to 1A to power these devices. It is not recommended to operate boost mode
when the battery voltage is less than 3.3V. Proper operation is not guaranteed.
8.4.2.1 PWM Controller In Boost Mode
Similar to charge mode operation, in boost mode the IC switches at 1.5MHz to regulate the voltage at IN to 5V.
The voltage control loop is internally compensated to provide enough phase margin for stable operation with the
full battery voltage range and up to 750mA.
In boost mode, the cycle-by-cycle current limit is set to 4A or 2A (depending on the I2C setting) to provide
protection against short circuit conditions. If the cycle-by-cycle current limit is active for 8 ms, an overload
condition is detected and the device exits boost mode, and signals an over-current fault. Additionally, discharge
current limit (ILIM(DISCH) is active to protect the battery from overload. Synchronous operation and burst mode are
used to maximize efficiency over the full load range.
The bq24187 will not enter boost mode unless the IN voltage is less than the UVLO and the IC is in high
impedance mode. When the boost function is enabled, the bq24187 enters a linear mode to bring IN up to the
battery voltage. Once VIN > (VBAT – 1V), the bq24187 begins switching and regulates IN up to 5V. If VIN does not
rise to within 1V of VBAT within 8ms, an over-current event is detected and boost mode is exited and a boost
mode over-current event is announced, the BOOST bit is reset to ‘0’ and the STAT_x and FAULT_x bits in the
Status/ Control register are updated.
8.4.2.2 Burst Mode During Light Load
In boost mode, the IC operates using burst mode to improve light load efficiency and reduce power loss. During
boost mode, the PWM converter is turned off when the devices reaches minimum duty cycle and the output
voltage rises to VBURST_ENT threshold. This corresponds to approximately a 75mA inductor current. The converter
then restarts when VIN falls to VBURST_EXT. See Figure 21 in the Application Curves for an example waveform.
8.4.2.3 Watchdog Timer In Boost Mode
During boost mode, the watchdog timer is active. The watchdog timer works the same as in charge mode. Write
a “1” to the TMR_RST reset bit in the control register. If the watchdog timer expires, the IC resets the BOOST bit
to 0, signals the fault pulse on the STAT and INT terminals and sets fault status bits in the status register.
8.4.2.4 STAT/ INT During Boost Mode
During boost mode, the STAT and INT outputs are high impedance. Under fault conditions, a 128µs pulse is sent
out to notify the host of the error condition.
22
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8.4.2.5 Protection In Boost Mode
8.4.2.5.1 Output Over-Voltage Protection
The bq24187 contains integrated over-voltage protection on the IN terminal. During boost mode, if an overvoltage condition is detected (VIN.VBOOSTOVP), the IC turns off the PWM converter, resets EN_BOOST bit to 0,
sets fault status bits and sends out a fault pulse on STAT and INT. The converter does not restart when VIN
drops to the normal level until the EN_BOOST bit is reset to 1.
8.4.2.5.2 Output Over-Current Protection
The bq24187 contains over current protection to prevent the device and battery damage when IN is overloaded.
When an over-current condition occurs, the cycle-by-cycle current limit limits the current from the battery to the
load. If the overload condition lasts for 8 consecutive cycles, the overload fault is detected. When an overload
condition is detected, the bq24187 turns off the PWM converter, resets BOOST bit to 0, sets the fault status bits
and sends out the fault pulse on STAT and INT. The boost starts only after the fault is cleared and the
EN_BOOST bit is reset to 1 using the I2C.
8.4.2.5.3 Battery Overvoltage Protection
During boost mode, when the battery voltage is below the minimum battery voltage threshold, VBATUVLO, the
IC turns off the PWM converter, resets BOOST bit to 0, sets fault status bits and sends out a fault pulse on STAT
and INT. Once the battery voltage returns to the acceptable level, the boost starts after the BOOST bit is set to 1.
Proper operation below 3.3V down to the VBATUVLO is not specified.
8.5 Programming
8.5.1 Serial Interface Description
The bq24187 uses an I2C compatible interface to program charge parameters. I2C™ is a 2-wire serial interface
developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of
a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines
are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O terminals, SDA and
SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addresses. The master also generates specific conditions
that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus
under control of the master device.
The bq24187 device works as a slave and supports the following data transfer modes, as defined in the I2C
Bus™ Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the
battery charge solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. Register contents remain intact as long as battery voltage remains
above 2.5 V (typical). The I2C circuitry is powered from VBUS when a supply is connected. If the VBUS supply is
not connected, the I2C circuitry is powered from the battery through CSOUT. The battery voltage must stay
above 2.5V with no input connected in order to maintain proper operation.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The bq24187/1 device only supports 7-bit addressing. The device 7-bit address is
defined as ‘1101011’ (0x6Bh).
8.5.1.1 F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 12. All I2C-compatible devices should
recognize a start condition.
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Programming (continued)
DATA
CLK
S
P
START Condition
STOP Condition
Figure 12. Start And Stop Condition
The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 13). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 13) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 13. Bit Transfer On The Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the
slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 15). This releases the bus and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of
a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to
prevent the slave I2C logic from getting stuck in a bad state. Attempting to read data from register addresses not
listed in this section will result in FFh being read out.
24
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Programming (continued)
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
1
2
9
8
Clock Pulse for
Acknowledgement
START
Condition
Figure 14. Acknowledge On The I2C Bus
Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
Acknowledgement
Signal From Slave
MSB
Sr
Address
R/W
SCL
S
or
Sr
ACK
ACK
Sr
or
P
Clock Line Held Low While
Interrupts are Serviced
Figure 15. Bus Protocol
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8.6 Register Maps
Table 2. Status/Control Register (READ/WRITE)
Memory Location: 00, Reset State: 00xx 0xxx
BIT
NAME (1)
(2)
READ/WRITE
FUNCTION
B7 (MSB)
TMR_RST
Read/Write
Write: TMR_RST function, write "1" to reset the watchdog timer (auto clear)
Read: Always 0
B
BOOST
Read/Write
0-Charger Mode
1-Boost Mode (default 0)
B5
STAT_1
Read Only
B4
STAT_0
Read Only
B3
NA
Read/Write
Only
B2
FAULT_2
Read Only
B1
FAULT_1
Read Only
B0 (LSB)
FAULT_0
Read Only
(1)
(2)
NA
000-Normal
001-VIN > VOVP or Boost Mode OVP
010- Low Supply connected (VIN<VUVLO or VIN<VSLP) or Boost Mode Overcurrent
011- Thermal Shutdown
100-Battery Temperature Fault
101- Timer Fault (watchdog or safety timer)
110-Battery OVP
111-No Battery connected
STAT_x bits show current status. These bits change based on the current condition.
FAULT_x bits show faults. If a fault occurs, these bits announce the fault and do not clear until read. If more than one fault occurs, the
first fault is shown.
BOOST Bit
(Operation Mode)
26
00-Ready
01-Charge in progress,
10-Charge done
11-Fault
The BOOST bit selects the operation mode for the bq24187. Write a “1” to enable
boost mode and regulate IN to 5V to supply OTG peripherals. See “Boost Mode
Operation” section for more details
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Table 3. Control Register (Read/Write)
Memory Location: 01, Reset State: 1xxx 1110
BIT
NAME
READ/WRITE
B7 (MSB)
RESET
Write only
B6
IN_LIMIT_2
Read/Write
B5
IN_LIMIT_1
Read/Write
B4
IN_LIMIT_0
Read/Write
B3
EN_STAT
Read/Write
0-Disable STAT function (STAT only shows faults)
1-Enable STAT function (default 1)
B2
TE
Read/Write
0-Disable charge current termination
1-Enable charge current termination (default 1)
B1
CE
Read/Write
0-Charger enabled
1-Charger is disabled (default 0)
B0 (LSB)
HZ_MODE
Read/Write
0-Not high impedance mode
1-High impedance mode (default 0)
(1)
FUNCTION
Write: 1-Reset all registers to default values
0-No effect
Read: always get “1”
000-USB2.0 host with 100mA current limit
001-USB3.0 host with 150mA current limit
010 – USB2.0 host with 500mA current limit
011 – USB3.0 host/charger with 900mA current limit
100 – Charger with 1500mA current limit
101—NA
110 – Charger with 2500mA current limit
111-NA (default xxx (1))
When in DEFAULT mode, the D+/D– inputs or PSEL determine the default input current limit.
RESET Bit
The RESET bit in the control register (0x01h) is used to reset all the charge
parameters. Write “1” to RESET bit to reset all the registers to default values and
place the bq24187 into DEFAULT mode and turn off the watchdog timer. The RESET
bit is automatically cleared to zero once the bq24187 enters DEFAULT mode.
CE Bit
(Charge Enable)
The CE bit in the control register (0x01h) is used to disable or enable the charge
process. A low logic level (0) on this bit enables the charge and a high logic level (1)
disables the charge.
HZ_MODE Bit
The HZ_MODE bit in the control register (0x01h) is used to disable or enable the high
(High Impedance Mode impedance mode. A low logic level (0) on this bit enables the IC and a high logic level
Enable)
(1) puts the IC in a low quiescent current state called high impedance mode. When in
high impedance mode, the converter is off.
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Table 4. Control/Battery Voltage Register (Read/Write)
Memory Location: 02, Reset State: 0001 0100
BIT
NAME
READ/WRITE
FUNCTION
B7 (MSB)
VBREG5
Read/Write
Battery Regulation Voltage: 640 mV (default 0)
B6
VBREG4
Read/Write
Battery Regulation Voltage: 320 mV (default 0)
B5
VBREG3
Read/Write
Battery Regulation Voltage: 160 mV (default 0)
B4
VBREG2
Read/Write
Battery Regulation Voltage: 80 mV (default 0)
B3
VBREG1
Read/Write
Battery Regulation Voltage: 40 mV (default 1)
B2
VBREG0
Read/Write
Battery Regulation Voltage: 20 mV (default 0)
B1
MOD_FREQ1
Read/Write
B0 (LSB)
MOD_FREQ2
Read/Write
Modify Switching Frequency Target –
00 – No Change to Nominal Frequency Target
01 – +10% Change to Nominal Frequency
10 – –10% Change to Nominal Frequency
11 – NA (default 00)
VBREG Bits
(Battery Regulation
Threshold setting)
Use VBREG bits to set the battery regulation threshold. The VBATREG is calculated
using the following equation:
VBATREG = 3.5 V + VBREGCODE × 20 mV
The charge voltage range is 3.5V to 4.44V with the offset of 3.5V and step of 20mV.
The default setting is 3.6V. If a value greater than 4.44V is written, the setting goes to
4.44V. It is recommended to set VBATREG above VMINSYS.
MOD_FREQx Bits
(Frequency
Modification)
The MOD_FREQx bits are used to change the switching frequency by ±10%. This is
used for applications where the 1.5MHz switching frequency noise interferes with
other device operation. The frequency may be modified by ±10% of the nominal
frequency.
Table 5. Vender/Part/Revision Register (Read only)
Memory Location: 03, Reset State: 0100 0110
28
BIT
NAME
READ/WRITE
B7 (MSB)
Vender2
Read Only
Vender Code: bit 2 (default 0)
B6
Vender1
Read Only
Vender Code: bit 1 (default 1)
B5
Vender0
Read Only
Vender Code: bit 0 (default 0)
B4
PN1
Read Only
B3
PN0
Read Only
B2
Revision2
Read Only
B1
Revision1
Read Only
B0 (LSB)
Revision0
Read Only
FUNCTION
For I2C Address 6Bh: 00–bq24187
Revision Code
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Table 6. Battery Termination/Fast Charge Current Register (Read/Write)
Memory Location: 04, Reset State: 0010 1010
BIT
NAME
READ/WRITE
FUNCTION
B7 (MSB)
VICHRG4
Read/Write
Charge current: 1600mA – (default 0)
B6
VICHRG3
Read/Write
Charge current: 800mA— (default 0)
B5
VICHRG2
Read/Write
Charge current: 400mA—(default 1)
B4
VICHRG1
Read/Write
Charge current: 200mA— (default 0)
B3
VICHRG0
Read/Write
Charge current: 100mA (default 1)
B2
VITERM2
Read/Write
Termination current sense: 200mA (default 0)
B1
VITERM1
Read/Write
Termination current sense voltage: 100mA (default 1)
B0 (LSB)
VITERM0
Read/Write
Termination current sense voltage: 50mA (default 0)
ICHRG Bits
(Charge Current Regulation
Threshold setting)
Use ICHRG bits to set the charge current regulation threshold. The charge
current is programmable from 500mA to 2A in 100mA steps. The default is
1A. The ICHARGE is calculated using the following equation:
ICHARGE = 500 mA + ICHRGCODE× 50 mA
ITERM Bits
(Charge Current Termination
Threshold setting)
Use ITERM bits to set the charge current termination threshold. The
termination threshold is programmable from 50mA to 300mA in 50mA steps.
The default is 150mA. The ITERM is calculated using the following equation:
ITERM = 50 mA + ITERMCODE × 50 mA
Any setting programmed above 300mA selects the 300mA setting.
Table 7. VIN-DPM Voltage/ DPPM Status Register
Memory location: 05, Reset state: xx00 x000
BIT
NAME
READ/WRITE
FUNCTION
B7 (MSB)
NA
Read Only
NA
B6
DPM_STATUS
Read Only
0 – VIN-DPM mode is not active
1 – VIN-DPM mode is active
B5
LOW_CHG
Read/Write
0 – Normal charge current set by 04h
1 – Low charge current setting 300mA (default 0)
B4
NA
Read Only
NA
B3
CD_STATUS
Read Only
0 – CD low, IC enabled
1 – CD high, IC disabled
B2
VINDPM2
Read/Write
Input VIN-DPM voltage: VDPMOFF + 8% (default 0)
B1
VINDPM1
Read/Write
Input VIN-DPM voltage: VDPMOFF + 4% (default 0)
B0 (LSB)
VINDPM0
Read/Write
Input VIN-DPM voltage: VDPMOFF + 2% (default 0)
VIN-DPM voltage offset is 4.2V.
LOW_CHG Bit
(Low Charge Mode
Enable)
The LOW_CHG bit is used to reduce the charge current to a minimum current. This
feature is used by systems where battery NTC is monitored by the host and requires
a reduced charge current setting or by systems that need a “preconditioning” current
for low battery voltages. Write a “1” to this bit to charge at 300mA. Write a “0” to this
bit to charge at the programmed charge current.
VINDPM Bits
(VINDPM Threshold
setting)
Use VINDPM bits to set the VINDPM regulation threshold. The VINDPM threshold is
calculated using the following equation:
VINDPM = VINDPM_OFF + VINDPMCODE × 2% ×VINDPM_OFF
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Table 8. Safety Timer/ NTC Monitor Register (READ/WRITE)
Memory location: 06, Reset state: 1001 1xx0
BIT
NAME
READ/WRITE
B7 (MSB)
2XTMR_EN
Read/Write
B6
TMR_1
Read/Write
B5
TMR_2
Read/Write
B4
BOOST_ILIM
Read/Write
0—500mA
1—750mA (Default 1)
B3
TS_EN
Read/Write
0 – TS function disabled
1 – TS function enabled (default 1)
B2
TS_FAULT1
Read only
B1
TS_FAULT0
Read only
B0 (LSB)
NA
Read/Write
BOOST_ILIM Bit
.(Boost current
limit setting)
30
FUNCTION
0 – Timer not slowed at any time
1 – Timer slowed by 2x when in thermal regulation, VIN_DPM or DPPM (default 1)
Safety Timer Time Limit –
00—40 minute fast charge
01 – 6 hour fast charge
10 – 9 hour fast charge
11 – Disable safety timers (default 00) (bq24187/1 only)
TS Fault Mode:
00— Normal, No TS fault
01— TS temp < TCOLD or TS temp > THOT(Charging suspended)
10— TCOOL > TS temp > TCOLD (Charge current reduced by half)
11— TWARM < TS temp < THOT (Charge voltage reduced by 100mV)
Always write to ‘0’
The BOOST_ILIM bit programs the cycle by cycle current limit threshold for boost
operation. The 1A setting sets the low side cycle by cycle current limit to 4A (typ).
This ensures that at least 1A can be supplied from the boost converter over the entire
battery range. The 500mA setting sets the current limit to 2A(typ) to ensure at least
500mA available from the boost converter. See the boost mode over-current section
for more details
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9 Applications and Implementation
9.1 Application Information
The bq24187-625 evaluation module (EVM) is a complete charger module for evaluating the bq24187. The
application curves were taken using the bq24187EVM-625. See Related Documentation.
9.2 Typical Application
1.5uH
PMID
SW
1uF
0.033uF
BOOT
CS+
IN
VBUS
D+
20uF
DGND
4.7uF
DRV
BAT
SYSTEM
VDRV
1uF
1uF
PGND
STAT
PACK+
TS
TEMP
VI/O
(1.8V)
PSEL
USB PHY
PACK-
HOST
bq24187
INT
GPIO1
SDA
SDA
SCL
SCL
CD
Figure 16. bq24187 Typical Application Circuit
9.2.1 Design Requirements
Table 9. Design Requirements
DESIGN PARAMATER
EXAMPLE VALUE
Input Voltage Range
4.75 V to 5.25 V nominal, withstand 28 V
Input Current Limit
1500 mA
Input DPM Threshold
4.25 V
Fast Charge Current
2000 mA
Battery Charge Voltage
4.2 V
Termination Current
150 mA
9.2.2 Detailed Design Procedure
The parameters are configurable using the EVM software.
The typical application circuit shows the minimum capacitance requirements for each terminal. Options for sizing
the inductor outside the 1.5 μH recommended value and additional SYS terminal capacitance are explained in
the next section. The resistors on STAT and INT are sized per each LED's current requirements. The TS resistor
divider for configuring the TS function to work with the battery's specific thermistor can be computed from
Equation 1 and Equation 2. The external battery FET is optional.
9.2.2.1 Output Inductor And Capacitor Selection Guidelines
When selecting an inductor, several attributes must be examined to find the right part for the application. First,
the inductance value should be selected. The bq24187 is designed to work with 1.5µH to 2.2µH inductors. The
chosen value will have an effect on efficiency and package size. Due to the smaller current ripple, some
efficiency gain is reached using the 2.2µH inductor, however, due to the physical size of the inductor, this may
not be a viable option. The 1.5µH inductor provides a good tradeoff between size and efficiency.
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Once the inductance has been selected, the peak current must be calculated in order to choose the current
rating of the inductor. Use Equation 5 and Equation 6 to calculate the peak current.
V - VBAT
VBAT
%RIPPLE = IN
´
L
VIN ´ ¦ SW
(5)
For the 5V adapter case, a good rule of thumb is to use 3.5V as VBAT. This provides a reasonable worst case
ripple. For higher adapters, the closer to 50% duty cycle, the worse the ripple.
æ %
ö
IPEAK = ICHARGE ´ ç 1 + RIPPPLE ÷
2
è
ø
(6)
The inductor selected must have a saturation current rating greater than or equal to the calculated IPEAK. Due to
the high currents possible with the bq24187, a thermal analysis must also be done for the inductor. Many
inductors have 40°C temperature rise rating. This is the DC current that will cause a 40°C temperature rise
above the ambient temperature in the inductor. For this analysis, the typical load current may be used adjusted
for the duty cycle of the load transients. For example, if the application requires a 1.5A DC load with peaks at
2.5A 20% of the time, a Δ40°C temperature rise current must be greater than 1.7A:
ITEMPRISE = ILOAD + D ´ (IPEAK - ILOAD ) = 1.5A + 0.2 ´ (2.5A - 1.5A) = 1.7A
(7)
The internal loop compensation of the bq24187 is designed to be stable with 10µF to 150µF of local capacitance
but requires at least 20µF total capacitance on CS+. To reduce the output voltage ripple, a ceramic capacitor
with the capacitance between 20µF and 47µF is recommended for local bypass to CS+. If more than 100µF is
placed on CS+, place at least 10µF from BAT to GND.
9.2.3 Application Curves
Figure 17. Boost Startup No Load
32
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Figure 19. Boost Transient Response
Figure 20. Input OVP Event With INT
95.00%
Efficiency (%)
90.00%
85.00%
80.00%
VBAT = 4.2 V
VBAT = 3.6 V
75.00%
0.5
1.0
1.5
2.0
ICHG (A)
C002
VIN = 5 V
Figure 21. Boost Burst Mode During Light Load
TA = 25°C
Figure 22. Charger Efficiency vs Battery Voltage
100.00%
95.00%
80.00%
Efficiency (%)
Efficiency (%)
90.00%
85.00%
80.00%
60.00%
40.00%
20.00%
VBAT = 3.6 V
ICHG = 1A
ICHG = 2A
75.00%
2.5
3
3.5
4
4.5
VBAT (V)
VIN = 5 V
VBATREG = 4.44 V
VBAT = 4.2 V
0.00%
0.0
0.2
0.4
0.6
0.8
Load Current (A)
C001
1.0
C003
TA = 25°C
Figure 23. Charger Efficiency vs Charge Current
Figure 24. Boost Efficiency vs Load Current
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10 Layout
10.1 Layout Guidelines
It is important to pay special attention to the PCB layout. Figure 25 provides a sample layout for the high current
paths of the bq24187YFF.
The following provides some guidelines:
• Place 4.7µF input capacitor as close to IN terminal and PGND terminal as possible to make high frequency
current loop area as small as possible.
• Place 1µF input capacitor as close to PMID terminal and PGND terminal as possible to make high frequency
current loop area as small as possible. Connect the GND of the PMID and IN caps as close as possible.
• The local bypass capacitor from CS+ to GND should be connected between the CS+ terminal and PGND of
the IC. The intent is to minimize the current path loop area from the SW terminal through the LC filter and
back to the PGND terminal.
• Place all decoupling capacitor close to their respective IC terminal and as close as to PGND (do not place
components such that routing interrupts power stage currents). All small control signals should be routed
away from the high current paths.
• The PCB should have a ground plane (return) connected directly to the return of all components through vias
(two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal components). It is
also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach is
typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noisecoupling and ground-bounce issues. A single ground plane for this design gives good results. With this small
layout and a single ground plane, there is no ground-bounce issue, and having the components segregated
minimizes coupling between signals.
• The high-current charge paths into IN, BAT, CS+ and from the SW terminals must be sized appropriately for
the maximum charge current in order to avoid voltage drops in these traces. The PGND terminals should be
connected to the ground plane to return current through the internal low-side FET.
• For high-current applications, the balls for the power paths should be connected to as much copper in the
board as possible. This allows better thermal performance as the board pulls heat away from the IC.
34
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10.2 Layout Example
PMID and IN
CAP Gnds
PMID
Close together
PGND
IN Cap
SW
Close to
IN Terminal
BOOT
Thermal
CS+ Cap
Vias Connect
Close to
to PGND
CS+ Terminals
BAT Cap
Close to
BAT Terminals
Figure 25. Recommended bq24187 PCB Layout For WCSP Package
PGND
SW
PMID
PMID and IN
Cap Gnds
BOOT
Close together
CS+ Cap
Close to
IN Cap
CS+ Terminals
Close to
IN Terminal
BAT Cap
Close to
Thermal
BAT Terminals
Vias connect
To GND
Figure 26. Recommended bq24187 PCB Layout For QFN Package
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Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: bq24187
35
bq24187
Not Recommended for New Designs
SLUSBM0 – APRIL 2014
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
High-efficiency, Switch-mode Battery Charge Evaluation Module User's Guide, SLUUAI5
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
36
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Product Folder Links: bq24187
PACKAGE OPTION ADDENDUM
www.ti.com
7-Aug-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ24187YFFR
NRND
DSBGA
YFF
36
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24187
BQ24187YFFT
NRND
DSBGA
YFF
36
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24187
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Aug-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
BQ24187YFFR
DSBGA
YFF
36
3000
180.0
8.4
BQ24187YFFT
DSBGA
YFF
36
250
180.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2.54
2.54
0.76
4.0
8.0
Q1
2.54
2.54
0.76
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ24187YFFR
DSBGA
YFF
36
3000
182.0
182.0
20.0
BQ24187YFFT
DSBGA
YFF
36
250
182.0
182.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0036
DSBGA - 0.625 mm max height
SCALE 4.500
DIE SIZE BALL GRID ARRAY
B
E
A
BUMP A1
CORNER
D
C
0.625 MAX
SEATING PLANE
BALL TYP
0.30
0.12
0.05 C
2 TYP
SYMM
F
D: Max = 2.485 mm, Min =2.425 mm
E
D
2
TYP
C
B
36X
A
0.4 TYP
E: Max = 2.485 mm, Min =2.425 mm
SYMM
1
2
3
4
5
6
0.3
0.2
0.015
C A
B
0.4 TYP
4222008/A 03/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0036
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
36X ( 0.23)
1
2
3
4
5
6
A
(0.4) TYP
B
C
SYMM
D
E
F
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
( 0.23)
METAL
0.05 MAX
0.05 MIN
( 0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4222008/A 03/2015
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0036
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
36X ( 0.25)
1
2
4
3
5
6
A
(0.4)
TYP
METAL
TYP
B
C
SYMM
D
E
F
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4222008/A 03/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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