DP7113 100-Tap Digital Potentiometer (DP) Description The DP7113 is a single digital potentiometer (DP) designed as an electronic replacement for mechanical potentiometers. Ideal for automated adjustments on high volume production lines, they are also well suited for applications where equipment requiring periodic adjustment is either difficult to access or located in a hazardous or remote environment. The DP7113 contains a ïWDS series resistor array connected between two terminals RH and RL. An up/down counter and decoder that are controlled by three input pins, determines which tap is connected to the wiper, RW. The wiper setting, stored in nonvolatile memory, is not lost when the device is powered down and is automatically reinstated when power is returned. The wiper can be adjusted to test new system values without affecting the stored setting. Wiperïcontrol of the DP7113 is accomplished with three input control pins, CS, U/D, and INC. The INC input increments the wiper in the direction which is determined by the logic state of the U/D input. The CS input is used to select the device and also store the wiper position prior to power down. The digital potentiometer can be used as a three-terminal resistive divider or as a two-terminal variable resistor. SOICï8 TSSOPï8 PIN CONFIGURATIONS 1 100ïposition Linear Taper Potentiometer Nonïvolatile EEPROM Wiper Storage 10 nA Ultraïlow Standby Current Single Supply Operation: 2.5 V ï 6.0 V Increment Up/Down Serial Interface Resistance Values: 1 k , 10 k , 50 k and 100 k Available in SOIC, TSSOP and MSOP Packages These Devices are PbïFree, Halogen Free/BFR Free and are RoHS Compliant SOIC (V), MSOP (Z) 1 RL RW GND RH CS VCC INC U/D TSSOP (Y) (Top Views) PIN FUNCTION Applications v v v v v v v VCC CS RL RW INC U/D RH GND Features v v v v v v v v MSOPï8 Pin Name Automated Product Calibration Remote Control Adjustments Offset, Gain and Zero Control Tamperïproof Calibrations Contrast, Brightness and Volume Controls Motor Controls and Feedback Systems Programmable Analog Functions Function INC Increment Control U/D Up/Down Control RH Potentiometer High Terminal GND Ground RW Wiper Terminal RL Potentiometer Low Terminal CS Chip Select VCC Supply Voltage ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. ¢ NIDEC COPAL ELECTRONICS CORP. August, 2010 ï Rev. 24 1 Publication Order Number: DP7113/D DP7113 DEVICE MARKING INFORMATION SOIC MSOP TSSOP RL4A CAT5113VI YMXXXX AARR YMP A3RL 4YMXXX R = Resistance: ABCN = DP7113ZIï01ïT3 0=1k AARR = DP7113ZIï10ïT3 2 = 10 k AARC = DP7113ZIï50ïT3 4 = 50 k AARG = DP7113ZIï00ïT3 5 = 100 k Y = Production Year (Last Digit) L = Assembly Location M = Production Month 4 = Lead Finish ï NiPdAu (ï9, A, B, C or O, N, D) P = Product Revision A = Product Revision (Fixed as “A”) CAT5113V = Device Code I = Temperature Range (Industrial) Y = Production Year (Last Digit) M = Production Month (ï9, A, B, C or O, N, D) XXXX = Last Four Digits of Assembly Lot Number 2 A3 = Device Code R = Resistance: 0=1k 2 = 10 k 4 = 50 k 5 = 100 k L = Assembly Location 4 = Lead Finish ï NiPdAu Y = Production Year (Last Digit) M = Production Month (ï9, A, B, C or O, N, D) XXX = Last Three Digits of XXX = Assembly Lot Number DP7113 Functional Diagram VCC U/D INC CS 7ïBit Up/Down Counter INC Control and Memory RW 97 7ïBit Nonvolatile Memory 96 1 of 100 Decoder CS Power On Recall GND RH 98 RH U/D RH 99 Transfer Gates Resistor Array RW 2 RL VCC GND Store and Recall Control Circuitry 1 0 RL RW Figure 1. General Figure 2. Detailed Pin Description INC: Increment Control Input The INC input moves the wiper in the up or down direction determined by the condition of the U/D input. U/D: Up/Down Control Input The U/D input controls the direction of the wiper movement. When in a high state and CS is low, any highïtoïlow transition on INC will cause the wiper to move one increment toward the RH terminal. When in a low state and CS is low, any highïtoïlow transition on INC will cause the wiper to move one increment towards the RL terminal. RH: High End Potentiometer Terminal RH is the high end terminal of the potentiometer. It is not required that this terminal be connected to a potential greater than the RL terminal. Voltage applied to the RH terminal cannot exceed the supply voltage, VCC or go below ground, GND. RW: Wiper Potentiometer Terminal RW is the wiper terminal of the potentiometer. Its position on the resistor array is controlled by the control inputs, INC, U/D and CS. Voltage applied to the RW terminal cannot exceed the supply voltage, VCC or go below ground, GND. RL: Low End Potentiometer Terminal RL is the low end terminal of the potentiometer. It is not required that this terminal be connected to a potential less than the RH terminal. Voltage applied to the RL terminal cannot exceed the supply voltage, VCC or go below ground, GND. RL and RH are electrically interchangeable. CS: Chip Select The chip select input is used to activate the control input of the DP7113 and is active low. When in a high state, activity on the INC and U/D inputs will not affect or change the position of the wiper. RL Figure 3. Electronic Potentiometer Implementation Device Operation The DP7113 operates like a digital potentiometer with R H and R L equivalent to the high and low terminals and RW equivalent to the mechanical potentiometer·s wiper. There are 100 available tap positions including the resistor end points, RH and RL. There are 99 resistor elements connected in series between the RH and RL terminals. The wiper terminal is connected to one of the 100 taps and controlled by three inputs, INC, U/D and CS. These inputs control a sevenïbit up/down counter whose output is decoded to select the wiper position. The selected wiper position can be stored in nonvolatile memory using the INC and CS inputs. With CS set LOW the DP7113 is selected and will respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement the wiper (depending on the state of the U/D input and sevenïbit counter). The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. When the DP7113 is powereGïdown, the last stored wiper counter position is maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the counter is set to the value stored. With INC set low, the DP7113 may be dHïselected and powered down without storing the current wiper position in nonvolatile memory. This allows the system to always power up to a preset value stored in nonvolatile memory. 3 DP7113 Table 1. OPERATION MODES INC CS U/D Operation High to Low Low High Wiper toward H High to Low Low Low Wiper toward L High Low to High X Store Wiper Position Low Low to High X No Store, Return to Standby X High X Standby Table 2. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Supply Voltage VCC to GND ï0.5 to +7 Inputs CS to GND ï0.5 to VCC +0.5 Units V V INC to GND ï0.5 to VCC +0.5 V U/D to GND ï0.5 to VCC +0.5 V RH to GND ï0.5 to VCC +0.5 V RL to GND ï0.5 to VCC +0.5 V RW to GND ï0.5 to VCC +0.5 V ï40 to +85 oC Junction Temperature +150 oC Storage Temperature ï65 to 150 oC +300 oC Operating Ambient Temperature Industrial ¶,· suffix) Lead Soldering (10 s max) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. RELIABILITY CHARACTERISTICS Symbol Parameter VZAP (Note 1) ESD Susceptibility MILïSTDï883, Test Method 3015 2000 V LatchïUp JEDEC Standard 17 100 mA Data Retention MILïSTDï883, Test Method 1008 100 Years Endurance MILïSTDï883, Test Method 1003 1,000,000 Stores ILTH (Notes 1, 2) TDR NEND Test Method Min Typ 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latchïup protection is provided for stresses up to 100 mA on address and data pins from ï1 V to VCC + 1 V 4 Max Units DP7113 Table 4. DC ELECTRICAL CHARACTERISTICS (VCC = +2.5 V to +6 V unless otherwise specified) Parameter Min Typ Max Units 2.5 – 6.0 V VCC = 6 V, f = 1 MHz, IW = 0 – – 100 A VCC = 6 V, f = 250 kHz, IW = 0 – – 50 A Programming, VCC = 6 V – – 1000 A VCC = 3 V – – 500 A Supply Current (Standby) CS = VCC ï 0.3 V U/D, INC = VCC ï 0.3 V or GND – 0.01 1 A IIH Input Leakage Current VIN = VCC – – 10 A IIL Input Leakage Current VIN = 0 V – – ï10 A VIH2 CMOS High Level Input Voltage 2.5 V b VCC b 6 V VCC x 0.7 – VCC + 0.3 V VIL2 CMOS Low Level Input Voltage ï0.3 – VCC x 0.2 V Symbol Conditions POWER SUPPLY VCC Operating Voltage Range ICC1 Supply Current (Increment) ICC2 ISB1 (Note 3) Supply Current (Write) LOGIC INPUTS POTENTIOMETER CHARACTERISTICS RPOT Potentiometer Resistance ï01 Device 1 ï10 Device 10 ï50 Device 50 ï00 Device 100 Pot. Resistance Tolerance VRH Voltage on RH pin 0 VRL Voltage on RL pin 0 Resolution k p20 % VCC V VCC 1 V % INL Integral Linearity Error IW b 2 A 0.5 1 LSB DNL Differential Linearity Error IW b 2 A 0.25 0.5 LSB RWI Wiper Resistance VCC = 5 V, IW = 1 mA 400 VCC = 2.5 V, IW = 1 mA 1000 IW Wiper Current TCRPOT TC of Pot Resistance TCRATIO Ratiometric TC VN CH/CL/CW fc Noise ï4.4 (Note 4) 100 kHz / 1 kHz Passive Attenuator, 10 k ppm/oC 8/24 nV/Hz 8/8/25 pF 1.7 MHz 3. Latchïup protection is provided for stresses up to 100 mA on address and data pins from ï1 V to VCC + 1 V 4. This parameter is not 100% tested. 5 mA ppm/oC 20 Potentiometer Capacitances Frequency Response 4.4 300 DP7113 Table 5. AC TEST CONDITIONS VCC Range 2.5 V b VCC b 6 V Input Pulse Levels 0.2 VCC to 0.7 VCC Input Rise and Fall Times 10 ns Input Reference Levels 0.5 VCC Table 6. AC OPERATING CHARACTERISTICS (VCC = +2.5 V to +6.0 V, VH = VCC, VL = 0 V, unless otherwise specified) Symbol Parameter Min Typ (Note 5) Max Units tCI CS to INC Setup 100 ï ï ns tDI U/D to INC Setup 50 ï ï ns tID U/D to INC Hold 100 ï ï ns tIL INC LOW Period 250 ï ï ns tIH INC HIGH Period 250 ï ï ns tIC INC Inactive to CS Inactive 1 ï ï s tCPH CS Deselect Time (NO STORE) 100 ï ï ns tCPH CS Deselect Time (STORE) 10 ï ï ms INC to VOUT Change ï 1 5 s INC Cycle Time 1 ï ï s tR, tF (Note 6) INC Input Rise and Fall Time ï ï 500 s tPU (Note 6) Powerïup to Wiper Stable – – 1 ms Store Cycle – 5 10 ms tIW tCYC tWR 5. Typical values are for TA = 25oC and nominal supply voltage. 6. This parameter is periodically sampled and not 100% tested. CS tCYC tCI tIL tIC tIH (store) tCPH 90% INC 90% 10% tDI tID tF U/D tR MI (Note 7) tIW RW Figure 4. A.C. Timing 7. MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position. 6 DP7113 Applications Information (a) resistive divider (b) variable resistance (c) twoïport Figure 5. Potentiometer Configuration Applications V1 (ï) 3 2 + 1 R3 +5 V 4A 9 – 3 10 8 + 11 R2 R1 +5 V +5 V 8 – +5 V 8 2 1 DP 7 R4 R2 2 1 DP 7 R1 RA 6 4 VO 4 pRPOT 8 7 5 (1ïp)R POT 3 3 RB 555 4 R2 6 5 – R4 R3 7 + 6 +2.5 V A1 = A2 = A3 = 1/4 LM6064 R2 = R3 = R4 = 5 k RPOT = 10 k Figure 6. Programmable Instrumentation Amplifier 7 +5 V +200 mV 8 10 k 0.01 F 1 0.01 F Figure 7. Programmable Sq. Wave Oscillator (555) IC3A 74HC132 OSC 2 6 + 1/ 4 5 0.01 F 0.003 F C – DP7113/7114 V2 (+) 20 k VREF = 1 V 5 IC1B 2 1 DP 7 + 499 k VCORR 4 – 499 k CS Sensor DP7111/7112 IC2 2 +5 V 4 – 3 + 1 11 IC1A ï5 V 499 k 499 k VSENSOR = 1 V ( 50 mV Figure 8. Sensor Auto Referencing Circuit 7 VOUT = 1 V ( 1 mV DP7113 +5 V 8 2 1 DP 7 100 k VOUT VIN (UNREG) VO (REG) SHUTDOWN SD 1.23 V FB GND 6 R2 820 2 3 3 R3 10 k 6 5 DP7113/7114 4 IS +5 V + – CLO + – CHI 7 0.1 F + IC3 DP7111/7112 +5 V 8 2 10 k 1 DP 7 2 A1 3 6 4 – +5 V 7 + 4 A2 C1 0.001 F 3 1 F 6 R3 5 +5 V VUL +2.5 V 0.001 F R2 10 k VO 0 ) VO ) 2.5 V AI IC4 R3 100 k +5 V 2 7 – 3 + 4 Figure 12. Programmable Bandpass Filter Figure 11. Automatic Gain Control R1 100 k +5 V – R1 100 k VS +5 V 2 – + +2.5 V R1 100 k DP7111/7112 3 + R 2.5 k 4 IS 1 11 R1 100 k 7 5 +2.5 V – A2 Figure 13. Programmable Current Source/Sink 8 A1 DP7113/7114 VS +2.5 V 0 ) VS ) 2.5 V Serial Bus VO 6 +2.5 V 4 3 4 50 k +5 V 8 2 1 DP 7 – + C2 R1 VS 6 +5 V VO 6 R1 VLL +5 V 5 2 10 k Figure 10. Programmable I to V Converter R2 10 k 3 5 IC1 393 1 OSC +5 V 7 – 1M 330 LT1097 Figure 9. Programmable Voltage Regulator IC2 74HC132 pR (1ïp)R + 2 1 DP 7 0.1 F 6.8 F 330 1 F +5 V 8 4 R1 11 k 2952 DP7113/7114 6 A1 = A2 = LMC6064A DP7113 PACKAGE DIMENSIONS SOIC 8, 150 mils E1 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 MAX 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 Q 0º 8º TOP VIEW D h A1 Q A c e b L END VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. 9 DP7113 PACKAGE DIMENSIONS TSSOP8, 4.4x3 b SYMBOL MIN NOM A E1 E MAX 1.20 A1 0.05 A2 0.80 0.15 b 0.19 0.30 c 0.09 0.20 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 0.90 e 0.65 BSC L 1.00 REF L1 0.50 Q 0º 0.60 1.05 0.75 8º e TOP VIEW D A2 A A1 c 1 L1 SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. 10 DP7113 PACKAGE DIMENSIONS MSOP 8, 3x3 SYMBOL MIN NOM MAX A1 0.05 0.10 0.15 A2 0.75 0.85 0.95 b 0.22 0.38 c 0.13 0.23 D 2.90 3.00 3.10 E 4.80 4.90 5.00 E1 2.90 3.00 3.10 A E E1 1.10 e L 0.65 BSC 0.40 0.60 0.80 L1 0.95 REF L2 0.25 BSC Q 0º 6º TOP VIEW D A A2 A1 DETAIL A e b c SIDE VIEW END VIEW L2 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187. L L1 DETAIL A 11 DP7113 Example of Ordering Information (Note 11) Prefix Device # Suffix DP 7113 V Temperature Range I = Industrial (ï40oC to +85oC) Product Number 7113 Company ID (Optional) ï10 I Package ïG Lead Finish (Note 9) G: NiPdAu Blank: MatteïTin Resistance ï01: 1 k ï10: 10 k ï50: 50 k ï00: 100 k V: SOIC Y: TSSOP Z: MSOP T3 Tape & Reel T: Tape & Reel 3: 3,000 Units / Reel Table 7. ORDERING INFORMATION Orderable Part Number Resistance (k ) PackageïPins Lead Finish DP7113VIï01ïGT3 1 SOICï8 NiPdAu DP7113VIï10ïGT3 10 DP7113VIï50ïGT3 50 DP7113VIï00ïGT3 100 DP7113YIï01ïGT3 1 TSSOPï8 NiPdAu DP7113YIï10ïGT3 10 DP7113YIï50ïGT3 50 DP7113YIï00ïGT3 100 MSOPï8 MatteïTin DP7113ZIï01ïT3 1 DP7113ZIï10ïT3 10 DP7113ZIï50ïT3 50 DP7113ZIï00ïT3 100 8. All packages are RoHSïcompliant (Leadïfree, Halogenïfree). 9. The standard lead finish is NiPdAu, except MSOP package is MatteïTin. 10. The device used in the above example is a DP7113VIï10ïGT3 (SOIC, Industrial Temperature, 10 k , NiPdAu, Tape & Reel, 3,000/Reel). NIDEC COPAL reserves the right to make changes without further notice to any products herein. NIDEC COPAL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does NIDEC COPAL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in NIDEC COPAL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. $OORSHUDWLQJSDUDPHWHUVLQFOXGLQJ´7\SLFDOVµPXVWEHYDOLGDWHGIRUHDFKFXVWRPHUDSSOLFDWLRQE\FXVWRPHU·VWHFKQLFDOH[SHUWV NIDEC COPAL does not convey any license under its patent rights nor the rights of others. NIDEC COPAL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the NIDEC COPAL product could create a situation where personal injury or death may occur. Should Buyer purchase or use NIDEC COPAL products for any such unintended or unauthorized application, Buyer shall indemnify and hold NIDEC COPAL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that NIDEC COPAL was negligent regarding the design or manufacture of the part. DP7113/D