ALSC AS7C1026B-12JC 5 v 64k x 16 cmos sram Datasheet

March 2004
AS7C1026B
®
5 V 64K X 16 CMOS SRAM
• TTL-compatible, three-state I/O
• JEDEC standard packaging
Features
• Industrial and commercial versions
• Organization: 65,536 words × 16 bits
• Center power and ground pins for low noise
• High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
- 605 mW / max @ 10 ns
- 44-pin 400 mil SOJ
- 44-pin TSOP 2-400
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Pin arrangement
• Low power consumption: STANDBY
- 55 mW / max CMOS I/O
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
Logic block diagram
A1
A2
A3
A4
A5
A6
Row decoder
A0
VCC
64 K × 16
Array
GND
A7
I/O
buffer
Control circuit
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
A15
A14
A11
A13
UB
OE
LB
CE
A12
A8
A9
Column decoder
WE
A10
I/O0–I/O7
I/O8–I/O15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
AS7C1026B
44-Pin SOJ (400 mil), TSOP 2
• 6 T 0.18 u CMOS technology
• Easy memory expansion with CE, OE inputs
Selection guide
-10
-12
-15
-20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access time
5
6
7
8
ns
Maximum operating current
110
100
90
80
mA
Maximum CMOS standby current
10
10
10
10
mA
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AS7C1026B
®
Functional description
The AS7C1026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words ×
16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for
high-performance applications.
When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full
standby power is reached (ISB1). For example, the AS7C1026B is guaranteed not to exceed 55 mW under nominal full standby conditions.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on
the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after
outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chip drives I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The device is packaged in common industry
standard packages.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Voltage on VCC relative to GND
Vt1
–0.50
+7.0
V
Voltage on any pin relative to GND
Vt2
–0.50
VCC +0.50
V
Power dissipation
PD
–
1.0
W
Storage temperature (plastic)
Tstg
–65
+150
°C
Ambient temperature with VCC
applied
Tbias
–55
+125
°C
DC current into outputs (low)
IOUT
–
20
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
WE
OE
LB
UB
I/O0–I/O7
I/O8–I/O15
Mode
H
X
X
X
X
High Z
High Z
Standby (ISB), ISBI)
L
H
L
L
H
DOUT
High Z
Read I/O0–I/O7 (ICC)
L
H
L
H
L
High Z
DOUT
Read I/O8–I/O15 (ICC)
L
H
L
L
L
DOUT
DOUT
Read I/O0–I/O15 (ICC)
L
L
X
L
L
DIN
DIN
Write I/O0–I/O15 (ICC)
L
L
X
L
H
DIN
High Z
Write I/O0–I/O7 (ICC)
L
L
X
H
L
High Z
DIN
Write I/O8–I/O15 (ICC)
L
L
H
X
H
X
X
H
X
H
High Z
High Z
Output disable (ICC)
Key: H = high, L = low, X = don’t care.
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AS7C1026B
®
Recommended operating conditions
Parameter
Symbol
Min
Nominal
Max
Unit
VCC
4.5
5.0
5.5
V
VIH
2.2
–
VCC + 0.5
V
VIL
–0.5
–
0.8
Supply voltage
Input voltage
Ambient operating temperature
commercial
TA
industrial
TA
0
–
–40
–
V
70
o
C
85
o
C
VIL min = -1.0V for pulse width less than 5ns
VIH max = VCC+2.0V for pulse width less than 5ns.
DC operating characteristics (over the operating range)1
-10
-12
-15
-20
Parameter
Sym
Test conditions
Input leakage current
| ILI |
VCC = Max,
VIN = GND to VCC
–
1
–
1
–
1
-
1
µA
Output leakage current
| ILO |
VCC = Max, CE = VIH,
VOUT = GND to VCC
–
1
–
1
–
1
-
1
µA
Operating power supply
current
ICC
VCC = Max,
CE ≤ VIL, IOUT = 0mA,
f = fMax
–
110
–
100
–
90
-
80
mA
–
50
–
45
–
45
40
mA
–
10
–
10
–
10
-
10
mA
ISB
Standby power supply current
ISB1
Output voltage
VCC = Max,
CE ≥ VIH , f = fMax
VCC = Max, CE ≥ VCC–0.2 V,
VIN ≤ 0.2 V or
VIN ≥ VCC–0.2 V, f = 0
Min Max Min Max Min Max Min Max Unit
VOL
IOL = 8 mA, VCC = Min
–
0.4
–
0.4
–
0.4
-
0.4
V
VOH
IOH = –4 mA, VCC = Min
2.4
–
2.4
–
2.4
–
2.4
-
V
Capacitance (f = 1MHz, Ta = 25 °C, VCC = NOMINAL)2
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
CIN
A, CE, WE, OE, LB, UB
VIN = 0 V
5
pF
I/O capacitance
CI/O
I/O
VIN = VOUT = 0 V
7
pF
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AS7C1026B
®
Read cycle (over the operating range)3,9
-10
Parameter
-12
-15
Symbol
Min
Max
Min
Max Min
Read cycle time
tRC
10
–
12
–
Address access time
tAA
–
10
–
Chip enable (CE) access time
tACE
–
10
Output enable (OE) access time
tOE
–
Output hold from address change
tOH
CE low to output in low Z
-20
Max
Min
Max Unit
Notes
15
–
20
-
ns
12
–
15
-
20
ns
3
–
12
–
15
-
20
ns
3
5
–
6
–
7
-
8
ns
3
–
3
–
3
–
3
-
ns
5
tCLZ
3
–
3
–
3
–
3
-
ns
4, 5
CE high to output in high Z
tCHZ
–
4
–
5
–
6
-
7
ns
4, 5
OE low to output in low Z
tOLZ
0
–
0
–
0
–
0
-
ns
4, 5
Byte select access time
tBA
–
5
–
6
–
7
-
8
ns
Byte select Low to low Z
tBLZ
0
–
0
–
0
–
0
-
ns
4, 5
Byte select High to high Z
tBHZ
–
5
–
6
–
6
-
7
ns
4, 5
OE high to output in high Z
tOHZ
–
4
–
5
–
6
-
7
ns
4, 5
Power up time
tPU
0
–
0
–
0
–
0
-
ns
4, 5
Power down time
tPD
–
10
–
12
–
15
-
20
ns
4, 5
Key to switching waveforms
Rising input
Falling input
Undefined output/don’t care
Read waveform 1 (address controlled)3,6,7,9
tRC
Address
DataOUT
3/26/04, v 1.3
tOH
Previous data valid
tAA
tOH
Data valid
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AS7C1026B
®
Read waveform 2 (OE, CE, UB, LB controlled)3,6,8,9
tRC
Address
tAA
OE
tOE
tOLZ
tOH
CE
tLZ
tOHZ
tHZ
tACE
LB, UB
tBA
tBLZ
tBHZ
DataIN
Data valid
Write cycle (over the operating range) 11
-10
Parameter
-12
-15
-20
Symbol Min Max Min Max Min Max Min Max
Unit
Notes
Write cycle time
tWC
10
–
12
–
15
–
20
-
ns
Chip enable (CE) to write end
tCW
8
–
9
–
10
–
12
-
ns
Address setup to write end
tAW
8
–
9
–
10
–
12
-
ns
Address setup time
tAS
0
–
0
–
0
–
0
-
ns
Write pulse width
tWP
7
–
8
–
9
–
12
-
ns
Write recovery time
tWR
0
–
0
–
0
–
0
-
ns
Address hold from end of write
tAH
0
–
0
–
0
–
0
-
ns
Data valid to write end
tDW
5
–
6
–
8
–
10
-
ns
Data hold time
tDH
0
–
0
–
0
–
0
-
ns
5
Write enable to output in high Z
tWZ
–
5
–
6
–
7
-
8
ns
4, 5
Output active from write end
tOW
1
–
1
–
1
–
2
-
ns
4, 5
Byte select low to end of write
tBW
7
–
8
–
9
–
9
-
ns
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P. 5 of 10
AS7C1026B
®
Write waveform 1 (WE controlled)11
tWC
tAH
Address
tWR
tCW
CE
tBW
LB, UB
tAW
tAS
tWP
WE
tDW
DataIN
tDH
Data valid
tWZ
DataOUT
tOW
Data undefined
high Z
Write waveform 2 (CE controlled)11
tWC
tAH
Address
tAS
CE
tWR
tCW
tAW
tBW
LB, UB
tWP
WE
tDH
tDW
Data valid
DataIN
tCLZ
DataOUT
3/26/04, v 1.3
high Z
tWZ
Data undefined
Alliance Semiconductor
tOW
high Z
P. 6 of 10
AS7C1026B
®
AC test conditions
–
–
–
–
Output load: see Figure B.
Input pulse level: GND to 3.5 V. See Figure A.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5
+5 V
480 Ω
+3.5V
GND
DOUT
90%
10%
90%
2 ns
10%
Figure A: Input pulse
255 Ω
C13
Thevenin Equivalent:
168 Ω
DOUT
+1.728 V
GND
Figure B: 5 V Output load
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A and B.
These parameters are specified with CL = 5 pF, as in Figures B. Transition is measured ± 500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is high for read cycle.
CE and OE are low for read cycle.
Address is valid prior to or coincident with CE transition low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
N/A.
All write cycle timings are referenced from the last valid address to the first transitioning address.
Not applicable.
C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
3/26/04, v 1.3
Alliance Semiconductor
P. 7 of 10
AS7C1026B
®
Package dimensions
c
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
44-pin TSOP 2
Min
(mm)
E He
44-pin TSOP 2
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
D
l
A2
A
0–5°
A1
e
b
Max
(mm)
1.2
A1
0.05
0.15
A2
0.95
1.05
b
0.30
0.45
c
0.120
0.21
D
18.31
18.52
E
10.06
10.26
He
11.68
11.94
e
l
0.80 (typical)
0.40
0.60
44-pin SOJ
400 mil
D
e
Min (in) Max (in)
44-pin SOJ
E1 E2
Pin 1
c
B
A2
A
A1
b
Seating
plane
E
A
0.128
0.148
A1
0.025
–
A2
0.105
0.115
B
0.026
0.032
b
0.015
0.020
c
0.007
0.013
D
1.120
1.130
E
E1
0.395
0.405
E2
0.435
0.445
e
3/26/04, v 1.3
Alliance Semiconductor
0.370 NOM
0.050 NOM
P. 8 of 10
AS7C1026B
®
Ordering codes
Package \ Access time
Plastic SOJ, 400 mil
TSOP 2, 10.2 x 18.4 mm
Temp
10 ns
12 ns
15 ns
20 ns
commercial
AS7C1026B-10JC
AS7C1026B-12JC
AS7C1026B-15JC
AS7C1026B-20JC
industrial
AS7C1026B-10JI
AS7C1026B-12JI
AS7C1026B-15JI
AS7C1026B-20JI
commercial
AS7C1026B-10TC
AS7C1026B-12TC
AS7C1026B-15TC
AS7C1026B-20TC
industrial
AS7C1026B-10TI
AS7C1026B-12TI
AS7C1026B-15TI
AS7C1026B-20TI
Note: Add suffix ‘N’ to the above ordering part number for LEAD FREE PARTS (Ex: AS7C1026B-10JCN)
Part numbering system
AS7C
1026B
–XX
SRAM
prefix
Device
number
Access
time
3/26/04, v 1.3
X
X
X
Package:
Temperature range:
C = commercial: 0° C to 70° C
J = SOJ 400 mil
T = TSOP 2, 10.2 x 18.4 mm I = industrial: -40° C to 85° C
Alliance Semiconductor
N = LEAD FREE PART
P. 9 of 10
AS7C1026B
®
®
Alliance Semiconductor Corporation
Copyright © Alliance Semiconductor
2575, Augustine Drive,
All Rights Reserved
Santa Clara, CA 95054
Part Number: AS7C1026B
Tel: 408 - 855 - 4900
Document Version: v 1.3
Fax: 408 - 855 - 4999
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The
information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate
as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application
or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including
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