LAPIS Semiconductor ML9212 FEDL9212-01 Issue Date: Nov., 26, 2002 32-Bit Duplex/Triplex (1/2 duty / 1/3 duty) VF Controller/Driver with Digital Dimming GENERAL DESCRIPTION The ML9212 is a full CMOS controller/driver for Duplex or Triplex (1/2 duty or 1/3 duty) vacuum fluorescent display tube. It consists of a 32-segment driver multiplexed to drive up to 96 segments, and 10-bit digital dimming circuit. ML9212 features a selection of a master mode and a slave mode, and therefore it can be used to expand segments for the VFD driver with keyscan and A/D converter function. ML9212 provides an interface with a microcontroller only by three signal lines: DATA IN, CLOCK and CS. FEATURES : 4.5 to 5.5 V Logic supply voltage (VDD) : 8 to 18 V Driver supply voltage (VDISP) Duplex/Triplex (1/2 duty / 1/3 duty) selectable DUP/TRI = 1/2 duty selectable at “H” level DUP/TRI = 1/3 duty selectable at “L” level Number of display segments Max. 64-segment display (during 1/2 duty mode) Max. 96-segment display (during 1/3 duty mode) Master/Slave selectable M/S = Master mode selectable at “H” level M/S = Slave mode selectable at “L” level Interface with a microcontroller Three lines: CS, CLOCK, and DATA IN 32-segment driver outputs : IOH = –5 mA at VOH = VDISP–0.8 V (SEG1 to 22) (can be directly connected to VFD tube : IOH = –10 mA at VOH = VDISP–0.8V (SEG23 to 32) and require no external resisters) : IOL = 500 A at VOL = 2 V (SEG1 to 32) 3-grid pre-driver outputs : IOH = –5.0 mA at VOH = VDISP–0.8 V (require external drivers) IOL = 10 mA at VOL = 2 V Logic outputs : IOH = –200 A at VOH = VDD–0.8 V IOL = 200 A at VOL = 0.8 V Built-in digital dimming circuit (10-bit resolution) Built-in oscillation circuit (external R and C) Built-in Power-On-Reset circuit Package options: 56-pin plastic QFP (QFP56-P-910-0.65-2K)(ML9212GA) 1/17 FEDL9212-01 LAPIS Semiconductor ML9212 BLOCK DIAGRAM SEG1 VDISP SEG32 GRID1 GRID2 GRID3 32 Segment Driver 3 Grid Pre Driver D-GND VDD L-GND Power On Reset 0H POR Mode Select in1-3 Control DATA IN OSC0 in1-32 4H CS CLOCK POR 1H 0H POR Out1-32 Segment Latch1 in1-32 Out1-32 96 to 32 Segment Control in1-32 in1-32 Out1-32 Segment Latch2 in1-32 Out1-32 Segment Latch3 in1-32 2H 0H POR Out1-3 3 bit Shift Register Out1-32 32 bit Shift Register POR POR 3H 0H POR 4H POR In1-10 Dimming Latch Out1-10 10 bit Digital Dimming OSC POR DIM OUT DIM IN SYNC OUT1 SYNC IN1 SYNC IN2 Timing Generator SYNC OUT2 M/S DUP/TRI 2/17 FEDL9212-01 LAPIS Semiconductor ML9212 43 VDISP SEG14 44 SEG15 45 SEG16 46 SEG17 47 SEG18 48 D-GND 49 SEG19 50 SEG20 51 SEG21 52 SEG22 53 SEG23 54 SEG24 55 56 VDISP PIN CONFIGURATION (TOP VIEW) SEG25 1 42 SEG13 SEG26 2 41 SEG12 SEG27 3 40 SEG11 SEG28 4 39 SEG10 SEG29 5 38 SEG9 SEG30 6 37 SEG8 SEG31 7 36 SEG7 SEG32 8 35 SEG6 GRID1 9 GRID2 10 34 SEG5 33 SEG4 GRID3 11 32 SEG3 D-GND 12 31 SEG2 NC 13 30 SEG1 29 NC SYNC OUT 1 27 DIM OUT 28 M/S 25 SYNC OUT 2 26 OSC0 23 DUP/TRI 24 L-GND 21 NC 22 CLOCK 19 DATA IN 20 SYNC IN 2 17 CS 18 DIM IN 15 SYNC IN 1 16 VDD 14 NC: No connection (OPEN) 56-pin Plastic QFP 3/17 FEDL9212-01 LAPIS Semiconductor ML9212 PIN DESCRIPTIONS Symbol Pin Type Description VDISP 43, 56 — Power supply pins for VFD driver circuit. 43 pin and 56 pin should be connected externally. VDD 14 — Power supply pin for logic drive. D-GND 12, 49 — L-GND 21 — D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for the logic circuit. 12 pin, 21 pin and 49 pin should be connected externally. SEG1 to 22 30 to 42, 44 to 48, 50 to 53 O Segment (anode) signal output pins for a VFD tube. These pins can be directly connected to the VFD tube. External circuit is not required. lOHL –5 mA SEG23 to 32 1 to 8, 54, 55 O Segment (anode) signal output pins for a VFD tube. These pins can be directly connected to the VFD tube. External circuit is not required. lOHL –10 mA GRID1 to 3 9, 10, 11 O Inverted Grid signal output pins. For pre-driver, the external circuit is required. lOL 10 mA CS 18 I Chip select input pin. Data is not transferred when CS is set to a Low level. CLOCK 19 I Shift clock input pin. Serial data shifts at the rising edge of the CLOCK. DATA IN 20 I Serial data input pin (positive logic). Data is input to the shift register at the rising edge of the CLOCK signal. DUP/TRl 24 I Duplex/Triplex operation select input pin. Duplex (1/2 duty) operation is selected when this pin is set to VDD. Triplex (1/3 duty) operation is selected when this pin is set to L-GND. M/S 25 I Master/Slave mode select input pin. Master mode is selected when this pin is set to VDD. Slave mode is selected when this pin is set to L-GND. I Dimming pulse input. When the slave mode is selected, the pulse width of the all segment output are controlled by a input pulse width of DIM IN. Connect this pin to the master side DIM OUT pin at the slave mode. When the master mode is selected, the input level of this pin is ignored and the pulse width of the all grids and segment outputs are controlled by a built-in 10-bit dimming circuit. Connect this pin to VDD or L-GND at the master mode. DIM IN 15 4/17 FEDL9212-01 LAPIS Semiconductor Symbol ML9212 Pin Type Description SYNC IN 1, 2 16, 17 I Synchronous signal input. When the slave mode is selected, connect these pins to the master side SYNC OUT 1, and 2 pins. When the master mode is selected, the input level of these pins are ignored. Connect these pins to VDD or L-GND at the master mode. DIM OUT 28 O Dimming pulse output. Connect this pin to the slave side DIM IN pin. SYNC OUT 1, 2 26, 27 O Synchronous signal output. Connect these pins to the slave side SYNC IN 1, and 2 pins. OSC0 NC 23 RC oscillator connecting pins. VDD Oscillation frequency depends OSC0 on display tubes to be used. For details refer to ELECTRICAL CHARACTERISTICS. I/O 13,22,29 R C OPEN pins. - ABSOLUTE MAXIMUM RATING Parameter Symbol Condition Ratings Unit Driver Supply Voltage VDISP — –0.3 to +20 V Logic Supply Voltage VDD — –0.3 to +6.5 V Input Voltage VIN — –0.3 to VDD+0.3 V Power Dissipation Storage Temperature Output Current PD Ta 105°C 233 mW TSTG — –55 to +150 °C Io1 SEG1 to 22 –10.0 to +2.0 mA Io2 SEG23 to 32 –20.0 to +2.0 mA Io3 GRID1 to 3 –10.0 to +20.0 mA Io4 DIM OUT, SYNC OUT1, SYNC OUT2 –2.0 to +2.0 mA RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Min. Typ. Max. Unit Driver Supply Voltage VDISP — 8.0 13.0 18.0 V Logic Supply Voltage VDD — 4.5 5.0 5.5 V High Level Input Voltage VIH All inputs except OSC0 0.8VDD — — V Low Level Input Voltage VIL All inputs except OSC0 — — 0.2VDD V Clock Frequency fC — — — 2.0 MHz 5/17 FEDL9212-01 LAPIS Semiconductor Parameter ML9212 Symbol Condition Min Typ. Max. Unit Oscillation Frequency fOSC R = 10 k±5%, C = 27 pF±5% 2.2 3.3 4.4 MHz Frame Frequency fFR 1/3 duty 179 269 358 1/2 duty 268 403 538 –40 — +105 Operating Temperature TOP R = 10 k±5%, C = 27 pF±5% — Hz °C 6/17 FEDL9212-01 LAPIS Semiconductor ML9212 ELECTRICAL CHARACTERISTICS DC Characteristics Ta = –40 to +105°C, VDISP = 8.0 to 18.0 V, VDD = 4.5 to 5.5 V Parameter Symbol Applied pin Condition Min. Max. Unit High Level Input Voltage VIH *1) — 0.8VDD — V Low Level Input Voltage VIL *1) — — 0.2VDD V High Level Input Current IIH *1) VIH = VDD –1.0 +1.0 A Low Level Input Current IIL *1) VIL = GND –1.0 +1.0 A VOH1 SEG1-22 VOH2 SEG23-32 VOH3 GRID1-3 VOH4 *2) VOL1 SEG1-22 Low Level Output VOL2 SEG23-32 Voltage VOL3 GRID1-3 VOL4 *2) IDISP VDISP IDD VDD High Level Output Voltage Supply Current lOH1 = –5 mA VDlSP – 0.8 — V VDISP = 9.5V lOH2 = –10 mA VDlSP – 0.8 — V lOH3 = –5 mA VDlSP – 0.8 — V VDD = 4.5 V lOH4 = –200 A VDD – 0.8 — V lOL1 = 500 A — 2.0 V VDlSP = 9.5V VDD = 4.5 V lOL2 = 500 A — 2.0 V lOL3 = 10 mA — 2.0 V lOL4 = 200 A — 0.8 V — 100 uA — 5.0 mA R = 10 k±5%, C = 27 pF±5% no load *1) CS, CLOCK, DATA IN, DIM IN, SYNC IN 1, SYNC IN 2, M/S, DUP/TRI *2) DIM OUT, SYNC OUT 1, SYNC OUT 2 7/17 FEDL9212-01 LAPIS Semiconductor ML9212 AC Characteristics Ta = –40 to +105°C, VDISP = 8.0 to 18.0 V, VDD = 4.5 to 5.5 V Parameter Symbol Condition Min. Max. Unit fC — — 2.0 MHz Clock Pulse Width tCW — 200 — ns Data Setup Time tDS — 200 — ns Data Hold Time tDH — 200 — ns CS Off Time tCSL — 20 — s CS Setup Time (CS-Clock) tCSS — 200 — ns CS Hold Time (Clock-CS) tCSH — 200 — ns CS Wait Time tRSOFF — 400 — ns — 2.0 s Clock Frequency tR Output Slew Rate Time CL = 100 pF tR = 20% to 80% — 2.0 s VDD Rise Time tPRZ Mounted in a unit — 100 s VDD Off Time tPOF Mounted in a unit, VDD = 0.0 V 5.0 — ms tF tF = 80% to 20% TIMING DIAGRAM Data Input Timing tCSL tCSS CS tCSH 1/fC tCW tCW –0.2VDD tDH VALID DATA IN –0.2VDD –0.8VDD CLOCK tDS –0.8VDD VALID VALID –0.8VDD VALID –0.2VDD Reset Timing VDD tPRZ –0.8VDD tPOF –0.0 V tRSOFF –0.8VDD CS –0.0 V Driver Output Timing SEG1-32, GRID1-3 tR tF tR –0.8VDISP –0.2VDISP 8/17 FEDL9212-01 LAPIS Semiconductor ML9212 Output Timing (Duplex Operation) *1bit time = 4/fOSC Solid line : The dimming data is 1016/1024 at the master mode Dotted line : The dimming data is 64/1024 at the master mode 2048 bit times(1 display cycle) GRID1 1016 bit times VDISP 1016 bit times 8 bit times 8 bit times 8 bit times VDISP 1016 bit times GRID2 D-GND D-GND VDISP GRID3 64 bit times 64 bit times D-GND 64 bit times VDISP SEG1-32 D-GND VDD DIM OUT L-GND VDD SYNC OUT1 L-GND VDD SYNC OUT2 L-GND Output Timing (Triplex Operation) *1bit time = 4/fOSC Solid line : The dimming data is 1016/1024 at the master mode Dotted line : The dimming data is 64/1024 at the master mode 3072 bit times(1 display cycle) GRID1 VDISP 1016 bit times 8 bit times 8 bit times D-GND VDISP 1016 bit times GRID2 8 bit times D-GND 1016 bit times GRID3 64 bit times 64 bit times 64 bit times VDISP D-GND VDISP SEG1-32 D-GND DIM OUT VDD L-GND SYNC OUT1 VDD L-GND SYNC OUT2 VDD L-GND 9/17 FEDL9212-01 LAPIS Semiconductor ML9212 FUNCTIONAL DESCRIPTION Power-on Reset When power is turned on, ML9212 is initialized by the internal power-on reset circuit. The status of the internal circuit after initialization is as follows: The contents of the shift registers and latches are set to “0”. The digital dimming duty cycle is set to “0”. All segment outputs are set to Low level. GRID1 outputs are set to Low level. GRID2 to 3 outputs are set to High level. Data Transfer Method Data can be transferred between the rising edge and the next falling edge of chip select input. The mode data, segment data and dimming data are written by a serial transfer method. The serial data is input to the shift register at the rising edge of a shift clock pulse. The mode data (M0 to M2) must be transferred after the segment data and dimming data succeedingly. When the chip select input falls, an internal LOAD signal is automatically generated and data is loaded to the latches. Function Mode Function mode is selected by the mode data (M0 to M2). The relation between function mode and mode data is as follows: FUNCTION DATA FUNCTION MODE OPERATING MODE 0 Segment Data for GRID1-3 Input 0 0 0 1 Segment Data for GRID1 Input 1 0 0 2 Segment Data for GRID2 Input 0 1 0 3 Segment Data for GRID3 Input 1 1 0 4 Digital Dimming Data Input 0 0 1 M0 M1 M2 Segment Data Input [Function Mode: 0 to 3] ML9212 receives the segment data when function mode 0 to 3 are selected. The same segment data is transferred to the 3 segment data latches corresponding to GRID1 to 3 at the same time when the function mode 0 is selected. The segment data is transferred to only one segment data latch corresponding to the specified GRID when the function mode is 1, 2 or 3 is selected. Segment output (SEG1 to 32) becomes High level (lightning) when the segment data (S1 to S32) is set to “1”. [Data Format] Input Data Segment Data Mode Data : 35 bits : 32 bits : 3 bits Bit 1 2 3 4 29 30 31 32 33 34 35 Input DATA S1 S2 S3 S4 S29 S30 S31 S32 M0 M1 M2 Segment Data (32 bits) Mode Data (3 bits) 10/17 FEDL9212-01 LAPIS Semiconductor ML9212 [Bit correspondence between segment output and segment data] SEG n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Segment data S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 SEG n 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Segment data S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 Digital Dimming Data Input [Function Mode: 4] ML9212 receives the digital dimming data when function mode 4 is selected. The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid. The 10-bit digital dimming data is input from LSB. [Data Format] Input Data Digital Dimming Data Mode Data : 13 bits : 10 bits : 3 bits Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 Input DATA D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 M0 M1 M2 LSB MSB Digital Dimming Data (10 bits) (LSB) Dimming Data (MSB) Mode Data (3 bits) Duty Cycle D3 D4 D5 D6 D7 D8 D9 D10 0 0 0 0 0 0 0 0 0 0 0/1024 1 0 0 0 0 0 0 0 0 0 1/1024 1 1 1 0 1 1 1 1 1 1 1015/1024 0 0 0 1 1 1 1 1 1 1 1016/1024 1 0 0 1 1 1 1 1 1 1 1016/1024 1 1 1 1 1 1 1 1 1 1016/1024 1 … … … D2 … D1 Master Mode Master Mode is selected when M/S pin is set at High level. The master mode operation is as follows: The input levels of DIM IN, SYNC IN1 and SYNC IN2 are ignored, and these pins should be connected to L-GND or VDD. The pulse width of GRID1 to 3 and SEG1 to 32 are controlled by the internal digital dimming circuit. The segment Latch1 to 3 corresponding to GRID1 to 3 are selected by the internal timing generator. 11/17 FEDL9212-01 LAPIS Semiconductor ML9212 Slave Mode Slave Mode is selected when M/S pin is set at Low level. The slave mode operation is as follows: The internal dimming circuit is ignored. The pulse width of SEG1 to 32 are controlled by the pulse width of DIM IN signal. The segment Latch1 to 3 corresponding to GRID1 to 3 are selected by SYNC IN1 and SYNC IN2 signals. The output levels of GRID1 to 3 are set at High level. The output levels of DIM OUT, SYNC OUT1 and SYNC OUT2 are set at Low level. [Correspondence between SYNC IN1, 2 and Segment Latch1 to 3] [Correspondence between DIM IN and SEG1 to 32] SYNC IN 1 SYNC IN 2 Segment Latch GRID DIM IN SEG1 to 32 0 0 No No 0 Low 1 0 Latch1 GRID1 1 High 0 1 Latch2 GRID2 Note: Low: Lights OFF 1 1 Latch3 GRID3 High: Lights ON 12/17 GND VDISP VDD GND C R GND VDD OSC 0 L-GND D-GND DIM OUT GND C R OSC 0 L-GND DIM IN CS DATA IN CLOCK DIM IN CS DATA IN CLOCK D-GND DIM OUT SYNC IN 1 SYNC OUT1 SYNC IN 2 SYNC OUT2 GRID2 GRID3 SYNC IN 1 SYNC OUT1 SYNC IN 2 SYNC OUT2 M/S VDISP VDD SEG1 ML9212 (SLAVE) VDD SEG32 DUP/TRI GRID1 GRID2 M/S GND GRID3 VDISP VDD SEG1 ML9212 (MASTER) SEG32 GRID1 DUP/TRI G2 G1 S62 S63 S64 Ef Duplex VF Tube S1 S2 S3 FEDL9212-01 LAPIS Semiconductor ML9212 APPLICATION CIRCUITS 1. Circuit for the duplex VFD tube with 128 segments (2 Grid 64 Anode) Microcontroller 13/17 GND VDISP VDD GND C R GND VDD OSC 0 L-GND D-GND DIM OUT GND C R OSC 0 L-GND D-GND DIM OUT DIM IN CS DATA IN CLOCK DUP/TRI DIM IN CS DATA IN CLOCK GND SYNC IN 1 SYNC OUT1 SYNC IN 2 SYNC OUT2 GRID2 GRID3 SEG32 GRID1 GRID2 GRID3 VDISP SEG1 SYNC IN 1 SYNC OUT1 SYNC IN 2 SYNC OUT2 DUP/TRI M/S VDD ML9212 (SLAVE) G1 G2 G3 S62 S63 S64 Ef Triplex VF Tube S1 S2 S3 2. VDISP VDD SEG1 ML9212 (MASTER) SEG32 M/S GRID1 FEDL9212-01 LAPIS Semiconductor ML9212 Circuit for the triplex VFD tube with 192 segments (3 Grid 64 Anode) Microcontroller 14/17 FEDL9212-01 LAPIS Semiconductor ML9212 NOTES ON TURNING POWER ON/OFF Connect L-GND and D-GND externally to be an equal potential voltage. To avoid wrong operations, turn on the driver power supply after turning on the logic power supply. Conversely, turn off the logic power supply after tuning off the driver power supply. [Voltage] VDISP VDD [Time] 15/17 FEDL9212-01 LAPIS Semiconductor ML9212 REVISION HISTORY Document No. Date FEDL9212-01 Nov., 26, 2002 Page Previous Current Edition Edition – – Description Final edition 1 16/17 FEDL9212-01 LAPIS Semiconductor ML9212 NOTICE No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from LAPIS Semiconductor upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. 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