Cirrus CS5101A 16-bit, 100 ksps / 20 ksps a/d converter Datasheet

CS5101A
CS5102A
16-bit, 100 kSps / 20 kSps A/D Converters
Features
z
Description
The CS5101A and CS5102A are 16-bit monolithic
CMOS analog-to-digital converters (ADCs) capable of
100 kSps (5101A) and 20 kSps (5102A) throughput. The
CS5102A’s low power consumption of 44mW, coupled
with a power-down mode, makes it particularly suitable
for battery-powered operation.
Monolithic CMOS A/D Converters
– Inherent Sampling Architecture
– 2-channel Input Multiplexer
– Flexible Serial Output Port
z
On-chip self-calibration circuitry achieves nonlinearity of
±0.001% of FS and guarantees 16-bit, no missing codes
over the entire specified temperature range. Superior linearity also leads to 92 dB S/(N+D) with harmonics below
-100 dB. Offset and full-scale errors are minimized during the calibration cycle, eliminating the need for external
trimming.
Ultra-low Distortion
– S/(N+D): 92 dB
– TDH: 0.001%
z
Conversion Time
– CS5101A: 8µs
– CS5102A: 40 µs
z
The CS5101A and CS5102A each consist of a 2-channel input multiplexer, DAC, conversion and calibration
microcontroller, clock generator, comparator, and serial
communications port. The inherent sampling architecture of the device eliminates the need for an external
track-and-hold amplifier.
Linearity Error: ±0.001% FS
– Guaranteed No Missing Codes
z
Self-calibration Maintains Accuracy
The converters’ 16-bit data is output in serial form with
either binary or two’s complement coding. Three output
timing modes are available for easy interfacing to microcontrollers and shift registers. Unipolar and bipolar input
ranges are digitally selectable
– Accurate Over Time & Temperature
z
Low Power Consumption
– CS5101A: 320 mW
– CS5102A: 44 mW
ORDERING INFORMATION
See “Ordering Information” on page 38.
I
HOLD SLEEPRST STBY CODE BP/UP CRS/FIN TRK1 TRK2 SSH/SDLSDATA
12
CLKIN
XOUT
REFBUF
VREF
AIN1
AIN2
CH1/2
AGND
3
4
28
5
16
19
24
13
22
8
10
Calibration
SRAM
+
11
15
16-Bit Charge
Redistribution
DAC
+
Comparator
+
23
VA-
6
DGND
SCLK
Microcontroller
26
+
25
9
Control
21
20
17
14
Clock
Generator
VA+
http://www.cirrus.com
2
1
7
VD-
VD+
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
27
18
TEST
SCKMOD
OUTMOD
JAN ‘06
DS45F6
CS5101A CS5102A
TABLE OF CONTENTS
1. CHARACTERISTICS & SPECIFICATIONS ............................................................................. 4
ANALOG CHARACTERISTICS, CS5101A............................................................................... 4
SWITCHING CHARACTERISTICS, CS5101A ......................................................................... 6
ANALOG CHARACTERISTICS, CS5102A............................................................................... 7
SWITCHING CHARACTERISTICS, CS5102A ......................................................................... 9
SWITCHING CHARACTERISTICS, ALL DEVICES ............................................................... 11
DIGITAL CHARACTERISTICS, ALL DEVICES...................................................................... 13
RECOMMENDED OPERATING CONDITIONS ..................................................................... 13
ABSOLUTE MAXIMUM RATINGS ......................................................................................... 14
2. OVERVIEW ............................................................................................................................. 15
3. THEORY OF OPERATION ..................................................................................................... 15
3.1 Calibration ........................................................................................................................ 16
4. FUNCTIONAL DESCRIPTION ............................................................................................... 17
4.1 Initiating Conversions ....................................................................................................... 17
4.2 Tracking the Input ............................................................................................................ 17
4.3 Master Clock .................................................................................................................... 18
4.4 Asynchronous Sampling Considerations ......................................................................... 18
4.5 Analog Input Range/Coding Format ................................................................................ 19
4.6 Output Mode Control ........................................................................................................ 19
4.6.1 Pipelined Data Transmission .............................................................................. 19
4.6.2 Register Burst Transmission (RBT) .................................................................... 20
4.6.3 Synchronous Self-clocking (SSC) ....................................................................... 20
4.6.4 Free Run (FRN) .................................................................................................. 20
5. SYSTEM DESIGN USING THE CS5101A & CS5102A ......................................................... 22
5.1 System Initialization ......................................................................................................... 22
5.2 Single-channel Operation ................................................................................................ 23
6. ANALOG CIRCUIT CONNECTIONS ...................................................................................... 23
6.1 Reference Considerations ............................................................................................... 23
6.2 Analog Input Connection ................................................................................................. 24
6.3 Sleep Mode Operation ..................................................................................................... 24
6.4 Grounding & Power Supply Decoupling ........................................................................... 25
7. CS5101A & CS5102A PERFORMANCE ............................................................................... 26
7.1 Differential Nonlinearity .................................................................................................... 26
7.2 FFT Tests and Windowing ............................................................................................... 28
7.3 Sampling Distortion .......................................................................................................... 30
7.4 Noise ................................................................................................................................ 31
7.5 Aperture Jitter .................................................................................................................. 31
7.6 Power Supply Rejection ................................................................................................... 32
8. PIN DESCRIPTIONS .............................................................................................................. 33
8.1 Power Supply Connections .............................................................................................. 33
8.2 Oscillator .......................................................................................................................... 34
8.3 Digital Inputs .................................................................................................................... 34
8.4 Analog Inputs ................................................................................................................... 35
8.5 Digital Outputs ................................................................................................................. 35
8.6 Analog Outputs ................................................................................................................ 35
8.7 Miscellaneous .................................................................................................................. 35
9. PARAMETER DEFINITIONS .................................................................................................. 36
10. PACKAGE DIMENSIONS ..................................................................................................... 37
11. ORDERING INFORMATION ................................................................................................ 38
12. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION .......................... 38
13. REVISIONS .......................................................................................................................... 39
2
DS45F6
CS5101A CS5102A
LIST OF FIGURES
Figure 1. Reset, Calibration, and Control Timing .......................................................................... 10
Figure 2. Serial Communication Timing ........................................................................................ 12
Figure 3. Coarse Charge Input Buffers & Charge Redistribution DAC.......................................... 15
Figure 4. Coarse/Fine Charge Control .......................................................................................... 18
Figure 5. Pipelined Data Transmission (PDT) Mode Timing ......................................................... 20
Figure 6. Register Burst Transmission (RBT) Mode Timing.......................................................... 21
Figure 7. Synchronous Self-clocking (SSC) Mode Timing ............................................................ 21
Figure 8. Free Run (FRN) Mode Timing........................................................................................ 21
Figure 9. CS5101A/CS5102A System Connection Diagram......................................................... 22
Figure 10. Power-up Reset Circuit ................................................................................................ 23
Figure 11. Reference Connections................................................................................................ 24
Figure 12. Charge Settling Time ................................................................................................... 24
Figure 13. CS5101A DNL Plot - Ambient Temperature at 25 °C .................................................. 27
Figure 14. CS5101A DNL Plot - Ambient Temperature at 138 °C ................................................ 27
Figure 15. CS5102A DNL Plot - Ambient Temperature at 25 °C .................................................. 27
Figure 16. CS5102A DNL Plot - Ambient Temperature at 138 °C ................................................ 27
Figure 17. CS5101A DNL Error Distribution.................................................................................. 28
Figure 18. CS5102A DNL Error Distribution.................................................................................. 28
Figure 19. CS5101A FFT (SSC Mode, 1-Channel)....................................................................... 29
Figure 20. CS5101A FFT (SSC Mode, 1-Channel)....................................................................... 29
Figure 21. CS5102A FFT (SSC Mode, 1-Channel)....................................................................... 29
Figure 22. CS5102A FFT (SSC Mode, 1-Channle)....................................................................... 29
Figure 23. CS5101A Histogram Plot of 8192 Conversion Inputs .................................................. 31
Figure 24. CS5102A Histogram Plot of 8192 Conversion Inputs .................................................. 31
Figure 25. Power Supply Rejection ............................................................................................... 32
Figure 26. CS5101A & CS5102A 28-pin PLCC Pinout ................................................................. 33
Figure 27. 28-Pin PLCC Mechanical Drawing............................................................................... 37
LIST OF TABLES
Table 1. Output Coding ................................................................................................................. 19
Table 2. Output Mode Control ....................................................................................................... 19
DS45F6
3
CS5101A CS5102A
1. CHARACTERISTICS & SPECIFICATIONS
ANALOG CHARACTERISTICS, CS5101A
(TA = TMIN to TMAX; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 4.5V; Full-scale Input sine wave, 1 kHz; CLKIN = 8 MHz; fs =
100 kSps; Bipolar Mode; FRN Mode; AIN1 and AIN2 tied together, each channel tested separately; Analog Source Impedance
= 50 Ω with 1000 pF to AGND unless otherwise specified)
CS5101A-J
Parameter*
Min
Specified Temperature Range
Typ
CS5101A-B
Max
Min
0 to +70
Typ
Max
-40 to +85
Unit
ºC
Accuracy
Linearity Error
-J
(Note 1)
-B
Drift (Note 2)
Differential Linearity
(Note 3)
-
0.002 0.003
0.001 0.002
±¼
-
-
0.002 0.003
0.001 0.002
±¼
-
%FS
%FS
∆LSB
16
-
-
16
-
-
Bits
Full-scale Error
-J
(Note 1)
-B
Drift (Note 2)
-
±1
±1
±1
±4
±3
-
-
±1
±1
±1
±4
±3
-
LSB
LSB
∆LSB
Unipolar Offset
-J
(Note 1)
-B
Drift (Note 2)
-
±2
±2
±1
±5
±4
-
-
±2
±2
±1
±5
±4
-
LSB
LSB
∆LSB
Bipolar Offset
-J
(Note 1)
-B
Drift (Note 2)
-
±2
±2
±1
±5
±3
-
-
±2
±2
±2
±5
±3
-
LSB
LSB
∆LSB
Bipolar Negative Full-scale Error
-J
(Note 1)
-B
Drift (Note 2)
-
±1
±1
±1
±4
±3
-
-
±1
±1
±1
±4
±3
-
LSB
LSB
∆LSB
-J
-B
-J
-B
96
98
85
85
100
102
88
91
-
96
98
85
85
100
102
88
91
-
dB
dB
dB
dB
-J
-B
-
0.002
0.001
-
-
0.002
0.001
-
%
%
87
90
-
90
92
30
32
-
87
90
-
90
92
30
32
-
dB
dB
dB
dB
-
35
70
-
-
35
70
-
µVrms
µVrms
Dynamic Performance (Bipolar Mode)
Peak Harmonic or Spurious Noise
1-kHz Input
12-kHz Input
Total Harmonic Distortion
Signal-to-Noise Ratio
0 dB Input
-60 dB Input
(Note 1)
(Note 1)
-J
-B
-J
-B
Noise
(Note 4)
Unipolar Mode
Bipolar Mode
Notes: 1. Applies after calibration at any temperature within the specified temperature range.
2. Total drift over specified temperature range after calibration at power-up, at 25º C.
3.
4.
Minimum resolution for which no missing codes is guaranteed over the specified temperature range.
Wideband noise aliased into the baseband, referred to the input.
* Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet.
4
DS45F6
CS5101A CS5102A
ANALOG CHARACTERISTICS, CS5101A (Continued)
CS5101A-J
Parameter*
Symbol
Specified Temperature Range
Min
-
Typ
CS5101A-B
Max
Min
0 to +70
Typ
Max
-40 to +85
Unit
ºC
Analog Input
Aperture Time
-
-
25
-
-
25
-
ns
Aperture Jitter
-
-
100
-
-
100
-
ps
-
-
320
200
425
265
-
320
200
425
265
pF
pF
tc
-
-
8.12
-
-
8.12
µs
ta
-
-
1.88
-
-
1.88
µs
ftp
100
-
-
100
-
-
kSps
I A+
I AID+
ID-
-
21
-21
11
-11
28
-28
15
-15
-
21
-21
11
-11
28
-28
15
-15
mA
mA
mA
mA
(Note 9, Note 10)
(SLEEP High)
(SLEEP Low)
Pdo
Pds
-
320
1
430
-
-
320
1
430
-
mW
mW
Power Supply Rejection
(Note 11)
Positive Supplies
Negative Supplies
PSR
PSR
-
84
84
-
-
84
84
-
dB
dB
Input Capacitance
(Note 5)
Unipolar Mode
Bipolar Mode
Conversion and Throughput
Conversion Time
(Note 6)
Acquisition Time
(Note 7)
Throughput
(Note 8)
Power Supplies
Power Supply Current
(SLEEP High)
Power Consumption
(Note 9)
Positive Analog
Negative Analog
Positive Digital
Negative Digital
Notes: 5. Applies only in the track mode. When converting or calibrating, input capacitance will not exceed 30 pF.
6.
7.
8.
9.
10.
11.
DS45F6
Conversion time scales directly to the master clock speed. The times shown are for synchronous, internal loopback
(FRN) mode) with 8.0 MHz CLKIN. In PDT, RBT, and SSC modes, asynchronous delay between the falling edge
of HOLD and the start of conversion may add to the apparent conversion time. This delay will not exceed 1.5
master clock cycles + 10 ns. In PDT, RBT, and SSC modes, CLKIN can be increased as long as the HOLD sample
rate is 100 kHz max.
The CS5101A requires 6 clock cycles of coarse charge, followed by a minimum of 1.125 µs of fine charge. FRN
mode allows 9 cycles for fine charge which provides for the minimum 1.125 µs with an 8MHz clock, however; in
PDT, RBT, or SSC modes and at clock frequencies of 8 MHz or less, fine charge may be less than 9 clock cycles.
This reflects the typical specification (6 clock cycles + 1.125 µs).
Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions affecting
acquisition and conversion times, as described above.
All outputs unloaded. All inputs at VD+ or DGND.
Power consumption in the sleep mode applies with no master clock applied (CLKIN held high or low).
With 300 mV p-p, 1-kHz ripple applied to each supply separately in the bipolar mode. Rejection improves by 6 dB
in the unipolar mode to 90 dB. Figure 25 shows a plot of typical power supply rejection versus frequency.
5
CS5101A CS5102A
SWITCHING CHARACTERISTICS, CS5101A
(TA = TMIN to TMAX; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF).
Parameter
Symbol
Min
Typ
Max
Unit
tclk
108
-
10,000
ns
CLKIN Low Time
tclkl
37.5
-
-
ns
CLKIN High Time
tclkh
37.5
-
-
ns
fxtal
2.0
-
9.216
MHz
-
-
2
-
ms
RST Pulse Width
trst
150
-
-
ns
RST to STBY falling
tdrrs
-
100
-
ns
RST Rising to STBY Rising
tcal
-
11,528,160
-
tclk
CLKIN Period
Crystal Frequency
SLEEP Rising to Oscillator Stable
(Note 12)
(Note 13)
CH1/2 Edge to TRK1, TRK2 Rising
(Note 14)
tdrsh1
-
80
-
ns
CH1/2 Edge to TRK1, TRK2 Falling
(Note 14)
tdfsh4
-
-
68tclk+260
ns
HOLD to SSH Falling
(Note 15)
tdfsh2
-
60
-
ns
HOLD to TRK1, TRK2 Falling
(Note 15)
tdfsh1
66tclk
-
68tclk+260
ns
HOLD to TRK1, TRK2, SSH Rising
(Note 15)
tdrsh
-
120
-
ns
HOLD Pulse Width
(Note 16)
thold
1tclk+20
-
63tclk
ns
HOLD to CH1/2 Edge
(Note 15)
tdhlri
15
-
64tclk
ns
HOLD Falling to CLKIN Falling
(Note 16)
thcf
95
-
1tclk+10
ns
Notes: 12. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency is 8.0 MHz in
FRN mode (100 kSps).
13.
With an 8.0 MHz crystal, two 10 pF loading capacitors and a 10 MΩ parallel resistor (see Figure 9).
14.
These timings are for FRN mode.
SSH only works correctly if HOLD falling edge is within +15 to +30 ns of CH1/2 edge or if CH1/2 edge occurs after
HOLD rises to 64tclk after HOLD has fallen. These timings are for PDT and RBT modes.
16. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must be latched
by a falling edge of CLLKIN. Conversion will begin on the next rising edge of CLKIN after HOLD is latched. If HOLD
is operated synchronous to CLKIN, the HOLD pulse width may be as narrow as 150 ns for all CLKIN frequencies
if CLKIN falls 95 ns after HOLD falls. This ensures that the HOLD pulse will meet the minimum specification for thcf.
15.
6
DS45F6
CS5101A CS5102A
ANALOG CHARACTERISTICS, CS5102A
(TA = TMIN to TMAX; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 4.5V; Full-scale Input Sine Wave, 200 Hz; CLKIN = 1.6 MHz;
fs = 20 kSps; Bipolar Mode; FRN Mode; AIN1 and AIN2 tied together, each channel tested separately; Analog Source
Impedance = 50 Ω with 1000 pF to AGND unless otherwise specified)
CS5102A-J
Parameter*
Min
Specified Temperature Range
Typ
CS5102A-B
Max
Min
0 to +70
Typ
Max
-40 to +85
Unit
ºC
Accuracy
Linearity Error
-J
(Note 1)
-B
Drift (Note 2)
Differential Linearity
(Note 3)
-
0.002 0.003
0.001 0.0015
±¼
-
-
0.002 0.003
0.001 0.0015
±¼
-
%FS
%FS
∆LSB
16
-
-
16
-
-
Bits
Full-scale Error
-J
(Note 1)
-B
Drift (Note 2)
-
±2
±2
±1
±4
±3
-
-
±2
±2
±1
±4
±3
-
LSB
LSB
∆LSB
Unipolar Offset
-J
(Note 1)
-B
Drift (Note 2)
-
±1
±1
±1
±4
±3
-
-
±1
±1
±1
±4
±3
-
LSB
LSB
∆LSB
Bipolar Offset
-J
(Note 1)
-B
Drift (Note 2)
-
±1
±1
±1
±4
±3
-
-
±1
±1
±2
±4
±3
-
LSB
LSB
∆LSB
Bipolar Negative Full-scale Error
-J
(Note 1)
-B
Drift (Note 2)
-
±2
±2
±1
±4
±3
-
-
±2
±2
±2
±4
±3
-
LSB
LSB
∆LSB
-J
-B
96
98
100
102
-
96
98
100
102
-
dB
dB
-J
-B
-
0.002
0.001
-
-
0.002
0.001
-
%
%
87
90
-
90
92
30
32
-
87
90
-
90
92
30
32
-
dB
dB
dB
dB
-
35
70
-
-
35
70
-
µVrms
µVrms
Dynamic Performance (Bipolar Mode)
Peak Harmonic or Spurious Noise
Total Harmonic Distortion
Signal-to-Noise Ratio
0 dB Input
-60 dB Input
(Note 1)
(Note 1)
-J
-B
-J
-B
Noise
(Note 4)
Unipolar Mode
Bipolar Mode
* Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet.
DS45F6
7
CS5101A CS5102A
ANALOG CHARACTERISTICS, CS5102A (Continued)
CS5102A-J
Parameter*
Symbol
Specified Temperature Range
Min
-
Typ
CS5102-B
Max
Min
0 to +70
Typ
Max
-40 to +85
Unit
ºC
Analog Input
Aperture Time
-
-
30
-
-
30
-
ns
Aperture Jitter
-
-
100
-
-
100
-
ps
-
-
320
200
425
265
-
320
200
425
265
pF
pF
Input Capacitance
(Note 5)
Unipolar Mode
Bipolar Mode
Conversion and Throughput
Conversion Time
(Note 17)
tc
-
-
40.625
-
-
40.625
µs
Acquisition Time
(Note 18)
ta
-
-
9.375
-
-
9.375
µs
Throughput
(Note 19)
ftp
20
-
-
20
-
-
kSps
I A+
I AID+
ID-
-
2.4
-2.4
2.5
-1.5
3.5
-3.5
3.5
-2.5
-
2.4
-2.4
2.5
-1.5
3.5
-3.5
3.5
-2.5
mA
mA
mA
mA
(Note 10, Note 20)
(SLEEP High)
(SLEEP Low)
Pdo
Pds
-
44
1
65
-
-
44
1
65
-
mW
mW
Power Supply Rejection
(Note 21)
Positive Supplies
Negative Supplies
PSR
PSR
-
84
84
-
-
84
84
-
dB
dB
Power Supplies
Power Supply Current
(SLEEP High)
Power Consumption
(Note 20)
Positive Analog
Negative Analog
Positive Digital
Negative Digital
Notes: 17. Conversion time scales directly to the master clock speed. The times shown are for synchronous, internal loopback
(FRN) mode. In PDT, RBT, and SSC modes, asynchronous delay between the falling edge of HOLD and the start
of conversion may add to the apparent conversion time. This delay will not exceed 1 master clock cycle + 140 ns.
The CS5102A requires 6 clock cycles of coarse charge, followed by a minimum of 5.625 µs of fine charge. FRN
mode allows 9 cycles for fine charge which provides for the minimum 5.625 µs with a 1.6 MHz clock, however; in
PDT, RBT, or SSC modes and at clock frequencies of less than 1.6 MHz, fine charge may be less than 9 clock
cycles.
19. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions affecting
acquisition and conversion times, as described above.
20. All outputs unloaded. All inputs at VD+ or DGND. See table below for power dissipation versus clock frequency.
21. With 300 mV p-p, 1-kHz ripple applied to each supply separately in the bipolar mode. Rejection improves by 6 dB
in the unipolar mode to 90 dB. Figure 25 shows a plot of typical power supply rejection versus frequency.
18.
8
Typical Power (mW)
CLKIN (MHz)
34
0.8
37
1.0
39
1.2
41
1.4
44
1.6
DS45F6
CS5101A CS5102A
SWITCHING CHARACTERISTICS, CS5102A
(TA = TMIN to TMAX; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF).
Parameter
Symbol
Min
Typ
Max
Unit
tclk
0.5
-
10
µs
CLKIN Low Time
tclkl
200
-
-
ns
CLKIN High Time
tclkh
200
-
-
ns
fxtal
0.9
1.6
2.0
MHz
-
-
20
-
ms
RST Pulse Width
trst
150
-
-
ns
RST to STBY falling
tdrrs
-
100
-
ns
RST Rising to STBY Rising
tcal
-
2,882,040
-
tclk
CLKIN Period
Crystal Frequency
SLEEP Rising to Oscillator Stable
(Note 22)
(Note 22, Note 23)
(Note 24)
CH1/2 Edge to TRK1, TRK2 Rising
(Note 25)
tdrsh1
-
80
-
ns
CH1/2 Edge to TRK1, TRK2 Falling
(Note 25)
tdfsh4
-
-
68tclk+260
ns
HOLD to SSH Falling
(Note 26)
tdfsh2
-
60
-
ns
HOLD to TRK1, TRK2 Falling
(Note 26)
tdfsh1
66tclk
-
68tclk+260
ns
HOLD to TRK1, TRK2, SSH Rising
(Note 26)
tdrsh
-
120
-
ns
HOLD Pulse Width
(Note 27)
thold
1tclk+20
-
63tclk
ns
HOLD to CH1/2 Edge
(Note 26)
tdhlri
15
-
64tclk
ns
HOLD Falling to CLKIN Falling
(Note 27)
thcf
55
-
1tclk+10
ns
Notes: 22. Minimum CLKIN period is 0.625 ms in FRN mode (20 kSps).
23.
External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency is 1.6 MHz in
FRN mode (20 kSps).
24.
With a 2.0 MHz crystal, two 33 pF loading capacitors and a 10 MΩ parallel resistor (see Figure 9).
25.
These timings are for FRN mode.
26.
SSH only works correctly if HOLD falling edge is within +15 to +30 ns of CH1/2 edge or if CH1/2 edge occurs after
HOLD rises to 64tclk after HOLD has fallen. These timings are for PDT and RBT modes.
27.
When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must be latched
by a falling edge of CLLKIN. Conversion will begin on the next rising edge of CLKIN after HOLD is latched. If HOLD
is operated synchronous to CLKIN, the HOLD pulse width may be as narrow as 150 ns for all CLKIN frequencies
if CLKIN falls 55 ns after HOLD falls. This ensures that the HOLD pulse will meet the minimum specification for thcf.
DS45F6
9
CS5101A CS5102A
t rst
RST
t ca l
STBY
t drrs
Reset and Calibration Timing
HO LD
C H 1 /2
S S H /S D L
t dfsh2
t drsh 1
T R K 1,T R K 2
T R K 1,T R K 2
t dfsh4
t drsh
S S H ,T R K 1 ,T R K 2
T R K 1,T R K 2
a. FRN Mode
t dfsh1
b. PDT, RBT Mode
Control Output Timing
th c f
C H 1 /2
t d h lri
C LK IN
HOLD
H OLD
t ho ld
Channel Selection Timing
Start Conversion Timing
Figure 1. Reset, Calibration, and Control Timing
10
DS45F6
CS5101A CS5102A
SWITCHING CHARACTERISTICS, ALL DEVICES
(TA = TMIN to TMAX; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF).
Parameter
Symbol
Min
Typ
Max
Unit
SCLK Input Pulse Period
tsclk
200
-
-
ns
SCLK Input Pulse Width Low
tsclkl
50
-
-
ns
SCLK Input Pulse Width High
tsclkh
50
-
-
ns
SCLK Input Falling to SDATA Valid
tdss
-
100
150
ns
PDT Mode
tdhs
-
140
230
ns
(Note 28)
tdts
-
65
125
ns
SCLK Output Pulse Width Low
tslkl
-
2tclk
-
tclk
SCLK Output Pulse Width High
tslkh
-
2tclk
-
tclk
SDATA Valid Before Rising SCLK
tss
2tclk-100
-
-
ns
SDATA Valid After RIsing SCLK
tsh
2tclk-100
-
-
ns
SDL Falling to 1st Rising SCLK
trsclk
66tclk
2tclk
68tclk+260
ns
PDT & RBT Modes
HOLD Falling to SDATA Valid
TRK1, TRK2 Falling to SDATA Valid
FRN & SSC Modes
Last Rising SCLK to SDL Rising
CS5101A
CS5102A
trsdl
trsdl
-
2tclk
2tclk
2tclk+165
2tclk+200
ns
HOLD Falling to 1st Falling SCLK
CS5101A
CS5102A
thfs
thfs
6tclk
6tclk
-
8tclk+165
8tclk+200
ns
tdhlri
-
7tclk
64tclk
tclk
CH1/2 Edge to 1st Falling SCLK
Notes: 28. Only valid for TRK1, TRK2 falling when SCLK is low. If SCLK is high when TRK1, TRK2 falls, then SDATA is
valid tdss time after the next falling SCLK.
DS45F6
11
CS5101A CS5102A
H O LD
t h fs
t chfs
C H 1 /2
S S H /S D L
t rsclk
t sclkl
t sc lkh
t slkl
t slkh
t rsd l
t d ss
SCLK
S C LK
t d ss
t sclk
t ss
SDATA
SDATA
a. SCLK Input (PDT & RBT Modes)
t sh
MSB
LSB
b. SCLK Output (FRN & SSC Modes)
Serial Data Timing
HOLD
T R K 1, T R K 2
t dhs
SDATA
MSB
t d ts
SDATA
SCLK
SCLK
a. Pipelined Data Transmission (PDT)
MSB
M S B -1
t dss
b. Register Burst Transmission (RBT)
Data Transmission Timing
Figure 2. Serial Communication Timing
12
DS45F6
CS5101A CS5102A
DIGITAL CHARACTERISTICS, ALL DEVICES
(TA = TMIN to TMAX; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10%
Parameter
Symbol
Min
Typ
Max
Unit
VMR
2.0
-
-
V
High-level Input Voltage
VIH
2.0
-
-
V
Low-level Input Voltage
VIL
-
-
0.8
V
(Note 30)
VOH
(VD+) -1.0
-
-
V
Iout = 1.6 mA
VOL
-
-
0.4
V
Iin
-
-
10
µA
Cout
-
9
-
pF
Calibration Memory Retention
Power Supply Voltage VA+ and VD+
(Note 29)
High-level Output Voltage
Low-level Output Voltage (except XOUT)
Input Leakage Current
Digital Output Pin Capacitance
29.
VA- and VD- can be any value from 0 to +5V for memory retention. Neither VA- nor VD- should be allowed to go
positive. AIN1, AIN2, or VREF must not be greater than VA+ or VD+. This parameter is guaranteed by
characterization.
30. IOUT = -100 µA. This specification guarantees TTL compatibility (VOH = 2.4V @ IOUT = -40 µA).
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND = 0V, see Note 31)
Parameter
Symbol
Min
Typ
Max
Unit
VD+
VDVA+
VA-
4.5
-4.5
4.5
-4.5
5.0
-5.0
5.0
-5.0
VA+
-5.5
5.5
-5.5
V
V
V
V
VREF
2.5
4.5
(VA+)-0.5
V
VAIN
VAIN
AGND
-VREF
-
VREF
VREF
V
V
DC Power Supplies:
Positive Digital
Negative Digital
Positive Analog
Negative Analog
Analog Reference Voltage
DC Power Supplies:
(Note 32)
Unipolar
Bipolar
31.
32.
DS45F6
All voltages with respect to ground.
The CS5101A and CS5102A can accept input voltages up to the analog supplies (VA+ and VA-). They will produce
an output of all 1s for input above VREF and all 0s for inputs below AGND in unipolar mode, and -VREF in bipolar
mode, with binary coding (CODE = low).
13
CS5101A CS5102A
ABSOLUTE MAXIMUM RATINGS
(AGND, DGND = 0V, all voltages with respect to ground.)
Parameter
Symbol
Min
Typ
Max
Unit
VD+
VDVA+
VA-
-0.3
0.3
-0.3
0.3
-
6.0
-6.0
6.0
-6.0
V
V
V
V
IIN
-
-
±10
mA
VINA
(VA-) - 0.3
-
(VA+) + 0.3
V
VIND
-0.3
-
(VA+) + 0.3
V
Ambient Operating Temperature
TA
-55
-
125
°C
Storage Temperature
Tstg
-65
-
150
°C
DC Power Supplies:
(Note 33)
Positive Digital
Negative Digital
Positive Analog
Negative Analog
Input Current, Any Pin Except Supplies
Analog Input Voltage
(Note 34)
(AIN and VREF pins)
Digital Input Voltage
Notes: 33. In addition, VD+ must not be greater than (VA+) + 0.3 V.
34.
Transient currents of up to 100 mA will not cause SCR latch-up
WARNING: Operation beyond these limits may result in permanent damage to the device.
14
DS45F6
CS5101A CS5102A
2.
OVERVIEW
The CS5101A and CS5102A are 2-channel, 16-bit
A/D converters. The devices include an inherent
sample/hold and an on-chip analog switch for 2channel operation. Both channels can thus be
sampled and converted at rates up to 50 kSps
each (CS5101A) or 10 kSps each (CS5102A). Alternatively, each of the devices can be operated as
a single channel ADC operating at 100 kSps
(CS5101A) or 20 kSps (CS5102A).
Both the CS5101A and CS5102A can be configured to accept either unipolar or bipolar input ranges, and data is output serially in either binary or 2's
complement coding. The devices can be configured in 3 different output modes, as well as an internal, synchronous loopback mode. The
CS5101A and CS5102A provide coarse
charge/fine charge control, to allow accurate tracking of high-slew signals.
3.
THEORY OF OPERATION
The CS5101A and CS5102A implement the successive approximation algorithm using a charge
redistribution architecture. Instead of the traditional
resistor network, the DAC is an array of binaryweighted capacitors. All capacitors in the array
share a common node at the comparator's input.
As shown in Figure 3, their other terminals are capable of being connected to AGND, VREF, or AIN
(1 or 2). When the device is not calibrating or converting, all capacitors are tied to AIN. Switch S1 is
closed and the charge on the array, tracks the input signal.
When the conversion command is issued, switch
S1 opens. This traps the charge on the comparator
side of the capacitor array and creates a floating
node at the comparator's input. The conversion algorithm operates on this fixed charge, and the signal at the analog input pin is ignored. In effect, the
entire DAC capacitor array serves as analog memory during conversion much like the hold capacitor
in a sample/hold amplifier.
The conversion consists of manipulating the free
plates of the capacitor array to VREF and AGND to
form a capacitive divider. Since the charge at the
floating node remains fixed, the voltage at that
point depends on the proportion of capacitance
tied to VREF versus AGND. The successive approximation algorithm is used to find the proportion
of capacitance, which when connected to the reference will drive the voltage at the floating node to
zero. That binary fraction of capacitance represents the converter's digital output.
Fine
A IN
+
-
C o arse
Fine
VREF
+
-
C o a rse
C
Bit 15
MSB
C /2
C /4
Bit 14
C /3 2 ,7 6 8
C /3 2 ,7 6 8
Bit 13
Bit 0
LSB
Dum m y
S1
+
Fine
AGND
+
-
C to t
= C + C /2 + C /4 + C /8 + ... C /3 2 ,7 68
C o a rse
Figure 3. Coarse Charge Input Buffers & Charge Redistribution DAC
DS45F6
15
CS5101A CS5102A
3.1
Calibration
The ability of the CS5101A or the CS5102A to convert accurately to 16-bits clearly depends on the
accuracy of its comparator and DAC. Each device
utilizes an “auto-zeroing” scheme to null errors introduced by the comparator. All offsets are stored
on the capacitor array while in the track mode and
are effectively subtracted from the input signal
when a conversion is initiated. Auto-zeroing enhances power supply rejection at frequencies well
below the conversion rate.
To achieve 16-bit accuracy from the DAC, the
CS5101A and CS5102A use a novel self-calibra-
16
tion scheme. Each bit capacitor shown in Figure 3
actually consists of several capacitors in parallel
which can be manipulated to adjust the overall bit
weight. An on-chip microcontroller precisely adjusts each capacitor with a resolution of 18 bits.
The CS5101A and CS5102A should be reset upon
power-up, thus initiating a calibration cycle. The
device then stores its calibration coefficients in onchip SRAM. When the CS5101A and CS5102A are
in power-down mode (SLEEP low), they retain the
calibration coefficients in memory, and need not be
recalibrated when normal operation is resumed.
DS45F6
CS5101A CS5102A
4. FUNCTIONAL DESCRIPTION
Monolithic design and inherent sampling architecture make the CS5101A and CS5102A extremely
easy to use.
4.1
Initiating Conversions
A falling transition on the HOLD pin places the input in the hold mode and initiates a conversion cycle. The charge is trapped on the capacitor array
the instant HOLD goes low. The device will complete conversion of the sample within 66 master
clock cycles, then automatically return to the track
mode. After allowing a short time for acquisition,
the device will be ready for another conversion.
In contrast to systems with separate track-andholds and A/D converters, a sampling clock can
simply be connected to the HOLD input. The duty
cycle of this clock is not critical. The HOLD input is
latched internally by the master clock, so it need
only remain low for 1/fclk + 20 ns, but no longer
than the minimum conversion time minus two master clocks or an additional conversion cycle will be
initiated with inadequate time for acquisition. In
Free Run mode, SCKMOD = OUTMOD = 0, the
device will convert at a rate of CLKIN/80, and the
HOLD input is ignored.
As with any high-resolution A-to-D system, it is recommended that sampling is synchronized to the
master system clock in order to minimize the effects of clock feed through. However, the
CS5101A and CS5102A may be operated entirely
asynchronous to the master clock if necessary.
4.2
Tracking the Input
Upon completing a conversion cycle the CS5101A
and CS5102A immediately return to the track
mode. The CH1/2 pin directly controls the input
switch, and therefore directly determines which
channel will be tracked. Ideally, the CH1/2 pin
should be switched during the conversion cycle,
thereby nullifying the input mux switching time, and
guaranteeing a stable input at the start of acquisition. If, however, the CH1/2 control is changed during the acquisition phase, adequate coarse charge
and fine charge time must be allowed before initiating conversion.
When the CS5101A or the CS5102A enters tracking mode, it uses an internal input buffer amplifier
DS45F6
to provide the bulk of the charge on the capacitor
array (coarse-charge), thereby reducing the current load on the external analog circuitry. Coarsecharge is internally initiated for 6 clock cycles at the
end of every conversion. The buffer amplifier is
then bypassed, and the capacitor array is directly
connected to the input. This is referred to as finecharge, during which the charge on the array is allowed to accurately settle to the input voltage (see
Figure 12).
With a full-scale input step, the coarse-charge input buffer of the CS5101A will charge the capacitor
array within 1% in 650 ns. The converter timing allows 6 clock cycles for coarse charge settling time.
When the CS5101A switches to fine-charge mode,
its slew rate is somewhat reduced. In fine-charge,
the CS5101A can slew at 2 V/µs in unipolar mode.
In bipolar mode, only half the capacitor array is
connected to the analog input, so the CS5101A
can slew at 4V/µs.
With a full-scale input step, the coarse-charge input buffer of the CS5102A will charge the capacitor
array within 1% in 3.75 µs. The converter timing allows 6 clock cycles for coarse charge settling time.
When in fine-charge mode, the CS5102A can slew
at 0.4 V/µs in unipolar mode; and at 0.8 V/µs in bipolar mode.
Acquisition of fast slewing signals can be hastened
if the voltage change occurs during or immediately
following the conversion cycle. For instance, in
multiple channel applications (using either the device's internal channel selector or an external
MUX), channel selection should occur while the
CS5101A or the CS5102A is converting. Multiplexer switching and settling time is thereby removed
from the overall throughput equation.
If the input signal changes drastically during the
acquisition period (such as changing the signal
source), the device should be in coarse-charge for
an adequate period following the change. The
CS5101A and CS5102A can be forced into coarsecharge by bringing CRS/FIN high. The buffer amplifier is engaged when CRS/FIN is high, and may
be switched in any number of times during tracking. If CRS/FIN is held low, the CS5101A and
CS5102A will only coarse-charge for the first 6
clock cycles following a conversion, and will stay in
17
CS5101A CS5102A
fine-charge until HOLD goes low. To get an accurate sample using the CS5101A, at least 750 ns of
coarse-charge, followed by 1.125 µs of fine-charge
is required before initiating a conversion. If coarse
charge is not invoked, then up to 25 µs should be
allowed after a step change input for proper acquisition. To get an accurate sample using the
CS5102A, at least 3.75 µs of coarse-charge, fol-
lowed by 5.625 µs of fine-charge is required before
initiating a conversion (see Figure 4). If coarse
charge is not invoked, then up to 125 µs should be
allowed after a step change input for proper acquisition. The CRS/FIN pin must be low prior to HOLD
becoming active and be held low during conversion.
C L K IN
M in: 750 ns*
3.75 µ s**
C R S /F IN
6 clk
In te rn al
S tatus
TR K 1 or
TR K2
C onv.
C o arse
M in : 1 .1 2 5 µ s*
5 .62 5 µ s**
F in e C hg.
C o arse
Fine C hg.
C on v.
2 clk
HOLD
* A pplies to 5101A
** A pplies to 51 02A
Figure 4. Coarse/Fine Charge Control
4.3
Master Clock
The CS5101A and CS5102A can operate either
from an externally-supplied master clock, or from
their own crystal oscillator (with a crystal). To enable the internal crystal oscillator, simply tie a crystal across the XOUT and CLKIN pins and add 2
capacitors and a resistor, as shown on the system
connection diagram in Figure 9.
Calibration and conversion times directly scale to
the master clock frequency. The CS5101A can operate with clock or crystal frequencies up to 9.216
MHz (8.0 MHz in FRN mode). This allows maximum throughput of up to 50 kSps per channel in
dual-channel operation, or 100 kSps in a singlechannel configuration. The CS5102A can operate
with clock or crystal frequencies up to 2.0 MHz (1.6
MHz in FRN mode). This allows maximum
throughput of up to 10 kSps per channel in dualchannel operation, or 20 kSps in a single channel
configuration. For 16-bit performance a 1.6 MHz
clock is recommended. This 1.6 MHz clock yields
a maximum throughput of 20 kSps in a singlechannel configuration.
18
4.4
Asynchronous Sampling
Considerations
When HOLD goes low, the analog sample is captured immediately. The HOLD signal is latched by
the next falling edge of CLKIN, and conversion
then starts on the subsequent rising edge. If HOLD
is asynchronous to CLKIN, then there will be a 1.5CLKIN-cycle uncertainty as to when conversion
starts. Considering the CS5101A with an 8 MHz
CLKIN, with a 100 kHz HOLD signal, then this 1.5CLKIN uncertainty will result in a 1.5-CLKIN-period
possible reduction in fine charge time for the next
conversion.
This reduced fine charge time will be less than the
minimum specification. If the CLKIN frequency is
increased slightly (for example, to 8.192 MHz) then
sufficient fine charge time will always occur. The
maximum frequency for CLKIN is specified at
9.216 MHz. It is recommended that for asynchronous operation at 100 kSps, CLKIN should be between 8.192 MHz and 9.216 MHz.
DS45F6
CS5101A CS5102A
4.5
Analog Input Range/Coding Format
The reference voltage directly defines the input
voltage range in both the unipolar and bipolar configurations. In the unipolar configuration
(BP/UP low), the first code transition occurs
0.5 LSB above AGND, and the final code transition
occurs 1.5 LSBs below VREF. In the bipolar configuration (BP/UP high), the first code transition oc-
curs 0.5 LSB above -VREF and the last transition
occurs 1.5 LSBs below +VREF. The CS5101A and
CS5102A can output data in either 2's complement, or binary format. If the CODE pin is high, the
output is in 2's complement format with a range of
-32,768 to +32,767. If the CODE pin is low, the output is in binary format with a range of 0 to +65,535.
See Table 1 for output coding.
Table 1. Output Coding
Offset
Binary
Two’s
Complement
Bipolar Input Voltage
>(VREF-1.5 LSB)
FFFF
7FFF
>(VREF-1.5 LSB)
VREF-1.5 LSB
FFFF
FFFE
7FFF
7FFE
VREF-1.5 LSB
(VREF/2)-0.5 LSB
8000
7FFF
0000
FFFF
-0.5 LSB
+0.5 LSB
0001
0000
8001
8000
-VREF+0.5 LSB
<(+0.5 LSB)
0000
8000
<(-VREF+0.5 LSB)
Unipolar Input Voltage
4.6
Output Mode Control
The CS5101A and CS5102A can be configured in
three different output modes, as well as an internal,
synchronous loop-back mode. This allows great
flexibility for design into a wide variety of systems.
The operating mode is selected by setting the
states of the SCKMOD and OUTMOD pins. In all
modes, data is output on SDATA, starting with the
MSB. Each subsequent data bit is updated on the
falling edge of SCLK.
Table 2. Output Mode Control
MODE
SCKMOD
OUTMOD
SCLK
CH1/2
PDT
1
1
Input
Input
Input
RBT
1
0
Input
Input
Input
SSC
0
1
Output
Input
Input
FRN
0
0
Output
Output
X
When SCKMOD is high, SCLK is an input, allowing
the data to be clocked out with an external serial
clock at rates up to 5 MHz. Additional clock edges
after #16 will clock out logic 1s on SDATA. Tying
SCKMOD low reconfigures SCLK as an output,
and the converter clocks out each bit as it is determined during the conversion process, at a rate of
1/4 the master clock speed. Table 2 shows an
overview of the different states of SCKMOD and
OUTMOD, and the corresponding output modes.
DS45F6
4.6.1
HOLD
Pipelined Data Transmission
PDT mode is selected by tying both SCKMOD and
OUTMOD high. In PDT mode, the SCLK pin is an
input. Data is registered during conversion, and
output during the following conversion cycle.
HOLD must be brought low, initiating another conversion, before data from the previous conversion
is available on SDATA. If all the data has not been
clocked out before the next falling edge of HOLD,
the old data will be lost (Figure 5).
19
CS5101A CS5102A
4.6.2
Register Burst Transmission (RBT)
RBT mode is selected by tying SCKMOD high, and
OUTMOD low. As in PDT mode, SCLK is an input,
however data is available immediately following
conversion, and may be clocked out the moment
TRK1 or TRK2 falls. The falling edge of HOLD
clears the output buffer, so any unread data will be
lost. A new conversion may be initiated before all
the data has been clocked out if the unread data
bits are not important (Figure 6).
4.6.3
Synchronous Self-clocking (SSC)
SSC mode is selected by tying SCKMOD low, and
OUTMOD high. In SSC mode, SCLK is an output,
and will clock out each bit of the data as it's being
converted. SCLK will remain high between conversions, and run at a rate of 1/4 the master clock
speed for 16 low pulses during conversion
(Figure 7).
The SSH/SDL goes low coincident with the first
falling edge of SCLK, and returns high 2 CLKIN cycles after the last rising edge of SCLK. This signal
frames the 16 data bits and is useful for interfacing
0
4
8
60
64
68
72
76
to shift registers (e.g. 74HC595) or to DSP serial
ports.
4.6.4
Free Run (FRN)
Free Run is the internal, synchronous loopback
mode. FRN mode is selected by tying SCKMOD
and OUTMOD low. SCLK is an output, and operates exactly the same as in the SSC mode. In Free
Run mode, the converter initiates a new conversion every 80 master clock cycles, and alternates
between channel 1 and channel 2. HOLD is disabled, and should be tied to either VD+ or DGND.
CH1/2 is an output, and will change at the start of
each new conversion cycle, indicating which channel will be tracked after the current conversion is
finished (Figure 8).
The SSH/SDL goes low coincident with the first
falling edge of SCLK, and returns high 2 CLKIN cycles after the last rising edge of SCLK. This signal
frames the 16 data bits and is useful for interfacing
to shift registers (e.g. 74HC595) or to DSP serial
ports.
0
4
8
60
64
68
72
76
0
C LK IN (i)
H O LD (i)
C H 1/2 (i)
In tern al
S tatus
C onverting C h. 2
T racking C h. 1
C onverting C h. 1
T racking C h. 2
S C LK (i)
S D A TA (o )
D 15
D 14
D 1 D 0 (C h. 1)
D 15
D 14
D1
D 0 (C h. 2)
D 15
S S H /S D L (o )
T R K1 (o )
T R K2 (o )
Figure 5. Pipelined Data Transmission (PDT) Mode Timing
20
DS45F6
CS5101A CS5102A
0
4
64
68
72
0
4
64
68
72
0
C L K IN (i)
H O L D (i)
C H 1 /2 (i)
In te rn a l
S tatu s
C o n ve rtin g C h . 2
T ra ckin g C h . 1
C o n ve rtin g C h . 1
T rac kin g C h . 2
S C L K (i)
C ha n n e l 2 D ata
S D A T A (o)
C ha nn e l 1 D ata
D0
D0
S S H /S D L (o )
T R K 1 (o )
T R K 2 (o )
Figure 6. Register Burst Transmission (RBT) Mode Timing
0
4
6
8
64
68
72
76
0
4
6
8
64
68
72
76
0
C L K IN (i)
H O LD (i)
C H 1 /2 (i)
In te rn a l
S tatu s
C on ve rtin g C h . 2
T ra ckin g C h. 1
C o n ve rtin g C h . 1
T ra ckin g C h. 2
S C L K (o )
D15
S D A T A (o)
D 14
D1
D 0 (C h. 2 )
D15
D14
D1
D 0 (C h . 1 )
S S H /S D L (o )
T R K 1 (o )
T R K 2 (o )
Figure 7. Synchronous Self-clocking (SSC) Mode Timing
0
4
7 8
64
68 69
72
76
0
4
7 8
64
68 69
72
76
0
C LK IN (i)
C H 1 /2 (o )
In te rn a l
S tatu s
C on ve rtin g C h . 2
T ra cking C h. 1
C o n ve rtin g C h . 1
T ra ckin g C h. 2
S C L K (o )
S D A T A (o)
D15
D1
D 0 (C h . 2 )
D 15
D1
D 0 (C h . 1 )
S S H /S D L (o )
T R K 1 (o )
T R K 2 (o )
Figure 8. Free Run (FRN) Mode Timing
DS45F6
21
CS5101A CS5102A
5. SYSTEM DESIGN USING THE CS5101A & CS5102A
Figure 9 shows a general system connection diagram for the CS5101A and CS5102A.
10
+5VA
+
+
4.7 µ F
0.1 µ F
0.1 µ F
26
25
VA+
TST
1 µF
7
VD+
XOUT
4
C1
XTAL
VD+
C L K IN
M od e C on tro l
18
O UTM O D
27
SCKMO D
17
16
2
B P /U P
RST
22
VREF
SLEEP
STBY
C H 1 /2
C S5102A
C R S /F IN
AGND
HOLD
TRK1
50
A n a log
S o urce s
*
C0G
NPO
1 nF
50
19
*
1 nF
24
TRK2
A IN 1
S S H /S D L
A IN 2
NPO
C0G
S CLK
SDATA
* Fo r b e st d y n a m ic
S /(N + D ) pe rform an c e.
21
DGND
REFB UF
VA-
0.1 µ F
5
13
C o n tro l
L og ic
10
XTA L & C1 Table
CS5101A
12
FR N
8
P D T, R B T ,
SSC
CS5102A
9
FR N
11
14
15
P D T, R B T ,
SSC
XTAL
C1, C2
8 .0 M H z
10 pF
8 .1 9 2 M H z
10 pF
1 .6 M H z
30 pF
1 .6 M H z
or
2 .0 M H z
30 pF
D a ta
Interfa ce
6
VD-
23
U nu se d Lo g ic in p uts s ho uld
b e tie d to V D + o r D G N D .
1
10
-5 V A
+ 4.7 µ F
EXT
C LO C K
28
CODE
OR
20
3
C2 = C1
C S5101A
V o lta g e R e fere n c e
10 M
0.1 µ F
0.1 µ F
+ 1 µF
Figure 9. CS5101A/CS5102A System Connection Diagram
5.1
System Initialization
Upon power up, the CS5101A and CS5102A must
be reset to guarantee a consistent starting condition and to initially calibrate the device. Due to
each device's low power dissipation and low temperature drift, no warm-up time is required before
reset to accommodate any self-heating effects.
However, the voltage reference input should have
stabilized to within 0.25% of its final value before
RST rises to guarantee an accurate calibration.
Later, the CS5101A and CS5102A may be reset at
any time to initiate a single full calibration.
When RST is brought low all internal logic clears.
When RST returns high on the CS5101A, a calibration cycle begins which takes 11,528,160 master clock cycles to complete (approximately
22
1.4 seconds with an 8 MHz master clock). The calibration cycle on the CS5102A takes 2,882,040
master clock cycles to complete (approximately
1.8 seconds with a 1.6 MHz master clock). The
CS5101A's and CS5102A's STBY output remains
low throughout the calibration sequence, and a rising transition indicates the device is ready for normal operation. While calibrating, the CS5101A and
CS5102A will ignore changes on the HOLD input.
To perform the reset function, a simple power-on
reset circuit can be built using a resistor and capacitor as shown in Figure 10. The resistor should
be less than or equal to 10 kΩ. The system power
supplies, voltage reference, and clock should all be
established prior RST rising.
DS45F6
CS5101A CS5102A
+5V
VD+
R
1N4148
C
CS5101A
OR
CS5102A
RST
Figure 10. Power-up Reset Circuit
5.2
Single-channel Operation
The CS5101A and CS5102A can alternatively be
used to sample one channel by tying the CH1/2 input high or low. The unused AIN pin should be tied
to the analog input signal or to AGND. (If operating
in free run mode, AIN1 and AIN2 must be tied to
the same source, as CH1/2 is reconfigured as an
output.)
6. ANALOG CIRCUIT CONNECTIONS
Most popular successive approximation A/D converters generate dynamic loads at their analog
connections. The CS5101A and CS5102A internally buffer all analog inputs (AIN1, AIN2, VREF,
and AGND) to ease the demands placed on external circuitry. However, accurate system operation
still requires careful attention to details at the design stage regarding source impedances as well
as grounding and decoupling schemes.
6.1
Reference Considerations
An application note titled AN004, Voltage
References for the CS5012A / CS5014 /CS5016 /
CS5101A/ CS5102A / CS5126 Series of A/D Con
verters is available for the CS5101A and
CS5102A. In addition to working through a reference circuit design example, it offers several builtand-tested reference circuits.
During conversion, each capacitor of the calibrated
capacitor array is switched between VREF and
AGND in a manner determined by the successiveapproximation algorithm. The charging and discharging of the array results in a current load at the
reference. The CS5101A and CS5102A each inDS45F6
clude an internal buffer amplifier to minimize the
external reference circuit's drive requirement and
preserve the reference's integrity. Whenever the
array is switched during conversion, the buffer is
used to coarse-charge the array thereby providing
the bulk of the necessary charge. The appropriate
array capacitors are then switched to the unbuffered VREF pin to avoid any errors due to offsets
and/or noise in the buffer.
The external reference circuitry need only provide
the residual charge required to fully charge the array after coarse-charging from the buffer. This creates an ac current load as the CS5101A and
CS5102A sequence through conversions. The reference circuitry must have a low enough output impedance to drive the requisite current without
changing its output voltage significantly. As the analog input signal varies, the switching sequence of
the internal capacitor array changes. The current
load on the external reference circuitry thus varies
in response with the analog input. Therefore, the
external reference must not exhibit significant
peaking in its output impedance characteristic at
signal frequencies or their harmonics.
A large capacitor connected between VREF and
AGND can provide sufficiently low output impedance at the high end of the frequency spectrum,
while almost all precision references exhibit extremely low output impedance at DC. The presence of large capacitors on the output of some
voltage references, however, may cause peaking
in the output impedance at intermediate frequencies. Care should be exercised to ensure that significant peaking does not exist or that some form of
compensation is provided to eliminate the effect.
The magnitude of the current load on the external
reference circuitry will scale to the master clock frequency. At the full-rated 9.216 MHz clock
(CS5101A), the reference must supply a maximum
load current of 20 µA peak-to-peak (2 µA typical).
An output impedance of 2 Ω will therefore yield a
maximum error of 40 µV. At the full-rated 2.0 MHz
clock (CS5102A), the reference must supply a
maximum load current of 5 µA peak-to-peak
(0.5µA typical). An output impedance of 2 Ω will
therefore yield a maximum error of 10.0 µV. With a
4.5 V reference and LSB size of 138 µV this would
ensure approximately 1/14 LSB accuracy. A 10 µF
23
CS5101A CS5102A
Peaking in the reference's output impedance can
occur because of capacitive loading at its output.
Any peaking that might occur can be reduced by
placing a small resistor in series with the capacitors. The equation in Figure 11 can be used to help
calculate the optimum value of R for a particular
reference. The term “fpeak” is the frequency of the
peak in the output impedance of the reference before the resistor is added.
+ V ee
20 V R E F
V ref
21 R E F B U F
10 µ F
0.01 µ F
0.1 µ F
23 V A-
R*
C S 5101A
OR
C S 5102A
-5V
1
R = ---------------------------------------------------------------( 2π ⋅ ( C1 + C2 ) ⋅ fpeak )
Figure 11. Reference Connections
The CS5101A and CS5102A can operate with a
wide range of reference voltages, but signal-tonoise performance is maximized by using as wide a
signal range as possible. The recommended reference voltage is 4.5 volts. The CS5101A and
CS5102A can actually accept reference voltages up
to the positive analog supply. However, the buffer's
offset may increase as the reference voltage approaches VA+ thereby increasing external drive requirements at VREF. A 4.5V reference is the
maximum reference voltage recommended. This allows 0.5V headroom for the internal reference buffer. Also, the buffer enlists the aid of an external
0.1 µF ceramic capacitor which must be tied between its output, REFBUF, and the negative analog
supply, VA-. For more information on references,
consult application note
AN004, Voltage References for CS5012A / CS5014 /CS5016 /
CS5101A / CS5102A / CS5126 Series of A/D Converters.
24
6.2
Analog Input Connection
The analog input terminal functions similarly to the
VREF input after each conversion when switching
into the track mode. During the first six master
clock cycles in the track mode, the buffered version
of the analog input is used for coarse-charging the
capacitor array. An additional period is required for
fine-charging directly from AIN to obtain the specified accuracy. Figure 12 shows this operation. During coarse-charge the charge on the capacitor
array first settles to the buffered version of the analog input. This voltage may be offset from the actual input voltage. During fine-charge, the charge
then settles to the accurate unbuffered version.
Fine-charge settling is specified as a maximum of
1.125 µs (CS5101A) or 5.625 µs (CS5102A) for an
analog source impedance of less than 50 Ω. In addition, the comparator requires a source impedance of less than 400 Ω around 2 MHz for stability.
The source impedance can be effectively reduced
at high frequencies by adding capacitance from
AIN to ground (typically 200 pF). However, high
DC source resistances will increase the input's RC
time constant and extend the necessary acquisition time. For more information on input amplifiers,
consult the application note,
AN006, Buffer Amplifiers for CS5012A / 14 / 16 / CS5101A /
CS5102A / CS5126 Series of A/D Converters.
+2 0 0
Internal C harge Error (LSB 's)
capacitor exhibits an impedance of less than 2 Ω at
frequencies greater than 16 kHz. A high-quality
tantalum capacitor in parallel with a smaller ceramic capacitor is recommended.
+1 0 0
0
-1 00
C o a rse -C h a rg e
F ine -C h a rg e
-2 00
-3 00
-4 00
8 M H z C lo ck 0 .2 5
2.0 M H z C lock 1.0
0 .5
2 .0
0 .7 5
3 .0
1 .0
4 .0
A cquisition Tim e (us)
Figure 12. Charge Settling Time
6.3
Sleep Mode Operation
The CS5101A and CS5102A include a SLEEP pin.
When SLEEP is active (low) each device will dissipate very low power to retain its calibration memo-
DS45F6
CS5101A CS5102A
ry when the device is not sampling. It does not
require calibration after SLEEP is made inactive
(high). When coming out of Sleep mode, sampling
can begin as soon as the oscillator starts (time will
depend on the particular oscillator components)
and the REFBUF capacitor is charged (which
takes about 3 ms for the CS5101A, 50 ms for the
CS5102A). To achieve minimum start-up time, use
an external clock and leave the voltage reference
powered-up. Connect a resistor (2 kΩ) between
pins 20 and 21 to keep the REFBUF capacitor
charged. Conversion can then begin as soon as
the A/D circuitry has stabilized and performed a
track cycle.
To retain calibration memory while SLEEP is active
(low) VA+ and VD+ must be maintained at greater
than 2.0V. VA- and VD- can be allowed to go to 0
volts. The voltages into VA- and VD- cannot just be
“shut-off” as these pins cannot be allowed to float
to potentials greater than AGND/DGND. If the supply voltages to VA- and VD- are removed, use a
transistor switch to short these to the power supply
ground while in Sleep mode.
6.4
Grounding & Power Supply
Decoupling
The CS5101A and CS5102A use the analog
ground connection, AGND, only as a reference
voltage. No DC power currents flow through the
AGND connection, and it is completely independent of DGND. However, any noise riding on the
AGND input relative to the system's analog ground
will induce conversion errors. Therefore, both the
analog input and reference voltage should be referred to the AGND pin, which should be used as
the entire system's analog ground reference.
DS45F6
The digital and analog supplies are isolated within
the CS5101A and CS5102A and are pinned out
separately to minimize coupling between the analog and digital sections of the chip. All four supplies
should be decoupled to their respective grounds
using 0.1 µF ceramic capacitors. If significant lowfrequency noise is present on the supplies, tantalum capacitors are recommended in parallel with
the 0.1 µF capacitors.
The positive digital power supply of the CS5101A
and CS5102A must never exceed the positive analog supply by more than a diode drop or the
CS5101A and CS5102A could experience permanent damage. If the two supplies are derived from
separate sources, care must be taken that the analog supply comes up first at power-up. The system connection diagram (Figure 9) shows a
decoupling scheme which allows the CS5101A
and CS5102A to be powered from a single set of
5V rails. The positive digital supply is derived from
the analog supply through a 10 Ω resistor to avoid
the analog supply dropping below the digital supply. If this scheme is utilized, care must be taken to
ensure that any digital load currents (which flow
through the 10 Ω resistors) do not cause the magnitude of digital supplies to drop below the analog
supplies by more than 0.5 volts. Digital supplies
must always remain above the minimum specification.
As with any high-precision A/D converter, the
CS5101A and CS5102A require careful attention
to grounding and layout arrangements. However,
no unique layout issues must be addressed to
properly apply the devices.
25
CS5101A CS5102A
7. CS5101A & CS5102A PERFORMANCE
7.1
Differential Nonlinearity
The self-calibration scheme utilized in the
CS5101A and CS5102A features a calibration resolution of 1/4 LSB, or 18-bits. This ideally yields
DNL of 1/4 LSB, with code widths ranging from 3/4
to 5/4 LSBs.
Traditional laser-trimmed ADCs have significant
differential nonlinearities. Appearing as wide and
narrow codes, DNL often causes entire sections of
the transfer function to be missing. Although their
affect is minor on S/(N+D) with high amplitude signals, DNL errors dominate performance with lowlevel signals. For instance, a signal 80 dB below
full-scale will slew past only 6 or 7 codes. Half of
those codes could be missing with a conventional
16-bit ADC which achieves only 14-bit DNL.
The most common source of DNL errors in conventional ADCs is bit weight errors. These can
arise due to accuracy limitations in factory trim stations, thermal or physical stresses after calibration,
and/or drifts due to aging or temperature variations
in the field. Bit-weight errors have a drastic effect
on a converter's AC performance. They can be analyzed as step functions superimposed on the input signal. Since bits (and their errors) switch in
and out throughout the transfer curve, their effect
is signal dependent. That is, harmonic and intermodulation distortion, as well as noise, can vary
with different input conditions.
Differential nonlinearities in successive-approximation ADCs also arise due to dynamic errors in
the comparator. Such errors can dominate if the
converter's throughput/sampling rate is too high.
The comparator will not be allowed sufficient time
to settle during each bit decision in the successiveapproximation algorithm. The worst-case codes for
dynamic errors are the major transitions (1/2 FS;
1/4, 3/4 FS; etc.). Since DNL effects are most crit-
26
ical with low-level signals, the codes around midscale (1/2 FS) are most important. Yet those codes
are worst-case for dynamic DNL errors!
With all linearity calibration performed on-chip to
18-bits, the CS5101A and CS5102A maintain accurate bit weights. DNL errors are dominated by
residual calibration errors of 1/4 LSB rather than
dynamic errors in the comparator. Furthermore, all
DNL effects on S/(N+D) are buried by white broadband noise. (See Figures 19 and 21).
Figure 13 illustrates the DNL histogram plot of a
typical CS5101A at 25 °C. Figure 14 illustrates the
DNL of the CS5101A at 138 °C ambient after calibration at 25 °C ambient. Figure 15 and Figure 16
illustrate the DNL of the CS5102A at 25 °C and
138 °C ambient, respectively. A histogram test is a
statistical method of deriving an A/D converter's
differential nonlinearity. A ramp is input to the A/D
and a large number of samples are taken to ensure
a high confidence level in the test's result. The
number of occurrences for each code is monitored
and stored. A perfect A/D converter would have all
codes of equal size and therefore equal numbers
of occurrences. In the histogram test a code with
the average number of occurrences will be considered ideal (DNL = 0). A code with more or less occurrences than average will appear as a DNL of
greater or less than zero LSB. A missing code has
zero occurrences, and will appear as a DNL of -1
LSB.
Figures 17 and 18 illustrate the code width distribution of the DNL plots shown in Figure 13 and
Figure 15 respectively. The DNL error distribution
plots indicate that the CS5101A and CS5102A calibrate the majority of their codes to tighter tolerance than the DNL plots in Figures 13 and 15
appear to indicate.
DS45F6
CS5101A CS5102A
+1
TA = 25°C
DNL (LSB)
+1/2
0
-1/2
-1
0
32,768
65,535
Codes
Figure 13. CS5101A DNL Plot - Ambient Temperature at 25 °C
+1
TA = 138 °C, CAL @ 25 °C
DNL (LSB)
+1/2
0
-1/2
-1
0
32,768
65,535
Codes
Figure 14. CS5101A DNL Plot - Ambient Temperature at 138 °C
+1
TA = 25°C
DNL (LSB)
+1/2
0
-1/2
-1
0
32,768
65,535
Codes
Figure 15. CS5102A DNL Plot - Ambient Temperature at 25 °C
+1
TA = 138 °C, CAL @ 25 °C
DNL (LSB)
+1/2
0
-1/2
-1
0
32,768
65,535
Codes
Figure 16. CS5102A DNL Plot - Ambient Temperature at 138 °C
DS45F6
27
CS5101A CS5102A
Figure 17. CS5101A DNL Error Distribution
Figure 18. CS5102A DNL Error Distribution
7.2
FFT Tests and Windowing
In the factory, the CS5101A and CS5102A are
tested using Fast Fourier Transform (FFT) techniques to analyze the converters' dynamic performance. A pure sine wave is applied to the device,
and a “time record” of 1024 samples is captured
and processed. The FFT algorithm analyzes the
28
spectral content of the digital waveform and distributes its energy among 512 “frequency bins.” Assuming an ideal sine wave, distribution of energy in
bins outside of the fundamental and DC can only
be due to quantization effects and errors in the
CS5101A and CS5102A.
DS45F6
CS5101A CS5102A
Figure 19. CS5101A FFT (SSC Mode, 1-Channel)
Figure 20. CS5101A FFT (SSC Mode, 1-Channel)
Figure 21. CS5102A FFT (SSC Mode, 1-Channel)
Figure 22. CS5102A FFT (SSC Mode, 1-Channel)
If sampling is not synchronized to the input sine
wave, it is highly unlikely that the time record will
contain an integer number of periods of the input
signal. However, the FFT assumes that the signal
is periodic, and will calculate the spectrum of a signal that appears to have large discontinuities,
thereby yielding a severely distorted spectrum. To
avoid this problem, the time record is multiplied by
a window function prior to performing the FFT. The
window function smoothly forces the endpoints of
the time record to zero, thereby removing the discontinuities.
rithm attenuates the side-lobes to below the noise
floor. Artifacts of windowing are discarded from the
signal-to-noise calculation using the assumption
that quantization noise is white. Averaging the FFT
results from ten time records filters the spectral
variability that can arise from capturing finite time
records without disturbing the total energy outside
the fundamental. All harmonics are visible in the
plots.
The effect of the window in the frequency-domain
is to convolute the spectrum of the window with
that of the actual input.
The quality of the window used for harmonic analysis is typically judged by its highest side-lobe level. A five term window is used in FFT testing of the
CS5101A and CS5102A. This windowing algoDS45F6
As illustrated in Figure 19, the CS5101A typically
provides about 92 dB S/(N+D) and 0.001% THD at
25 °C. Figure 20 illustrates only minor degradation
in performance when the ambient temperature is
raised to 138 °C. Figures 21 and 22 illustrate that
the CS5102A typically yields 92 dB S/(N+D) and
0.001% THD even with a large change in ambient
temperature. Unlike conventional successive-approximation ADC's, the signal-to-noise and dynamic range of the CS5101A and CS5102A are
29
CS5101A CS5102A
not limited by differential nonlinearities (DNL)
caused by calibration errors. Rather, the dominant
noise source is broadband thermal noise which
aliases into the baseband. This white broadband
noise also appears as an idle channel noise of
1/2 LSB (rms).
7.3
Sampling Distortion
Like most discrete sample/hold amplifier designs,
the inherent sample/hold of the CS5101A and
CS5102A exhibits a frequency-dependent distortion due to non-ideal sampling of the analog input
voltage. The calibrated capacitor array used during
conversions is also used to track and hold the analog input signal. The conversion is not performed
on the analog input voltage per se, but is actually
performed on the charge trapped on the capacitor
array at the moment the HOLD command is given.
The charge on the array ideally assumes a linear
relationship to the analog input voltage. Any deviation from this linear relationship will result in con-
30
version errors even if the conversion process
proceeds flawlessly.
At DC, the DAC capacitor array's voltage coefficient dictates the converter's linearity. This variation in capacitance with respect to applied signal
voltage yields a nonlinear relationship between the
charge on the array and the analog input voltage
and places a bow or wave in the transfer function.
This is the dominant source of distortion at low input frequencies (Figures 19, 20, 21, and 22).
The ideal relationship between the charge on the
array and the input voltage can also be distorted at
high signal frequencies due to nonlinearities in the
internal MOS switches. Dynamic signals cause ac
current to flow through the switches connecting the
capacitor array to the analog input pin in the track
mode. Nonlinear on-resistance in the switches
causes a nonlinear voltage drop. This effect worsens with increased signal frequency and slew rate.
This distortion is negligible at signal levels below 10 dB of full scale.
DS45F6
CS5101A CS5102A
C ou nt
81 92
C o unt
8 19 2
61 44
6 14 4
N o ise les s
C on verte r
N o is ele ss
C on ve rter
40 96
4 09 6
C S 510 1 A
CS5102A
20 48
C ou nts :
2 04 8
7F F B
7F F C
0
0
7F F D 7F F E 7F F F
8000
C od e (H e xa de cim al)
989
63 59
844
0
8001
0
C o unts:
Figure 23. CS5101A Histogram Plot of 8192
Conversion Inputs
7.4
7F F D
7 FF E
0
5
7 FF F 8 00 0 (H ) 8 00 1
8 00 2
C od e (H e xa de cim a l)
1 72 7 4 98 8
1 46 7
5
8 00 3
0
Figure 24. CS5102A Histogram Plot of 8192
Conversion Inputs
Noise
An A/D converter's noise can be described like that
of any other analog component. However, the converter's output is in digital form so any filtering of its
noise must be performed in the digital domain. Digitized samples of analog inputs are often considered individual, static snap-shots in time with no
uncertainty or noise. In reality, the result of each
conversion depends on the analog input level and
the instantaneous value of noise sources in the
ADC. If sequential samples from the ADC are
treated as a “waveform”, simple filtering can be implemented in software to improve noise performance with minimal processing overhead.
All analog circuitry in the CS5101A and CS5102A
is wideband in order to achieve fast conversions
and high throughput. Wideband noise in the
CS5101A and CS5102A integrates to 35 µV rms in
unipolar mode (70 µV rms in bipolar mode). This is
approximately 1/2 LSB rms with a 4.5V reference
in both modes. Figure 23 shows a histogram plot of
output code occurrences obtained from 8192 samples taken from a CS5101A in the bipolar mode.
Hexadecimal code 7FFE was arbitrarily selected
and the analog input was set close to code center.
With a noiseless converter, code 7FFE would always appear. The histogram plot of the device has
a “bell” shape with all codes other than 7FFE due
to internal noise. Figure 24 illustrates the noise histogram of the CS5102A.
DS45F6
In a sampled data system all information about the
analog input applied to the sample/hold appears in
the baseband from DC to one-half the sampling
rate. This includes high-frequency components
which alias into the baseband. Low-pass (antialias) filters are therefore used to remove frequency components in the input signal which are above
one-half the sample rate. However, all wideband
noise introduced by the CS5101A and CS5102A
still aliases into the baseband. This “white” noise is
evenly spread from DC to one-half the sampling
rate and integrates to 35 µV rms in unipolar mode.
Noise in the digital domain can be reduced by sampling at higher than the desired word rate and averaging multiple samples for each word.
Oversampling spreads the device's noise over a
wider band (for lower noise density), and averaging applies a low-pass response which filters noise
above the desired signal bandwidth. In general, the
device's noise performance can be maximized in
any application by always sampling at the maximum specified rate of 100 kSps (CS5101A) or
20 kSps (CS5102A) (for lowest noise density) and
digitally filtering to the desired signal bandwidth.
7.5
Aperture Jitter
Track-and-hold amplifiers commonly exhibit two
types of aperture jitter. The first, more appropriately termed “aperture window”, is an input-voltagedependent variation in the aperture delay. Its signal dependency causes distortion at high frequen31
CS5101A CS5102A
cies. The proprietary architecture of the CS5101A
and CS5102A avoids applying the input voltage
across a sampling switch, thus avoiding any “aperture window” effects. The second type of aperture
jitter, due to component noise, assumes a random
nature. With only 100 ps peak-to-peak aperture jitter, the CS5101A and CS5102A can process fullscale signals up to 1/2 the throughput frequency
without significant errors due to aperture jitter.
90
Pow er Supply Rejection (dB)
80
70
60
50
40
30
20
1 kH z
10 kH z
1 0 0 kH z
1 MHz
Pow er Sup ply R ipple Frequency
Figure 25. Power Supply Rejection
7.6
Power Supply Rejection
The power supply rejection performance of the
CS5101A and CS5102A is enhanced by the onchip self-calibration and an “auto-zero” process.
Drifts in power supply voltages at frequencies less
than the calibration rate have negligible effect on
the device's accuracy. This is because the
CS5101A and CS5102A adjust their offset to within
a small fraction of an LSB during calibration. Above
the calibration frequency the excellent power sup-
32
ply rejection of the internal amplifiers is augmented
by an auto-zero process. Any offsets are stored on
the capacitor array and are effectively subtracted
once conversion is initiated. Figure 25 shows power supply rejection of the CS5101A and CS5102A
in the bipolar mode with the analog input grounded
and a 300 mV p-p ripple applied to each supply.
Power supply rejection improves by 6 dB in the unipolar mode.
DS45F6
CS5101A CS5102A
SCKMOD
TEST
26
VD1
27
RST
2
SLEEP
CLKIN
3
28
XOUT
4
8. PIN DESCRIPTIONS
STBY
5
25
VA+
DGND
6
24
AIN2
VD+
7
23
VA-
TRK1
8
22
AGND
21
REFBUF
TRK2
CS5101A
CS5102A
(TOP VIEW)
9
15
16
17
18
CODE
BP/UP
OUTMOD
AIN1
SDATA
19
14
11
SCLK
SSH/SDL
13
VREF
CH1/2
20
12
10
HOLD
CRS/FIN
Figure 26. CS5101A & CS5102A 28-pin PLCC Pinout
8.1
Power Supply Connections
VD+ - Positive Digital Power, PIN 7
Positive digital power supply. Nominally +5 volts.
VD- - Negative Digital Power, PIN 1.
Negative digital power supply. Nominally -5 volts.
DGND - Digital Ground, PIN 6.
Digital ground [reference].
VA+ - Positive Analog Power, PIN 25.
Positive analog power supply. Nominally +5 volts.
VA- - Negative Analog Power, PIN 23.
Negative analog power supply. Nominally -5 volts.
AGND - Analog Ground, PIN 22.
Analog ground reference.
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33
CS5101A CS5102A
8.2
Oscillator
CLKIN - Clock Input, PIN 3.
All conversions and calibrations are timed from a master clock which can be externally supplied by
driving CLKIN [this input TTL-compatible, CMOS recommended].
XOUT - Crystal Output, PIN 4.
The master clock can be generated by tying a crystal across the CLKIN and XOUT pins. If an external
clock is used, XOUT must be left floating.
8.3
Digital Inputs
HOLD - Hold, PIN 12.
A falling transition on this pin sets the CS5101A or CS5102A to the hold state and initiates a
conversion. This input must remain low for at least 1/tclk + 20 ns. When operating in Free Run Mode,
HOLD is disabled, and should be tied to DGND or VD+.
CRS/FIN - Coarse Charge/Fine Charge Control, PIN 10.
When brought high during acquisition time, CRS/FIN forces the CS5101A or CS5102A into coarse
charge state. This engages the internal buffer amplifier to track the analog input and charges the
capacitor array much faster, thereby allowing the CS5101A or CS5102A to track high-slewing signals. In
order to get an accurate sample, the last coarse charge period before initiating a conversion (bringing
HOLD low) must be longer than 0.75µs (CS5101A) or 3.75µs (CS5102A). Similarly, the fine charge
period immediately prior to conversion must be at least 1.125µs (CS5101A) or 5.625µs (CS5102A). The
CRS/FIN pin must be low during conversion time. For normal operation, CRS/FIN should be tied low, in
which case the CS5101A or CS5102A will automatically enter coarse charge for 6 clock cycles
immediately after the end of conversion.
CH1/2 - Left/Right Input Channel Select, PIN 13.
Status at the end of a conversion cycle determines which analog input channel will be acquired for the
next conversion cycle. When in Free Run Mode, CH1/2 is an output, and will indicate which channel is
being sampled during the current acquisition phase.
SLEEP - Sleep, PIN 28.
When brought low causes the CS5101A or CS5102A to enter a power-down state. All calibration
coefficients are retained in memory, so no recalibration is needed after returning to the normal operating
mode. If using the internal crystal oscillator, time must be allowed after SLEEP returns high for the
crystal oscillator to stabilize. SLEEP should be tied high for normal operation.
CODE - 2's Complement/Binary Coding Select, PIN 16.
Determines whether output data appears in 2's complement or binary format. If high, 2's complement; if
low, binary.
BP/UP - Bipolar/Unipolar Input Range Select, PIN 17.
When low, the CS5101A or CS5102A accepts a unipolar input range from AGND to VREF. When high,
the CS5101A or CS5102A accepts bipolar inputs from -VREF to +VREF.
SCKMOD - Serial Clock Mode Select, PIN 27.
When high, the SCLK pin is an input; when low, it is an output. Used in conjunction with OUTMOD to
select one of 4 output modes described in Table 2.
OUTMOD - Output Mode Select, PIN 18.
The status of SCKMOD and OUTMOD determine which of four output modes is utilized. The four
modes are described in Table 2.
34
DS45F6
CS5101A CS5102A
SCLK - Serial Clock, PIN 14.
Serial data changes status on a falling edge of this input, and is valid on a rising edge. When SCKMOD
is high SCLK acts as an input. When SCKMOD is low the CS5101A or CS5102A generates its own
serial clock at ¼ the master clock frequency and SCLK is an output.
RST - Reset, PIN 2.
When taken low, all internal digital logic is reset. Upon returning high, a full calibration sequence is
initiated which takes 11,528,160 CLKIN cycles (CS5101A) or 2,882,040 CLKIN cycles (CS5102A) to
complete. During calibration, the HOLD input will be ignored. The CS5101A or CS5102A must be reset
at power-up for calibration, however; calibration is maintained during SLEEP mode, and need not be
repeated when resuming normal operation.
8.4
Analog Inputs
AIN1, AIN2 - Channel 1 and 2 Analog Inputs, PINS 19 and 24.
Analog input connections for the left and right input channels.
VREF - Voltage Reference, PIN 20.
The analog reference voltage which sets the analog input range. In unipolar mode VREF sets full-scale;
in bipolar mode its magnitude sets both positive and negative full-scale.
8.5
Digital Outputs
STBY - Standby (Calibrating), PIN 5.
Indicates calibration status after reset. Remains low throughout the calibration sequence and returns
high upon completion.
SDATA - Serial Output, PIN 15.
Presents each output data bit on a falling edge of SCLK. Data is valid to be latched on the rising edge
of SCLK.
SSH/SDL - Simultaneous Sample/Hold / Serial Data Latch, PIN 11.
Used to control an external sample/hold amplifier to achieve simultaneous sampling between channels.
In FRN and SSC modes (SCLK is an output), this signal provides a convenient latch signal which forms
the 16 data bits. This can be used to control external serial to parallel latches, or to control the serial
port in a DSP.
TRK1, TRK2 - Tracking Channel 1, Tracking Channel 2, PINS 8 and 9.
Falls low at the end of a conversion cycle, indicating the acquisition phase for the corresponding
channel. The TRK1 or TRK2 pin will return high at the beginning of conversion for that channel.
8.6
Analog Outputs
REFBUF - Reference Buffer Output, PIN 21.
Reference buffer output.
8.7
Miscellaneous
TEST - Test, PIN 26.
Allows access to the CS5101A's and the CS5102A's test functions which are reserved for factory use.
Must be tied to VD+.
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CS5101A CS5102A
9. PARAMETER DEFINITIONS
Linearity Error
The deviation of a code from a straight line passing through the endpoints of the transfer function after
zero- and full-scale errors have been accounted for. “Zero-scale” is a point 1/2 LSB below the first code
transition and “full-scale” is a point 1/2 LSB beyond the code transition to all ones. The deviation is measured from the middle of each particular code. Units in % Full-Scale.
Differential Linearity
Minimum resolution for which no missing codes is guaranteed. Units in bits.
Full-scale Error
The deviation of the last code transition from the ideal (VREF-3/2 LSBs). Units in LSBs.
Unipolar Offset
The deviation of the first code transition from the ideal (1/2 LSB above AGND) when in unipolar mode
(BP/UP low). Units in LSBs.
Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100...000) from the ideal (1/2 LSB below AGND)
when in bipolar mode (BP/UP high). Units in LSBs.
Bipolar Negative Full-scale Error
The deviation of the first code transition from the ideal when in bipolar mode (BP/UP high). The ideal is
defined as lying on a straight line which passes through the final and mid-scale code transitions. Units in
LSBs.
Signal-to-peak Harmonic or Noise
The ratio of the rms value of the signal to the rms value of the next largest spectral component below the
Nyquist rate (excepting DC). This component is often an aliased harmonic when the signal frequency is
a significant proportion of the sampling rate. Expressed in decibels.
Total Harmonic Distortion
The ratio of the rms sum of all harmonics to the rms value of the signal. Units in percent.
Signal-to-(Noise + Distortion)
The ratio of the rms value of the signal to the rms sum of all other spectral components below the Nyquist
rate (excepting DC), including distortion components. Expressed in decibels.
Aperture Time
The time required after the hold command for the sampling switch to open fully. Effectively a sampling
delay which can be nulled by advancing the sampling signal. Units in nanoseconds.
Aperture Jitter
The range of variation in the aperture time. Effectively the “sampling window” which ultimately dictates the
maximum input signal slew rate acceptable for a given accuracy. Units in picoseconds.
36
DS45F6
CS5101A CS5102A
10. PACKAGE DIMENSIONS
28L PLCC PACKAGE DRAWING
e
D2/E2
E1 E
B
A1
D1
D
DIM
A
A1
B
D
D1
D2
E
E1
E2
e
MIN
0.165
0.090
0.013
0.485
0.450
0.390
0.485
0.450
0.390
0.040
A
INCHES
NOM
MAX
MIN
0.1725
0.180
4.191
0.105
0.120
2.286
0.017
0.021
0.3302
0.490
0.495
12.319
0.453
0.456
11.430
0.410
0.430
9.906
0.490
0.495
12.319
0.453
0.456
11.430
0.410
0.430
9.906
0.050
0.060
1.016
JEDEC # : MS-047 AA-AF
MILLIMETERS
NOM
4.3815
2.667
0.4318
12.446
11.506
10.414
12.446
11.506
10.414
1.270
MAX
4.572
3.048
0.533
12.573
11.582
10.922
12.573
11.582
10.922
1.524
Controlling Dimension is Inches
Figure 27. 28-Pin PLCC Mechanical Drawing
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CS5101A CS5102A
11. ORDERING INFORMATION
Model
CS5101A-JL8
CS5101A-JL8Z (lead free)
CS5101A-BL8
CS5101A-BL8Z (lead free)
CS5102A-JL
CS5102A-JLZ (lead free)
CS5102A-BL
CS5102A-BLZ (lead free)
Linearity
Temperature
0.003
0 to +70 °C
0.002
Conversion Time
Throughput
8.13 µs
100 kSps
Package
-40 to +85 °C
28-pin PLCC
0.003
0 to +70 °C
40 µs
0.0015
20 kSps
-40 to +85 °C
12. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number
Peak Reflow Temp
CS5101A-JL8
225 °C
CS5101A-JL8Z (lead free)
260 °C
CS5101A-BL8
225 °C
CS5101A-BL8Z (lead free)
260 °C
CS5102A-JL
225 °C
CS5102A-JLZ (lead free)
260 °C
CS5102A-BL
225 °C
CS5102A-BLZ (lead free)
260 °C
MSL Rating*
Max Floor Life
2
365 Days
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
38
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CS5101A CS5102A
13. REVISIONS
Revision
Date
Changes
F1
September 2004
F2
October 2004
F3
June 2005
Minor edits, added lead-free device ordering information
F4
July 2005
removed obsolete packages, corrected lead-free device information
Initial Release
Corrected table heading on Page 6.
F5
August 2005
Added MSL, reflow temp, & floor life specifications.
F6
January 2006
Corrected Linearity Error mislabeled in Characteristics & Specifications as “Differential Input Range”.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
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DS45F6
39