BOARDCOM APDS-9250 Digital rgb, ir and ambient light sensor Datasheet

APDS-9250
Digital RGB, IR and Ambient Light Sensor
Data Sheet
Description
Features
The APDS-9250 device uses 4 individual channels of red,
green, blue, and IR (RGB+IR) in a specially designed matrix
arrangement. This allows the device to have optimal
angular response and accurate RGB spectral response
with high lux accuracy over various light sources.
APDS-9250 supports the I2C interface and has a programmable interrupt controller that frees up micro-controller
resources.
• Colour and Ambient Light Sensing (CS-RGB and ALS)
- Accuracy of Correlated Color Temperature (CCT)
- Individual channels for Red, Green, Blue and Infared
- Approximates Human Eye Response with Green
Channel
- Red, Green, Blue, Infrared and ALS Sensing
- High Sensitivity in low lux condition – Ideally suited
for Operation Behind Dark Glass
- Wide Dynamic Range: 18,000,000: 1
- Up to 20-Bit Resolution
• Power Management
- Low Active Current – 130 μA typical
- Low Standby Current – 1μA typical
• I2C-bus Fast Mode Compatible Interface
- Up to 400 kHz (I2C Fast-Mode)
- Dedicated Interrupt Pin
• Small Package L 2.0 × W 2.0 × H 0.65 mm
The device detects light intensity under a variety of
lighting conditions and through a variety of attenuation materials, including dark glass. APDS-9250 could be
configured as Ambient Light Sensor and RGB+IR Sensor.
The color-sensing feature is useful in applications such as
LED RGB backlight control, solid-state lighting, reflected
LED color sampler, or fluorescent light color temperature
detection. The integrated IR blocking filter makes this
device an excellent ambient light sensor and color temperature monitor sensor together with the temperature
compensation that allows output to have less variation
over the temperature.
Ordering Information
Part Number
Packaging
Quantity
APDS-9250
Tape & Reel
5000 per reel
Applications
• OLED Display Control
• RGB LED Backlight Control
• Ambient Light Color Temperature Sensing
Functional Block Diagram
VDD
GND
Interrupt
RGB + IR Control
INT
SCL
Upper Threshold
Lower Threshold
GREEN ADC/Data
BLUE ADC/Data
I2C Interfacing
RED ADC/Data
SDA
IR ADC/Data
Description:
I/O Pins Configuration
The APDS-9250 device contains multiple photodiodes for
Light Sensor (R, G, B, IR channel) that are designed in a
matrix placement to achieve optimal angular response at
the fall of incident light angle.
Pin
Name
Type
Description
1
SCL
I
I2C Serial Clock Input Terminal –
Clock Signal for I2C Serial Data
2
SDA
I/O
Serial Data I/O for I2C
The device provides on-chip multiple diodes, ADCs, state
machine, non-volatile memory and an I2C interface.
3
VDD
Supply
Power Supply Voltage
4
INT
O
Interrupt – Open Drain
Integration of all color sensing channels occurs simultaneously. Upon completion of the conversion cycle, the
conversion result is transferred to the corresponding data
registers. Communication with the device is accomplished
through a fast (up to 400 kHz), two-wire I2C serial bus for
easy connection to a microcontroller or embedded controller.
5
NC
6
GND
The APDS-9250 provides a separate pin for interrupts. When interrupts are enabled and a preset value
is exceeded, the interrupt pin is asserted and remains
asserted until cleared by the controlling firmware. The
interrupt feature simplifies and improves system efficiency by eliminating the need to poll a sensor for a light
intensity. An interrupt is generated after completion of
new conversion of the light sensor channels where the
light sensor interrupt source can work on any of the Red,
Green, Blue, IR channels. Additionally, a programmable
interrupt persistence feature allows the user to determine
how many consecutive exceeded thresholds are necessary
to trigger an interrupt.
2
No Connect
Ground
Power Supply Ground. All
Voltages are referenced to GND
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)†
Parameter
Symbol
Min.
Max.
Units
Power Supply Voltage [1]
VDD
VI2C
Tstg
-0.5
−40
3.8
3.8
85
V
V
°C
Max Voltage on SCL, SDA, INT pads
Storage Temperature Range
Conditions
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Note 1. All voltages are with respect to GND.
Recommended Operating Conditions
Parameter
Symbol
Min.
Operating Ambient Temperature
Supply voltage
Supply Voltage Accuracy, VDD
total error including transients
TA
VDD
-40
1.7
-3
Typ.
Max.
Units
85
3.6
3
°C
V
%
Max
Units
Test Conditions
2
µA
µA
VDD=2.8V, Gain Mode 3
In Standby Mode. No
active I2C communication
VDD
0.4
0.4
5
V
V
V
µA
Operating Characteristics, VDD = 2.8 V, TA = 25°C (unless otherwise noted)
Parameter
Symbol
Active Mode Current
Standby Current
ICS
ISTBY
SCL, SDA Input High Voltage
SCL, SDA Input Low Voltage
VOL INT, Output Low Voltage
ILEAK Leakage Current, SDA, SCL, INT Pins
VIH
VIL
VOL
ILEAK
Min
Typ
130
1
1.5
0
0
-5
Optical Characteristics, VDD = 2.8 V, TA = 25°C (unless otherwise noted)
Parameter
Irradiance
Response
Test
Condition
λ = 465
λ = 525
λ = 625
λ = 850
RED Channel
Min.
Max.
0
3
80
0
5
10
120
3
Green Channel
Min.
Max.
6
80
18
0
17
120
33
3
Blue Channel
Min.
Max.
80
10
0
0
120
30
3
3
IR Channel
Min.
Max.
0
0
0
80
4
3
3
120
Notes:
1. The percentage shown represents the ratio of the respective red, green, or blue channel value to the IR channel value.
2. The 465 nm input irradiance is supplied by an InGaN light-emitting diode with the following characteristics:
dominant wavelength _D = 465 nm, spectral halfwidth __½ = 22 nm.
3. The 525 nm input irradiance is supplied by an InGaN light-emitting diode with the following characteristics:
dominant wavelength _D = 525 nm, spectral halfwidth __½ = 35 nm.
4. The 625 nm input irradiance is supplied by a AlInGaP light-emitting diode with the following characteristics:
dominant wavelength _D = 625 nm, spectral halfwidth __½ = 15 nm.
5. The 850 nm input irradiance is supplied by a AlInGaP light-emitting diode with the following characteristics:
dominant wavelength _D = 850 nm, spectral halfwidth __½ = 40 nm.
RGB Characteristics, VDD = 2.8 V, TA = 25°C (unless otherwise noted)
Parameter
Min.
Dark Count
ADC Integration Time
Full Scale ADC Counts Per Step
Full Scale ADC Count Value
0
2.97
3
Typ.
3.125
8192
Max.
Units
Test Conditions
3
3.28
counts
ms
counts
counts
13 bit
18 bit, 100ms, G=1x
262,143
Unit
%
ALS Characteristics, VDD = 2.8 V, TA = 25°C (unless otherwise noted)
Symbol
Peak Wavelength
Min Integration Time
λP
Tintmin1
Tintmin2
Tintmax
RESALS
Max Integration Time
Output Resolution
ADC Count Value
Min
13
Typ
550
3.125
50
400
18
1000
Max
20
NORMALIZED RESPONSIVITY
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
ANGULAR DISPLACEMENT (DEGREE)
0.5
0.4
0.3
0.2
0.1
0
300
0.9
0.8
14000
0.7
6000
900
1000
1100
0.4
0.3
2000
0.1
Figure 3. ALS Sensor LUX vs Meter LUX using White Light
600
700
800
WAVELENGTH (nm)
0.5
0.2
2000 4000 6000 8000 10000 12000 14000 16000 18000 20000
Meter LUX
500
0.6
4000
0
400
Figure 2. Normalized PD Spectral Response
16000
0
4
0.6
18000
8000
IR
RED
GREEN
BLUE
0.7
1.0
10000
With 50/60Hz rejection
With 50/60Hz rejection
Programmable
λ= 530nm, 50ms, Gain=3x, Ee=59uW/cm2
0.8
20000
12000
Test Conditions
nm
ms
ms
ms
bit
count
1
Avg Sensor LUX
Avg Sensor LUX
Figure 1. Normalized ALS PD Angular Response
Units
0.9
RELATIVE RESPONSE
Parameter
0.0
0
0.1
0.2
0.3
0.4 0.5 0.6
Meter LUX
0.7
Figure 4. ALS Sensor LUX vs Meter LUX using White Light
0.8
0.9
1
2.0
900
1.8
800
1.6
Normalized IDD @ 2.8V , 25°C
1000
AVg Sensor LUX
700
600
500
400
300
200
100
0
1.0
0.8
0.6
0.4
0
100
200
300
400
500 600
Meter LUX
700
800
900 1000
0.0
1.6
2.0
1.10
1.8
1.08
1.6
1.06
1.4
1.04
1.2
1.0
0.8
0.6
0
20
40
TEMPERATURE (°C)
Figure 7. Normalized IDD vs Temperature
60
2.6 2.8
VDD (V)
3.0
3.2
3.4
3.6
3.8
80
100
Gain 1X
Gain 3X
Gain 6X
Gain 9X
Gain 18X
0.96
0.92
-20
2.4
0.98
0.2
-40
2.2
1.00
0.94
-60
2.0
1.02
0.4
0.0
1.8
Figure 6. Normalized IDD vs VDD
RELATIVE DEVIATION
Normalized IDD @ 2.8V, 25°C
1.2
0.2
Figure 5. ALS Sensor LUX vs Meter LUX using Incandescent Light
5
1.4
0.90
-60
-40
-20
0
20
40
TEMPERATURE (°C)
Figure 8. ALS vs Temperature @ 1000 LUX (White LED)
60
80
100
System State Machine
Light Sensor Operation
Start Up after Power-On or Software Reset
Light Sensor (LS) measurements can be activated by
setting the LS_EN bit to 1 in the MAIN_CTRL register.
The main state machine is set to “Start State” during
power-on or software reset. As soon as the reset is released,
the internal oscillator is started and the programmed I²C
address and the trim values are read from the internal non
volatile memory (NVM) trimming data block. The device
enters Standby Mode as soon as the Idle State is reached.
NOTE: As long as the I²C address has not yet been read,
the device will respond with NACK to any I²C command
and ignore any request to avoid responding to a wrong
I²C address.
Standby Mode
Standby Mode is the default mode after power-up. In
this state, the oscillator, all internal support blocks, and
the ADCs are switched off but I²C communication is fully
supported.
In Light Sensor mode the user can select to activate either
ALS or CS operation mode. ALS mode is activated by
setting CS_Mode bit to 0 while CS mode is activated by
CS_Mode bit set to 1 in the MAIN_CTRL register.
As soon as Light Sensor become activated through I²C
command, the internal support blocks are powered on.
Once the voltages and currents are settled (typically after
5ms), the state machine checks for trigger events from
a measurement scheduler to start the LS conversions
according to the selected measurement repeat rates.
Once LS_EN is changed back to 0, a conversion running on
the respective sensor will be completed and the relevant
ADCs and support blocks will move to standby mode
thereafter.
Light Sensor Interrupt
The LS interrupt is enabled by LS_INT_EN=1. It can
function as either threshold triggered (LS_VAR_MODE=0)
or variance trigged (LS_VAR_MODE=1). The LS interrupt
source generator can work on any of the four LS channels
(R, G, B, IR). The LS interrupt source is selected by the LS_
INT_SEL bits in the INT_CFG register.
Start
NVM Read
Idle
LS_EN==0
Wait for OSC Power Up
Check CS
LS_EN==1
CS_MODE==1
Do CS Conversion
LS_EN==1
CS_MODE==0
Do ALS Conversion
The Light Sensor threshold interrupt is enabled with
LS_INT_EN = 1 and LS_VAR_MODE = 0. It is set when
the data of the selected LS_DATA input register (LS_RED,
LS_GREEN, LS_BLUE, LS_IR) is above the upper or below
the lower threshold for a specified number of consecutive
measurements.
The Light Sensor variance interrupt is enabled with LS_
INT_EN = 1 and LS_VAR_MODE = 1. It is set when the
absolute value of the difference between the previous
and current LS_DATA data value is above the decoded LS
variance threshold for a specified number of consecutive
measurements.
I²C Protocol
Interface and control of the APDS-9250 is accomplished
through an I2C serial compatible interface (standard or fast
mode) to a set of registers that provide access to device
control functions and output data. The device supports
a single slave address of 0x52 hex using 7 bit addressing
protocol. (Contact factory for other addressing options.)
6
I²C Register Read
I²C Register Write
The registers can be read individually or in block read
mode. When two or more bytes are read in block read
mode, reserved register addresses are skipped and the
next valid address is referenced. If the last valid address
has been reached, but the master continues with the
block read, the address counter in the device will not roll
over and the device returns 00HEX for every subsequent
byte read.
The device registers can be written to individually or in
block write mode. When two or more bytes are written
in block write mode, reserved registers and read-only
registers are skipped. The transmitted data is automatically applied to the next writable register. If a register
includes read (R) and read/write (RW) bits, the register is
not skipped. Data written to read-only bits are ignored.
The block read operation is the only way to ensure correct
data read out of multi-byte registers and to avoid splitting
of results with HIGH and LOW bytes originating from
different conversions. During block read access on LS and
PS result registers, the result update is blocked.
If a read access is started on an address belonging to a
non-readable register, the device will return NACK until
the I2C™ operation is ended.
Read operations must follow the timing diagram shown
below.
If the last valid address of the device address range is
reached but the master attempts to continue the block
write operation, the address counter of the device will not
roll over. The device will return NACK for every following
byte sent by the master until the I2C™ operation is ended.
If a write access is started on an address belonging to a
non-writeable register, the device will return NACK until
the I2C™ operation is ended.
Write operations must follow the timing diagram shown
below.
I2C Register Read Timing Diagram
Register Read (I2CTM Read)
S
Slave Addr
0
7 Bit
A
Slave Addr
Address
A S
7 Bit
8 Bit
Write
1
A
Data
N
8 Bit
P
Read
From Master to Slave
S Start Condition
From Slave to Master
P Stop Condition
A Acknowledge (ACK)
Register Block Read (I2CTM Read)
S
Slave Addr
0
7 Bit
A
Address
Slave Addr
A S
8 Bit
7 Bit
Write
1
A
Data
8-Bit
Data
8-Bit
A
A
…
Data
N
8-Bit
P
N Not Acknowledge (NACK)
Read
I2C Register Write Timing Diagram
Register Write (I2CTM Write)
S
Slave Addr
0
7 Bit
A Address
A
Data
8-Bit
A
From Master to Slave
P
From Slave to Master
Write
Register Block Write (I2CTM Write)
S
Slave Addr
0
7 Bit
Write
7
A Address
A
S Start Condition
P Stop Condition
A Acknowledge (ACK)
Data
8-Bit
A
Data
8-Bit
A
…
Data
8-Bit
A
P
N Not Acknowledge (NACK)
I2C Interface – Bus Timing
SDA
t SUDAT
t LOW
t HDSTA
t BUS
SCL
t HDSTA
t HDDAT
t HIGH
t SUSTO
t SUSTA
Bus Timing Characteristics
Parameter
Symbol
Standard Mode
Fast Mode
Units
Maximum SCL Clock Frequency
fSCL
100
400
kHz
Minimum START Condition Hold Time Relative to SCL Edge
tDSTA
4
µs
Minimum SCL Clock Low Width
tLOW
4.7
µs
Minimum SCL Clock High Width
tHIGH
4
µs
Minimum START Condition Setup Time Relative to SCL Edge
tSUSTA
4.7
µs
Minimum Data Hold Time on SDA Relative to SCL Edge
tHDDAT
0
Minimum Data Setup Time on SDA Relative to SCL Edge
tSUDAT
0.1
Minimum STOP Condition Setup Time on SCL
tSUSTO
4
µs
Minimum Bus Free Time Between Stope Condition and Start Condition
tBUS
4.7
µs
8
µs
0.1
µs
Register set:
The APDS-9250 is controlled and monitored by data registers and a command register accessed through the serial
interface. These registers provide for a variety of control functions and can be read to determine results of the ADC
conversions.
Address
Type
Name
Description
Reset Value
00HEX
RW
MAIN_CTRL
LS operation mode control, SW reset
00HEX
04HEX
RW
LS_MEAS_RATE
LS measurement rate and resolution in active mode
22HEX
05HEX
RW
LS_GAIN
LS analog gain range
01HEX
06HEX
R
PART_ID
Part number ID and revision ID
B2HEX
07HEX
R
MAIN_STATUS
Power-on status, interrupt status, data status
20HEX
0AHEX
R
LS_DATA_IR_0
IR ADC measurement data - LSB
00HEX
0BHEX
R
LS_DATA_IR_1
IR ADC measurement data
00HEX
0CHEX
R
LS_DATA_IR_2
IR ADC measurement data - MSB
00HEX
0DHEX
R
LS_DATA_GREEN_0
Green ADC measurement data - LSB
00HEX
0EHEX
R
LS_DATA_GREEN_1
Green ADC measurement data
00HEX
0FHEX
R
LS_DATA_GREEN_2
Green ADC measurement data - MSB
00HEX
10HEX
R
LS_DATA_BLUE_0
Blue ADC measurement data - LSB
00HEX
11HEX
R
LS_DATA_BLUE_1
Blue ADC measurement data
00HEX
12HEX
R
LS_DATA_BLUE_2
Blue ADC measurement data - MSB
00HEX
13HEX
R
LS_DATA_RED_0
Red ADC measurement data - LSB
00HEX
14HEX
R
LS_DATA_RED_1
Red ADC measurement data
00HEX
15HEX
R
LS_DATA_RED_2
Red ADC measurement data - MSB
00HEX
19HEX
RW
INT_CFG
Interrupt configuration
10HEX
1AHEX
RW
INT_PERSISTENCE
Interrupt persist setting
00HEX
21HEX
RW
LS_THRES_UP_0
LS interrupt upper threshold, LSB
FFHEX
22HEX
RW
LS_THRES_UP_1
LS interrupt upper threshold
FFHEX
23HEX
RW
LS_THRES_UP_2
LS interrupt upper threshold, MSB
0FHEX
24HEX
RW
LS_THRES_LOW_0
LS interrupt lower threshold, LSB
00HEX
25HEX
RW
LS_THRES_LOW_1
LS interrupt lower threshold
00HEX
26HEX
RW
LS_THRES_LOW_2
LS interrupt lower threshold, MSB
00HEX
27HEX
RW
LS_THRES_VAR
LS interrupt variance threshold
00HEX
9
MAIN_CTRL
Default Value : 00HEX
7
6
5
4
3
2
1
0
0
0
0
SW_Reset
0
CS_Mode
LS_EN
0
FIELD
BIT
DESCRIPTION
SW_Reset
4
1 = Reset will be triggered
CS_Mode
2
0 = ALS, IR and compensation channels activated
1 = All RGB+IR + compensation channels activated
LS_EN
1
1 = Light sensor active
0 = Light sensor standby
0X00
Writing to this register stops the ongoing measurements and starts new measurements (depends on the enable bit).
LS_MEAS_RATE
Default Value : 22HEX
7
6
0
5
4
LS Resolution/Bit Width
3
0
FIELD
BIT
DESCRIPTION
LS
Resolution/Bit Width
6:4
000 : 20 bit – 400ms
001 : 19 bit – 200ms
010 : 18 bit – 100ms (default)
011 : 17 bit – 50ms
100 : 16 bit – 25ms
101 : 13 bit – 3.125ms
110 : Reserved
111 : reserved
LS
Measurement Rate
2:0
000 – 25ms
001 – 50ms
010 – 100ms (default)
011 – 200ms
100 – 500ms
101 – 1000ms
110 – 2000ms
111 – 2000ms
2
1
LS Measurement Rate
0
0X04
When the measurement repeat rate is programmed to be faster than possible for the specified ADC measurement time,
the repeat rate will be lower than programmed (maximum speed).
Writing to this register stops the ongoing measurement and starts new measurements (depending on the respective
bits)
10
LS_GAIN
Default Value : 01HEX
7
6
5
4
3
0
0
0
0
0
FIELD
BIT
DESCRIPTION
Gain Range
2:0
000 : Gain 1
001 : Gain 3
010 : Gain 6
011 : Gain 9
100 : Gain 18
2
1
0
Gain Range
0X05
The channels of the light sensor always run on the same gain range setting. Sensitivity settings correlate between the
channels. Result output in Lux is available from ALS/green channel.
Writing to this register stops the ongoing measurement and starts new measurements (depending on the respective
bits)
PART_ID
Default Value : B2HEX
7
6
5
4
3
2
Part ID
1
0
Revision ID
FIELD
BIT
DESCRIPTION
Part Number ID
7:4
Part number ID
Revision ID
3:0
Revision ID of the component.
0X06
MAIN_STATUS
Default Value : 20HEX
7
6
5
4
3
2
1
0
0
0
Power
On
Status
LS
Interrupt
Status
LS Data
Status
0
0
0
FIELD
BIT
DESCRIPTION
Power On Status
5
1 = Part went through a power-up event, either because the part
was turned on or because there was power supply disturbance.
All interrupt threshold settings in the registers have been reset
to power-on default states and should be examined if necessary.
The flag is cleared after the register is read.
LS Interrupt Status
4
0 : Interrupt condition not fulfilled (default)
1 : Interrupt condition fulfilled (cleared after read)
LS Data Status
3
0 : old data, already read (default)
1 : new data, not yet read (cleared after read)
11
0X07
LS_DATA_IR
Default Value : 00HEX, 00HEX, 00HEX
7
0
6
0
5
4
0
3
2
1
0
LS_DATA_IR_0 [7:0]
0X0A
LS_DATA_IR_1 [15:8]
0X0B
0
LS_DATA_IR_2 [19:16]
0X0C
IR channel output data (unsigned integer, 13 to 20 bit, LSB aligned)
The IR channel output is already temperature compensated internally:
LS_DATA_IR – (IRint – LS_DATA_COMP)
When an I²C™ read operation is active and points to an address in the range 07HEX to 18HEX, all registers in this range
are locked until the I²C™ read operation is completed or this address range is left.
This guarantees that the data in the registers comes from the same measurement even if an additional measurement
cycle ends during the read operation. New measurement data is stored into temporary registers and the actual LS_DATA
registers are updated as soon as there is no on-going I²C™ read operation to the address range 07HEX to 18HEX.
Reg 0AHEX
Bit[7:0] IR diode data least significant data byte
Reg 0BHEX
Bit[7:0] IR diode data intervening data byte
Reg 0CHEX
Bit[3:0] IR diode data most significant data byte
LS_DATA_GREEN
Default Value : 00HEX, 00HEX, 00HEX
7
6
5
4
3
2
1
LS_DATA_GREEN_0 [7:0]
0X0D
LS_DATA_GREEN_1 [15:8]
0
0
0
0
0
0X0E
LS_DATA_GREEN_2 [19:16]
0X0F
ALS/CS Green channel digital output data.
The channel output is already temperature compensated internally:
LS_DATA_GREEN = (Greenint – LS_DATA_COMP)
When an I²C™ read operation is active and points to an address in the range 07HEX to 18HEX, all registers in this range
are locked until the I²C™ read operation is completed or this address range is left.
This guarantees that the data in the registers comes from the same measurement even if an additional measurement
cycle ends during the read operation. New measurement data is stored into temporary registers and the actual LS_DATA
registers are updated as soon as there is no on-going I²C™ read operation to the address range 07HEX to 18HEX.
Reg 0DHEX
Bit[7:0] ALS / Green diode data least significant data byte
Reg 0EHEX
Bit[7:0] ALS / Green diode data intervening data byte
Reg 0FHEX
Bit[3:0] ALS / Green diode data most significant data byte
12
LS_DATA_BLUE
Default Value : 00HEX, 00HEX, 00HEX
7
0
6
0
5
0
4
3
2
1
0
LS_DATA_BLUE_0 [7:0]
0X10
LS_DATA_BLUE_1 [15:8]
0X11
0
LS_DATA_BLUE_2 [19:16]
0X12
CS Blue channel output data.
The channel output is already temperature compensated internally:
LS_DATA_BLUE = (Blueint – LS_DATA_COMP)
When an I²C™ read operation is active and points to an address in the range 07HEX to 18HEX, all registers in this range
are locked until the I²C™ read operation is completed or this address range is left.
This guarantees that the data in the registers comes from the same measurement even if an additional measurement
cycle ends during the read operation. New measurement data is stored into temporary registers and the actual LS_DATA
registers are updated as soon as there is no on-going I²C™ read operation to the address range 07HEX to 18HEX.
Reg 10HEX
Bit[7:0] Blue diode data least significant data byte
Reg 11HEX
Bit[7:0] Blue diode data intervening data byte
Reg 12HEX
Bit[3:0] Blue diode data most significant data byte
LS_DATA_RED
Default Value : 00HEX, 00HEX, 00HEX
7
6
5
4
3
2
1
LS_DATA_RED_0 [7:0]
0X13
LS_DATA_RED_1 [15:8]
0
0
0
0
0
0X14
LS_DATA_RED_2 [19:16]
0X15
The channel output is already temperature compensated internally:
LS_DATA_RED = (Redint – LS_DATA_COMP)
When an I²C™ read operation is active and points to an address in the range 07HEX to 18HEX, all registers in this range
are locked until the I²C™ read operation is completed or this address range is left.
This guarantees that the data in the registers comes from the same measurement even if an additional measurement
cycle ends during the read operation. New measurement data is stored into temporary registers and the actual LS_DATA
registers are updated as soon as there is no on-going I²C™ read operation to the address range 07HEX to 18HEX.
Reg 13HEX
Bit[7:0] Red diode data least significant data byte
Reg 14HEX
Bit[7:0] Red diode data intervening data byte
Reg 15HEX
Bit[3:0] Red diode data most significant data byte
13
INT_CFG
Default Value : 10HEX
7
6
0
0
0
0
5
4
3
2
1
0
LS Interrupt
Source
LS Variation
Int Mode
LS Interrupt
Enable
0
0
LS_INT_SEL
LS_VAR_MODE
LS_INT_EN
0
0
FIELD
BIT
DESCRIPTION
LS_INT_SEL
5:4
00 : IR channel
01 : ALS/Green channel (default)
10 : Red channel
11 : Blue channel
LS_VAR_MODE
3
0 : LS threshold interrupt mode (default)
1 : LS variation interrupt mode
LS_INT_EN
2
0 : LS Interrupt disabled (default)
1 : LS Interrupt enabled
0X19
INT_PERSISTENCE
Default Value : 00HEX
7
6
5
4
LS_PERSIST
3
2
1
0
0
0
0
0
0X1A
This register sets the number of similar consecutive LS interrupt events that must occur before the interrupt is asserted.
FIELD
BIT
DESCRIPTION
LS_PERSIST
7:4
0000 : Every LS value out of threshold range (default) asserts an interrupt
0001 : 2 consecutive LS values out of threshold range assert an interrupt
1111 : 16 consecutive LS values out of threshold range assert an interrupt
14
LS_THRES_UP
Default Value : FFHEX, FFHEX, 0FHEX
7
0
6
5
0
0
4
3
2
1
0
LS_THRES_UP_0 [7:0]
0X21
LS_THRES_UP_1 [15:8]
0X22
0
LS_THRES_UP_2 [19:16]
0X23
LS_THRES_UP sets the upper threshold value for the LS interrupt. The Interrupt Controller compares the value in LS_
THRES_UP against measured data in the LS_DATA registers of the selected LS interrupt channel. It generates an interrupt
event if DATA exceeds the threshold level.
The data format for LS_THRES_UP must match that of the LS_DATA registers.
Reg 21HEX Bit[7:0] LS upper interrupt threshold value, LSB
Reg 22HEX Bit[7:0] LS upper interrupt threshold value, intervening byte
Reg 23HEX Bit[3:0] LS upper interrupt threshold value, MSB
LS_THRES_LOW
Default value: 00HEX, 00HEX, 00HEX
7
0
6
5
0
0
4
3
2
1
0
LS_THRES_LOW_0 [7:0]
0X24
LS_THRES_LOW_1 [15:8]
0X25
0
LS_THRES_LOW_2 [19:16]
0X26
LS_THRES_LOW sets the lower threshold value for the LS interrupt. The Interrupt Controller compares the value in
LS_THRES_LOW against measured data in the LS_DATA registers of the selected LS interrupt channel. It generates an
interrupt event if the LS_DATA is below the threshold level.
The data format for LS_THRES_LOW must match that of the LS_DATA registers.
Reg 24HEX
Bit[7:0] LS lower interrupt threshold value, LSB
Reg 25HEX
Bit[7:0] LS lower interrupt threshold value, intervening byte
Reg 26HEX
Bit[3:0] LS lower interrupt threshold value, MSB
LS_THRES_VAR
Default Value : 00HEX
7
6
5
4
3
0
0
0
0
0
2
1
0
LS_THRES_VAR
FIELD
BIT
DESCRIPTION
LS_THRES_VAR
2:0
000 : new LS_DATA varies by 8 counts compared to previous result
001 : new LS_DATA varies by 16 counts compared to previous result
010 : new LS_DATA varies by 32 counts compared to previous result
011 : new LS_DATA varies by 64 counts compared to previous result
111 : new LS_DATA varies by 1024 counts compared to previous result
15
0X27
Application Information Hardware
The application hardware circuit for using implementing RGB, ALS and IR solution is simple with the APDS-9250 and is
shown in following figure. The bypass capacitor is placed as close to the device package and is connected directly to the
power source and to the ground, as shown in Figure below. It allows the AC component of the VDD to pass through to
ground. Suggested to have bypass capacitor that have low effective series resistance (ESR) and low effec­tive series inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies
to handle transient currents caused by internal logic switching.
Pull-up resistors, RSDA and RSCL, maintain the SDA and SCL lines at a high level when the bus is free and ensure the
signals are pulled up from a low to a high level within the required rise time. A pull-up resistor, RINT, is also required
for the interrupt (INT), which functions as a wired-AND signal in a similar fashion to the SCL and SDA lines. A typical
impedance value of 10 kΩ can be used.
For a complete description of I2C maxi­mum and minimum R1 and R2 values, please review the I2C Specification at http://
www.semiconductors.philips.com.
VBUS
VDD
R INT RSDA R SCL
1uF
MCU
SCL
SCL
SDA
SDA
INT
INT
APDS-9250
GND
16
Package Outline Dimensions
2 ±0.10
3
0.65 ±0.10
(4x)
0.65 ±0.10
2
1
1
2
3
0.75 ±0.15
(6x)
0.625 ±0.100
(6x)
CL
2 ±0.10
4
5
CL
6
IC Active Area Center
6
PINOUT
1- SCL
2- SDA
3- VDD
4- INT
5- NC
6- GND
PCB Pad Layout
(2)
(2)
1.300
(x3)
0.900
(x6)
0.650
(x4)
Dimensions are in mm
17
4
CL
(0.103)
CL
5
0.400
(x6)
0.300 ±0.050
(6x)
0.100 ±0.050
(6x)
Tape Dimensions
Ø 1.50 ±0.10
2±0.050
4 ±0.10
4 ±0.10
A
0.200 ±0.200
1.75 ±0.10
5 Deg Max
+ 0.300
8 - 0.100
3.500 ±0.050
2.180±0.050
B
B
C
A
Ø1±0.25
2.180 ±0.050
0.830±0.050
SECTION A-A
SCALE 10 : 1
5 Deg Max
SECTION B-B
SCALE 10 : 1
Unit Orientation
DETAIL C
SCALE 20 : 1
Dimensions are in mm
Reel Dimensions
T
Tape Start Slot
Measured at Hub
W1
T
Tape Start Slot
CCD/KEACO
MADE IN MALAYSIA
Access Hole
Access Hole
13 ± 0.2
Arbor Hole
20.2 Min.
∅180 ± 0.50
Diameter
Access Hole
W2
Measured at Hub
W3
Measured at Outer Edge
Front View
18
Back View
TAPE WIDTH
T
W1
W2
W3
8 MM
3 ± 0.50
8.4 + 1.5
- 0.0
14.4 MAX
7.9 MIN
10.9 MAX
Side View
60 ± 0.50
Hub Dia.
Moisture Proof Packaging
All APDS-9250 options are shipped in moisture proof package. Once opened, moisture absorption begins. This part is
compliant to JEDEC MSL 3.
Units in A Sealed
Mositure-Proof
Package
Package Is
Opened (Unsealed)
Environment
less than 30 deg C, and
less than 60% RH?
Yes
No Baking
Is Necessary
Package Is
Opened less
than 168 hours?
Yes
No
Perform Recommended
Baking Conditions
No
Baking conditions
Recommended Storage Conditions
Storage Temperature
10° C to 30° C
Relative Humidity
Below 60% RH
If the parts are not stored per the recommended storage
conditions they must be baked before reflow to prevent
damage to the parts.
Time from Unsealing to Soldering
Package
Temp.
Time
After removal from the bag, the parts should be soldered
within seven days if stored at the recommended storage
conditions. When MBB (Moisture Barrier Bag) is opened
and the parts are exposed to the recommended storage
conditions more than seven days the parts must be baked
before reflow to prevent damage to the parts.
In Reels
60°C
48 hours
In Bulk
100°C
4 hours
19
Note: Baking should only be done once.
Recommended Reflow Profile
MAX 260° C
R3
R4
TEMPERATURE (°C)
255
230
217
200
180
150
120
R2
60 sec to 120 sec
Above 217° C
R1
R5
80
25
0
P1
HEAT UP
Process Zone
Heat Up
Solder Paste Dry
50
100
150
P2
SOLDER PASTE DRY
Symbol
P1, R1
P2, R2
P3, R3
Solder Reflow
P3, R4
Cool Down
P4, R5
Time maintained above liquidus point , 217° C
Peak Temperature
Time within 5° C of actual Peak Temperature
Time 25° C to Peak Temperature
200
P3
SOLDER
REFLOW
300
t-TIME
(SECONDS)
∆T
Maximum ∆T/∆time
or Duration
25° C to 150° C
150° C to 200° C
200° C to 260° C
260° C to 200° C
200° C to 25° C
> 217° C
260° C
> 255° C
25° C to 260° C
3° C/s
100 s to 180s
3° C/s
-6° C/s
-6° C/s
60 s to 120 s
–
20 s to 40 s
8 mins
The reflow profile is a straight-line representation of
a nominal temperature profile for a convective reflow
solder process. The temperature profile is divided into
four process zones, each with different ∆T/∆time temperature change rates or duration. The ∆T/∆time rates or
duration are detailed in the above table. The temperatures
are measured at the component to printed circuit board
connections.
In process zone P1, the PC board and component pins
are heated to a temperature of 150° C to activate the flux
in the solder paste. The temperature ramp up rate, R1, is
limited to 3° C per second to allow for even heating of
both the PC board and component pins.
Process zone P2 should be of sufficient time duration (100
to 180 seconds) to dry the solder paste. The temperature is
raised to a level just below the liquidus point of the solder.
Process zone P3 is the solder reflow zone. In zone P3, the
temperature is quickly raised above the liquidus point of
solder to 260° C (500° F) for optimum results. The dwell
20
250
P4
COOL
DOWN
time above the liquidus point of solder should be between
60 and 120 seconds. This is to assure proper coalescing
of the solder paste into liquid solder and the formation
of good solder connections. Beyond the recommended
dwell time the intermetallic growth within the solder connections becomes excessive, resulting in the formation of
weak and unreliable connections. The temperature is then
rapidly reduced to a point below the solidus temperature
of the solder to allow the solder within the connections to
freeze solid.
Process zone P4 is the cool down after solder freeze. The
cool down rate, R5, from the liquidus point of the solder to
25° C (77° F) should not exceed 6° C per second maximum.
This limitation is necessary to allow the PC board and
component pins to change dimensions evenly, putting
minimal stresses on the component.
It is recommended to perform reflow soldering no more
than twice.
DISCLAIMER: Avago’s products and software are not specifically designed, manufactured or authorized for sale
as parts, components or assemblies for the planning, construction, maintenance or direct operation of a nuclear facility or for use in medical devices or applications. Customer is solely responsible, and waives all rights to
make claims against Avago or its suppliers, for all loss, damage, expense or liability in connection with such use.
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2015 Avago Technologies. All rights reserved.
AV02-4733EN - November 13, 2015