14 Pin DIP 5 Tap Fast-TTL Logic Compatible Active Delay Lines TAP DELAYS ±5% or ±2 nS† TOTAL DELAYS ±5% or ±2 nS† *3±1, 1±.5, 2±.5, 3±.5 *3±1, 1.5±.5, 3±.5, 4.5±.5 *3±1, 2±.5, 4±.5,6±.5 *3±1, 6±1.5, 9, 12 4, 8, 12, 16 5, 10, 15, 20 6, 12, 18, 24 8, 16, 24, 32 10, 20, 30, 40 12, 24, 36, 48 15, 30, 45, 60 20, 40, 60, 80 25, 50, 75, 100 30, 60, 90, 120 4 6 8 15 20 25 30 40 50 60 75 100 125 150 PART NUMBER TAP DELAYS ±5% or ±2 nS† EPA1145-4 EPA1145-6 EPA1145-8 EPA1145-15 EPA1145-20 EPA1145-25 EPA1145-30 EPA1145-40 EPA1145-50 EPA1145-60 EPA1145-75 EPA1145-100 EPA1145-125 EPA1145-150 TOTAL DELAYS ±5% or ±2 nS† 35, 70, 105, 140 40, 80, 120, 160 45, 90, 135, 180 50, 100, 150, 200 60, 120, 180, 240 70, 140, 210, 280 80, 160, 240, 320 90, 180, 270, 360 100, 200, 300, 400 120, 240, 360, 480 140, 280, 420, 560 160, 320, 480, 640 180, 360, 540, 720 200, 400, 600, 800 PART NUMBER 175 200 225 250 300 350 400 450 500 600 700 800 900 1000 EPA1145-175 EPA1145-200 EPA1145-225 EPA1145-250 EPA1145-300 EPA1145-350 EPA1145-400 EPA1145-450 EPA1145-500 EPA1145-600 EPA1145-700 EPA1145-800 EPA1145-900 EPA1145-1000 †Whichever is greater. Delay times referenced from input to leading edges at 25°C, 5.0V, with no load. * First tap is inherent delay (3 ± 1 nS), all other taps are measured referenced from first tap. Schematic DC Electrical Characteristics Parameter Test Conditions VOH VOL VIK IIH Min Max Unit High-Level Output Voltage Low-Level Output Voltage Input Clamp Voltage High-Level Input Current VCC = min. V IL = max. I OH = max 2.7 VCC = min. V IH = min. I OL = max VCC = min. II = II K VCC = max. V IN = 2.7V VCC = max. V IN = 5.25V IIL Low-Level Input Current VCC = max. V IN = 0.5V IOS Short Circuit Output Current VCC = max. V OUT = 0. -40 (One output at a time) ICCH High-Level Supply Current VCC = max. V IN = OPEN ICCL Low-Level Supply Current VCC = max. V IN = 0 TRO Output Rise Time Td ≤ 500 nS (0.75 to 2.4 Volts) Td > 500 nS NH Fanout High-Level Output VCC = max. V OH = 2.7V NL Fanout Low-Level Output VCC = max. V OL = 0.5V Recommended Operating Conditions VCC VIH VIL IIK IOH IOL PW* d* TA Supply Voltage High-Level Input Voltage Low-Level Input Voltage Input Clamp Current High-Level Output Current Low-Level Output Current Pulse Width of Total Delay Duty Cycle Operating Free-Air Temperature 0.5 -1.2 50 1.0 -0.6 -150 V V V µA mA mA mA 14 VCC 10 6 8 OUTPUT 7 GROUND mA 15 mA 50 nS 3 nS 3 20 TTL LOAD 10 TTL LOAD Max Unit 4.75 2.0 5.25 V V V mA mA mA % % °C 0.8 -18 -1.0 20 40 -55 40 +125 .200 PCA EPA1145-4 Date Code White Dot Pin#1 .300 .280 Max. .100 .780 Max. Unit 3.2 110 2.0 1.0 100 5.0 Volts % nS MHz KHz Volts .020 Min. .250 Max. .020 Typ. .010 Typ. .150 Typ. .365 Max. QAF-CSO1 Rev. B 8/25/94 DSA1145 Rev. A 2/5/96 Unless Otherwise Noted Dimensions in Inches Tolerances: Fractional = ± 1/32 .XX = ± .030 .XXX = ± .010 4 Package Dimensions Min Input Pulse Test Conditions @ 25° C Pulse Input Voltage Pulse Width % of Total Delay Pulse Rise Time (0.75 - 2.4 Volts) Pulse Repetition Rate @ Td ≤ 200 nS Pulse Repetition Rate @ Td > 200 nS Supply Voltage 12 INPUT 1 *These two values are inter-dependent. EIN PW TRI PRR VCC ELECTRONICS INC. 16799 SCHOENBORN ST. NORTH HILLS, CA 91343 TEL: (818) 892-0761 FAX: (818) 894-5791