H CAT1021, CAT1022, CAT1023 EE GEN FR ALO Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer LE A D F R E ETM FEATURES ■ Precision power supply voltage monitor — 5V, 3.3V and 3V systems — Five threshold voltage options ■ Built-in inadvertent write protection — WP pin (CAT1021) ■ 1,000,000 Program/Erase cycles ■ Watchdog timer ■ Manual reset input ■ Active high or low reset ■ 100 year data retention — Valid reset guaranteed at VCC = 1 V 2 ■ 400kHz I C bus ■ 3.0V to 5.5V operation ■ Low power CMOS technology ■ 8-pin DIP, SOIC, TSSOP, MSOP or TDFN (3 x 3 mm foot-print) packages — TDFN max height is 0.8mm ■ Industrial and extended temperature ranges ■ 16-Byte page write buffer DESCRIPTION The CAT1021, CAT1022 and CAT1023 are complete memory and supervisory solutions for microcontrollerbased systems. A 2k-bit serial EEPROM memory and a system power supervisor with brown-out protection are integrated together in low power CMOS technology. Memory interface is via a 400kHz I2C bus. The power supply monitor and reset circuit protect memory and system controllers during power up/down and against brownout conditions. Five reset threshold voltages support 5V, 3.3V and 3V systems. If power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, ASIC or peripherals from operating. Reset signals become inactive typically 200 ms after the The CAT1021 and CAT1023 provide a precision VCC supply voltage exceeds the reset threshold level. With both sense circuit and two open drain outputs: one (RESET) active high and low reset signals, interface to microcontrollers drives high and the other (RESET) drives low whenever and other ICs is simple. In addition, the RESET pin or a VCC falls below the reset threshold voltage. The CAT1022 separate input, MR, can be used as an input for push-button has only a RESET output and does not have a Write manual reset capability. Protect input. The CAT1021 also has a Write Protect input (WP). Write operations are disabled if WP is The on-chip, 2k-bit EEPROM memory features a 16-byte page. In addition, hardware data protection is provided by a connected to a logic high. VCC sense circuit that prevents writes to memory whenever All supervisors have a 1.6 second watchdog timer circuit VCC falls below the reset threshold or until VCC reaches the that resets a system to a known state if software or a reset threshold during power up. hardware glitch halts or “hangs” the system. For the CAT1021 and CAT1022, the watchdog timer monitors Available packages include an 8-pin DIP, 8-pin SOIC, 8-pin the SDA signal. The CAT1023 has a separate watchdog TSSOP, 8-pin TDFN and 8-pin MSOP. The TDFN package timer interrupt input pin, WDI. thickness is 0.8mm maximum. TDFN footprint options are 3x3mm. © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc No. 3009, Rev. K CAT1021, CAT1022, CAT1023 Threshold Voltage Options BLOCK DIAGRAM Part Dash Minimum Number Threshold EXTERNAL LOAD SENSE AMPS SHIFT REGISTERS DOUT ACK VCC WORD ADDRESS BUFFERS VSS SDA COLUMN DECODERS START/STOP LOGIC -45 4.50 4.75 -42 4.25 4.50 -30 3.00 3.15 -28 2.85 3.00 -25 2.55 2.70 2kbit EEPROM XDEC CONTROL LOGIC WP (CAT1021) DATA IN STORAGE HIGH VOLTAGE/ TIMING CONTROL RESET Controller Precision MR Vcc Monitor RESET (CAT1021/23) RESET STATE COUNTERS SCL SLAVE ADDRESS COMPARATORS WDI (CAT1023) PIN CONFIGURATION DIP Package (P, L) SOIC Package (J, W) TSSOP Package (U, Y) MSOP Package (R, Z) MR 1 RESET 2 WP 3 8 VCC CAT1021 7 RESET 6 SCL 5 SDA VSS 4 (Bottom View) TDFN Package: 3mm x 3mm 0.8mm maximum height - (RD4, ZD4) VCC 8 1 MR RESET 7 2 RESET SCL 6 3 WP SDA 5 4 VSS CAT1021 8 VCC 7 NC VCC 8 1 NC 7 2 RESET NC 3 6 SCL SCL 6 3 NC VSS 4 5 SDA SDA 5 4 VSS MR 1 8 VCC 7 WDI MR 1 RESET 2 RESET 2 CAT1022 CAT1023 RESET 3 VSS 4 Doc. No. 3009, Rev. K CAT1022 VCC 8 1 MR WDI 7 6 SCL SCL 6 5 SDA SDA 5 MR 2 RESET CAT1023 3 RESET 4 V SS 2 Maximum Threshold CAT1021, CAT1022, CAT1023 PIN DESCRIPTION RESET/RESET RESET: RESET OUTPUTS RESET (RESET CAT1021/23 Only) These are open drain pins and RESET can be used as a manual reset trigger input. By forcing a reset condition on the pin the device will initiate and maintain a reset condition. The RESET pin must be connected through a pull-down resistor, and the RESET pin must be connected through a pull-up resistor. SDA: SERIAL DATA ADDRESS The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. SCL: SERIAL CLOCK Serial clock input. MR: MANUAL RESET INPUT Manual Reset input is a debounced input that can be connected to an external source for Manual Reset. Pulling the MR input low will generate a Reset condition. Reset outputs are active while MR input is low and for the reset timeout period after MR returns to high. The input has an internal pull up resistor. WP (CAT1021 Only): WRITE PROTECT INPUT When WP input is tied to VSS or left unconnected write operations to the entire array are allowed. When tied to VCC, the entire array is protected. This input has an internal pull down resistor. WDI (CAT1023 Only): WATCHDOG TIMER INTERRUPT Watchdog Timer Interrupt Input is used to reset the watchdog timer. If a transition from high to low or low to high does not occur every 1.6 seconds, the RESET outputs will be driven active. OPERATING TEMPERATURE RANGE PIN FUNCTIONS Pin Name Function Industrial -40˚C to 85˚C NC No Connect Extended -40˚C to 125˚C Independent Auxiliary Voltage Sense RESET: Active High and LOW RESET Active Low Reset Input/Output VSS Ground SDA Serial Data/Address SCL Clock Input RESET Active High Reset Output (CAT1021/23) VCC Power Supply WP Write Protect (CAT1021 only) MR Manual Reset Input WDI Watchdog Timer Interrupt (CAT1023) CAT102X FAMILY OVERVIEW Device Manual Reset Input Pin Watchdog Watchdog Monitor Pin Write Protection Pin EEPROM CAT1021 SDA 2k CAT1022 SDA 2k CAT1023 WDI 2k CAT1024 2k CAT1025 2k CAT1026 2k CAT1027 WDI 2k For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163 data sheets. 3 Doc No. 3009, Rev. K CAT1021, CAT1022, CAT1023 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Temperature Under Bias ................. –55°C to +125°C Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to Ground(1) ........... –2.0 V to VCC + 2.0 V Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. VCC with Respect to Ground ................ –2.0V to 7.0 V Package Power Dissipation Capability (TA = 25°C) .................................. 1.0 W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA DC OPERATING CHARACTERISTICS VCC = 3.0V to 5.5V and over the recommended temperature conditions unless otherwise specified. Symbol Parameter Test Conditions Min ILI Input Leakage Current VIN = GND to Vcc ILO Output Leakage Current VIN = GND to Vcc ICC1 Power Supply Current (Write) ICC2 Max Units -2 10 µA -10 10 µA fSCL = 400 kHz VCC = 5.5V 3 mA Power Supply Current (Read) fSCL = 400 kHz VCC = 5.5 V 1 mA ISB Standby Current Vcc = 5.5 V, VIN = GND or Vcc 60 µA VIL(1) Input Low Voltage -0.5 0.3 x Vcc V VIH(1) Input High Voltage 0.7 x Vcc Vcc + 0.5 V VOL Output Low Voltage (SDA, RESET) IOL = 3 mA VCC = 2.7 V 0.4 V VOH Output High Voltage (RESET) IOH = -0.4 mA VCC = 2.7 V Vcc 0.75 CAT102x-45 (VCC = 5.0 V) 4.50 4.75 CAT102x-42 (VCC = 5.0 V) 4.25 4.50 CAT102x-30 (VCC = 3.3 V) 3.00 3.15 CAT102x-28 (VCC = 3.3 V) 2.85 3.00 CAT102x-25 (VCC = 3.0 V) 2.55 2.70 Reset Threshold VTH Typ V V VRVALID Reset Output Valid VCC Voltage 1.00 V VRT(2) Reset Threshold Hysteresis 15 mV Notes: 1. VIL min and VIH max are reference values only and are not tested. 2. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested. Doc. No. 3009, Rev. K 4 CAT1021, CAT1022, CAT1023 CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol COUT (1) CIN(1) Test Test Conditions Max Units VOUT = 0V 8 pF VIN = 0V 6 pF Output Capacitance Input Capacitance AC CHARACTERISTICS VCC = 3.0 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified. Memory Read & Write Cycle(2) Symbol Parameter fSCL Min Max Units Clock Frequency 400 kHz tSP Input Filter Spike Suppression (SDA, SCL) 100 ns tLOW Clock Low Period 1.3 µs tHIGH Clock High Period 0.6 µs tR(1) SDA and SCL Rise Time 300 ns tF(1) SDA and SCL Fall Time 300 ns tHD;STA Start Condition Hold Time 0.6 µs tSU;STA Start Condition Setup Time (for a Repeated Start) 0.6 µs tHD;DAT Data Input Hold Time 0 ns tSU;DAT Data Input Setup Time 100 ns tSU;STO Stop Condition Setup Time 0.6 µs tAA SCL Low to Data Out Valid tDH Data Out Hold Time 50 ns tBUF(1) Time the Bus must be Free Before a New Transmission Can Start 1.3 µs tWC(3) Write Cycle Time (Byte or Page) 900 5 ns ms Notes: 1. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. 2. Test Conditions according to “AC Test Conditions” table. 3. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address. 5 Doc No. 3009, Rev. K CAT1021, CAT1022, CAT1023 RESET CIRCUIT AC CHARACTERISTICS Symbol Parameter Test Conditions Min Typ Max Units tPURST Reset Timeout Note 2 130 200 270 ms tRPD VTH to RESET Output Delay Note 3 5 µs tGLITCH VCC Glitch Reject Pulse Width Note 4, 5 30 ns MR Glitch Manual Reset Glitch Immunity Note 1 100 ns tMRW MR Pulse Width Note 1 tMRD MR Input to RESET Output Delay Note 1 tWD Watchdog Timeout Note 1 1.0 Test Conditions Min 5 µs 1 µs 1.6 2.3 sec Typ Max Units POWER-UP TIMING5,6 Symbol Parameter tPUR Power-Up to Read Operation 270 ms tPUW Power-Up to Write Operation 270 ms AC TEST CONDITIONS Parameter Test Conditions Input Pulse Voltages 0.2 VCC to 0.8 VCC Input Rise and Fall times 10 ns Input Reference Voltages 0.3 VCC , 0.7 VCC Output Reference Voltages 0.5 VCC Output Load Current Source: IOL = 3 mA; CL = 100 pF RELIABILITY CHARACTERISTICS Symbol Parameter NEND(5) Endurance MIL-STD-883, Test Method 1033 1,000,000 Data Retention MIL-STD-883, Test Method 1008 100 Years VZAP(5) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts ILTH(5)(7) Latch-Up JEDEC Standard 17 100 mA TDR (5) Reference Test Method Min Max Units Cycles/Byte Notes: 1. Test Conditions according to “AC Test Conditions” table. 2. Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table 3. Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table 4. VCC Glitch Reference Voltage = VTHmin; Based on characterization data 5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. 6. tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated. 7. Latch-up protection is provided for stresses up to 100 mA on input and output pins from -1 V to VCC + 1 V. Doc. No. 3009, Rev. K 6 CAT1021, CAT1022, CAT1023 DEVICE OPERATION Reset Controller Description The CAT1021/22/23 precision RESET controllers ensure correct system operation during brownout and power up/down conditions. They are configured with open drain RESET outputs. embedded EEPROM is disabled for all operations, including write operations. If the Reset output(s) are active, in progress communications to the EEPROM are aborted and no new communications are allowed. In this condition an internal write cycle to the memory can not be started, but an in progress internal non-volatile memory write cycle can not be aborted. An internal write cycle initiated before the Reset condition can be successfully finished if there is enough time (5ms) before VCC reaches the minimum value of 2V. During power-up, the RESET outputs remain active until VCC reaches the VTH threshold and will continue driving the outputs for approximately 200ms (tPURST) after reaching VTH. After the tPURST timeout interval, the device will cease to drive the reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/down resistors. In addition, the CAT1021 includes a Write Protection Input which when tied to VCC will disable any write operations to the device. During power-down, the RESET outputs will be active when VCC falls below VTH. The RESET output will be valid so long as VCC is >1.0V (VRVALID). The device is designed to ignore the fast negative going VCC transient pulses (glitches). Watchdog Timer The Watchdog Timer provides an independent protection for microcontrollers. During a system failure, CAT1021/ 22/23 devices will provide a reset signal after a time-out interval of 1.6 seconds for a lack of activity. The CAT1023 is designed with the Watchdog timer feature on the WDI pin. The CAT1021 and CAT1022 monitor the SDA line. If WDI or SDA does not toggle within a 1.6 second interval, the reset condition will be generated on the reset outputs. The watchdog timer is cleared by any transition on a monitored line. Reset output timing is shown in Figure 1. Manual Reset Operation The RESET pin can operate as reset output and manual reset input. The input is edge triggered; that is, the RESET input will initiate a reset timeout after detecting a high to low transition. When RESET I/O is driven to the active state, the 200 msec timer will begin to time the reset interval. If external reset is shorter than 200 ms, Reset outputs will remain active at least 200 ms. As long as reset signal is asserted, the watchdog timer will not count and will stay cleared. The CAT1021/22/23 also have a separate manual reset input. Driving the MR input low by connecting a pushbutton (normally open) from MR pin to GND will generate a reset condition. The input has an internal pull up resistor. Reset remains asserted while MR is low and for the Reset Timeout period after MR input has gone high. Glitches shorter than 100 ns on MR input will not generate a reset pulse. No external debouncing circuits are required. Manual reset operation using MR input is shown in Figure 2. Hardware Data Protection The CAT1021/22/23 supervisors have been designed to solve many of the data corruption issues that have long been associated with serial EEPROMs. Data corruption occurs when incorrect data is stored in a memory location which is assumed to hold correct data. Whenever the device is in a Reset condition, the 7 Doc No. 3009, Rev. K CAT1021, CAT1022, CAT1023 t Figure 1. RESET Output Timing GLITCH VTH VRVALID t PURST VCC t RPD t PURST RESET RESET Figure 2. MR Operation and Timing t MRW MR t MRD t PURST RESET RESET Doc. No. 3009, Rev. K 8 t RPD CAT1021, CAT1022, CAT1023 SDA when SCL is HIGH. The CAT1021/22/23 monitor the SDA and SCL lines and will not respond until this condition is met. EMBEDDED EEPROM OPERATION The CAT1021/22/23 feature a 2kbit embedded serial EEPROM that supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. DEVICE ADDRESSING The Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are programmable in metal and the default is 1010. I2C Bus Protocol The features of the I2C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. After the Master sends a START condition and the slave address byte, the CAT1021/22/23 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT1021/22/23 then perform a Read or Write operation depending on the R/W bit. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of Figure 3. Bus Timing tF tHIGH tLOW tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tBUF tDH SDA OUT Figure 4. Write Cycle Timing SCL SDA 8TH BIT BYTE n ACK tWR STOP CONDITION 9 START CONDITION ADDRESS Doc No. 3009, Rev. K CAT1021, CAT1022, CAT1023 ACKNOWLEDGE WRITE OPERATIONS After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends a 8-bit address that is to be written into the address pointers of the device. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The device acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to non-volatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. All devices respond with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8bit byte. When a device begins a READ mode it transmits 8 bits of data, releases the SDA line and monitors the line for an acknowledge. Once it receives this acknowledge, the device will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. Figure 5. Start/Stop Timing SDA SCL START BIT STOP BIT Figure 6. Acknowledge Timing SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACKNOWLEDGE START Figure 7. Slave Address Bits Default Configuration CAT Doc. No. 3009, Rev. K 1 0 1 0 0 0 10 0 R/W CAT1021, CAT1022, CAT1023 Page Write The CAT1021/22/23 writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted, the CAT1021/22/23 will respond with an acknowledge and internally increment the lower order address bits by one. The high order bits remain unchanged. If the Master transmits more than 16 bytes before sending the STOP condition, the address counter ‘wraps around,’ and previously transmitted data will be overwritten. When all 16 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT1021/22/23 in a single write cycle. Figure 8. Byte Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS S T O P DATA P S A C K A C K A C K Figure 9. Page Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS (n) DATA n S T DATA n+15 O P DATA n+1 S P A C K A C K A C K 11 A C K A C K Doc No. 3009, Rev. K CAT1021, CAT1022, CAT1023 Acknowledge Polling memory array is protected and becomes read only. The CAT1021 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received. Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write opration, the CAT1021/22/23 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the device is still busy with the write operation, no ACK will be returned. If a write operation has completed, an ACK will be returned and the host can then proceed with the next read or write operation. Read Operations The READ operation for the CAT1021/22/23 is initiated in the same manner as the write operation with one exception, the R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. WRITE PROTECTION PIN (WP) The Write Protection feature (CAT1021 only) allows the user to protect against inadvertent memory array programming. If the WP pin is tied to VCC, the entire Figure 10. Immediate Address Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T S T O P SLAVE ADDRESS S P A C K DATA N O A C K SCL SDA 8 9 8TH BIT DATA OUT Doc. No. 3009, Rev. K NO ACK 12 STOP CAT1021, CAT1022, CAT1023 Immediate/Current Address Read Sequential Read The CAT1021/22/23 address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N + 1. For N = E = 255, the counter will wrap around to zero and continue to clock out valid data. After the CAT1021/22/23 receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT1021/22/23 sends the inital 8bit byte requested, the Master will responds with an acknowledge which tells the device it requires more data. The CAT1021/22/23 will continue to output an 8-bit byte for each acknowledge, thus sending the STOP condition. The data being transmitted from the CAT1021/22/23 is sent sequentially with the data from address N followed by data from address N + 1. The READ operation address counter increments all of the CAT1021/22/23 address bits so that the entire memory array can be read during one operation. Selective/Random Read Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After the CAT1021/22/23 acknowledges, the Master device sends the START condition and the slave address again, this time with the R/W bit set to one. The CAT1021/22/23 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Figure 11. Selective Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS S T A R T BYTE ADDRESS (n) S T O P SLAVE ADDRESS S S P A C K A C K A C K DATA n N O A C K Figure 12. Sequential Read Timing BUS ACTIVITY: MASTER SLAVE ADDRESS DATA n DATA n+1 DATA n+2 S T O P DATA n+x SDA LINE P A C K A C K A C K A C K N O A C K 13 Doc No. 3009, Rev. K CAT1021, CAT1022, CAT1023 PACKAGE OUTLINES 8-LEAD 300 MIL WIDE PLASTIC DIP (P, L) 0.245 (6.17) 0.295 (7.49) 0.300 (7.62) 0.325 (8.26) D 0.120 (3.05) 0.150 (3.81) 0.180 (4.57) MAX 0.015 (0.38) — 0.110 (2.79) 0.150 (3.81) 0.100 (2.54) BSC 0.310 (7.87) 0.380 (9.65) 0.045 (1.14) 0.060 (1.52) 0.014 (0.36) 0.022 (0.56) Dimension D Pkg Min Max 8L 0.355 (9.02) 0.400 (10.16) Notes: 1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. Doc. No. 3009, Rev. K 14 CAT1021, CAT1022, CAT1023 8-LEAD 150 MIL WIDE SOIC (J, W) 0.1497 (3.80) 0.1574 (4.00) 0.2284 (5.80) 0.2440 (6.20) D 0.0532 (1.35) 0.0688 (1.75) 0.050 (1.27) BSC 0.0040 (0.10) 0.0098 (0.25) 0.013 (0.33) 0.020 (0.51) 0.0099 (0.25) X 45° 0.0196 (0.50) 0.0075 (0.19) 0.0098 (0.25) 0°–8° 0.016 (0.40) 0.050 (1.27) Dimension D Pkg Min Max 8L 0.1890(4.80) 0.1968(5.00) Notes: 1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. 3. Lead coplanarity is 0.004" (0.102mm) maximum. 15 Doc No. 3009, Rev. K CAT1021, CAT1022, CAT1023 8-LEAD TSSOP (U, Y) Doc. No. 3009, Rev. K 16 CAT1021, CAT1022, CAT1023 8 LEAD MSOP (R, Z) 0.38 0.28 0.0150 0.0110 0.1970 0.1890 5.00 4.80 S 0.0256 [0.65] BSC 0.1220 0.1142 3.10 2.90 0.0374 0.0295 0.0433 [1.10] MAX. 0.039 [0.10] MAX. S 0.0059 0.0020 0.15 0.05 0.95 0.75 S 0.0150 0.0110 0.38 0.28 WITH PLATING 0.0276 0.0157 0.70 0.40 0.1220 0.1142 3.10 2.90 0.0091 0.0051 0.23 0.13 0.0050 [0.127] 0˚ - 6˚ WITH PLATING BASE METAL 0.0118 [0.30] REF. SECTION A - A Notes: (1) All dimensions are in mm Angles in degrees. 2 Does not include Mold Flash, Protrusion or Gate Burrs. Mold Flash, Protrusions or Gate Burrs shall not exceed 0.15 mm. per side. 3 Does not include Interlead Flash orProtrusion. Interlead Flash or Protrusion shall not exceed 0.25 mm per side. 4 Does not include Dambar Protrusion, allowable Dambar Protrusion shall be 0.08 mm. (5) This part is compliant with JEDEC Specification MO-187 Variations AA. (6) Lead span/stand off height/coplanarity are considered as special characteristics. (S) (7) Controlling dimensions in inches. [mm] 17 Doc No. 3009, Rev. K CAT1021, CAT1022, CAT1023 TDFN 3X3 PACKAGE (RD4, ZD4) 5 0.75 + 0.05 A B 3.00 + 0.10 (S) 8 2X 1 3.00 + 0.10 (S) 4 0.15 C 2X 0.0 - 0.05 0.15 C PIN 1 INDEX AREA 5 8 1.50 + 0.10 0.75 + 0.05 C 2.30 + 0.10 C0.35 0.25 min. PIN 1 ID 1 0.30 + 0.07 (8x) 1.95 REF. (2x) NOTE: 1. ALL DIMENSION ARE IN mm. ANGLES IN DEGREES. 2. COPLANARITY SHALL NOT EXCEED 0.08 mm. 3. WARPAGE SHALL NOT EXCEED 0.10 mm. 4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC(S) 5. REFER JEDEC MO-229 / WEEC Doc. No. 3009, Rev. K 18 0.30 + 0.10 (8x) 0.65 TYP. (6x) CAT1021, CAT1022, CAT1023 Ordering Information Prefix CAT Optional Company ID Device # Suffix 1021 Product Number 1021: 2K 1022: 2K 1023: 2K J I Temperature Range I = Industrial (-40˚C to 85˚C) E = Extended (-40˚C to +125˚C) Package P: PDIP J: SOIC R: MSOP U: TSSOP RD4: 8-pad TDFN (3x3mm) L: PDIP (Lead free, Halogen free) W: SOIC (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) Z: MSOP (Lead free, Halogen free) ZD4: TDFN 3x3mm (Lead free, Halogen free) -30 TE13 Tape & Reel SOIC: 2000/Reel TSSOP: 2000/Reel MSOP: 2500/Reel TDFN: 2000/Reel Reset Threshold Voltage 45: 4.5-4.75V 42: 4.25-4.5V 30: 3.0-3.15V 28: 2.85-3.0V 25: 2.55-2.7V Note: (1) The device used in the above example is a CAT1021JI-30TE13 (Supervisory circuit with I2C serial 2k CMOS EEPROM, SOIC, Industrial Temperature, 3.0-3.15V Reset Threshold Voltage, Tape and Reel). 19 Doc No. 3009, Rev. K REVISION HISTORY Date Rev. Reason 9/25/2003 F Added Green Package logo Updated DC Operating Characteristic notes Updated Reliability Characteristics notes 11/7/2003 G Eliminated Automotive temperature range Updated Ordering Information with “Green” package codes Updated Reset Circuit AC Characteristics 4/12/2004 H Eliminated data sheet designation Updated Reel Ordering Information 11/1/2004 I Eliminated 8-pad TDFN package (3x4.9mm) Changed SOIC package designators Added package outlines 11/04/04 J Update Pin Configuration 11/11/04 K Update Features Update Description Updae DC Operating Characteristic Update AC Characteristics Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ I2C is a trademark of Philips Corporation Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. 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Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: Type: 3009 K 11/11/04 Preliminary