AD ADSP-BF532SBBZ400 Blackfin embedded processor Datasheet

Blackfin®
Embedded Processor
ADSP-BF531/ADSP-BF532
a
FEATURES
External memory controller with glueless support for
SDRAM, SRAM, FLASH, and ROM
Flexible memory booting options from SPI® and
external memory
Up to 400 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
0.8 V to 1.2 V core VDD with on-chip voltage regulation
1.8 V, 2.5 V, and 3.3 V compliant I/O
160-ball mini-BGA, 169-ball lead free PBGA, and 176-lead
LQFP packages
PERIPHERALS
Parallel peripheral interface PPI/GPIO, supporting
ITU-R 656 video data formats
Two dual-channel, full duplex synchronous serial ports, supporting eight stereo I2S channels
12-channel DMA controller
SPI-compatible port
Three timer/counters with PWM support
UART with support for IrDA®
Event handler
Real-time clock
Watchdog timer
Debug/JTAG interface
On-chip PLL capable of 0.5ⴛ to 64ⴛ frequency multiplication
Core timer
MEMORY
Up to 84K bytes of on-chip memory:
16K bytes of instruction SRAM/Cache
32K bytes of instruction SRAM
32K bytes of data SRAM/Cache
4K bytes of scratchpad SRAM
Two dual-channel memory DMA controllers
Memory management unit providing memory protection
JTAG TEST AND
EMULATION
VOLTAGE
REGULATOR
EVENT
CONTROLLER/
CORE TIMER
WATCHDOG TIMER
B
L1
INSTRUCTION
MEMORY
MMU
REAL-TIME CLOCK
UART PORT
IrDA
L1
DATA
MEMORY
TIMER0, TIMER1,
TIMER2
CORE/SYSTEM BUS INTERFACE
PPI / GPIO
DMA
CONTROLLER
SERIAL PORTS (2)
SPI PORT
BOOT ROM
EXTERNAL PORT
FLASH, SDRAM
CONTROL
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. D
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However, no responsibility is assumed by Analog Devices for its use, nor for any
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Specifications subject to change without notice. No license is granted by implication
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Fax: 781.461.3113
© 2006 Analog Devices, Inc. All rights reserved.
ADSP-BF531/ADSP-BF532
TABLE OF CONTENTS
General Description ................................................. 4
Portable Low Power Architecture ............................. 4
Universal Asynchronous Receiver-Transmitter
(UART) Port—Receive and Transmit Timing ...... 39
System Integration ................................................ 4
Programmable Flags Cycle Timing ....................... 40
ADSP-BF531/ADSP-BF532 Processor Peripherals ........ 4
Timer Cycle Timing .......................................... 41
Blackfin Processor Core .......................................... 4
JTAG Test and Emulation Port Timing .................. 42
Memory Architecture ............................................ 5
Output Drive Currents ......................................... 43
DMA Controllers .................................................. 8
Power Dissipation ............................................... 45
Real-Time Clock ................................................... 9
Test Conditions .................................................. 45
Watchdog Timer .................................................. 9
Environmental Conditions .................................... 48
Timers ............................................................. 10
160-Ball BGA Pinout ............................................... 50
Serial Ports (SPORTs) .......................................... 10
169-Ball PBGA Pinout ............................................. 53
Serial Peripheral Interface (SPI) Port ....................... 10
176-Lead LQFP Pinout ............................................ 56
UART Port ........................................................ 10
Outline Dimensions ................................................ 58
Programmable Flags (PFx) .................................... 11
Ordering Guide ..................................................... 60
Parallel Peripheral Interface ................................... 11
Dynamic Power Management ................................ 12
Voltage Regulation .............................................. 13
Clock Signals ..................................................... 13
Booting Modes ................................................... 14
Instruction Set Description ................................... 14
Development Tools ............................................. 15
Designing an Emulator-Compatible Processor Board .. 16
Related Documents ............................................. 16
Pin Descriptions .................................................... 17
Specifications ........................................................ 20
Operating Conditions .......................................... 20
Electrical Characteristics ....................................... 21
Absolute Maximum Ratings .................................. 22
Package Information ........................................... 22
ESD Sensitivity ................................................... 22
Timing Specifications .......................................... 23
Clock and Reset Timing .................................... 24
Asynchronous Memory Read Cycle Timing ........... 25
Asynchronous Memory Write Cycle Timing .......... 26
SDRAM Interface Timing .................................. 27
External Port Bus Request and Grant Cycle Timing .. 28
Parallel Peripheral Interface Timing ..................... 29
Serial Ports ..................................................... 32
Serial Peripheral Interface (SPI) Port
—Master Timing .......................................... 37
Serial Peripheral Interface (SPI) Port
—Slave Timing ............................................. 38
Rev. D |
Page 2 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
REVISION HISTORY
8/06—Revision D: Changed from Rev. C to Rev. D
Added 1.8 V I/O to Features ....................................... 1
Changed Text in Figure External Components for RTC .... 9
Added Text to Serial Ports (SPORTs) ........................... 10
Changed Font in Formula in Power Savings .................. 12
Minor Edit to Figure Voltage Regulator Circuit .............. 13
Complete Rewrite of Operating Conditions ................... 20
Complete Rewrite of Electrical Characteristics ............... 21
Added 1.8 V and 125°C Specifications
to Multiple Tables of Timing Specifications .................. 23
Edit to Asynchronous Memory Read Cycle Timing ......... 25
Edit to Asynchronous Memory Write Cycle Timing ........ 26
Changed Data in SDRAM Interface Timing .................. 27
Changed Data in Parallel Peripheral Interface Timing ...... 29
Changed Data in Serial Ports ..................................... 32
Deleted References to Temperature in Figures
in Output Drive Currents ......................................... 43
Added 1.8 V Data to Output Drive Currents .................. 43
Moved Data to Operating Conditions
and Rewrote Power Dissipation ................................. 45
Deleted References to Temperature in Figures
in Test Conditions .................................................. 45
Added 1.8 V References in Test Conditions ................... 45
Added 1.8 V Characterization Data Capacitive Loading ... 45
Changed Thermal Characteristics for BC-160 Package ..... 49
Added Models to Ordering Guide ............................... 60
Rev. D |
Page 3 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
GENERAL DESCRIPTION
The ADSP-BF531/ADSP-BF532 processors are members of the
Blackfin family of products, incorporating the Analog Devices/
Intel Micro Signal Architecture (MSA). Blackfin processors
combine a dual-MAC state-of-the-art signal processing engine,
the advantages of a clean, orthogonal RISC-like microprocessor
instruction set, and single instruction, multiple data (SIMD)
multimedia capabilities into a single instruction set architecture.
The Blackfin processors are completely code and pin compatible, differing only with respect to their performance and onchip memory. Specific performance and memory configurations are shown in Table 1.
Table 1. Processor Comparison
ADSP-BF531
ADSP-BF532
Maximum Performance 400 MHz 800 MMACs 400 MHz 800 MMACs
Instruction
16K bytes
16K bytes
SRAM/Cache
Instruction SRAM
16K bytes
32K bytes
Data
16K bytes
32K bytes
SRAM/Cache
Scratchpad
4K bytes
4K bytes
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next generation applications that require RISC-like programmability, multimedia support, and leading-edge signal
processing in one integrated package.
PORTABLE LOW POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. Blackfin processors are designed in a low
power and low voltage design methodology and feature
dynamic power management—the ability to vary both the voltage and frequency of operation to significantly lower overall
power consumption. Varying the voltage and frequency can
result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This
translates into longer battery life for portable appliances.
SYSTEM INTEGRATION
The ADSP-BF531/ADSP-BF532 processors are highly integrated system-on-a-chip solutions for the next generation of
digital communication and consumer multimedia applications.
By combining industry-standard interfaces with a high performance signal processing core, users can develop cost-effective
solutions quickly without the need for costly external components. The system peripherals include a UART port, an SPI port,
two serial ports (SPORTs), four general-purpose timers (three
with PWM capability), a real-time clock, a watchdog timer, and
a parallel peripheral interface.
ADSP-BF531/ADSP-BF532 PROCESSOR
PERIPHERALS
The ADSP-BF531/ADSP-BF532 processor contains a rich set of
peripherals connected to the core via several high bandwidth
buses, providing flexibility in system configuration as well as
excellent overall system performance (see the functional block
diagram in Figure 1 on Page 1). The general-purpose peripherals include functions such as UART, timers with PWM (pulsewidth modulation) and pulse measurement capability, generalpurpose flag I/O pins, a real-time clock, and a watchdog timer.
This set of functions satisfies a wide variety of typical system
support needs and is augmented by the system expansion capabilities of the part. In addition to these general-purpose
peripherals, the ADSP-BF531/ADSP-BF532 processor contains
high speed serial and parallel ports for interfacing to a variety of
audio, video, and modem codec functions; an interrupt controller for flexible management of interrupts from the on-chip
peripherals or external sources; and power management control
functions to tailor the performance and power characteristics of
the processor and system to many application scenarios.
All of the peripherals, except for general-purpose I/O, real-time
clock, and timers, are supported by a flexible DMA structure.
There is also a separate memory DMA channel dedicated to
data transfers between the processor’s various memory spaces,
including external SDRAM and asynchronous memory. Multiple on-chip buses running at up to 133 MHz provide enough
bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals.
The ADSP-BF531/ADSP-BF532 processor includes an on-chip
voltage regulator in support of the ADSP-BF531/ADSP-BF532
processor dynamic power management capability. The voltage
regulator provides a range of core voltage levels from a single
2.25 V to 3.6 V input. The voltage regulator can be bypassed at
the user’s discretion.
BLACKFIN PROCESSOR CORE
As shown in Figure 2 on Page 6, the Blackfin processor core
contains two 16-bit multipliers, two 40-bit accumulators, two
40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-bit, 16-bit, or 32-bit data from the
register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and
Rev. D |
Page 4 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
population count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection. The set of
video instructions includes byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average
operations, and 8-bit subtract/absolute value/accumulate (SAA)
operations. Also provided are the compare/select and vector
search instructions.
For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). By also using the second
ALU, quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
Rev. D |
The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
MEMORY ARCHITECTURE
The ADSP-BF531/ADSP-BF532 processor views memory as a
single unified 4G byte address space, using 32-bit addresses. All
resources, including internal memory, external memory, and
I/O control registers, occupy separate sections of this common
address space. The memory portions of this address space are
arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low latency on-chip
memory as cache or SRAM, and larger, lower cost and performance off-chip memory systems. See Figure 3 on Page 7, and
Figure 4 on Page 7.
The L1 memory system is the primary highest performance
memory available to the Blackfin processor. The off-chip memory system, accessed through the external bus interface unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 132M bytes of
physical memory.
The memory DMA controller provides high bandwidth datamovement capability. It can perform block transfers of code or
data between the internal memory and the external
memory spaces.
Internal (On-Chip) Memory
The ADSP-BF531/ADSP-BF532 processor has three blocks of
on-chip memory providing high bandwidth access to the core.
The first is the L1 instruction memory, consisting of up to
48K bytes SRAM, of which 16K bytes can be configured as a
four way set-associative cache. This memory is accessed at full
processor speed.
The second on-chip memory block is the L1 data memory, consisting of one bank of 32K bytes. The memory bank is
configurable, offering both cache and SRAM functionality. This
memory block is accessed at full processor speed.
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
External (Off-Chip) Memory
The external bus interface can be used with both asynchronous
devices such as SRAM, FLASH, EEPROM, ROM, and I/O
devices, and synchronous devices such as SDRAMs. The bus
width is always 16 bits. A1 is the least significant address of a
16-bit word. 8-bit peripherals should be addressed as if they
were 16-bit devices, where only the lower eight bits of data
should be used.
The PC133-compliant SDRAM controller can be programmed
to interface to up to 128M bytes of SDRAM. The SDRAM controller allows one row to be open for each internal SDRAM
bank, for up to four internal SDRAM banks, improving overall
system performance.
Page 5 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
ADDRESS ARITHMETIC UNIT
L3
B3
M3
I2
L2
B2
M2
I1
L1
B1
M1
I0
L0
B0
M0
SP
FP
P5
DAG1
P4
P3
DAG0
P2
32
32
P1
P0
TO MEMORY
DA1
DA0
I3
32
PREG
32
RAB
SD
LD1
LD0
32
32
32
ASTAT
32
32
SEQUENCER
R7.H
R6.H
R7.L
R6.L
R5.H
R5.L
R4.H
R4.L
R3.H
R3.L
R2.H
R2.L
R1.H
R1.H
R0.H
R0.L
16
ALIGN
16
8
8
8
8
DECODE
BARREL
SHIFTER
40
40
40
A0
32
40
A1
LOOP BUFFER
CONTROL
UNIT
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks will only be contiguous if each is fully populated with 1M byte of memory.
I/O Memory Space
Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space.
On-chip I/O devices have their control registers mapped into
memory mapped registers (MMRs) at addresses near the top of
the 4G byte address space. These are separated into two smaller
blocks, one of which contains the control MMRs for all core
functions, and the other of which contains the registers needed
for setup and control of the on-chip peripherals outside of the
core. The MMRs are accessible only in supervisor mode and
appear as reserved space to on-chip peripherals.
boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more information, see
Booting Modes on Page 14.
Event Handling
The event controller on the ADSP-BF531/ADSP-BF532 processor handles all asynchronous and synchronous events to the
processor. The ADSP-BF531/ADSP-BF532 processor provides
event handling that supports both nesting and prioritization.
Nesting allows multiple event service routines to be active
simultaneously. Prioritization ensures that servicing of a higher
priority event takes precedence over servicing of a lower priority
event. The controller provides support for five different types
of events:
Booting
The ADSP-BF531/ADSP-BF532 processor contains a small boot
kernel, which configures the appropriate peripheral for booting.
If the ADSP-BF531/ADSP-BF532 processor is configured to
Rev. D |
Page 6 of 60 |
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• Reset – This event resets the processor.
• Nonmaskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shutdown of the system.
August 2006
ADSP-BF531/ADSP-BF532
• Exceptions – Events that occur synchronously to program
flow (i.e., the exception will be taken before the instruction
is allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTE)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTE)
0xFFC0 0000
RESERVED
0xFFB0 1000
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
SCRATCHPAD SRAM (4K BYTE)
INTERNAL MEMORY MAP
0xFFB0 0000
RESERVED
0xFFA1 4000
INSTRUCTION SRAM/CACHE (16K BYTE)
0xFFA1 0000
INSTRUCTION SRAM (32K BYTE)
0xFFA0 8000
RESERVED
0xFFA0 0000
RESERVED
0xFF90 8000
DATA BANK B SRAM/CACHE (16K BYTE)
0xFF90 4000
RESERVED
0xFF80 8000
DATA BANK A SRAM/CACHE (16K BYTE)
0xFF80 4000
RESERVED
0xEF00 0000
EXTERNAL MEMORY MAP
RESERVED
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTE)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTE)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTE)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTE)
0x2000 0000
RESERVED
0x0800 0000
SDRAM MEMORY (16M BYTE TO 128M BYTE)
0x0000 0000
Figure 3. ADSP-BF532 Internal/External Memory Map
0xFFFF FFFF
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The ADSP-BF531/ADSP-BF532 processor event controller consists of two stages, the core event controller (CEC) and the
system interrupt controller (SIC). The core event controller
works with the system interrupt controller to prioritize and control all system events. Conceptually, interrupts from the
peripherals enter into the SIC, and are then routed directly into
the general-purpose interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority interrupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of theADSP-BF531/ADSP-BF532 processor. Table 2 describes the inputs to the CEC, identifies their
names in the event vector table (EVT), and lists their priorities.
Table 2. Core Event Controller (CEC)
CORE MMR REGISTERS (2M BYTE)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTE)
Priority
(0 is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0xFFC0 0000
RESERVED
0xFFB0 1000
SCRATCHPAD SRAM (4K BYTE)
0xFFB0 0000
RESERVED
INTERNAL MEMORY MAP
0xFFA1 4000
INSTRUCTION SRAM/CACHE (16K BYTE)
0xFFA1 0000
RESERVED
0xFFA0 C000
INSTRUCTION SRAM (16K BYTE)
0xFFA0 8000
RESERVED
0xFFA0 0000
RESERVED
0xFF90 8000
RESERVED
0xFF90 4000
RESERVED
0xFF80 8000
DATA BANK A SRAM/CACHE (16K BYTE)
0xFF80 4000
RESERVED
0xEF00 0000
EXTERNAL MEMORY MAP
RESERVED
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTE)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTE)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTE)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTE)
0x2000 0000
RESERVED
0x0800 0000
SDRAM MEMORY (16M BYTE TO 128M BYTE)
0x0000 0000
Figure 4. ADSP-BF531 Internal/External Memory Map
Rev. D |
Event Class
Emulation/Test Control
Reset
Nonmaskable Interrupt
Exception
Reserved
Hardware Error
Core Timer
General Interrupt 7
General Interrupt 8
General Interrupt 9
General Interrupt 10
General Interrupt 11
General Interrupt 12
General Interrupt 13
General Interrupt 14
General Interrupt 15
EVT Entry
EMU
RST
NMI
EVX
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Page 7 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
preventing the processor from servicing the event even
though the event may be latched in the ILAT register. This
register may be read or written while in supervisor mode.
(Note that general-purpose interrupts can be globally
enabled and disabled with the STI and CLI instructions,
respectively.)
Although the ADSP-BF531/ADSP-BF532 processor provides a
default mapping, the user can alter the mappings and priorities
of interrupt events by writing the appropriate values into the
interrupt assignment registers (IAR). Table 3 describes the
inputs into the SIC and the default mappings into the CEC.
Table 3. System Interrupt Controller (SIC)
Peripheral Interrupt Event
PLL Wakeup
DMA Error
PPI Error
SPORT 0 Error
SPORT 1 Error
SPI Error
UART Error
Real-Time Clock
DMA Channel 0 (PPI)
DMA Channel 1 (SPORT 0 Receive)
DMA Channel 2 (SPORT 0 Transmit)
DMA Channel 3 (SPORT 1 Receive)
DMA Channel 4 (SPORT 1 Transmit)
DMA Channel 5 (SPI)
DMA Channel 6 (UART Receive)
DMA Channel 7 (UART Transmit)
Timer 0
Timer 1
Timer 2
PF Interrupt A
PF Interrupt B
DMA Channels 8 and 9
(Memory DMA Stream 1)
DMA Channels 10 and 11
(Memory DMA Stream 0)
Software Watchdog Timer
• CEC interrupt pending register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
Default Mapping
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG8
IVG8
IVG9
IVG9
IVG9
IVG9
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
IVG12
IVG12
IVG13
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in Table 3.
• SIC interrupt mask register (SIC_IMASK) – This register
controls the masking and unmasking of each peripheral
interrupt event. When a bit is set in the register, that
peripheral event is unmasked and will be processed by the
system when asserted. A cleared bit in the register masks
the peripheral event, preventing the processor from servicing the event.
• SIC interrupt status register (SIC_ISR) – As multiple
peripherals can be mapped to a single event, this register
allows the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indicates the peripheral is not asserting the event.
• SIC interrupt wakeup enable register (SIC_IWR) – By
enabling the corresponding bit in this register, a peripheral
can be configured to wake up the processor, should the
core be idled when the event is generated. (For more information, see Dynamic Power Management on Page 12.)
Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt
acknowledgement.
IVG13
IVG13
Event Control
The ADSP-BF531/ADSP-BF532 processor provides the user
with a very flexible mechanism to control the processing of
events. In the CEC, three registers are used to coordinate and
control events. Each register is 16 bits wide:
• CEC interrupt latch register (ILAT) – The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it may be written only when its corresponding IMASK bit
is cleared.
• CEC interrupt mask register (IMASK) – The IMASK register controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event,
Rev. D |
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor.
DMA CONTROLLERS
The ADSP-BF531/ADSP-BF532 processor has multiple, independent DMA controllers that support automated data transfers
with minimal overhead for the processor core. DMA transfers
can occur between the ADSP-BF531/ADSP-BF532 processor’s
internal memories and any of its DMA-capable peripherals.
Page 8 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
Additionally, DMA transfers can be accomplished between any
of the DMA-capable peripherals and external devices connected
to the external memory interfaces, including the SDRAM
controller and the asynchronous memory controller. DMAcapable peripherals include the SPORTs, SPI port, UART, and
PPI. Each individual DMA-capable peripheral has at least one
dedicated DMA channel.
The ADSP-BF531/ADSP-BF532 processor DMA controller
supports both 1-dimensional (1-D) and 2-dimensional (2-D)
DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called
descriptor blocks.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be
de-interleaved on the fly.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day. The second alarm is for a day and time of
that day.
The stopwatch function counts down from a programmed
value, with one second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like other peripherals, the RTC can wake up the processor from
sleep mode upon generation of any RTC wakeup event.
Additionally, an RTC wakeup event can wake up the processor
from deep sleep mode, and wake up the on-chip internal voltage
regulator from a powered-down state.
Connect RTC pins RTXI and RTXO with external components
as shown in Figure 5.
RTXI
RTXO
R1
Examples of DMA types supported by the ADSP-BF531/
ADSP-BF532 processor DMA controller include:
X1
• A single, linear buffer that stops upon completion
C1
C2
• A circular, autorefreshing buffer that interrupts on each
full or fractionally full buffer
• 1-D or 2-D DMA using a linked list of descriptors
SUGGESTED COMPONENTS:
X1 = ECL IPTEK EC38J (THROUGH-HOLE PACKAGE) OR
EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)
C1 = 22 pF
C2 = 22 pF
R1 = 10 MΩ
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECI FICATIO NS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels provided for transfers between the
various memories of the ADSP-BF531/ADSP-BF532 processor
system. This enables transfers of blocks of data between any of
the memories—including external SDRAM, ROM, SRAM, and
flash memory—with minimal processor intervention. Memory
DMA transfers can be controlled by a very flexible descriptorbased methodology or by a standard register-based autobuffer
mechanism.
REAL-TIME CLOCK
The ADSP-BF531/ADSP-BF532 processor real-time clock
(RTC) provides a robust set of digital watch features, including
current time, stopwatch, and alarm. The RTC is clocked by a
32.768 kHz crystal external to the ADSP-BF531/ADSP-BF532
processor. The RTC peripheral has dedicated power supply pins
so that it can remain powered up and clocked even when the
rest of the processor is in a low power state. The RTC provides
several programmable interrupt options, including interrupt
per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a
programmed alarm time.
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60 second counter, a 60 minute counter, a 24
hour counter, and a 32,768 day counter.
Rev. D |
Figure 5. External Components for RTC
WATCHDOG TIMER
The ADSP-BF531/ADSP-BF532 processor includes a 32-bit
timer that can be used to implement a software watchdog function. A software watchdog can improve system availability by
forcing the processor to a known state through generation of a
hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by
software. The programmer initializes the count value of the
timer, enables the appropriate interrupt, then enables the timer.
Thereafter, the software must reload the counter before it
counts to zero from the programmed value. This protects the
system from remaining in an unknown state where software,
which would normally reset the timer, has stopped running due
to an external noise condition or software error.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the ADSP-BF531/ADSP-BF532 processor peripherals. After a reset, software can determine if the
watchdog was the source of the hardware reset by interrogating
a status bit in the watchdog timer control register.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK.
Page 9 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
TIMERS
There are four general-purpose programmable timer units in
the ADSP-BF531/ADSP-BF532 processor. Three timers have an
external pin that can be configured either as a pulse-width modulator (PWM) or timer output, as an input to clock the timer, or
as a mechanism for measuring pulse widths and periods of
external events. These timers can be synchronized to an external
clock input to the PF1 pin, an external clock input to the
PPI_CLK pin, or to the internal SCLK.
The timer units can be used in conjunction with the UART to
measure the width of the pulses in the data stream to provide an
autobaud detect function for a serial channel.
• Interrupts – Each transmit and receive port generates an
interrupt upon completing the transfer of a data-word or
after transferring an entire data buffer or buffers
through DMA.
• Multichannel capability – Each SPORT supports 128 channels out of a 1,024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
An additional 250 mV of SPORT input hysteresis can be
enabled by setting Bit 15 of the PLL_CTL register. When this bit
is set, all SPORT input pins have the increased hysteresis.
SERIAL PERIPHERAL INTERFACE (SPI) PORT
The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system
clock or to a count of external signals.
The ADSP-BF531/ADSP-BF532 processor has an SPI-compatible port that enables the processor to communicate with
multiple SPI-compatible devices.
In addition to the three general-purpose programmable timers,
a fourth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
The SPI interface uses three pins for transferring data: two data
pins (master output-slave input, MOSI, and master input-slave
output, MISO) and a clock pin (serial clock, SCK). An SPI chip
select input pin (SPISS) lets other SPI devices select the processor, and seven SPI chip select output pins (SPISEL7–1) let the
processor select other SPI devices. The SPI select pins are reconfigured programmable flag pins. Using these pins, the SPI port
provides a full-duplex, synchronous serial interface which supports both master/slave modes and multimaster environments.
SERIAL PORTS (SPORTs)
The ADSP-BF531/ADSP-BF532 processor incorporates two
dual-channel synchronous serial ports (SPORT0 and SPORT1)
for serial and multiprocessor communications. The SPORTs
support the following features:
2
• I S capable operation.
• Bidirectional operation – Each SPORT has two sets of independent transmit and receive pins, enabling eight channels
of I2S stereo audio.
• Buffered (8-deep) transmit and receive ports – Each port
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
• Clocking – Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
• Word length – Each SPORT supports serial data words
from 3 bits to 32 bits in length, transferred most-significant-bit first or least-significant-bit first.
• Framing – Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.
• Companding in hardware – Each SPORT can perform
A-law or µ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
The baud rate and clock phase/polarities for the SPI port are
programmable, and it has an integrated DMA controller, configurable to support transmit or receive data streams. The SPI
DMA controller can only service unidirectional accesses at any
given time.
The SPI port clock rate is calculated as:
f SCLK
SPI Clock Rate = -------------------------------2 × SPI_Baud
Where the 16-bit SPI_Baud register contains a value of 2 to
65,535.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.
UART PORT
The ADSP-BF531/ADSP-BF532 processor provides a fullduplex universal asynchronous receiver/transmitter (UART)
port, which is fully compatible with PC-standard UARTs. The
UART port provides a simplified UART interface to other
peripherals or hosts, supporting full-duplex, DMA-supported,
asynchronous transfers of serial data. The UART port includes
support for 5 data bits to 8 data bits, 1 stop bit or 2 stop bits, and
none, even, or odd parity. The UART port supports two modes
of operation:
• DMA operations with single-cycle overhead – Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
Rev. D |
Page 10 of 60 |
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
August 2006
ADSP-BF531/ADSP-BF532
inputs can be configured to generate hardware interrupts,
while output PFx pins can be triggered by software
interrupts.
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
• Flag interrupt sensitivity registers – The two flag interrupt
sensitivity registers specify whether individual PFx pins are
level- or edge-sensitive and specify—if edge-sensitive—
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.
The baud rate, serial data format, error code generation and status, and interrupts for the UART port are programmable.
The UART programmable features include:
• Supporting bit rates ranging from (fSCLK/1,048,576) bits per
second to (fSCLK/16) bits per second.
• Supporting data formats from seven bits to 12 bits per
frame.
PARALLEL PERIPHERAL INTERFACE
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The UART port’s clock rate is calculated as:
f SCLK
UART Clock Rate = ---------------------------------------------16 × UART_Divisor
Where the 16-bit UART_Divisor comes from the DLH register
(most significant 8 bits) and DLL register (least significant
8 bits).
In conjunction with the general-purpose timer functions,
autobaud detection is supported.
The capabilities of the UART are further extended with support
for the Infrared Data Association (IrDA) serial infrared physical
layer link specification (SIR) protocol.
The processor provides a parallel peripheral interface (PPI) that
can connect directly to parallel A/D and D/A converters,
ITU-R 601/656 video encoders and decoders, and other generalpurpose peripherals. The PPI consists of a dedicated input clock
pin, up to three frame synchronization pins, and up to 16 data
pins. The input clock supports parallel data rates up to half the
system clock rate.
In ITU-R 656 modes, the PPI receives and parses a data stream
of 8-bit or 10-bit data elements. On-chip decode of embedded
preamble control and synchronization information is
supported.
Three distinct ITU-R 656 modes are supported:
• Active video only – The PPI does not read in any data
between the end of active video (EAV) and start of active
video (SAV) preamble symbols, or any data present during
the vertical blanking intervals. In this mode, the control
byte sequences are not stored to memory; they are filtered
by the PPI.
PROGRAMMABLE FLAGS (PFx)
The ADSP-BF531/ADSP-BF532 processor has 16 bidirectional,
general-purpose programmable flag (PF15–0) pins. Each programmable flag can be individually controlled by manipulation
of the flag control, status and interrupt registers:
• Vertical blanking only – The PPI only transfers vertical
blanking interval (VBI) data, as well as horizontal blanking
information and control byte sequences on VBI lines.
• Flag direction control register – Specifies the direction of
each individual PFx pin as input or output.
• Flag control and status registers – The ADSP-BF531/
ADSP-BF532 processor employs a “write one to modify”
mechanism that allows any combination of individual flags
to be modified in a single instruction, without affecting the
level of any other flags. Four control registers are provided.
One register is written in order to set flag values, one register is written in order to clear flag values, one register is
written in order to toggle flag values, and one register is
written in order to specify a flag value. Reading the flag status register allows software to interrogate the sense of the
flags.
• Flag interrupt mask registers – The two flag interrupt mask
registers allow each individual PFx pin to function as an
interrupt to the processor. Similar to the two flag control
registers that are used to set and clear individual flag values,
one flag interrupt mask register sets bits to enable interrupt
function, and the other flag interrupt mask register clears
bits to disable interrupt function. PFx pins defined as
• Entire field – The entire incoming bitstream is read in
through the PPI. This includes active video, control preamble sequences, and ancillary data that may be embedded in
horizontal and vertical blanking intervals.
Though not explicitly supported, ITU-R 656 output functionality can be achieved by setting up the entire frame structure
(including active video, blanking, and control information) in
memory and streaming the data out the PPI in a frame sync-less
mode. The processor’s 2-D DMA features facilitate this transfer
by allowing the static frame buffer (blanking and control codes)
to be placed in memory once, and simply updating the active
video information on a per-frame basis.
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications. The
modes are divided into four main categories, each allowing up
to 16 bits of data transfer per PPI_CLK cycle:
• Data receive with internally generated frame syncs
• Data receive with externally generated frame syncs
• Data transmit with internally generated frame syncs
• Data transmit with externally generated frame syncs
Rev. D |
Page 11 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
These modes support ADC/DAC connections, as well as video
communication with hardware signaling. Many of the modes
support more than one level of frame synchronization. If
desired, a programmable delay can be inserted between assertion of a frame sync and reception/transmission of data.
DYNAMIC POWER MANAGEMENT
The ADSP-BF531/ADSP-BF532 processor provides five operating modes, each with a different performance/power profile. In
addition, dynamic power management provides the control
functions to dynamically alter the processor core supply voltage,
further reducing power dissipation. Control of clocking to each
of the ADSP-BF531/ADSP-BF532 processor peripherals also
reduces power consumption. See Table 5 for a summary of the
power settings for each mode.
Table 4. Power Domains
Power Domain
All internal logic, except RTC
RTC internal logic and crystal I/O
All other I/O
VDD Range
VDDINT
VDDRTC
VDDEXT
Hibernate Operating Mode—Maximum Static Power
Savings
The hibernate mode maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and
to all the synchronous peripherals (SCLK). The internal voltage
regulator for the processor can be shut off by writing b#00 to
the FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply voltage (VDDINT) to 0 V to provide the lowest static power dissipation.
Any critical information stored internally (memory contents,
register contents, etc.) must be written to a nonvolatile storage
device prior to removing power if the processor state is to be
preserved. Since VDDEXT is still supplied in this mode, all of the
external pins three-state, unless otherwise specified. This allows
other devices that may be connected to the processor to have
power still applied without drawing unwanted current. The
internal supply regulator can be woken up either by a real-time
clock wakeup or by asserting the RESET pin.
Sleep Operating Mode—High Dynamic Power Savings
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled
peripherals run at full speed.
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity will wake up the
processor. When in the sleep mode, assertion of wakeup will
cause the processor to sense the value of the BYPASS bit in the
PLL control register (PLL_CTL). If BYPASS is disabled, the processor will transition to the full-on mode. If BYPASS is enabled,
the processor will transition to the active mode.
Active Operating Mode—Moderate Power Savings
When in the sleep mode, system DMA access to L1 memory is
not supported.
Full-On Operating Mode—Maximum Performance
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the full-on mode is
entered. DMA access is available to appropriately configured L1
memories.
In the active mode, it is possible to disable the PLL through the
PLL control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the full-on or sleep modes.
Table 5. Power Settings
PLL
Mode
PLL
Bypassed
Full-On
Enabled No
Active
Enabled/ Yes
Disabled
Sleep
Enabled
Deep Sleep Disabled
Hibernate Disabled
Core
Clock
(CCLK)
Enabled
Enabled
System
Clock
Core
(SCLK)
Power
Enabled On
Enabled On
Disabled Enabled On
Disabled Disabled On
Disabled Disabled Off
Rev. D |
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but will not be able to
access internal resources or external memory. This powereddown mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in deep sleep mode, an RTC asynchronous interrupt causes the processor to transition to the active mode.
Assertion of RESET while in deep sleep mode causes the processor to transition to the full-on mode.
Power Savings
As shown in Table 4, the ADSP-BF531/ADSP-BF532 processor
supports three different power domains. The use of multiple
power domains maximizes flexibility, while maintaining compliance with industry standards and conventions. By isolating
the internal logic of the ADSP-BF531/ADSP-BF532 processor
into its own power domain, separate from the RTC and other
I/O, the processor can take advantage of dynamic power management, without affecting the RTC or other I/O devices. There
are no sequencing requirements for the various power domains.
Page 12 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
VD D EX T
100µF
10µH
VD D INT
0.1µF
100µF
The dynamic power management feature of the ADSP-BF531/
ADSP-BF532 processor allows both the processor’s input voltage (VDDINT) and clock frequency (fCCLK) to be dynamically
controlled.
2.25V TO 3.6V
INPUT VO LTAGE
RANGE
1µF
FDS9431A
ZHCS1000
VR OU T 1–0
EXTERNAL COMPO NENT S
The savings in power dissipation can be modeled using the
power savings factor and % power savings calculations.
NOTE: VROU T 1–0 SHOULD BE TIED TOGETHER EXTERNALLY
AND DESIG NER SHOULD MINIMIZ E TRACE LENGTH TO FDS9431A.
The power savings factor is calculated as:
Figure 6. Voltage Regulator Circuit
power savings factor
If an external clock is used, it must not be halted, changed, or
operated below the specified frequency during normal operation. This signal is connected to the processor’s CLKIN pin.
When an external clock is used, the XTAL pin must be left
unconnected.
f CCLKRED ⎛ V DDINTRED ⎞ 2 ⎛ t RED ⎞
- × -------------------------- × ----------= -------------------f CCLKNOM ⎝ V DDINTNOM⎠ ⎝ t NOM ⎠
where the variables in the equations are:
fCCLKNOM is the nominal core clock frequency
Alternatively, because the ADSP-BF531/ADSP-BF532 processor
includes an on-chip oscillator circuit, an external crystal may be
used. The crystal should be connected across the CLKIN and
XTAL pins, with two capacitors connected as shown in Figure 7.
Capacitor values are dependent on crystal type and should be
specified by the crystal manufacturer. A parallel-resonant,
fundamental frequency, microprocessor-grade crystal should
be used.
fCCLKRED is the reduced core clock frequency
VDDINTNOM is the nominal internal supply voltage
VDDINTRED is the reduced internal supply voltage
tNOM is the duration running at fCCLKNOM
tRED is the duration running at fCCLKRED
The percent power savings is calculated as:
% power savings = ( 1 – power savings factor ) × 100%
VOLTAGE REGULATION
The Blackfin processor provides an on-chip voltage regulator
that can generate processor core voltage levels 0.85 V to 1.2 V
from an external 2.25 V to 3.6 V supply. Figure 6 shows the typical external components required to complete the power
management system.† The regulator controls the internal logic
voltage levels and is programmable with the voltage regulator
control register (VR_CTL) in increments of 50 mV. To reduce
standby power consumption, the internal voltage regulator can
be programmed to remove power to the processor core while
keeping I/O power (VDDEXT) supplied. While in hibernation,
VDDEXT can still be applied, eliminating the need for external
buffers. The voltage regulator can be activated from this powerdown state either through an RTC wakeup or by asserting
RESET, which will then initiate a boot sequence. The regulator
can also be disabled and bypassed at the user’s discretion.
CLOCK SIGNALS
The ADSP-BF531/ADSP-BF532 processor can be clocked by an
external crystal, a sine wave input, or a buffered, shaped clock
derived from an external clock oscillator.
†
CLKIN
CLKOUT
Figure 7. External Crystal Connections
As shown in Figure 8 on Page 14, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a user programmable 0.5× to 64× multiplication factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10×, but it can be
modified by a software instruction sequence. On-the-fly
frequency changes can be effected by simply writing to the
PLL_DIV register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
See EE-228: Switching Regulator Design Considerations for Blackfin Processors.
Rev. D |
XTAL
Page 13 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
“FI NE” ADJUSTMENT
REQUI RES PLL SEQ UENCING
PLL
0.5× to 64×
CLKIN
BOOTING MODES
“CO ARSE” ADJUSTMENT
ON-THE-FLY
÷ 1, 2, 4, 8
CCLK
÷ 1 to 15
SCLK
The ADSP-BF531/ADSP-BF532 processor has two mechanisms
(listed in Table 8) for automatically loading internal L1 instruction memory after a reset. A third mode is provided to execute
from external memory, bypassing the boot sequence.
VCO
Table 8. Booting Modes
BMODE1–0
00
SCLK ≤ CCLK
SCLK ≤ 133 MHz
01
10
11
Figure 8. Frequency Modification Methods
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 6 illustrates typical system clock ratios.
Table 6. Example System Clock Ratios
Signal Name
SSEL3–0
0001
0011
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, implement the following modes:
• Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
Example Frequency Ratios
Divider Ratio (MHz)
VCO/SCLK
VCO
SCLK
1:1
100
100
3:1
400
133
• Boot from 8-bit or 16-bit external flash memory – The flash
boot routine located in boot ROM memory space is set up
using asynchronous memory bank 0. All configuration settings are set for the slowest device possible (3-cycle hold
time; 15-cycle R/W access times; 4-cycle setup).
The maximum frequency of the system clock is fSCLK. Note that
the divisor ratio must be chosen to limit the system clock frequency to its maximum of fSCLK. The SSEL value can be changed
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
• Boot from SPI serial EEPROM (8-, 16-, or 24-bit
addressable) – The SPI uses the PF2 output pin to select a
single SPI EEPROM device, submits successive read commands at addresses 0x00, 0x0000, and 0x000000 until a
valid 8-, 16-, or 24-bit addressable EEPROM is detected,
and begins clocking data into the beginning of L1 instruction memory.
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 7. This programmable core clock capability is useful for
fast core frequency modifications.
Table 7. Core Clock Ratios
Signal Name
CSEL1–0
00
01
10
11
Divider Ratio
VCO/CCLK
1:1
2:1
4:1
8:1
Example Frequency Ratios
(MHz)
VCO
CCLK
300
300
300
150
400
100
200
25
Description
Execute from 16-bit external memory (bypass
boot ROM)
Boot from 8-bit or 16-bit FLASH
Boot from SPI host slave mode
Boot from SPI serial EEPROM (8-, 16-, or 24-bit
address range)
For each of the boot modes, a 10-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.
In addition, Bit 4 of the reset configuration register can be set by
application code to bypass the normal boot sequence during a
software reset. For this case, the processor jumps directly to the
beginning of L1 instruction memory.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single
Rev. D |
Page 14 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor
resources.
The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/CPU features are optimized for
both 8-bit and 16-bit operations.
• View mixed C/C++ and assembly code (interleaved source
and object information).
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified programming model.
• Set conditional breakpoints on registers, memory,
and stacks.
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data types; and separate user and
supervisor stack pointers.
• Perform linear or statistical profiling of program execution.
• Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded in
16 bits.
• Create custom debugger windows.
The ADSP-BF531/ADSP-BF532 processor is supported with a
complete set of CROSSCORE®† software and hardware development tools, including Analog Devices emulators and
VisualDSP++®‡ development environment. The same emulator
hardware that supports other Blackfin processors also fully
emulates the ADSP-BF531/ADSP-BF532 processor.
The VisualDSP++ project management environment lets programmers develop and debug an application. This environment
includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to processor assembly. The processor
has architectural features that improve the efficiency of compiled C/C++ code.
The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity.
‡
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
• A multi-issue load/store modified Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
DEVELOPMENT TOOLS
†
Statistical profiling enables the programmer to nonintrusively
poll the processor as it is running the program. This feature,
unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without
interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly
and efficiently. By using the profiler, the programmer can focus
on those areas in the program that impact performance and take
corrective action.
CROSSCORE is a registered trademark of Analog Devices, Inc.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
Rev. D |
• Insert breakpoints.
• Trace instruction execution.
• Fill, dump, and graphically plot the contents of memory.
• Perform source level debugging.
The VisualDSP++ IDDE lets programmers define and manage
software development. Its dialog boxes and property pages let
programmers configure and manage all of the Blackfin development tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
• Control how the development tools process inputs and
generate outputs
• Maintain a one-to-one correspondence with the tool’s
command line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the memory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error prone tasks
and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the
system state, when debugging an application that uses the VDK.
VCSE is Analog Devices technology for creating, using, and
reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software
Page 15 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
applications. Components can be downloaded from the Web
and dropped into the application. Component archives can be
published from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language.
Use the expert linker to visually manipulate the placement of
code and data on the embedded system. View memory utilization in a color coded graphical form, easily move code and data
to different areas of the processor or external memory with the
drag of the mouse, and examine runtime stack and heap usage.
The expert linker is fully compatible with existing linker definition file (LDF), allowing the developer to move between the
graphical and textual environments.
Reference on the Analog Devices website (www.analog.com)—
use site search on “EE-68.” This document is updated regularly
to keep pace with improvements to emulator support.
RELATED DOCUMENTS
The following publications that describe the ADSP-BF531/
ADSP-BF532 processors (and related processors) can be
ordered from any Analog Devices sales office or accessed electronically on our website:
Analog Devices emulators use the IEEE 1149.1 JTAG test access
port of the ADSP-BF531/ADSP-BF532 processor to monitor
and control the target board processor during emulation. The
emulator provides full speed emulation, allowing inspection and
modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the
processor’s JTAG interface—the emulator does not affect target
system loading or timing.
• Getting Started With Blackfin Processors
• ADSP-BF533 Blackfin Processor Hardware Reference
• ADSP-BF53x/BF56x Blackfin Processor Programming
Reference
• ADSP-BF531/ADSP-BF532 Blackfin Processor Anomaly List
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the Blackfin processor family. Hardware tools include Blackfin processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.
EZ-KIT Lite Evaluation Board
For evaluation of ADSP-BF531/ADSP-BF532 processors, use
the ADSP-BF531/ADSP-BF532 EZ-KIT Lite® board available
from Analog Devices. Order part number ADDSBF533-EZLITE. The board comes with on-chip emulation capabilities and is equipped to enable software development.
Multiple daughter cards are available.
DESIGNING AN EMULATOR-COMPATIBLE
PROCESSOR BOARD
The Analog Devices family of emulators are tools that every system developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG test
access port (TAP) on each JTAG processor. The emulator uses
the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe
variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an
operation has been completed by the emulator, the processor
system is set running at full speed with no impact on
system timing.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Rev. D |
Page 16 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
PIN DESCRIPTIONS
ADSP-BF531/ADSP-BF532 processor pin definitions are listed
in Table 9.
All pins are three-stated during and immediately after reset,
except the memory interface, asynchronous memory control,
and synchronous memory control pins, which are driven high.
If BR is active, then the memory pins are also three-stated. All
unused I/O pins have their input buffers disabled with the
exception of the pins that need pull-ups or pull-downs as noted
in the table footnotes.
In order to maintain maximum functionality and reduce package size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate functionality is shown in italics.
Table 9. Pin Descriptions
Type Function
Driver
Type1 Pull-Up/Down Requirement
ADDR19–1
O
Address Bus for Async/Sync Access
A
None
DATA15–0
I/O
Data Bus for Async/Sync Access
A
None
ABE1–0/SDQM1–0
O
Byte Enables/Data Masks for Async/Sync Access A
None
BR
I
Bus Request
Pull-up Required If Function Not Used
BG
O
Bus Grant
A
None
BGH
O
Bus Grant Hang
A
None
AMS3–0
O
Bank Select
A
None
ARDY
I
Hardware Ready Control
AOE
O
Output Enable
A
None
ARE
O
Read Enable
A
None
AWE
O
Write Enable
A
None
SRAS
O
Row Address Strobe
A
None
SCAS
O
Column Address Strobe
A
None
SWE
O
Write Enable
A
None
SCKE
O
Clock Enable
A
None
CLKOUT
O
Clock Output
B
None
SA10
O
A10 Pin
A
None
SMS
O
Bank Select
A
None
TMR0
I/O
Timer 0
C
None
TMR1/PPI_FS1
I/O
Timer 1/PPI Frame Sync1
C
None
TMR2/PPI_FS2
I/O
Timer 2/PPI Frame Sync2
C
None
Pin Name
Memory Interface
Asynchronous Memory Control
Pull-up Required If Function Not Used
Synchronous Memory Control
Timers
Rev. D |
Page 17 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
Table 9. Pin Descriptions (Continued)
Type Function
Driver
Type1 Pull-Up/Down Requirement
PF0/SPISS
I/O
Programmable Flag 0/SPI Slave Select Input
C
None
PF1/SPISEL1/TMRCLK
I/O
Programmable Flag 1/SPI Slave Select
Enable 1/External Timer Reference
C
None
PF2/SPISEL2
I/O
Programmable Flag 2/SPI Slave Select Enable 2
C
None
PF3/SPISEL3/PPI_FS3
I/O
Programmable Flag 3/SPI Slave Select
Enable 3/PPI Frame Sync 3
C
None
PF4/SPISEL4/PPI15
I/O
Programmable Flag 4/SPI Slave Select
Enable 4/PPI 15
C
None
PF5/SPISEL5/PPI14
I/O
Programmable Flag 5/SPI Slave Select
Enable 5/PPI 14
C
None
PF6/SPISEL6/PPI13
I/O
Programmable Flag 6/SPI Slave Select
Enable 6/PPI 13
C
None
PF7/SPISEL7/PPI12
I/O
Programmable Flag 7/SPI Slave Select
Enable 7/PPI 12
C
None
PF8/PPI11
I/O
Programmable Flag 8/PPI 11
C
None
PF9/PPI10
I/O
Programmable Flag 9/PPI 10
C
None
PF10/PPI9
I/O
Programmable Flag 10/PPI 9
C
None
PF11/PPI8
I/O
Programmable Flag 11/PPI 8
C
None
PF12/PPI7
I/O
Programmable Flag 12/PPI 7
C
None
PF13/PPI6
I/O
Programmable Flag 13/PPI 6
C
None
PF14/PPI5
I/O
Programmable Flag 14/PPI 5
C
None
PF15/PPI4
I/O
Programmable Flag 15/PPI 4
C
None
PPI3–0
I/O
PPI3–0
C
None
PPI_CLK
I
PPI Clock
C
None
TCK
I
JTAG Clock
TDO
O
JTAG Serial Data Out
TDI
I
JTAG Serial Data In
Internal Pull-down
TMS
I
JTAG Mode Select
Internal Pull-down
TRST
I
JTAG Reset
External Pull-down If JTAG Not Used
EMU
O
Emulation Output
C
None
MOSI
I/O
Master Out Slave In
C
None
MISO
I/O
Master In Slave Out
C
Pull HIGH Through a 4.7 kΩ Resistor
if Booting via the SPI Port.
SCK
I/O
SPI Clock
D
None
Pin Name
Parallel Peripheral Interface Port/GPIO
JTAG Port
Internal Pull-down
C
None
SPI Port
Rev. D |
Page 18 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
Table 9. Pin Descriptions (Continued)
Pin Name
Driver
Type1 Pull-Up/Down Requirement
Type Function
Serial Ports
RSCLK0
I/O
SPORT0 Receive Serial Clock
D
None
RFS0
I/O
SPORT0 Receive Frame Sync
C
None
DR0PRI
I
SPORT0 Receive Data Primary
None
DR0SEC
I
SPORT0 Receive Data Secondary
None
TSCLK0
I/O
SPORT0 Transmit Serial Clock
D
None
TFS0
I/O
SPORT0 Transmit Frame Sync
C
None
DT0PRI
O
SPORT0 Transmit Data Primary
C
None
DT0SEC
O
SPORT0 Transmit Data Secondary
C
None
RSCLK1
I/O
SPORT1 Receive Serial Clock
D
None
RFS1
I/O
SPORT1 Receive Frame Sync
C
None
DR1PRI
I
SPORT1 Receive Data Primary
DR1SEC
I
SPORT1 Receive Data Secondary
TSCLK1
I/O
SPORT1 Transmit Serial Clock
D
None
TFS1
I/O
SPORT1 Transmit Frame Sync
C
None
DT1PRI
O
SPORT1 Transmit Data Primary
C
None
DT1SEC
O
SPORT1 Transmit Data Secondary
C
None
RX
I
UART Receive
TX
O
UART Transmit
RTXI
I
RTC Crystal Input
Pull LOW when not used
RTXO
O
RTC Crystal Output
N/A
CLKIN
I
Clock/Crystal Input
Needs to be at a Level or Clocking
XTAL
O
Crystal Output
None
RESET
I
Reset
Always Active if Core Power On
NMI
I
Nonmaskable Interrupt
Pull LOW when not used
BMODE1–0
I
Boot Mode Strap
Pull-up or Pull-down Required
O
External FET Drive
N/A
None
None
UART Port
None
C
None
Real-Time Clock
Clock
Mode Controls
Voltage Regulator
VROUT1–0
Supplies
1
VDDEXT
P
I/O Power Supply
N/A
VDDINT
P
Core Power Supply
N/A
VDDRTC
P
Real-Time Clock Power Supply
N/A
GND
G
External Ground
N/A
Refer to Figure 28 on Page 43 to Figure 39 on Page 44.
Rev. D |
Page 19 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
SPECIFICATIONS
Component specifications are subject to change
without notice.
OPERATING CONDITIONS
Parameter
Min Nominal
Max Unit
VDDINT Internal Supply Voltage
1, 2
Conditions
0.8
1.2
1.32
V
VDDINT Internal Supply Voltage
1, 3
0.95 1.2
1.32
V
2
VDDEXT External Supply Voltage
1.75 1.8/2.5/3.3 3.6
V
VDDEXT External Supply Voltage3, 4
2.7
3.6
V
VDDRTC Real-Time Clock
Power Supply Voltage2
1.75 1.8/2.5/3.3 3.6
V
VDDRTC Real-Time Clock
Power Supply Voltage3, 4
2.7
3.6
V
3.3
3.3
VIH
High Level Input Voltage5, 6
VDDEXT =1.85 V
1.3
1.85
V
VIH
5, 6
VDDEXT =Maximum
2.0
3.6
V
7
V
High Level Input Voltage
VIHCLKIN High Level Input Voltage
VDDEXT =Maximum
2.2
3.6
VIL
Low Level Input Voltage5, 8
VDDEXT =1.75 V
–0.3
+0.3 V
VIL
Low Level Input Voltage5, 8
VDDEXT =2.25 V
–0.3
+0.6 V
TJ
Junction Temperature
160-Ball Chip Scale Ball Grid Array (Mini-BGA) @ TAMBIENT = –40°C to +85°C –40
+100 °C
TJ
Junction Temperature
160-Ball Chip Scale Ball Grid Array (Mini-BGA) @ TAMBIENT = –40°C to +105°C –40
+125 °C
TJ
Junction Temperature
169-Ball Plastic Ball Grid Array (PBGA) @ TAMBIENT = –40°C to +85°C
–40
+100 °C
TJ
Junction Temperature
169-Ball Plastic Ball Grid Array (PBGA) @ TAMBIENT = –40°C to +105°C
–40
+125 °C
TJ
Junction Temperature
176-Lead Quad Flatpack (LQFP) @ TAMBIENT = –40°C to +85°C
–40
+100 °C
1
The regulator can generate VDDINT at levels of 0.85 V to 1.2 V with –5 % to +10 % tolerance.
Nonautomotive grade parts, see Ordering Guide on Page 60.
3
Automotive grade parts, see Ordering Guide on Page 60.
4
Automotive grade parts in 169-Ball Plastic Ball Grid Array (PBGA) package, see Ordering Guide on Page 60.
5
The ADSP-BF531/ADSP-BF532 processors are 3.3 V tolerant (always accepts up to 3.6 V maximum VIH), but voltage compliance (on outputs, VOH) depends on the input
VDDEXT, because VOH (maximum) approximately equals VDDEXT (maximum). This 3.3 V tolerance applies to bidirectional pins (DATA15–0, TMR2–0, PF15–0, PPI3–0, RSCLK1–0,
TSCLK1–0, RFS1–0, TFS1–0, MOSI, MISO, SCK) and input only pins (BR, ARDY, PPI_CLK, DR0PRI, DR0SEC, DR1PRI, DR1SEC, RX, RTXI, TCK, TDI, TMS, TRST,
CLKIN, RESET, NMI, and BMODE1–0).
6
Parameter value applies to all input and bidirectional pins except CLKIN.
7
Parameter value applies to CLKIN pin only.
8
Parameter value applies to all input and bidirectional pins.
2
Rev. D |
Page 20 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
Min Typical Max Unit
VOH
High Level Output Voltage
1
@ VDDEXT = 1.75 V, IOH = –0.5 mA
1.5
V
VOH
High Level Output Voltage1
@ VDDEXT = 2.25 V, IOH = –0.5 mA
1.9
V
VOH
High Level Output Voltage
1
@ VDDEXT = 3.0 V, IOH = –0.5 mA
2.4
V
VOL
Low Level Output Voltage
1
@ VDDEXT = 1.75 V, IOL = 2.0 mA
0.2
V
Low Level Output Voltage
1
@ VDDEXT = 2.25 V/3.0 V, IOL = 2.0 mA
0.4
V
@ VDDEXT = Maximum, VIN = VDD Maximum
10.0 µA
@ VDDEXT = Maximum, VIN = VDD Maximum
50.0 µA
VOL
2
IIH
High Level Input Current
IIHP
High Level Input Current JTAG3
4
Low Level Input Current
IIL
IOZH
IOZL
4
2
@ VDDEXT = Maximum, VIN = 0 V
10.0 µA
Three-State Leakage Current
5
@ VDDEXT = Maximum, VIN = VDD Maximum
10.0 µA
Three-State Leakage Current
5
@ VDDEXT = Maximum, VIN = 0 V
10.0 µA
Input Capacitance6
fIN = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V
4
VDDINT Current in Hibernate Mode
VDDEXT = 3.65 V with voltage regulator off (VDDINT = 0 V)
50
µA
VDDINT Current in Deep Sleep Mode
VDDINT = 0.8 V, TJUNCTION = 25°C
7.5
mA
IDDSLEEP
VDDINT Current in Sleep Mode
VDDINT = 0.8 V, TJUNCTION = 25°C
10
mA
IDD_TYP8, 9
VDDINT Current Dissipation (Typical)
VDDINT = 0.8 V, fIN = 50 MHz, TJUNCTION = 25°C
20
mA
8, 9
VDDINT Current Dissipation (Typical)
VDDINT = 1.14 V, fIN = 400 MHz, TJUNCTION = 25°C
132
mA
VDDRTC Current
VDDRTC = 3.3 V, TJUNCTION = 25°C
20
µA
CIN
IDDHIBERNATE
IDDDEEPSLEEP
IDD_TYP
IDDRTC
8
1
Applies to output and bidirectional pins.
Applies to input pins except JTAG inputs.
3
Applies to JTAG input pins (TCK, TDI, TMS, TRST).
4
Absolute value.
5
Applies to three-statable pins.
6
Applies to all signal pins.
7
Guaranteed, but not tested.
8
See Power Dissipation on Page 45.
9
Processor executing 75% dual MAC, 25% ADD with moderate data bus activity.
2
Rev. D |
Page 21 of 60 |
August 2006
87
pF
ADSP-BF531/ADSP-BF532
ABSOLUTE MAXIMUM RATINGS
PACKAGE INFORMATION
Stresses greater than those listed in the table may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
The information presented in Figure 9 and Table 11 provides
information about how to read the package brand and relate it
to specific product features. For a complete listing of product
offerings, see the Ordering Guide on Page 60.
a
ADSP-BF531
Parameter
Rating
Internal (Core) Supply Voltage (VDDINT)
–0.3 V to +1.4 V
External (I/O) Supply Voltage (VDDEXT)
–0.5 V to +3.8 V
yyww country_of_origin
–0.5 V to +3.8 V
B
tppZccc
Input Voltage
1
vvvvvv.x n.n
Output Voltage Swing
–0.5 V to VDDEXT +0.5 V
Load Capacitance
200 pF
Storage Temperature Range
–65°C to +150°C
Junction Temperature Under Bias
125°C
1
Figure 9. Product Information on Package
Table 11. Package Brand Information
Applies to 100% transient duty cycle. For other duty cycles see Table 10.
Table 10. Maximum Duty Cycle for Input Transient Voltage1
VIN Min (V)
VIN Max (V)
Maximum Duty Cycle
–0.50
+3.80
100%
–0.70
+4.00
40%
–0.80
+4.10
25%
–0.90
+4.20
15%
–1.00
+4.30
10%
1
Brand Key
Field Description
t
Temperature Range
pp
Package Type
Z
Lead Free Option (Optional)
ccc
See Ordering Guide
vvvvvv.x
Assembly Lot Code
n.n
Silicon Revision
yyww
Date Code
Applies to all signal pins with the exception of CLKIN, XTAL, VROUT1–0.
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the
ADSP-BF531/ADSP-BF532 processor features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. D |
Page 22 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
TIMING SPECIFICATIONS
Table 12 through Table 14 describe the timing requirements for
the ADSP-BF531/ADSP-BF532 processor clocks. Take care in
selecting MSEL, SSEL, and CSEL ratios so as not to exceed the
maximum core clock and system clock as described in Absolute
Maximum Ratings on Page 22, and the voltage controlled oscillator (VCO) operating frequencies described in Table 13.
Table 13 describes phase-locked loop operating conditions.
Table 12. Core Clock Requirements
TJUNCTION = 125°C
Min
Max
2.50
3.00
3.39
Parameter
tCCLK Core Cycle Period (VDDINT =1.14 V minimum)
tCCLK Core Cycle Period (VDDINT =1.045 V minimum)
tCCLK Core Cycle Period (VDDINT =0.95 V minimum)
tCCLK Core Cycle Period (VDDINT =0.85 V minimum)
tCCLK Core Cycle Period (VDDINT =0.8 V )
1
All1 Other TJUNCTION
Min
Max
2.50
2.75
3.00
3.57
4.00
Unit
ns
ns
ns
ns
ns
See Operating Conditions on Page 20.
Table 13. Phase-Locked Loop Operating Conditions
Parameter
fVCO Voltage Controlled Oscillator (VCO) Frequency
Min
50
Max
Maximum fCCLK
Unit
MHz
Table 14. Maximum SCLK Conditions
Parameter1
MBGA/PBGA
fSCLK
fSCLK
LQFP
fSCLK
fSCLK
1
VDDEXT = 1.8 V
VDDEXT = 2.5 V
VDDEXT = 3.3 V
Unit
CLKOUT/SCLK Frequency (VDDINT ≥ 1.14 V)
CLKOUT/SCLK Frequency (VDDINT < 1.14 V)
100
100
133
100
133
100
MHz
MHz
CLKOUT/SCLK Frequency (VDDINT ≥ 1.14 V)
CLKOUT/SCLK Frequency (VDDINT < 1.14 V)
100
83
133
83
133
83
MHz
MHz
tSCLK (= 1/fSCLK) must be greater than or equal to tCCLK.
Rev. D |
Page 23 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
Clock and Reset Timing
Table 15 and Figure 10 describe clock and reset operations. Per
Absolute Maximum Ratings on Page 22, combinations of
CLKIN and clock multipliers must not select core/peripheral
clocks in excess of 400 MHz/133 MHz.
Table 15. Clock and Reset Timing
Parameter
Timing Requirements
tCKIN
CLKIN Period
tCKINL
CLKIN Low Pulse2
CLKIN High Pulse1
tCKINH
tWRST
RESET Asserted Pulse Width Low3
1
Min
Max
Unit
25.0
10.0
10.0
11 tCKIN
100.01
ns
ns
ns
ns
If DF bit in PLL_CTL register is set, then the maximum tCKIN period is 50 ns.
Applies to bypass mode and nonbypass mode.
3
Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2,000 CLKIN cycles, while RESET is asserted,
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
2
tCKIN
CLKIN
tCKINL
tCKINH
tWRST
RESET
Figure 10. Clock and Reset Timing
Rev. D |
Page 24 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
Asynchronous Memory Read Cycle Timing
Table 16. Asynchronous Memory Read Cycle Timing
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Min Max Min
Max
Unit
Parameter
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
tHDAT
DATA15–0 Hold After CLKOUT
tSARDY
ARDY Setup Before CLKOUT
tHARDY
ARDY Hold After CLKOUT
Switching Characteristics
Output Delay After CLKOUT1
tDO
tHO
Output Hold After CLKOUT 1
1
2.1
1.0
4.0
1.0
2.1
0.8
4.0
0.0
ns
ns
ns
ns
6.0
6.0
1.0
ns
ns
0.8
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
SETUP
2 CYCLES
PROGRAMMED READ ACCESS
4 CYCLES
HOLD
1 CYCLE
ACCESS EXTENDED
3 CYCLES
CLKOUT
t DO
t HO
AMSx
ABE1–0
ABE, ADDRESS
ADDR19–1
AOE
t DO
tHO
ARE
t SARDY
t HARDY
tHARDY
ARDY
t SARDY
t SDAT
tHDAT
DATA15–0
READ
Figure 11. Asynchronous Memory Read Cycle Timing
Rev. D |
Page 25 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
Asynchronous Memory Write Cycle Timing
Table 17. Asynchronous Memory Write Cycle Timing
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Min Max Min
Max
Unit
Parameter
Timing Requirements
tSARDY
ARDY Setup Before CLKOUT
tHARDY
ARDY Hold After CLKOUT
Switching Characteristics
tDDAT
DATA15–0 Disable After CLKOUT
tENDAT
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT1
tDO
tHO
Output Hold After CLKOUT 1
1
4.0
1.0
6.0
1.0
PROGRAMMED WRITE
ACCESS 2 CYCLES
ACCESS
EXTENDED
1 CYCLE
HOLD
1 CYCLE
CLKOUT
t DO
t HO
AMSx
ABE1–0
ABE, ADDRESS
ADDR19–1
tDO
tHO
AWE
t HARDY
t SARDY
ARDY
tSARDY
t ENDAT
DATA15–0
t DD AT
WRITE DATA
Figure 12. Asynchronous Memory Write Cycle Timing
Rev. D |
Page 26 of 60 |
August 2006
ns
ns
6.0
1.0
6.0
1.0
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
SETUP
2 CYCLES
4.0
0.0
6.0
0.8
ns
ns
ns
ns
ADSP-BF531/ADSP-BF532
SDRAM Interface Timing
Table 18. SDRAM Interface Timing1
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Min Max Min
Max
Unit
Parameter
Timing Requirements
tSSDAT
DATA Setup Before CLKOUT
tHSDAT
DATA Hold After CLKOUT
Switching Characteristics
tSCLK
CLKOUT Period2
tSCLKH
CLKOUT Width High
CLKOUT Width Low
tSCLKL
tDCAD
Command, ADDR, Data Delay After CLKOUT3
tHCAD
Command, ADDR, Data Hold After CLKOUT1
tDSDAT
Data Disable After CLKOUT
tENSDAT
Data Enable After CLKOUT
2.1
0.0
1.5
0.8
ns
ns
10.0
2.5
2.5
7.5
2.5
2.5
ns
ns
ns
ns
ns
ns
ns
6.0
4.0
1.0
1.0
6.0
4.0
1.0
1.0
1
SDRAM timing for TJUNCTION = 125°C is limited to 100 MHz.
Refer to Table 14 on Page 23 for maximum fSCLK at various VDDINT.
3
Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
2
tSCLK
tSCLKH
CLKOUT
tSSDAT
tSCLKL
tH SDAT
DATA(IN)
tDC AD
tENSDAT
tHCAD
DATA(OUT)
tDCAD
CMND ADDR
(OUT)
tHCAD
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 13. SDRAM Interface Timing
Rev. D |
Page 27 of 60 |
tDSDAT
August 2006
ADSP-BF531/ADSP-BF532
External Port Bus Request and Grant Cycle Timing
Table 19 and Figure 14 describe external port bus request and
bus grant operations.
Table 19. External Port Bus Request and Grant Cycle Timing
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Min Max Min
Max
Unit
Parameter
Timing Requirements
tBS
BR Asserted to CLKOUT High Setup
tBH
CLKOUT High to BR Deasserted Hold Time
Switching Characteristics
CLKOUT Low to xMS, Address, and RD/WR Disable
tSD
tSE
CLKOUT Low to xMS, Address, and RD/WR Enable
tDBG
CLKOUT High to BG High Setup
tEBG
CLKOUT High to BG Deasserted Hold Time
tDBH
CLKOUT High to BGH High Setup
tEBH
CLKOUT High to BGH Deasserted Hold Time
4.6
1.0
4.6
0.0
ns
ns
4.5
4.5
4.6
4.6
4.6
4.6
4.5
4.5
3.6
3.6
3.6
3.6
CLKOUT
tBS
tBH
BR
tSD
tSE
AMSx
tSD
tSE
ADDR19-1
ABE1-0
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
BGH
Figure 14. External Port Bus Request and Grant Cycle Timing
Rev. D |
Page 28 of 60 |
August 2006
tEBH
ns
ns
ns
ns
ns
ns
ADSP-BF531/ADSP-BF532
Parallel Peripheral Interface Timing
Table 20 and Figure 15 on Page 29 describe parallel peripheral
interface operations.
Table 20. Parallel Peripheral Interface Timing
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Min Max Min
Max
Unit
Parameter
Timing Requirements
tPCLKW
PPI_CLK Width
tPCLK
PPI_CLK Period1
tSFSPE
External Frame Sync Setup Before PPI_CLK Edge
(Nonsampling Edge for Rx, Sampling Edge for Tx)
tHFSPE
External Frame Sync Hold After PPI_CLK
tSDRPE
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
tHDRPE
Switching Characteristics—GP Output and Frame Capture Modes
tDFSPE
Internal Frame Sync Delay After PPI_CLK
tHOFSPE
Internal Frame Sync Hold After PPI_CLK
tDDTPE
Transmit Data Delay After PPI_CLK
tHDTPE
Transmit Data Hold After PPI_CLK
1
1.0
3.5
1.5
ns
ns
ns
1.8
DATA0
IS
SAMPLED
PPI_CLK
POLC = 1
DFSPE
tHOFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
tHDRPE
PPI_DATA
Figure 15. PPI GP Rx Mode with Internal Frame Sync Timing
Rev. D |
1.0
3.5
1.5
8.0
1.7
9.0
PPI_CLK
tSDRPE
ns
ns
ns
1.7
POLC = 0
t
6.0
15.0
4.0
8.0
PPI_CLK frequency cannot exceed fSCLK/2
FRAME
SYNC IS
DRIVEN
OUT
6.0
15.0
6.0
Page 29 of 60 |
August 2006
9.0
1.8
ns
ns
ns
ns
ADSP-BF531/ADSP-BF532
DATA0 IS
SAMPLED
FRAME
SYNC IS
SAMPLED
FOR
DATA0
DATA1 IS
SAMPLED
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
t
HFSPE
tSFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
t
t
SDRPE
HDRPE
PPI_DATA
Figure 16. PPI GP Rx Mode with External Frame Sync Timing
FRAME
SYNC IS
SAMPLED
DATA0 IS
DRIVEN
OUT
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
t
HFSPE
t
SFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
t
HDTPE
PPI_DATA
DATA0
t
DDTPE
Figure 17. PPI GP Tx Mode with External Frame Sync Timing
Rev. D |
Page 30 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
FRAME
SYNC IS
DRIVEN
OUT
DATA0 IS
DRIVEN
OUT
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
t
DFSPE
tHOFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
tDDTPE
t
HDTPE
PPI_DATA
DATA0
Figure 18. PPI GP Tx Mode with Internal Frame Sync Timing
Rev. D |
Page 31 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
Serial Ports
Table 21 on Page 32 through Table 24 on Page 33 and Figure 19
on Page 34 through Figure 21 on Page 36 describe Serial Port
operations.
Table 21. Serial Ports—External Clock
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Min Max Min
Max
Unit
Parameter
Timing Requirements
tSFSE
TFS/RFS Setup Before TSCLK/RSCLK1
tHFSE
TFS/RFS Hold After TSCLK/RSCLK1
tSDRE
Receive Data Setup Before RSCLK1
tHDRE
Receive Data Hold After RSCLK1
tSCLKEW TSCLK/RSCLK Width
TSCLK/RSCLK Period
tSCLKE
Switching Characteristics
tDFSE
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)2
tHOFSE
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1
tDDTE
Transmit Data Delay After TSCLK1
tHDTE
Transmit Data Hold After TSCLK1
1
2
3.0
3.0
3.0
3.0
4.5
15.0
3.0
3.0
3.0
3.0
4.5
15.0
10.0
0.0
ns
ns
ns
ns
ns
ns
10.0
0.0
10.0
0.0
10.0
0.0
ns
ns
ns
ns
Referenced to sample edge.
Referenced to drive edge.
Table 22. Serial Ports—Internal Clock
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Min Max Min
Max
Unit
Parameter
Timing Requirements
tSFSI
TFS/RFS Setup Before TSCLK/RSCLK1
tHFSI
TFS/RFS Hold After TSCLK/RSCLK1
tSDRI
Receive Data Setup Before RSCLK1
tHDRI
Receive Data Hold After RSCLK1
tSCLKEW TSCLK/RSCLK Width
tSCLKE
TSCLK/RSCLK Period
Switching Characteristics
tDFSI
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)2
tHOFSI
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1
tDDTI
Transmit Data Delay After TSCLK1
Transmit Data Hold After TSCLK1
tHDTI
tSCLKIW TSCLK/RSCLK Width
1
2
11.0
−2.0
9.0
0.0
4.5
15.0
3.0
−1.0
−2.0
4.5
Page 32 of 60 |
August 2006
ns
ns
ns
ns
ns
ns
3.0
−1.0
3.0
Referenced to sample edge.
Referenced to drive edge.
Rev. D |
9.0
−2.0
9.0
0.0
4.5
15.0
3.0
−2.0
4.5
ns
ns
ns
ns
ns
ADSP-BF531/ADSP-BF532
Table 23. Serial Ports—Enable and Three-State
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Min Max Min
Max
Unit
Parameter
Switching Characteristics
tDTENE
Data Enable Delay from External TSCLK1
tDDTTE
Data Disable Delay from External TSCLK1
tDTENI
Data Enable Delay from Internal TSCLK1
tDDTTI
Data Disable Delay from Internal TSCLK1
1
0
0
10.0
−2.0
10.0
−2.0
3.0
3.0
ns
ns
ns
ns
Referenced to drive edge.
Table 24. External Late Frame Sync
Parameter
Switching Characteristics
tDDTLFSE Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 01, 2
tDTENLFS Data Enable from Late FS or MCE = 1, MFD = 01,2
1
2
MCE = 1, TFS enable and TFS valid follow tDTENLFS and tDDTLFSE.
If external RFS/TFS setup to RSCLK/TSCLK > tSCLKE/2, then tDDTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply.
Rev. D |
Page 33 of 60 |
August 2006
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Min Max Min
Max
Unit
10.0
0
10.0
0
ns
ns
ADSP-BF531/ADSP-BF532
DATA RECEIVE—INTERNAL CLOCK
DATA RECEIVE—EXTERNAL CLOCK
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKEW
RSCLK
RSCLK
tDFSE
tDFSE
tHOFSE
tSFSI
tHFSI
tHOFSE
RFS
tSFSE
tHFSE
tSDRE
tHDRE
RFS
tSDRI
tHDRI
DR
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT—INTERNAL CLOCK
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKEW
TSCLK
TSCLK
tDFSI
tHOFSI
tDFSE
tSFSI
tHFSI
tHOFSE
TFS
tSFSE
TFS
tDDTI
tDDTE
tHDTI
tHDTE
DT
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
TSCLK (EXT)
TFS ("LATE", EXT.)
TSCLK / RSCLK
tDDTTE
tDTENE
DT
DRIVE
EDGE
DRIVE
EDGE
TSCLK (INT)
TFS ("LATE", INT.)
TSCLK / RSCLK
tDTENI
tDDTTI
DT
Figure 19. Serial Ports
Rev. D |
Page 34 of 60 |
August 2006
tHFSE
ADSP-BF531/ADSP-BF532
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RSCLK
tHOFSE/I
tSFSE/I
RFS
tDDTE/I
tDTENLFS
tHDTE/I
1ST BIT
DT
2ND BIT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TSCLK
tSFSE/I
tHOFSE/I
TFS
tDDTE/I
tDTENLFS
DT
tHDTE/I
1ST BIT
2ND BIT
tDDTLFSE
Figure 20. External Late Frame Sync (Frame Sync Setup < tSCLKE/2)
Rev. D |
Page 35 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RSCLK
tSFSE/I
tHOFSE/I
RFS
tDDTE/I
tHDTE/I
tDTENLSCK
DT
1ST BIT
2ND BIT
tDDTLSCK
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TSCLK
tSFSE/I
tHOFSE/I
TFS
tDDTE/I
tDTENLSCK
DT
tHDTE/I
1ST BIT
2ND BIT
tDDTLSCK
Figure 21. External Late Frame Sync (Frame Sync Setup > tSCLKE/2)
Rev. D |
Page 36 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
Serial Peripheral Interface (SPI) Port
—Master Timing
Table 25 and Figure 22 describe SPI port master operations.
Table 25. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
tSSPIDM
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
tHSPIDM
Switching Characteristics
tSDSCIM
SPISELx Low to First SCK Edge (x=0 or x=1)
tSPICHM
Serial Clock High Period
tSPICLM
Serial Clock Low Period
tSPICLK
Serial Clock Period
Last SCK Edge to SPISELx High (x=0 or x=1)
tHDSM
tSPITDM
Sequential Transfer Delay
tDDSPIDM
SCK Edge to Data Out Valid (Data Out Delay)
tHDSPIDM
SCK Edge to Data Out Invalid (Data Out Hold)
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Min
Max Min
Max
Unit
8.5
–1.5
7.5
–1.5
ns
ns
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
0
6
–1.0
+4.0
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
0
–1.0
ns
ns
ns
ns
ns
ns
ns
ns
SPISELx
(OUTPUT)
tSDSCIM
tSPICHM
tSPICLM
tSPICLM
tSPICHM
tSPICLK
tHDSM
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
tDDSPIDM
MOSI
(OUTPUT)
tHDSPIDM
MSB
CPHA = 1
tSSPIDM
MISO
(INPUT)
LSB
tHSPIDM
tSSPIDM
MSB VALID
LSB VALID
tDDSPIDM
MOSI
(OUTPUT)
CPHA = 0
tHDSPIDM
MSB
tSSPIDM
MISO
(INPUT)
tHSPIDM
LSB
tHSPIDM
MSB VALID
LSB VALID
Figure 22. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. D |
Page 37 of 60 |
August 2006
tSPITDM
6
+4.0
ADSP-BF531/ADSP-BF532
Serial Peripheral Interface (SPI) Port
—Slave Timing
Table 26 and Figure 23 describe SPI port slave operations.
Table 26. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
tSPICHS
Serial Clock High Period
Serial Clock Low Period
tSPICLS
tSPICLK
Serial Clock Period
tHDS
Last SCK Edge to SPISS Not Asserted
tSPITDS
Sequential Transfer Delay
tSDSCI
SPISS Assertion to First SCK Edge
tSSPID
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
tHSPID
Switching Characteristics
tDSOE
SPISS Assertion to Data Out Active
tDSDHI
SPISS Deassertion to Data High Impedance
tDDSPID
SCK Edge to Data Out Valid (Data Out Delay)
tHDSPID
SCK Edge to Data Out Invalid (Data Out Hold)
VDDEXT = 1.8 V
Min
Max
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
1.6
1.6
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
1.6
1.6
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
9
9
10
10
0
0
0
0
SPISS
(INPUT)
tSPICHS
tSPICLS
tSPICLS
tSPICHS
tSPICLK
tHDS
tSPITDS
SCK
(CPOL = 0)
(INPUT)
tSDSCI
SCK
(CPOL = 1)
(INPUT)
tDSOE
tDDSPID
tHDSPID
MISO
(OUTPUT)
tDSDHI
MSB
CPHA = 1
tSSPID
MOSI
(INPUT)
LSB
tHSPID
tSSPID
tHSPID
MSB VALID
tDSOE
MISO
(OUTPUT)
tDDSPID
LSB VALID
tDDSPID
tDSDHI
MSB
LSB
tHSPID
CPHA = 0
tSSPID
MOSI
(INPUT)
MSB VALID
LSB VALID
Figure 23. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. D |
Page 38 of 60 |
August 2006
8
8
10
10
ns
ns
ns
ns
ADSP-BF531/ADSP-BF532
Universal Asynchronous Receiver-Transmitter
(UART) Port—Receive and Transmit Timing
Figure 24 describes UART port receive and transmit operations.
The maximum baud rate is SCLK/16. As shown in Figure 24
there is some latency between the generation internal UART
interrupts and the external data operations. These latencies are
negligible at the data transmission rates for the UART.
CLKOUT
(SAMPLE CLOCK)
RXD
DATA[8:5]
STOP
RECEIVE
INTERNAL
UART RECEIVE
INTERRUPT
UART RECEIVE BIT SET BY DATA STOP;
CLEARED BY FIFO READ
START
TXD
DATA[8:5]
STOP[2:1]
TRANSMIT
INTERNAL
UART TRANSMIT
INTERRUPT
UART TRANSMIT BIT SET BY PROGRAM;
CLEARED BY WRITE TO TRANSMIT
Figure 24. UART Port—Receive and Transmit Timing
Rev. D |
Page 39 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
Programmable Flags Cycle Timing
Table 27 and Figure 25 describe programmable flag operations.
Table 27. Programmable Flags Cycle Timing
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Min
Max Min
Max
Unit
Parameter
Timing Requirement
tWFI
Flag Input Pulse Width
Switching Characteristic
tDFO
Flag Output Delay from CLKOUT Low
tSCLK + 1
tSCLK + 1
6
CLKOUT
tDFO
PF (OUTPUT)
FLAG OUTPUT
tWFI
PF (INPUT)
FLAG INPUT
Figure 25. Programmable Flags Cycle Timing
Rev. D |
Page 40 of 60 |
August 2006
ns
6
ns
ADSP-BF531/ADSP-BF532
Timer Cycle Timing
Table 28 and Figure 26 describe timer expired operations. The
input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input frequency
of fSCLK/2 MHz.
Table 28. Timer Cycle Timing
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Min Max
Min
Max
Unit
Parameter
Timing Characteristics
tWL
Timer Pulse Width Input Low1 (Measured in SCLK Cycles)
tWH Timer Pulse Width Input High1 (Measured in SCLK Cycles)
Switching Characteristic
tHTO Timer Pulse Width Output2 (Measured in SCLK Cycles)
1
1
1
1
1
1
(232–1) 1
SCLK
SCLK
(232–1)
SCLK
The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
2
The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232–1) cycles.
CLKOUT
tHTO
TMRx
(PWM OUTPUT MODE)
TMRx
(WIDTH CAPTURE AND
EXTERNAL CLOCK MODES)
tWL
tWH
Figure 26. Timer PWM_OUT Cycle Timing
Rev. D |
Page 41 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
JTAG Test and Emulation Port Timing
Table 29 and Figure 27 describe JTAG port operations.
Table 29. JTAG Port Timing
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Min Max Min
Max
Unit
Parameter
Timing Requirements
tTCK
TCK Period
TDI, TMS Setup Before TCK High
tSTAP
tHTAP
TDI, TMS Hold After TCK High
tSSYS
System Inputs Setup Before TCK High1
tHSYS
System Inputs Hold After TCK High1
tTRSTW
TRST Pulse Width2 (Measured in TCK Cycles)
Switching Characteristics
tDTDO
TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low3
20
4
4
4
5
4
0
1
20
4
4
4
5
4
10
12
0
ns
ns
ns
ns
ns
TCK
10
12
ns
ns
System Inputs = DATA15–0, ARDY, TMR2–0, PF15–0, PPI_CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,
RESET, NMI, BMODE1–0, BR, PP3–0.
50 MHz maximum
3
System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2–0, PF15–0, RSCLK0–1, RFS0–1,
TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPI3–0.
2
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 27. JTAG Port Timing
Rev. D |
Page 42 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
OUTPUT DRIVE CURRENTS
150
150
VDDEXT = 2.75V
VDDEXT = 2.50V
VDDEXT = 2.25V
SOURCE CURRENT (mA)
100
VDDEXT = 2.75V
VDDEXT = 2.50V
VDDEXT = 2.25V
100
SOURCE CURRENT (mA)
Figure 28 through Figure 39 show typical current-voltage characteristics for the output drivers of the ADSP-BF531/
ADSP-BF532 processor. The curves represent the current drive
capability of the output drivers as a function of output voltage.
50
50
0
VOH
–50
–100
0
–150
VOH
VOL
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
–50
Figure 31. Drive Current B (VDDEXT = 2.5 V)
VOL
–100
0
0.5
1.0
1.5
2.0
2.5
SOURCE VOLTAGE (V)
Figure 28. Drive Current A (VDDEXT = 2.5 V)
80
SOURCE CURRENT (mA)
60
VDDEXT = 1.9V
VDDEXT = 1.8V
40
VDDEXT = 1.7V
3.0
SOURCE CURRENT (mA)
–150
80
60
VDDEXT = 1.9V
VDDEXT = 1.8V
40
VDDEXT = 1.7V
20
0
-20
-40
20
-60
0
-80
0
0.5
1.0
1.5
2.0
SOURCE VOLTAGE (V)
-20
Figure 32. Drive Current B (VDDEXT = 1.8 V)
-40
-60
150
-80
0
0.5
1.0
1.5
100
150
VDDEXT = 3.65V
VDDEXT = 3.30V
VDDEXT = 2.95V
100
50
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
Figure 29. Drive Current A (VDDEXT = 1.8 V)
SOURCE CURRENT (mA)
VDDEXT = 3.65V
VDDEXT = 2.95V
VDDEXT = 3.30V
2.0
50
0
VOH
–50
–100
VOL
0
–150
VOH
0
–50
0.5
1.0
1.5
2.0
SOURCE VOLTAGE (V)
2.5
Figure 33. Drive Current B (VDDEXT = 3.3 V)
–100
VOL
–150
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
Figure 30. Drive Current A (VDDEXT = 3.3 V)
Rev. D |
Page 43 of 60 |
August 2006
3.0
3.5
ADSP-BF531/ADSP-BF532
100
60
VDDEXT = 2.75V
VDDEXT = 2.50V
VDDEXT = 2.25V
60
SOURCE CURRENT (mA)
40
SOURCE CURRENT (mA)
20
0
VOH
–20
40
20
0
VOH
–20
–40
–60
–40
VOL
–60
VDDEXT = 2.75V
VDDEXT = 2.50V
VDDEXT = 2.25V
80
0
0.5
1.0
1.5
2.0
2.5
VOL
–80
–100
3.0
0
0.5
SOURCE VOLTAGE (V)
Figure 34. Drive Current C (VDDEXT = 2.5 V)
VDDEXT = 1.9V
VDDEXT = 1.8V
60
VDDEXT = 1.7V
40
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
20
10
0
-10
-20
-30
2.0
2.5
3.0
VDDEXT = 1.9V
VDDEXT = 1.8V
VDDEXT = 1.7V
20
0
-20
-40
0
1.0
0.5
1.5
-60
2.0
0
0.5
SOURCE VOLTAGE (V)
1.5
2.0
150
100
VDDEXT = 3.65V
VDDEXT = 3.30V
VDDEXT = 2.95V
60
40
20
0
VOH
–20
–40
50
0
VOH
–50
VOL
–100
VOL
–60
VDDEXT = 3.65V
VDDEXT = 3.30V
VDDEXT = 2.95V
100
SOURCE CURRENT (mA)
80
–150
–80
–100
0
1.0
SOURCE VOLTAGE (V)
Figure 38. Drive Current D (VDDEXT = 1.8 V)
Figure 35. Drive Current C (VDDEXT = 1.8 V)
SOURCE CURRENT (mA)
1.5
Figure 37. Drive Current D (VDDEXT = 2.5 V)
30
-40
1.0
SOURCE VOLTAGE (V)
0
0.5
1.0
1.5
2.0
2.5
3.0
0.5
3.5
SOURCE VOLTAGE (V)
1.0
1.5
2.0
SOURCE VOLTAGE (V)
2.5
Figure 39. Drive Current D (VDDEXT = 3.3 V)
Figure 36. Drive Current C (VDDEXT = 3.3 V)
Rev. D |
Page 44 of 60 |
August 2006
3.0
3.5
ADSP-BF531/ADSP-BF532
POWER DISSIPATION
Many operating conditions can affect power dissipation. System
designers should refer to EE-229: Estimating Power for
ADSP-BF531/ADSP-BF532/ADSP-BF533 Blackfin Processors on
the Analog Devices website (www.analog.com)—use site search
on “EE-229.” This document provides detailed information for
optimizing your design for lowest power.
See the ADSP-BF53x Blackfin Processor Hardware Reference
Manual for definitions of the various operating modes and for
instructions on how to minimize system power.
TEST CONDITIONS
All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 40
shows the measurement point for ac measurements (except output enable/disable). The measurement point VMEAS is 0.95 V for
VDDEXT (nominal) = 1.8 V, and 1.5 V for
VDDEXT (nominal) = 2.5 V/3.3 V.
INPUT
OR
OUTPUT
VMEAS
VMEAS
The time for the voltage on the bus to decay by ∆V is dependent
on the capacitive load CL and the load current II. This decay time
can be approximated by the equation:
t DECAY = ( C L ∆V ) ⁄ I L
The time tDECAY is calculated with test loads CL and IL, and with
∆V equal to 0.1 V for VDDEXT (nominal) = 1.8 V or 0.5 V for
VDDEXT (nominal) = 2.5 V/3.3 V.
The time tDIS_MEASURED is the interval from when the reference
signal switches, to when the output voltage decays ∆V from the
measured output high or output low voltage.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ∆V
to be the difference between the ADSP-BF531/ADSP-BF532
processor’s output voltage and the input threshold for the
device requiring the hold time. CL is the total bus capacitance
(per data line), and IL is the total leakage or three-state current
(per data line). The hold time will be tDECAY plus the various output disable times as specified in the Timing Specifications on
Page 23 (for example tDSDAT for an SDRAM write cycle as shown
in SDRAM Interface Timing on Page 27).
Figure 40. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
REFERENCE
SIGNAL
Output Enable Time Measurement
tDIS_MEASURED
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving.
tDIS
VOH
(MEASURED)
The output enable time tENA is the interval from the point when a
reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of
Figure 41.
tENA_MEASURED
tENA
VOL
(MEASURED)
VOH(MEASURED)
VTRIP(HIGH)
VTRIP(LOW)
VOL(MEASURED)
VOH (MEASURED) ⴚ ⌬V
VOL (MEASURED) + ⌬V
tDECAY
The time tENA_MEASURED is the interval, from when the reference signal switches, to when the output voltage reaches VTRIP(high) or
VTRIP (low). For VDDEXT (nominal) = 1.8 V—VTRIP (high) is 1.3 V
and VTRIP (low) is 0.7 V. For VDDEXT (nominal) = 2.5 V/3.3 V—
VTRIP (high) is 2.0 V and VTRIP (low) is 1.0 V . Time tTRIP is the
interval from when the output starts driving to when the output
reaches the VTRIP (high) or VTRIP (low) trip voltage.
tTRIP
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
Figure 41. Output Enable/Disable
50⍀
TO
OUTPUT
PIN
Time tENA is calculated as shown in the equation:
t ENA = t ENA_MEASURED – t TRIP
VLOAD
30pF
If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
Figure 42. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Output Disable Time Measurement
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time tDIS is the
difference between tDIS_MEASURED and tDECAY as shown on the left
side of Figure 40.
t DIS = t DIS_MEASURED – t DECAY
Rev. D |
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 42). VLOAD is 0.95 V for VDDEXT
(nominal) = 1.8 V, and 1.5 V for VDDEXT (nominal) =
2.5 V/3.3 V. Figure 43 on Page 46 through Figure 54 on Page 48
show how output rise time varies with capacitance. The delay
Page 45 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
and hold specifications given should be derated by a factor
derived from these figures. The graphs in these figures may not
be linear outside the ranges shown.
RISE AND FALL TIME ns (10% to 90%)
ABEB0 (133MHz DRIVER), VDDEXT = 1.7V
16
RISE AND FALL TIME ns (10% to 90%)
14
RISE TIME
12
10
FALL TIME
8
10
RISE TIME
8
FALL TIME
6
4
2
6
0
4
2
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 45. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver A at VDDEXT = 3.65 V
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
RISE AND FALL TIME ns (10% to 90%)
ABE_B0 (133MHz DRIVER), VDDEXT (MIN) = 2.25V
14
12
RISE TIME
10
FALL TIME
8
CLKOUT (CLKOUT DRIVER), VDDEXT = 1.7V
14
Figure 43. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver A at VDDEXT = 1.8 V
RISE AND FALL TIME ns (10% to 90%)
ABE0 (133MHz DRIVER), VDDEXT (MAX) = 3.65V
12
6
12
RISE TIME
10
8
FALL TIME
6
4
2
4
0
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
0
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 46. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver B at VDDEXT = 1.8 V
Figure 44. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver A at VDDEXT = 2.25 V
Rev. D |
50
Page 46 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
CLKOUT (CLKOUT DRIVER), VDDEXT (MIN) = 2.25V
10
RISE TIME
8
FALL TIME
6
4
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
25
RISE TIME
20
FALL TIME
15
10
5
0
0
Figure 47. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver B at VDDEXT = 2.25 V
50
200
250
Figure 49. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver C at VDDEXT = 1.8 V
TMR0 (33MHz DRIVER), VDDEXT (MIN) = 2.25V
30
RISE AND FALL TIME ns (10% to 90%)
9
8
RISE TIME
7
6
FALL TIME
5
4
3
2
25
RISE TIME
20
15
FALL TIME
10
5
1
0
100
150
LOAD CAPACITANCE (pF)
CLKOUT (CLKOUT DRIVER), VDDEXT (MAX) = 3.65V
10
RISE AND FALL TIME ns (10% to 90%)
TMR0 (33MHz DRIVER), VDDEXT = 1.7V
30
RISE AND FALL TIME ns (10% to 90%)
RISE AND FALL TIME ns (10% to 90%)
12
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 48. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver B at VDDEXT = 3.65 V
Rev. D |
Page 47 of 60 |
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 50. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver C at VDDEXT = 2.25 V
August 2006
ADSP-BF531/ADSP-BF532
TMR0 (33MHz DRIVER), VDDEXT (MAX) = 3.65V
SCK (66MHz DRIVER), VDDEXT (MAX) = 3.65V
14
RISE AND FALL TIME ns (10% to 90%)
RISE AND FALL TIME ns (10% to 90%)
20
18
16
RISE TIME
14
12
FALL TIME
10
8
6
4
12
RISE TIME
10
8
FALL TIME
6
4
2
2
0
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 51. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver C at VDDEXT = 3.65 V
RISE AND FALL TIME ns (10% to 90%)
100
150
LOAD CAPACITANCE (pF)
200
14
12
where:
RISE TIME
TJ = junction temperature (ⴗC).
FALL TIME
10
8
TCASE = case temperature (ⴗC) measured by customer at top
center of package.
6
ΨJT = from Table 30 through Table 32.
4
PD = power dissipation (see Power Dissipation on Page 45 for
the method to calculate PD).
0
0
50
100
150
200
Values of θJA are provided for package comparison and printed
circuit board design considerations. θJA can be used for a first
order approximation of TJ by the equation:
250
LOAD CAPACITANCE (pF)
Figure 52. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver D at VDDEXT = 1.8 V
T J = T A + ( θ JA × P D )
where:
TA = ambient temperature (ⴗC).
SCK (66MHz DRIVER), VDDEXT (MIN) = 2.25V
18
In Table 30 through Table 32, airflow measurements comply
with JEDEC standards JESD51–2 and JESD51–6, and the junction-to-board measurement complies with JESD51–8. The
junction-to-case measurement complies with MIL-STD-883
(Method 1012.1). All measurements use a 2S2P JEDEC test
board.
16
14
RISE TIME
12
10
FALL TIME
8
6
4
2
0
250
Figure 54. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver D at VDDEXT = 3.65 V
To determine the junction temperature on the application
printed circuit board use:
T J = T CASE + ( Ψ JT × P D )
16
2
RISE AND FALL TIME ns (10% to 90%)
50
ENVIRONMENTAL CONDITIONS
SCK (66MHz DRIVER), VDDEXT = 1.7V
18
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 53. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver D at VDDEXT = 2.25 V
Rev. D |
Page 48 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
Thermal resistance θJA in Table 30 through Table 32 is the figure
of merit relating to performance of the package and board in a
convective environment. θJMA represents the thermal resistance
under two conditions of airflow. ΨJT represents the correlation
between TJ and TCASE.
Table 30. Thermal Characteristics for BC-160 Package
Parameter
Condition
Typical
Unit
θJA
0 Linear m/s Airflow
27.1
ⴗC/W
θJMA
1 Linear m/s Airflow
23.85
ⴗC/W
θJMA
2 Linear m/s Airflow
22.7
ⴗC/W
θJC
Not Applicable
7.26
ⴗC/W
ΨJT
0 Linear m/s Airflow
0.14
ⴗC/W
ΨJT
1 Linear m/s Airflow
0.26
ⴗC/W
ΨJT
2 Linear m/s Airflow
0.35
ⴗC/W
Table 31. Thermal Characteristics for ST-176-1 Package
Parameter
Condition
Typical
Unit
θJA
0 Linear m/s Airflow
34.9
ⴗC/W
θJMA
1 Linear m/s Airflow
33.0
ⴗC/W
θJMA
2 Linear m/s Airflow
32.0
ⴗC/W
ΨJT
0 Linear m/s Airflow
0.50
ⴗC/W
ΨJT
1 Linear m/s Airflow
0.75
ⴗC/W
ΨJT
2 Linear m/s Airflow
1.00
ⴗC/W
Table 32. Thermal Characteristics for B-169 Package
Parameter
Condition
Typical
Unit
θJA
0 Linear m/s Airflow
22.8
ⴗC/W
θJMA
1 Linear m/s Airflow
20.3
ⴗC/W
θJMA
2 Linear m/s Airflow
19.3
ⴗC/W
θJC
Not Applicable
10.39
ⴗC/W
ΨJT
0 Linear m/s Airflow
0.59
ⴗC/W
ΨJT
1 Linear m/s Airflow
0.88
ⴗC/W
ΨJT
2 Linear m/s Airflow
1.37
ⴗC/W
Rev. D |
Page 49 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
160-BALL BGA PINOUT
Table 33 lists the BGA pinout by signal. Table 34 on Page 51
lists the BGA pinout by ball number.
Table 33. 160-Ball Mini-BGA Ball Assignment (Alphabetically by Signal)
Signal
ABE0
ABE1
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
AMS0
AMS1
AMS2
AMS3
AOE
ARDY
ARE
AWE
BG
BGH
BMODE0
BMODE1
BR
CLKIN
CLKOUT
DATA0
DATA1
DATA2
DATA3
Ball No.
H13
H12
J14
K14
L14
J13
K13
L13
K12
L12
M12
M13
M14
N14
N13
N12
M11
N11
P13
P12
P11
E14
F14
F13
G12
G13
E13
G14
H14
P10
N10
N4
P3
D14
A12
B14
M9
N9
P9
M8
Signal
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DR0PRI
DR0SEC
DR1PRI
DR1SEC
DT0PRI
DT0SEC
DT1PRI
DT1SEC
EMU
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
N8
P8
M7
N7
P7
M6
N6
P6
M5
N5
P5
P4
K1
J2
G3
F3
H1
H2
F2
E3
M2
A10
A14
B11
C4
C5
C11
D4
D7
D8
D10
D11
F4
F11
G11
H4
H11
K4
K11
L5
Rev. D |
Signal
GND
GND
GND
GND
GND
GND
MISO
MOSI
NMI
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PPI_CLK
PPI0
PPI1
PPI2
PPI3
RESET
RFS0
RFS1
RSCLK0
RSCLK1
RTXI
RTXO
RX
SA10
SCAS
Page 50 of 60 |
August 2006
Ball No.
L6
L8
L10
M4
M10
P14
E2
D3
B10
D2
C1
C2
C3
B1
B2
B3
B4
A2
A3
A4
A5
B5
B6
A6
C6
C9
C8
B8
A7
B7
C10
J3
G2
L1
G1
A9
A8
L3
E12
C14
Signal
SCK
SCKE
SMS
SRAS
SWE
TCK
TDI
TDO
TFS0
TFS1
TMR0
TMR1
TMR2
TMS
TRST
TSCLK0
TSCLK1
TX
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDRTC
VROUT0
VROUT1
XTAL
Ball No.
D1
B13
C13
D13
D12
P2
M3
N3
H3
E1
L2
M1
K2
N2
N1
J1
F1
K3
A1
C7
C12
D5
D9
F12
G4
J4
J12
L7
L11
P1
D6
E4
E11
J11
L4
L9
B9
A13
B12
A11
ADSP-BF531/ADSP-BF532
Table 34. 160-Ball Mini-BGA Ball Assignment (Numerically by Ball Number)
Ball No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
Signal
VDDEXT
PF8
PF9
PF10
PF11
PF14
PPI2
RTXO
RTXI
GND
XTAL
CLKIN
VROUT0
GND
PF4
PF5
PF6
PF7
PF12
PF13
PPI3
PPI1
VDDRTC
NMI
GND
VROUT1
SCKE
CLKOUT
PF1
PF2
PF3
GND
GND
PF15
VDDEXT
PPI0
PPI_CLK
RESET
GND
VDDEXT
Ball No.
C13
C14
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
E1
E2
E3
E4
E11
E12
E13
E14
F1
F2
F3
F4
F11
F12
F13
F14
G1
G2
G3
G4
G11
G12
G13
G14
Signal
SMS
SCAS
SCK
PF0
MOSI
GND
VDDEXT
VDDINT
GND
GND
VDDEXT
GND
GND
SWE
SRAS
BR
TFS1
MISO
DT1SEC
VDDINT
VDDINT
SA10
ARDY
AMS0
TSCLK1
DT1PRI
DR1SEC
GND
GND
VDDEXT
AMS2
AMS1
RSCLK1
RFS1
DR1PRI
VDDEXT
GND
AMS3
AOE
ARE
Rev. D |
Ball No.
H1
H2
H3
H4
H11
H12
H13
H14
J1
J2
J3
J4
J11
J12
J13
J14
K1
K2
K3
K4
K11
K12
K13
K14
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
M1
M2
Page 51 of 60 |
Signal
DT0PRI
DT0SEC
TFS0
GND
GND
ABE1
ABE0
AWE
TSCLK0
DR0SEC
RFS0
VDDEXT
VDDINT
VDDEXT
ADDR4
ADDR1
DR0PRI
TMR2
TX
GND
GND
ADDR7
ADDR5
ADDR2
RSCLK0
TMR0
RX
VDDINT
GND
GND
VDDEXT
GND
VDDINT
GND
VDDEXT
ADDR8
ADDR6
ADDR3
TMR1
EMU
August 2006
Ball No.
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
Signal
TDI
GND
DATA12
DATA9
DATA6
DATA3
DATA0
GND
ADDR15
ADDR9
ADDR10
ADDR11
TRST
TMS
TDO
BMODE0
DATA13
DATA10
DATA7
DATA4
DATA1
BGH
ADDR16
ADDR14
ADDR13
ADDR12
VDDEXT
TCK
BMODE1
DATA15
DATA14
DATA11
DATA8
DATA5
DATA2
BG
ADDR19
ADDR18
ADDR17
GND
ADSP-BF531/ADSP-BF532
Figure 55 lists the top view of the BGA ball configuration.
Figure 56 lists the bottom view of the BGA ball configuration.
1
2
3
4
5
6
7
8
9 10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
KEY:
VDDINT
VDDRTC
GND
VDDEXT
VROUT
I/O
Figure 55. 160-Ball Mini-BGA Ground Configuration (Top View)
14 13 12 11 10 9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
KEY:
VDDINT
VDDEXT
GND
I/O
VDDRTC
VROUT
Figure 56. 160-Ball Mini-BGA Ground Configuration (Bottom View)
Rev. D |
Page 52 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
169-BALL PBGA PINOUT
Table 35 lists the PBGA pinout by signal. Table 36 on Page 54
lists the PBGA pinout by ball number.
Table 35. 169-Ball PBGA Ball Assignment (Alphabetically by Signal)
Signal
ABE0
ABE1
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
AMS0
AMS1
AMS2
AMS3
AOE
ARDY
ARE
AWE
BG
BGH
BMODE0
BMODE1
BR
CLKIN
CLKOUT
DATA0
DATA1
DATA2
DATA3
Ball No.
H16
H17
J16
J17
K16
K17
L16
L17
M16
M17
N17
N16
P17
P16
R17
R16
T17
U15
T15
U16
T14
D17
E16
E17
F16
F17
C16
G16
G17
T13
U17
U5
T5
C17
A14
D16
U14
T12
U13
T11
Signal
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DR0PRI
DR0SEC
DR1PRI
DR1SEC
DT0PRI
DT0SEC
DT1PRI
DT1SEC
EMU
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
U12
U11
T10
U10
T9
U9
T8
U8
U7
T7
U6
T6
M2
M1
H1
H2
K2
K1
F1
F2
U1
B16
F11
G7
G8
G9
G10
G11
H7
H8
H9
H10
H11
J7
J8
J9
J10
J11
K7
K8
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MISO
MOSI
NMI
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PPI_CLK
PPI0
PPI1
PPI2
PPI3
RESET
RFS0
RFS1
RSCLK0
RSCLK1
RTCVDD
Rev. D |
Ball No.
K9
K10
K11
L7
L8
L9
L10
L11
M9
T16
E2
E1
B11
D2
C1
B1
C2
A1
A2
B3
A3
B4
A4
B5
A5
A6
B6
A7
B7
B10
B9
A9
B8
A8
A12
N1
J1
N2
J2
F10
Page 53 of 60 |
Signal
RTXI
RTXO
RX
SA10
SCAS
SCK
SCKE
SMS
SRAS
SWE
TCK
TDI
TDO
TFS0
TFS1
TMR0
TMR1
TMR2
TMS
TRST
TSCLK0
TSCLK1
TX
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
August 2006
Ball No.
A10
A11
T1
B15
A16
D1
B14
A17
A15
B17
U4
U3
T4
L1
G2
R1
P2
P1
T3
U2
L2
G1
R2
F12
G12
H12
J12
K12
L12
M10
M11
M12
B2
F6
F7
F8
F9
G6
H6
J6
Signal
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VROUT0
VROUT1
XTAL
Ball No.
K6
L6
M6
M7
M8
T2
B12
B13
A13
ADSP-BF531/ADSP-BF532
Table 36. 169-Ball PBGA Ball Assignment (Numerically by Ball Number)
Ball No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
C1
C2
C16
C17
D1
D2
Signal
PF4
PF5
PF7
PF9
PF11
PF12
PF14
PPI3
PPI1
RTXI
RTXO
RESET
XTAL
CLKIN
SRAS
SCAS
SMS
PF2
VDDEXT
PF6
PF8
PF10
PF13
PF15
PPI2
PPI0
PPI_CLK
NMI
VROUT0
VROUT1
SCKE
SA10
GND
SWE
PF1
PF3
ARDY
BR
SCK
PF0
Ball No.
D16
D17
E1
E2
E16
E17
F1
F2
F6
F7
F8
F9
F10
F11
F12
F16
F17
G1
G2
G6
G7
G8
G9
G10
G11
G12
G16
G17
H1
H2
H6
H7
H8
H9
H10
H11
H12
H16
H17
J1
Signal
CLKOUT
AMS0
MOSI
MISO
AMS1
AMS2
DT1PRI
DT1SEC
VDDEXT
VDDEXT
VDDEXT
VDDEXT
RTCVDD
GND
VDD
AMS3
AOE
TSCLK1
TFS1
VDDEXT
GND
GND
GND
GND
GND
VDD
ARE
AWE
DR1PRI
DR1SEC
VDDEXT
GND
GND
GND
GND
GND
VDD
ABE0
ABE1
RFS1
Ball No.
J2
J6
J7
J8
J9
J10
J11
J12
J16
J17
K1
K2
K6
K7
K8
K9
K10
K11
K12
K16
K17
L1
L2
L6
L7
L8
L9
L10
L11
L12
L16
L17
M1
M2
M6
M7
M8
M9
M10
M11
Rev. D |
Signal
RSCLK1
VDDEXT
GND
GND
GND
GND
GND
VDD
ADDR1
ADDR2
DT0SEC
DT0PRI
VDDEXT
GND
GND
GND
GND
GND
VDD
ADDR3
ADDR4
TFS0
TSCLK0
VDDEXT
GND
GND
GND
GND
GND
VDD
ADDR5
ADDR6
DR0SEC
DR0PRI
VDDEXT
VDDEXT
VDDEXT
GND
VDD
VDD
Page 54 of 60 |
Ball No.
M12
M16
M17
N1
N2
N16
N17
P1
P2
P16
P17
R1
R2
R16
R17
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
U1
U2
U3
U4
U5
U6
U7
U8
August 2006
Signal
VDD
ADDR7
ADDR8
RFS0
RSCLK0
ADDR10
ADDR9
TMR2
TMR1
ADDR12
ADDR11
TMR0
TX
ADDR14
ADDR13
RX
VDDEXT
TMS
TDO
BMODE1
DATA15
DATA13
DATA10
DATA8
DATA6
DATA3
DATA1
BG
ADDR19
ADDR17
GND
ADDR15
EMU
TRST
TDI
TCK
BMODE0
DATA14
DATA12
DATA11
Ball No.
U9
U10
U11
U12
U13
U14
U15
U16
U17
Signal
DATA9
DATA7
DATA5
DATA4
DATA2
DATA0
ADDR16
ADDR18
BGH
ADSP-BF531/ADSP-BF532
A1 BALL PAD CORNER
A
B
C
D
E
F
G
KEY
H
V
GND
NC
V
I/O
V
DDINT
J
K
L
DDEXT
M
N
P
R
T
U
2
1
4
6
5
3
8
7
10
12
11
9
14
13
16
15
17
TOP VIEW
Figure 57. 169-Ball PBGA Ground Configuration (Top View)
A1 BALL PAD CORNER
A
B
KEY:
C
D
E
F
G
V
DDINT
GND
NC
V
DDEXT
I/O
V
H
J
K
L
M
N
P
R
T
U
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BOTTOM VIEW
Figure 58. 169-Ball PBGA Ground Configuration (Bottom View)
Rev. D |
Page 55 of 60 |
August 2006
ROUT
ROUT
ADSP-BF531/ADSP-BF532
176-LEAD LQFP PINOUT
Table 37 lists the LQFP pinout by signal. Table 38 on Page 57
lists the LQFP pinout by lead number.
Table 37. 176-Lead LQFP Pin Assignment (Alphabetically by Signal)
Signal
ABE0
ABE1
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
AMS0
AMS1
AMS2
AMS3
AOE
ARDY
ARE
AWE
BG
BGH
BMODE0
BMODE1
BR
CLKIN
CLKOUT
DATA0
DATA1
DATA10
Lead No.
151
150
149
148
147
146
142
141
140
139
138
137
136
135
127
126
125
124
123
122
121
161
160
159
158
154
162
153
152
119
120
96
95
163
10
169
116
115
103
Signal
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DR0PRI
DR0SEC
DR1PRI
DR1SEC
DT0PRI
DT0SEC
DT1PRI
DT1SEC
EMU
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Lead No.
113
112
110
109
108
105
104
103
102
101
100
99
98
74
73
63
62
68
67
59
58
83
1
2
3
7
8
9
15
19
30
39
40
41
42
43
44
56
70
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MISO
MOSI
NMI
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
Rev. D |
Lead No.
88
89
90
91
92
97
106
117
128
129
130
131
132
133
144
155
170
174
175
176
54
55
14
51
50
49
48
47
46
38
37
36
35
34
33
32
29
28
27
Page 56 of 60 |
Signal
PPI_CLK
PPI0
PPI1
PPI2
PPI3
RESET
RFS0
RFS1
RSCLK0
RSCLK1
RTXI
RTXO
RX
SA10
SCAS
SCK
SCKE
SMS
SRAS
SWE
TCK
TDI
TDO
TFS0
TFS1
TMR0
TMR1
TMR2
TMS
TRST
TSCLK0
TSCLK1
TX
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
August 2006
Lead No.
21
22
23
24
26
13
75
64
76
65
17
16
82
164
166
53
173
172
167
165
94
86
87
69
60
79
78
77
85
84
72
61
81
6
12
20
31
45
57
Signal
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDRTC
VROUT0
VROUT1
XTAL
Lead No.
71
93
107
118
134
145
156
171
25
52
66
80
111
143
157
168
18
5
4
11
ADSP-BF531/ADSP-BF532
Table 38. 176-Lead LQFP Pin Assignment (Numerically by Lead Number)
Lead No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Signal
GND
GND
GND
VROUT1
VROUT0
VDDEXT
GND
GND
GND
CLKIN
XTAL
VDDEXT
RESET
NMI
GND
RTXO
RTXI
VDDRTC
GND
VDDEXT
PPI_CLK
PPI0
PPI1
PPI2
VDDINT
PPI3
PF15
PF14
PF13
GND
VDDEXT
PF12
PF11
PF10
PF9
PF8
PF7
PF6
GND
GND
Lead No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Signal
GND
GND
GND
GND
VDDEXT
PF5
PF4
PF3
PF2
PF1
PF0
VDDINT
SCK
MISO
MOSI
GND
VDDEXT
DT1SEC
DT1PRI
TFS1
TSCLK1
DR1SEC
DR1PRI
RFS1
RSCLK1
VDDINT
DT0SEC
DT0PRI
TFS0
GND
VDDEXT
TSCLK0
DR0SEC
DR0PRI
RFS0
RSCLK0
TMR2
TMR1
TMR0
VDDINT
Lead No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Rev. D |
Signal
TX
RX
EMU
TRST
TMS
TDI
TDO
GND
GND
GND
GND
GND
VDDEXT
TCK
BMODE1
BMODE0
GND
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
GND
VDDEXT
DATA7
DATA6
DATA5
VDDINT
DATA4
DATA3
DATA2
DATA1
DATA0
GND
VDDEXT
BG
BGH
Page 57 of 60 |
Lead No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
August 2006
Signal
ADDR19
ADDR18
ADDR17
ADDR16
ADDR15
ADDR14
ADDR13
GND
GND
GND
GND
GND
GND
VDDEXT
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
VDDINT
GND
VDDEXT
ADDR4
ADDR3
ADDR2
ADDR1
ABE1
ABE0
AWE
ARE
AOE
GND
VDDEXT
VDDINT
AMS3
AMS2
AMS1
Lead No.
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
Signal
AMS0
ARDY
BR
SA10
SWE
SCAS
SRAS
VDDINT
CLKOUT
GND
VDDEXT
SMS
SCKE
GND
GND
GND
ADSP-BF531/ADSP-BF532
OUTLINE DIMENSIONS
Dimensions in the outline dimension figures are shown in
millimeters.
26.00 BSC SQ
0.75
0.60
0.45
24.00 BSC SQ
176
1
133
132
PIN 1
0.27
0.22
0.17
SEATING
PLANE
0.08 MAX LEAD
COPLANARITY
0.15
0.05
1.45
1.40
1.35
1.60 MAX
89
88
44
45
0.50 BSC
LEAD PITCH
DETAIL A
DETAIL A
TOP VIEW (PINS DOWN)
NOTES
1. DIMENSIONS IN MILLIMETERS
2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS
IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION.
3. CENTER DIMENSIONS ARE NOMINAL
Figure 59. Quad Flatpack (LQFP) ST-176-1
12.00 BSC SQ
14 12 10
8
6
4
2
13 11 9
7
5
3
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
BALL A1
INDICATOR
10.40
BSC
SQ
TOP VIEW
1.70
MAX
A1 CORNER
INDEX AREA
0.80 BSC
BALL PITCH
1.31
1.21
1.11
DETAIL A
SEATING
PLANE
0.40 NOM
(NOTE 3)
NOTES
1. DIMENSIONS ARE IN MILLIMETERS.
2. COMPLIES WITH JEDEC REGISTERED OUTLINE
MO-205, VARIATION AE WITH EXCEPTION OF
THE BALL DIAMETER.
3. MINIMUM BALL HEIGHT 0.25.
BOTTOM VIEW
0.12
0.50
MAX
0.45
COPLANARITY
0.40
BALL DIAMETER
DETAIL A
Figure 60. Chip Scale Package Ball Grid Array (Mini-BGA) BC-160
Rev. D |
Page 58 of 60 |
August 2006
ADSP-BF531/ADSP-BF532
BOTTOM VIEW
A1 BALL PAD CORNER
19.00 BSC SQ
16.00 BSC SQ
1.00 BSC
BALL PITCH
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
16 14 12 10 8
6
4
2
17 15 13 11 9
7
5
3
1
TOP VIEW
0.40 MIN
2.50
2.23
1.97
SIDE VIEW
0.20 MAX
COPLANARITY
DETAIL A
0.70
BALL DIAMETER 0.60
0.50
NOTES
1. DIMENSIONS ARE IN MILLIMETERS.
2. COMPLIES WITH JEDEC REGISTERED OUTLINE
MS-034, VARIATION AAG-2
.
3. MINIMUM BALL HEIGHT 0.40
SEATING PLANE
DETAIL A
Figure 61. Plastic Ball Grid Array (PBGA) B-169
SURFACE MOUNT DESIGN
Table 39 is provided as an aid to PCB design. For industrystandard design recommendations, refer to IPC-7351,
Generic Requirements for Surface Mount Design and Land Pattern Standard.
Table 39. BGA Data for Use with Surface Mount Design
Package
Chip Scale Package Ball Grid Array (Mini-BGA) BC-160
Plastic Ball Grid Array (PBGA) B-169
Rev. D |
Ball Attach Type
Solder Mask Defined
Solder Mask Defined
Page 59 of 60 |
August 2006
Solder Mask Opening
0.40 mm diameter
0.43 mm diameter
Ball Pad Size
0.55 mm diameter
0.56 mm diameter
ADSP-BF531/ADSP-BF532
ORDERING GUIDE
Model
Temperature
Range1
Package Instruction Operating Voltage
Option Rate (Max) (Nom)
ADSP-BF532SBBC400
–40°C to +85°C
160-Ball Chip Scale Package
Ball Grid Array (Mini-BGA)
BC-160
400 MHz
1.2 V internal,
1.8 V, 2.5 V or 3.3 V I/O
ADSP-BF532SBBCZ4002
–40°C to +85°C
160-Ball Chip Scale Package
Ball Grid Array (Mini-BGA)
BC-160
400 MHz
1.2 V internal,
1.8 V, 2.5 V or 3.3 V I/O
ADSP-BF532WBBCZ-4A2, 3 –40°C to +85°C
160-Ball Chip Scale Package
Ball Grid Array (Mini-BGA)
BC-160
400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
ADSP-BF532WYBCZ-4A2, 3 –40°C to +105°C 160-Ball Chip Scale Package
Ball Grid Array (Mini-BGA)
BC-160
400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
ADSP-BF532SBST400
Package Description
–40°C to +85°C
176-Lead Quad Flatpack (LQFP)
ST-176-1 400 MHz
1.2 V internal, 2.5 V or 3.3 V I/O
–40°C to +85°C
176-Lead Quad Flatpack (LQFP)
ST-176-1 400 MHz
1.2 V internal, 2.5 V or 3.3 V I/O
–40°C to +85°C
176-Lead Quad Flatpack (LQFP)
ST-176-1 400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
ADSP-BF532SBB400
–40°C to +85°C
169-Ball Plastic Ball Grid Array (PBGA) B-169
400 MHz
1.2 V internal, 2.5 V or 3.3 V I/O
ADSP-BF532SBBZ4002
–40°C to +85°C
169-Ball Plastic Ball Grid Array (PBGA) B-169
400 MHz
1.2 V internal, 2.5 V or 3.3 V I/O
ADSP-BF532WBBZ-4A2, 3
–40°C to +85°C
169-Ball Plastic Ball Grid Array (PBGA) B-169
400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
–40°C to +105°C 169-Ball Plastic Ball Grid Array (PBGA) B-169
400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
ADSP-BF531SBBC400
–40°C to +85°C
160-Ball Chip Scale Package
Ball Grid Array (Mini-BGA)
BC-160
400 MHz
1.2 V internal,
1.8 V, 2.5 V or 3.3 V I/O
ADSP-BF531SBBCZ4002
–40°C to +85°C
160-Ball Chip Scale Package
Ball Grid Array (Mini-BGA)
BC-160
400 MHz
1.2 V internal,
1.8 V, 2.5 V or 3.3 V I/O
ADSP-BF531WBBCZ-4A2, 3 –40°C to +85°C
160-Ball Chip Scale Package
Ball Grid Array (Mini-BGA)
BC-160
400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
ADSP-BF531WYBCZ-4A2, 3 –40°C to +105°C 160-Ball Chip Scale Package
Ball Grid Array (Mini-BGA)
BC-160
400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
ADSP-BF531SBST400
2
ADSP-BF532SBSTZ400
ADSP-BF532WBSTZ-4A
ADSP-BF532WYBZ-4A
2, 3
2, 3
2
ADSP-BF531SBSTZ400
ADSP-BF531WBSTZ-4A
2, 3
ADSP-BF531SBB400
ADSP-BF531SBBZ400
2
176-Lead Quad Flatpack (LQFP)
ST-176-1 400 MHz
1.2 V internal, 2.5 V or 3.3 V I/O
–40°C to +85°C
176-Lead Quad Flatpack (LQFP)
ST-176-1 400 MHz
1.2 V internal, 2.5 V or 3.3 V I/O
ST-176-1 400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
–40°C to +85°C
176-Lead Quad Flatpack (LQFP)
–40°C to +85°C
169-Ball Plastic Ball Grid Array (PBGA) B-169
400 MHz
1.2 V internal, 2.5 V or 3.3 V I/O
–40°C to +85°C
169-Ball Plastic Ball Grid Array (PBGA) B-169
400 MHz
1.2 V internal, 2.5 V or 3.3 V I/O
2, 3
–40°C to +85°C
169-Ball Plastic Ball Grid Array (PBGA) B-169
400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
2, 3
–40°C to +105°C 169-Ball Plastic Ball Grid Array (PBGA) B-169
400 MHz
1.2 V internal, 3.0 V or 3.3 V I/O
ADSP-BF531WBBZ-4A
ADSP-BF531WYBZ-4A
–40°C to +85°C
1
Referenced temperature is ambient temperature.
Z = Pb-free part.
3
Automotive grade part.
2
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03728-0-8/06(D)
Rev. D |
Page 60 of 60 |
August 2006