86 CY7C186 8Kx8 Static RAM Features provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state drivers. The device has an automatic power-down feature (CE1), reducing the power consumption by over 80% when deselected. The CY7C186 is in a 600-mil-wide PDIP package and a 32-pin TSOP (std. pinout). • High speed — 20 ns • Low active power An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A12). Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. — 605 mW • Low standby power — 110 mW • CMOS for optimum speed/power • Easy memory expansion with CE1, CE2, and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected Functional Description The CY7C186 is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A die coat is used to insure alpha immunity. Pin Configuration LogicBlock Diagram DIP Top View NC A4 A5 A6 A7 A8 A9 A10 A11 A12 I/O0 I/O1 I/O2 GND I/O0 I/O1 I/O2 SENSE AMPS A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER INPUT BUFFER 256 x 32 x 8 ARRAY I/O3 I/O4 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC WE CE 2 A3 A2 A1 OE A0 CE 1 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O5 I/O6 POWER 12 11 9 I/O7 DOWN A A A A A 10 COLUMN DECODER 0 CE1 CE2 WE OE Selection Guide[1] 7C186-20 20 110 20/15 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 7C186-25 25 100 20/15 7C186-35 35 100 20/15 Notes: 1. For military specifications, see the CY7C186A datasheet. Cypress Semiconductor Corporation Document #: 38-05280 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised March 22, 2002 CY7C186 Pin Configurations (continued) TSOP Top View OE A1 A2 A3 CE2 WE VCC NC NC NC A4 A5 A6 A7 A8 A9 1 32 2 21 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 13 21 20 14 19 15 18 16 17 A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 NC NC GND I/O2 I/O1 I/O0 A12 A11 A10 C186-3 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Output Current into Outputs (LOW)............................. 20 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Latch-Up Current.................................................... >200 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Operating Range Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] ............................................ –0.5V to +7.0V Range Ambient Temperature VCC DC Input Voltage[2] ........................................ –0.5V to +7.0V Commercial 0°C to +70°C 5V ± 10% Electrical Characteristics Over the Operating Range 7C186-20 Parameter Description Test Conditions Min. Max. 7C186-25,35 Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 V VIH Input HIGH Voltage 2.2 VCC 2.2 VCC V VIL Input LOW Voltage[2] –0.5 0.8 –0.5 0.8 V IIX Input Load Current –5 +5 –5 +5 µA +5 –5 GND < VI < VCC 2.4 2.4 0.4 V IOZ Output Leakage Current GND < VI < VCC, Output Disabled +5 µA IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND –300 –300 mA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA 110 100 mA ISB1 Automatic CE1 Power-Down Current Max. VCC, CE1 > VIH, Min. Duty Cycle=100% 20 20 mA ISB2 Automatic CE1 Power-Down Current Max. VCC, CE1 > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V 15 15 mA –5 Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 7 7 Unit pF pF Notes: 2. Minimum voltage is equal to –3.0V for pulse durations less than 30 ns. 3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05280 Rev. ** Page 2 of 9 CY7C186 AC Test Loads and Waveforms R1 481Ω 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES 3.0V 5 pF R2 255Ω INCLUDING JIG AND SCOPE (a) Equivalent to: R1 481Ω 5V OUTPUT R2 255Ω 90% 10% 90% 10% GND ≤ 5 ns ≤ 5 ns (b) THÉVENIN EQUIVALENT OUTPUT 167Ω 1.73V Switching Characteristics Over the Operating Range[5] 7C186-20 Parameter Description Min. Max. 7C186-25 Min. Max. 7C186-35 Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE1 CE1 LOW to Data Valid 20 tACE2 CE2 HIGH to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[6] tLZCE1 CE1 LOW to Low Z 20 20 [7] tLZCE2 CE2 HIGH to Low Z CE1 HIGH to High Z[6, 7] CE2 LOW to High Z tPU CE1 LOW to Power-Up tPD CE1 HIGH to Power-Down 35 ns 25 35 ns 20 25 35 ns 9 12 15 ns 5 25 ns 35 5 3 tHZCE WRITE 25 5 3 8 5 3 10 5 3 0 0 ns 10 0 20 ns ns 3 10 20 ns 10 5 3 8 ns ns ns 20 ns CYCLE[8] tWC Write Cycle Time 20 25 35 ns tSCE1 CE1 LOW to Write End 15 20 20 ns tSCE2 CE2 HIGH to Write End 15 20 20 ns tAW Address Set-Up to Write End 15 20 25 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE WE Pulse Width 15 15 20 ns tSD Data Set-Up to Write End 10 10 12 ns tHD Data Hold from Write End 0 0 0 ns tHZWE WE LOW to High Z tLZWE WE HIGH to Low Z [6] 7 5 7 5 8 5 ns ns Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. 8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All signals must be active to initiate a write, and any signal can terminate a write by going inactive. The data input set-up and hold timing should be referenced to the trailing edge of the signal that terminates the write. Document #: 38-05280 Rev. ** Page 3 of 9 CY7C186 Switching Waveforms Read Cycle No. 1[9] tRC ADDRESS tOHA DATA OUT tAA DATA VALID PREVIOUS DATA VALID Read Cycle No. 2[10, 11] tRC CE1 CE2 tACE OE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tHZCE tPD tPU ICC 50% 50% ISB Write Cycle No. 1 (WE Controlled)[11, 12] tWC ADDRESS tSCEI CE1 t HA tAW tSCE2 CE CE2 tSA WE tPWE OE tSD DATA I/O t HD DATAIN VALID NOTE 13 tHZOE Notes: 9. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH. 10. WE is HIGH for read cycle. 11. Data I/O is High Z if OE = VIH, CE1 = VIH, or WE = VIL. 12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 13. During this period, the I/Os are in the output state and input signals should not be applied. Document #: 38-05280 Rev. ** Page 4 of 9 CY7C186 Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled)[11,12,14] tWC ADDRESS tSCE1 CE1 tSA tSCE2 CE2 tAW tHA WE tSD tHD DATAIN VALID DATA I/O Write Cycle No. 3 (WE Controlled, OE LOW)[11, 14] tWC ADDRESS CE1 tSCE1 CE2 tSCE2 tAW WE tSA tHA tPWE t SD DATA I/O tHD DATAIN VALID NOTE 13 tHZWE tLZWE Notes: 14. If CE1 goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05280 Rev. ** Page 5 of 9 CY7C186 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.2 NORMALIZED ICC , I SB 1.2 ICC 0.8 0.6 0.4 0.0 4.0 4.5 ICC 0.8 0.6 0.4 VCC =5.0V VIN =5.0V 0.2 ISB 0.2 1.0 5.0 5.5 ISB 0.0 –55 6.0 NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.6 NORMALIZED t AA AA 1.4 NORMALIZED t 125 1.3 1.2 1.1 TA =25°C 1.0 1.4 1.2 1.0 VCC =5.0V 0.8 0.9 0.8 4.0 4.5 5.0 5.5 0.6 –55 6.0 25 AMBIENT TEMPERATURE (°C) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 2.5 25.0 DELTA t AA (ns) 3.0 2.0 1.5 1.0 0.5 20.0 15.0 10.0 VCC =4.5V TA =25°C 5.0 1.0 2.0 3.0 4.0 SUPPLYVOLTAGE(V) Document #: 38-05280 Rev. ** 120 100 80 VCC =5.0V TA =25°C 60 40 20 0 0.0 5.0 0.0 0 200 400 600 800 1000 CAPACITANCE (pF) 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 VCC = 5.0V TA = 25°C 80 60 40 20 0 0.0 125 SUPPLYVOLTAGE (V) 0.0 0.0 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE AMBIENT TEMPERATURE (°C) SUPPLYVOLTAGE (V) NORMALIZED I PO 25 OUTPUT SINK CURRENT (mA) 1.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) NORMALIZED I CC NORMALIZED ICC , I SB 1.4 OUTPUT SOURCE CURRENT (mA) Typical DC and AC Characteristics NORMALIZED I CC vs. CYCLE TIME 1.25 VCC =5.0V TA =25°C VCC =0.5V 1.00 0.75 0.50 10 20 30 40 CYCLE FREQUENCY (MHz) Page 6 of 9 CY7C186 Truth Table CE1 CE2 WE OE Input/Output Mode H X X X High Z Deselect/Power-Down X L X X High Z Deselect L H H L Data Out Read L H L X Data In Write L H H H High Z Deselect Address Designators Address Name Address Function DIP Pin Number TSOP Pin Number A4 X3 2 11 A5 X4 3 12 A6 X5 4 13 A7 X6 5 14 A8 X7 6 15 A9 Y1 7 16 A10 Y4 8 17 A11 Y3 9 18 A12 Y0 10 19 A0 Y2 21 32 A1 X0 23 2 A2 X1 24 3 A3 X2 25 4 Ordering Information Speed (ns) 20 Ordering Code Package Name Package Type Operating Range CY7C186-20PC P15 28-Lead (600-Mil) Molded DIP CY7C186-20ZC Z32 32-Lead Thin Small Outline Package 25 CY7C186-25PC P15 28-Lead (600-Mil) Molded DIP Commercial 35 CY7C186-35PC P15 28-Lead (600-Mil) Molded DIP Commercial Document #: 38-05280 Rev. ** Commercial Page 7 of 9 CY7C186 Package Diagrams 28-Lead (600-Mil) Molded DIP P15 51-85017-A 32-Lead Thin Small Outline Package Type I (8x20 mm) Z32 51-85056-*D Document #: 38-05280 Rev. ** Page 8 of 9 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C186 Document Title: CY7C186 8Kx8 Static RAM Document Number: 38-05280 REV. ECN NO. Issue Date Orig. of Change ** 114447 3/26/02 DSG Document #: 38-05280 Rev. ** Description of Change Change from Spec number: 38-00240 to 38-05280 Page 9 of 9