TI1 ADC121C027CIMK/NOPB 12-bit analog-to-digital converter with alert function Datasheet

ADC121C021, ADC121C021Q, ADC121C027
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SNAS415F – JANUARY 2008 – REVISED MARCH 2013
ADC121C021/ADC121C021Q/ADC121C027 I2C-Compatible, 12-Bit Analog-to-Digital
Converter with Alert Function
Check for Samples: ADC121C021, ADC121C021Q, ADC121C027
FEATURES
1
•
23
•
•
•
•
•
•
2
I C-Compatible 2-Wire Interface Which
Supports Standard (100kHz), Fast (400kHz),
and High Speed (3.4MHz) Modes
Extended Power Supply Range (+2.7V to
+5.5V)
Up to Nine Pin-Selectable Chip Addresses
(VSSOP Only)
Out-of-Range Alert Function
Automatic Power-Down Mode while Not
Converting
Very Small 6-Pin SOT and 8-Pin VSSOP
Packages
ADC121C021Q is an Automotive Grade
Product that is AEC-Q100 Grade 2 Qualified
APPLICATIONS
•
•
•
•
•
•
System Monitoring
Peak Detection
Portable Instruments
Medical Instruments
Test Equipment
Automotive
KEY SPECIFICATIONS
•
•
•
•
•
Resolution: 12 Bits (No Missing Codes)
Conversion Time: 1µs (Typ)
INL & DNL: ±1 LSB (Max) (Up to 22ksps)
Throughput Rate: 188.9 ksps (Max)
Power Consumption (at 22 ksps)
– 3V Supply: 0.26 mW (Typ)
– 5v Supply: 0.78 mW (Typ)
DESCRIPTION
These converters are low-power, monolithic, 12-bit,
analog-to-digital converters (ADCs) that operates
from a +2.7 to 5.5V supply. The converter is based
upon
a
successive
approximation
register
architecture with an internal track-and-hold circuit that
can handle input frequencies up to 11MHz. These
converters operate from a single supply which also
serves as the reference. The device features an I2Ccompatible serial interface that operates in all three
speed modes, including high speed mode (3.4MHz).
The ADC121C021's Alert feature provides an
interrupt that is activated when the analog input
violates a programmable upper or lower limit value.
The device features an automatic conversion mode,
which frees up the controller and I2C interface. In this
mode, the ADC continuously monitors the analog
input for an "out-of-range" condition and provides an
interrupt if the measured voltage goes out-of-range.
The ADC121C021 comes in two packages: a small 6pin SOT package with an alert output, and an 8-pin
VSSOP package with an alert output and two
address selection inputs. The
ADC121C021Q is
available in a 6-pin SOT package. The ADC121C027
comes in a small 6-pin SOT package with an address
selection input. The ADC121C027 provides three pinselectable addresses while the 8-pin VSSOP version
of the ADC121C021 provides nine pin-selectable
addresses. Pin-compatible alternatives to the 6-pin
SOT options are available with additional address
options.
Normal power consumption using a +3V or +5V
supply is 0.26mW or 0.78mW, respectively. The
automatic power-down feature reduces the power
consumption to less than 1µW while not converting.
Operation over the industrial temperature range of
−40°C to +105°C is ensured. Their low power
consumption and small packages make this family of
ADCs an excellent choice for use in battery operated
equipment.
The ADC121C021 and ADC121C027 are part of a
family of pin-compatible ADCs that also provide 8 and
10 bit resolution. For 8-bit ADCs see the
ADC081C021 and ADC081C027. For 10-bit ADCs
see the ADC101C021 and ADC101C027.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I C is a registered trademark of Phillips Corporation..
All other trademarks are the property of their respective owners.
2
2
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
ADC121C021, ADC121C021Q, ADC121C027
SNAS415F – JANUARY 2008 – REVISED MARCH 2013
www.ti.com
Pin-Compatible Alternatives (All devices are fully pin and function compatible across resolution)
Resolution
SOT (Alert only) and VSSOP
SOT (Addr only)
12-bit
ADC121C021
ADC121C027
10-bit
ADC101C021
ADC101C027
8-bit
ADC081C021
ADC081C027
Connection Diagrams
VA
1
6
VA
SDA
GND
2
5
SCL
VIN
3
4
ALERT
1
SCL
1
8
SDA
ALERT
2
7
GND
SDA
GND
2
5
SCL
VIN
3
4
ADDR
ADR0
3
6
ADR1
VIN
4
5
VA
ADC121C027
ADC121C021
Figure 2. 6-Pin SOT
See DDC Package
Figure 3. 8-Pin VSSOP
See DGK Package
ADC121C021/ADC121C021Q
Figure 1. 6-Pin SOT
See DDC Package
6
Block Diagram
VA
VIN
ADC121C021/
ADC121C027
REF
12-Bit
Successive
Approximation
ADC
T/H
Oscillator
Conversion Result
Highest Conversion
Lowest Conversion
Pointer
Register
and
Decode
Logic
Configuration
Alert Status
Hysteresis
High Limit
Alert
Set-Point
Comparator
ALERT*
Low Limit
SDA
I2C Serial Interface
ADDR*
SCL
GND
* Note: The ADC121C021 has the ALERT pin but no ADDR pin.
The ADC121C027 has the ADDR pin but no ALERT pin.
2
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PIN DESCRIPTIONS
Symbol
Type
VA
Supply
Equivalent Circuit
Description
Power and unbuffered reference voltage. VA must be free of
noise and decoupled to GND.
GND
Ground
VIN
Analog Input
Ground for all on-chip circuitry.
ALERT
Digital Output
SCL
Digital Input
SDA
Digital
Input/Output
See Figure 22
Analog input. This signal can range from GND to VA.
Alert output. Can be configured as active high or active low.
This is an open drain data line that must be pulled to the
supply (VA) with an external pull-up resistor.
Serial Clock Input. SCL is used together with SDA to control
the transfer of data in and out of the device. This is an open
drain data line that must be pulled to the supply (VA) with an
external pull-up resistor.
PIN
D1
Snap
Back
ADR0
ADR1
Serial Data bi-directional connection. Data is clocked into or
out of the internal 16-bit register with SCL. This is an open
drain data line that must be pulled to the supply (VA) with an
external pull-up resistor.
GND
Tri-level Address Selection Input. Sets Bits A0 & A1 of the
7-bit slave address. (see Table 1)
V+
Digital Input,
three levels
PIN
Snap
Back
2.1k
D1
41.5k
Tri-level Address Selection Input. Sets Bits A2 & A3 of the
7-bit slave address. (see Table 1)
41.5k
GND
Package Pinouts
VA
GND
VIN
ALERT
SCL
SDA
ADR0
ADR1
ADC121C021, SOT
1
2
3
4
5
6
N/A
N/A
ADC121C027, SOT
1
2
3
N/A
5
6
4
N/A
ADC121C021, VSSOP
5
7
4
2
1
8
3
6
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1) (2) (3)
Supply Voltage, VA
-0.3V to +6.5V
−0.3V to (VA +0.3V)
Voltage on any Analog Input Pin to GND
−0.3V to 6.5V
Voltage on any Digital Input Pin to GND
Input Current at Any Pin (4)
Package Input Current
±15 mA
(4)
±20 mA
See (5)
Power Dissipation at TA = 25°C
HBM
2500V
VA, GND, VIN, ALERT, ADDR Pins SDA
250V
CDM
1250V
HBM
8000V
ESD Susceptibility per JESD22 (6)
SDA
MM
400V
HBM
2500V
VA, GND, VIN, ALERT, ADDR Pins MM
ESD Susceptibility per AEC-Q100 (6)
SDA, SCL Pins
250V
CDM
1250V
HBM
2500V
MM
250V
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
(1)
(2)
(3)
(4)
(5)
(6)
4
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating
Ratings is not recommended.
All voltages are measured with respect to GND = 0V, unless otherwise specified.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited per the Absolute Maximum
Ratings. The maximum package input current rating limits the number of pins that can safely exceed the power supplies.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe
fault condition (e.g., when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).
Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged
through 0 Ω. Charged device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an
automated assembler) then rapidly being discharged.
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Operating Ratings (1) (2)
−40°C ≤ TA ≤ +105°C
Operating Temperature Range
Supply Voltage, VA
+2.7V to 5.5V
Analog Input Voltage, VIN
0V to VA
Digital Input Voltage (3)
0V to 5.5V
Sample Rate
(1)
(2)
(3)
up to 188.9 ksps
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating
Ratings is not recommended.
All voltages are measured with respect to GND = 0V, unless otherwise specified.
The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of VA, will not cause errors in the conversion
result. For example, if VA is 3V, the digital input pins can be driven with a 5V logic device.
I/O
TO INTERNAL
CIRCUITRY
GND
Package Thermal Resistances (1) (2)
(1)
(2)
Package
θJA
6-Lead SOT
250°C/W
8-Lead VSSOP
200°C/W
Soldering process must comply with Reflow Temperature Profile specifications.
Reflow temperature profiles are different for lead-free packages.
Electrical Characteristics
The following specifications apply for VA = +2.7V to +5.5V, GND = 0V, fSCL up to 3.4MHz, fIN = 1kHz for fSCL up to 400kHz,
fIN = 10kHz for fSCL = 3.4MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C
unless otherwise noted. (1)
Symbol
Parameter
Conditions
Typical (2)
VA = +2.7V to +3.6V, fSCL up to 400kHz (3)
±0.5
Limits (2)
Units (Limits)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
INL
Integral Non-Linearity (End Point
Method)
VA = +2.7V to +5.5V. fSCL up to 3.4MHz
VA = +2.7V to +3.6V, fSCL up to 400kHz (3)
DNL
Differential Non-Linearity
VA = +2.7V to +5.5V, fSCL up to 3.4MHz
(1)
(2)
(3)
VOFF
Offset Error
GE
Gain Error
12
Bits
±1
LSB (max)
+1.2
LSB
−0.9
LSB
+0.5
+1
LSB (max)
−0.5
−0.9
LSB (min)
+1.3
LSB
−0.9
VA = +2.7V to +3.6V, fSCL up to 400kHz (3)
+0.1
VA = +2.7V to +5.5V. fSCL up to 3.4MHz
+1.4
-0.8
LSB
±1.6
LSB (max)
LSB
±6
LSB (max)
To ensure accuracy, it is required that VA be well bypassed and free of noise.
Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing
Quality Level).
The ADC will meet Minimum/Maximum specifications for fSCL up to 3.4MHz and VA = 2.7V to 3.6V when operating in the Quiet Interface
Mode (See Quiet Interface Mode).
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Electrical Characteristics (continued)
The following specifications apply for VA = +2.7V to +5.5V, GND = 0V, fSCL up to 3.4MHz, fIN = 1kHz for fSCL up to 400kHz,
fIN = 10kHz for fSCL = 3.4MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C
unless otherwise noted. (1)
Symbol
Typical (2)
Limits (2)
Units (Limits)
VA = +2.7V to +3.6V
11.7
11.3
Bits (min)
VA = +3.6V to +5.5V
11.5
VA = +2.7V to +3.6V
72.5
VA = +3.6V to +5.5V
71
VA = +2.7V to +3.6V
−92
VA = +3.6V to +5.5V
−87
VA = +2.7V to +3.6V
72.6
VA = +3.6V to +5.5V
71
VA = +2.7V to +3.6V
90
VA = +3.6V to +5.5V
87
dB (min)
VA = +3.0V,
fa = 1.035 kHz, fb = 1.135 kHz
−89
dB
VA = +5.0V,
fa = 1.035 kHz, fb = 1.135 kHz
−91
dB
VA = +3.0V,
fa = 1.035 kHz, fb = 1.135 kHz
−88
dB
VA = +5.0V,
fa = 1.035 kHz, fb = 1.135 kHz
−88
dB
VA = +3.0V
8
MHz
VA = +5.0V
11
MHz
0 to VA
V
Parameter
Conditions
DYNAMIC CONVERTER CHARACTERISTICS
ENOB
Effective Number of Bits
SNR
Signal-to-Noise Ratio
THD
Total Harmonic Distortion
SINAD
Signal-to-Noise Plus Distortion Ratio
SFDR
Spurious-Free Dynamic Range
Intermodulation Distortion, Second
Order Terms (IMD2)
IMD
Intermodulation Distortion, Third
Order Terms (IMD3)
FPBW
Full Power Bandwidth (−3dB)
Bits (min)
70.4
dB (min)
dB (min)
−78
dB (max)
dB (max)
70
dB (min)
dB (min)
76
dB (min)
ANALOG INPUT CHARACTERISTICS
VIN
Input Range
IDCL
DC Leakage Current
CINA
(4)
±1
Input Capacitance
µA (max)
Track Mode
30
pF
Hold Mode
3
pF
SERIAL INTERFACE INPUT CHARACTERISTICS (SCL, SDA)
VIH
Input High Voltage
0.7 x VA
V (min)
VIL
Input Low Voltage
0.3 x VA
V (max)
IIN
Input Current (4)
±1
µA (max)
CIN
Input Pin Capacitance
0.1 x VA
V (min)
VHYST
3
Input Hysteresis
pF
ADDRESS SELECTION INPUT CHARACTERISTICS (ADDR)
VIH
Input High Voltage
VA - 0.5V
V (min)
VIL
Input Low Voltage
0.5
V (max)
IIN
Input Current (4)
±1
µA (max)
ISINK = 3 mA
0.4
V (max)
ISINK = 6 mA
0.6
V (max)
±1
µA (max)
LOGIC OUTPUT CHARACTERISTICS, OPEN-DRAIN (SDA, ALERT)
VOL
Output Low Voltage
IOZ
High Impedance Output Leakage
Current (4)
Output Coding
(4)
6
Straight (Natural) Binary
This parameter is ensured by design and/or characterization and is not tested in production.
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Electrical Characteristics (continued)
The following specifications apply for VA = +2.7V to +5.5V, GND = 0V, fSCL up to 3.4MHz, fIN = 1kHz for fSCL up to 400kHz,
fIN = 10kHz for fSCL = 3.4MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C
unless otherwise noted. (1)
Symbol
Limits (2)
Units (Limits)
Supply Voltage Minimum
2.7
V (min)
Supply Voltage Maximum
5.5
V (max)
Parameter
Conditions
Typical (2)
POWER REQUIREMENTS
VA
Continuous Operation Mode -- 2-wire interface active.
fSCL=400kHz
IN
Supply Current
fSCL=3.4MHz
fSCL=400kHz
PN
Power Consumption
fSCL=3.4MHz
VA = 2.7V to 3.6V
0.08
0.14
mA (max)
VA = 4.5V to 5.5V
0.16
0.30
mA (max)
VA = 2.7V to 3.6V
0.37
0.55
mA (max)
VA = 4.5V to 5.5V
0.74
0.99
mA (max)
VA = 3.0V
0.26
mW
VA = 5.0V
0.78
mW
VA = 3.0V
1.22
mW
VA = 5.0V
3.67
mW
Automatic Conversion Mode -- 2-wire interface stopped and quiet (SCL = SDA = VA). fSAMPLE = TCONVERT * 32
IA
Supply Current
PA
Power Consumption
VA = 2.7V to 3.6V
0.41
0.59
mA (max)
VA = 4.5V to 5.5V
0.78
1.2
mA (max)
VA = 3.0V
1.35
mW
VA = 5.0V
3.91
mW
Power Down Mode (PD1) -- 2-wire interface stopped and quiet. (SCL = SDA = VA).
IPD1
Supply Current
PPD1
Power Consumption
See (5)
0.1
0.2
µA (max)
0.5
0.9
µW (max)
45
µA (max)
Power Down Mode (PD2) -- 2-wire interface active. Master communicating with a different device on the bus.
fSCL=400kHz
IPD2
Supply Current
fSCL=3.4MHz
fSCL=400kHz
PPD2
Power Consumption
fSCL=3.4MHz
(5)
VA = 2.7V to 3.6V
13
VA = 4.5V to 5.5V
27
80
µA (max)
VA = 2.7V to 3.6V
89
150
µA (max)
VA = 4.5V to 5.5V
168
250
µA (max)
VA = 3.0V
0.04
mW
VA = 5.0V
0.14
mW
VA = 3.0V
0.29
mW
VA = 5.0V
0.84
mW
This parameter is ensured by design and/or characterization and is not tested in production.
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A.C. and Timing Characteristics
The following specifications apply for VA = +2.7V to +5.5V. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are
at TA = 25°C, unless otherwise specified.
Symbol
Conditions (1)
Parameter
Typical (2)
Limits (2)
Units
(Limits)
CONVERSION RATE
Conversion Time
fCONV
Conversion Rate
1
µs
fSCL = 100kHz
5.56
ksps
fSCL = 400kHz
22.2
ksps
fSCL = 1.7MHz
94.4
ksps
fSCL = 3.4MHz
188.9
ksps
DIGITAL TIMING SPECS (SCL, SDA)
fSCL
Serial Clock Frequency
Standard Mode
Fast Mode
High Speed Mode, Cb = 100pF
High Speed Mode, Cb = 400pF
100
400
3.4
1.7
tLOW
SCL Low Time
Standard Mode
Fast Mode
High Speed Mode, Cb = 100pF
High Speed Mode, Cb = 400pF
4.7
1.3
160
320
us
us
ns
ns
(min)
(min)
(min)
(min)
tHIGH
SCL High Time
Standard Mode
Fast Mode
High Speed Mode, Cb = 100pF
High Speed Mode, Cb = 400pF
4.0
0.6
60
120
us
us
ns
ns
(min)
(min)
(min)
(min)
tSU;DAT
Data Setup Time
Standard Mode
Fast Mode
High Speed Mode
250
100
10
ns (min)
ns (min)
ns (min)
Standard Mode (3)
0
3.45
us (min)
us (max)
Fast Mode (3)
0
0.9
us (min)
us (max)
High Speed Mode, Cb = 100pF
0
70
ns (min)
ns (max)
High Speed Mode, Cb = 400pF
0
150
ns (min)
ns (max)
tHD;DAT
Data Hold Time
kHz (max)
kHz (max)
MHz (max)
MHz (max)
tSU;STA
Setup time for a start or a repeated
start condition
Standard Mode
Fast Mode
High Speed Mode
4.7
0.6
160
us (min)
us (min)
ns (min)
tHD;STA
Hold time for a start or a repeated start
condition
Standard Mode
Fast Mode
High Speed Mode
4.0
0.6
160
us (min)
us (min)
ns (min)
tBUF
Bus free time between a stop and start
condition
Standard Mode
Fast Mode
4.7
1.3
us (min)
us (min)
tSU;STO
Setup time for a stop condition
Standard Mode
Fast Mode
High Speed Mode
4.0
0.6
160
us (min)
us (min)
ns (min)
Standard Mode
1000
ns (max)
20+0.1Cb
300
ns (min)
ns (max)
High Speed Mode, Cb = 100pF
10
80
ns (min)
ns (max)
High Speed Mode, Cb = 400pF
20
160
ns (min)
ns (max)
Fast Mode
trDA
(1)
(2)
(3)
8
Rise time of SDA signal
Cb refers to the capacitance of one bus line. Cb is expressed in pF units.
Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing
Quality Level).
The ADC121C021 will provide a minimum data hold time of 300ns to comply with the I2C Specification.
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A.C. and Timing Characteristics (continued)
The following specifications apply for VA = +2.7V to +5.5V. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are
at TA = 25°C, unless otherwise specified.
Symbol
Conditions (1)
Parameter
Typical (2)
Standard Mode
Fall time of SDA signal
250
ns (max)
ns (min)
ns (max)
High Speed Mode, Cb = 100pF
10
80
ns (min)
ns (max)
High Speed Mode, Cb = 400pF
20
160
ns (min)
ns (max)
Standard Mode
1000
ns (max)
20+0.1Cb
300
ns (min)
ns (max)
High Speed Mode, Cb = 100pF
10
40
ns (min)
ns (max)
High Speed Mode, Cb = 400pF
20
80
ns (min)
ns (max)
1000
ns (max)
20+0.1Cb
300
ns (min)
ns (max)
High Speed Mode, Cb = 100pF
10
80
ns (min)
ns (max)
High Speed Mode, Cb = 400pF
20
160
ns (min)
ns (max)
Standard Mode
300
ns (max)
20+0.1Cb
300
ns (min)
ns (max)
High Speed Mode, Cb = 100pF
10
40
ns (min)
ns (max)
High Speed Mode, Cb = 400pF
20
80
ns (min)
ns (max)
400
pF (max)
50
10
ns (max)
ns (max)
Fast Mode
trCL
Rise time of SCL signal
Standard Mode
trCL1
Fast Mode
Rise time of SCL signal after a
repeated start condition and after an
acknowledge bit.
Fast Mode
tfCL
Fall time of a SCL signal
Cb
Capacitive load for each bus line (SCL
and SDA)
tSP
Pulse Width of spike suppressed (4)
(4)
Units
(Limits)
20+0.1Cb
250
Fast Mode
tfDA
Limits (2)
Fast Mode
High Speed Mode
Spike suppression filtering on SCL and SDA will suppress spikes that are less than the indicated width.
Timing Diagrams
SDA
tLOW
tf
tHD;STA
tr
tf
tBUF
tr
tSP
SCL
tSU;STA
tHD;STA
tHIGH
tHD;DAT
START
tSU;STO
tSU;DAT
REPEATED
START
STOP
START
Figure 4. Serial Timing Diagram
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Specification Definitions
ACQUISITION TIME is the time required for the ADC to acquire the input voltage. During this time, the hold
capacitor is charged by the input voltage.
APERTURE DELAY is the time between the start of a conversion and the time when the input signal is internally
acquired or held for conversion.
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF - 1.5
LSB), after adjusting for offset error.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code
transition). The deviation of any given code from this straight line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to an individual ADC input at the same time. It is defined as the ratio of the
power in both the second and the third order intermodulation products to the power in one of the original
frequencies. Second order products are fa ± fb, where fa and fb are the two sine wave input frequencies. Third
order products are (2fa ± fb) and (fa ± 2fb). IMD is usually expressed in dB.
MISSING CODES are those output codes that will never appear at the ADC output. The ADC121C021 is
ensured not to have any missing codes.
OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +
0.5 LSB).
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral components below half the clock frequency, including
harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal
amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is
any signal present in the output spectrum that is not present at the input and may or may not be a harmonic.
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TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first n harmonic
components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated
as
THD = 20 x log 10
A f22 + / + A Fn 2
A f12
(1)
where Af1 is the RMS power of the input frequency at the output and Af2 through Afn are the RMS power in the
first n harmonic frequencies.
THROUGHPUT TIME is the minimum time required between the start of two successive conversions. It is the
acquisition time plus the conversion time.
LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is
LSB = VA / 2n
(2)
where VA is the supply voltage for this product, and "n" is the resolution in bits, which is 12 for the ADC121C021.
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is
1/2 of VA.
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Typical Performance Characteristics
fSCL = 400kHz, fSAMPLE = 22ksps, fIN = 1kHz, VA = 5.0V, TA = +25°C, unless otherwise stated.
12
INL vs. Code - VA=3V
DNL vs. Code - VA=3V
Figure 5.
Figure 6.
INL vs. Code - VA=5V
DNL vs. Code - VA=5V
Figure 7.
Figure 8.
INL vs. Supply
DNL vs. Supply
Figure 9.
Figure 10.
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Typical Performance Characteristics (continued)
fSCL = 400kHz, fSAMPLE = 22ksps, fIN = 1kHz, VA = 5.0V, TA = +25°C, unless otherwise stated.
ENOB vs. Supply
SINAD vs. Supply
Figure 11.
Figure 12.
FFT Plot
FFT Plot
Figure 13.
Figure 14.
Offset Error vs. Temperature
Gain Error vs. Temperature
Figure 15.
Figure 16.
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Typical Performance Characteristics (continued)
fSCL = 400kHz, fSAMPLE = 22ksps, fIN = 1kHz, VA = 5.0V, TA = +25°C, unless otherwise stated.
Continuous Operation Supply Current vs. VA
Automatic Conversion Supply Current vs. VA
Figure 17.
Figure 18.
Power Down (PD1) Supply Current vs. VA
Figure 19.
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Functional Description
The ADC121C021 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter. Unless otherwise stated, references to the ADC121C021 in this section
will apply to both the ADC121C021 and the ADC121C027.
CONVERTER OPERATION
Simplified schematics of the ADC121C021 in both track and hold operation are shown in Figure 20 and
Figure 21 respectively. In Figure 20, the ADC121C021 is in track mode. SW1 connects the sampling capacitor to
the analog input channel, and SW2 equalizes the comparator inputs. The ADC is in this state for approximately
0.4µs at the beginning of every conversion cycle, which begins at the ACK fall of SDA. Conversions occur when
the conversion result register is read and when the ADC is in automatic conversion mode (see Automatic
Conversion Mode).
Figure 21 shows the ADC121C021 in hold mode. SW1 connects the sampling capacitor to ground and SW2
unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add or subtract
fixed amounts of charge to or from the sampling capacitor until the comparator is balanced. At this time the
digital word supplied to the DAC is also the digital representation of the analog input voltage. This digital word is
stored in the conversion result register and read via the 2-wire interface.
In the Normal (non-Automatic) Conversion mode, a new conversion is started after the previous conversion result
is read. In the Automatic Mode, conversions are started at set intervals, as determined by bits D7 through D5 of
the Configuration Register. The intent of the Automatic mode is to provide a "watchdog" function to ensure that
the input voltage remains within the limits set in the Alert Limit Registers. The minimum and maximum
conversion results can then be read from the Lowest Conversion Register and the Highest Conversion Register,
as described in Internal Registers.
CHARGE
REDISTRIBUTION
DAC
VIN
SAMPLING
CAPACITOR
SW1
SW2
+
-
CONTROL
LOGIC
AGND
VA/2
Figure 20. ADC121C021 in Track Mode
CHARGE
REDISTRIBUTION
DAC
VIN
SAMPLING
CAPACITOR
SW1
SW2
+
-
CONTROL
LOGIC
AGND
VA/2
Figure 21. ADC121C021 in Hold Mode
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ANALOG INPUT
An equivalent circuit for the input of the ADC121C021 is shown in Figure 22. The diodes provide ESD protection
for the analog input. The operating range for the analog input is 0 V to VA. Going beyond this range will cause
the ESD diodes to conduct and may result in erratic operation. For this reason, these diodes should NOT be
used to clamp the input signal.
The capacitor C1 in Figure 22 has a typical value of 3 pF and is mainly the package pin capacitance. Resistor R1
is the on resistance (RON) of the multiplexer and track / hold switch and is typically 500Ω. Capacitor C2 is the
ADC121C021 sampling capacitor, and is typically 30 pF. The ADC121C021 will deliver best performance when
driven by a low-impedance source (less than 100Ω). This is especially important when using the ADC121C021 to
sample dynamic signals. A buffer amplifier may be necessary to limit source impedance. Use a precision op-amp
to maximize circuit performance. Also important when sampling dynamic signals is a band-pass or low-pass filter
to reduce noise at the input.
VA
D1
R1
C2
30 pF
VIN
C1
3 pF
D2
Conversion Phase - Switch Open
Track Phase - Switch Closed
Figure 22. Equivalent Input Circuit
The analog input is sampled for eight internal clock cycles, or for typically 400 ns, after the fall of SDA for
acknowledgement. This time could be as long as about 530 ns. The sampling switch opens and the conversion
begins this time after the fall of ACK. This time are typical at room temperature and may vary with temperature.
ADC TRANSFER FUNCTION
The output format of the ADC121C021 is straight binary. Code transitions occur midway between successive
integer LSB values. The LSB width for the ADC121C021 is VA / 4096. The ideal transfer characteristic is shown
in Figure 23. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB,
or a voltage of VA / 8192. Other code transitions occur at intervals of 1 LSB.
111...111
111...000
|
|
ADC CODE
111...110
1 LSB = VA/4096
011...111
000...010
|
000...001
000...000
0V
0.5 LSB
ANALOG INPUT
+VA - 1.5 LSB
Figure 23. Ideal Transfer Characteristic
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REFERENCE VOLTAGE
The ADC121C021 uses the supply (VA) as the reference, so VA must be treated as a reference. The analog-todigital conversion will only be as precise as the reference (VA), so the supply voltage should be free of noise. The
reference should be driven by a low output impedance voltage source.
The Applications section provides recommended ways to drive the ADC reference input appropriately. Refer to
Typical Application Circuit for details.
POWER-ON RESET
An internal power-on reset (POR) occurs when the supply voltage transitions above the power-on reset
threshold. Each of the registers contains a defined value upon POR and this data remains there until any of the
following occurs:
• The first conversion is completed, causing the Conversion Result and Status registers to be updated.
• A different data word is written to a writable register.
• The ADC is powered down.
The internal registers will lose their contents if the supply voltage goes below 2.4V. Should this happen, it is
important that the VA supply be lowered to a maximum of 200mV before the supply is raised again to properly
reset the device and ensure that the ADC performs as specified.
INTERNAL REGISTERS
The ADC121C021 has 8 internal data registers and one address pointer. The registers provide additional ADC
functions such as storing minimum and maximum conversion results, setting alert threshold levels, and storing
data to configure the operation of the device. Figure 24 shows all of the registers and their corresponding
address pointer values. All of the registers are read/write capable except the conversion result register, which is
read-only.
Conversion Result
Pointer = 00000000
Alert Status
Pointer = 00000001
Configuration
Pointer = 00000010
Pointer
Register
Low Limit
(selects
register to
read from
or write to)
Pointer = 00000011
High Limit
Pointer = 00000100
Hysteresis
Pointer Address
Pointer = 00000101
Lowest Conversion
Pointer = 00000110
Data
Highest Conversion
Pointer = 00000111
2
SDA
I C Serial Interface
SCL
Figure 24. Register Structure
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Address Pointer Register
The address pointer determines which of the data registers is accessed by the I2C interface. The first data byte
of every write operation is stored in the address pointer register. This value selects the register that the following
data bytes will be written to or read from. Only the three LSBs of this register are variable. The other bits must
always be written to as zeros. After a power-on reset, the pointer register defaults to all zeros (conversion result
register).
Default Value: 00h
P7
P6
P5
P4
P3
0
0
0
0
0
P2
P1
P2
P1
P0
REGISTER
0
0
0
Conversion Result (read only)
0
0
1
Alert Status (read/write)
0
1
0
Configuration (read/write)
0
1
1
Low Limit (read/write)
1
0
0
High Limit (read/write)
1
0
1
Hysteresis (read/write)
1
1
0
Lowest Conversion (read/write)
1
1
1
Highest Conversion (read/write)
P0
Register Select
Conversion Result Register
This register holds the result of the most recent conversion. In the normal mode, a new conversion is started
whenever this register is read. The conversion result data is in straight binary format with the MSB at D11.
Pointer Address 00h (Read Only)
Default Value: 0000h
D15
D14
Alert Flag
D7
D13
D12
D11
Reserved
D6
D5
D10
D9
D8
Conversion Result [11:8]
D4
D3
D2
D1
D0
Conversion Result [7:0]
Bits
Name
Description
15
Alert Flag
This bit indicates when an alert condition has occurred. When the Alert Bit Enable is set in the
Configuration Register, this bit will be high if either alert flag is set in the Alert Status Register.
Otherwise, this bit is a zero. The I2C controller will typically read the Alert Status register and other data
registers to determine the source of the alert.
14:12
Reserved
Always reads zeros.
11:0
Conversion Result
The Analog-to-Digital conversion result. The Conversion result data is a 12-bit data word in straight
binary format. The MSB is D11.
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Alert Status Register
This register indicates if a high or a low threshold has been violated. The bits of this register are active high. That
is, a high indicates that the respective limit has been violated.
Pointer Address 01h (Read/Write)
Default Value: 00h
D7
D6
D5
D4
D3
D2
Reserved
D1
D0
Over Range
Alert
Under Range
Alert
Bits
Name
Description
7:2
Reserved
Always reads zeros. Zeros must be written to these bits.
1
Over Range
Alert Flag
Bit is set to 1 when the measured voltage exceeds the VHIGH limit stored in the programmable VHIGH
limit register. Flag is reset to 0 when one of the following two conditions is met: (1) The controller writes
a one to this bit. (2) The measured voltage decreases below the programmed VHIGH limit minus the
programmed VHYST value (See Figure 27). The alert will only self-clear if the Alert Hold bit is cleared in
the Configuration register. If the Alert Hold bit is set, the only way to clear an over range alert is to write
a zero to this bit.
0
Under Range
Alert Flag
Bit is set to 1 when the measured voltage falls below the VLOW limit stored in the programmable VLOW
limit register. Flag is reset to 0 when one of the following two conditions is met: (1) The controller writes
a one to this bit. (2) The measured voltage increases above the programmed VLOW limit plus the
programmed VHYST value. The alert will only self-clear if the Alert Hold bit is cleared in the
Configuration register. If the Alert Hold bit is set, the only way to clear an under range alert is to write a
zero to this bit.
Configuration Register
Pointer Address 02h (Read/Write)
Default Value: 00h
D7
D6
D5
Cycle Time [2:0]
D4
D3
D2
D1
D0
Alert Hold
Alert Flag Enable
Alert Pin Enable
0
Polarity
Cycle Time[2:0]
Typical
fconvert (ksps)
D7
D6
D5
Conversion
Interval
0
0
0
Automatic Mode Disabled
0
0
0
1
Tconvert x 32
27
0
1
0
Tconvert x 64
13.5
0
1
1
Tconvert x 128
6.7
1
0
0
Tconvert x 256
3.4
1
0
1
Tconvert x 512
1.7
1
1
0
Tconvert x 1024
0.9
1
1
1
Tconvert x 2048
0.4
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Bits
Name
Description
7:5
Cycle Time
Configures Automatic Conversion mode. When these bits are set to zeros, the automatic conversion
mode is disabled. This is the case at power-up.
When these bits are set to a non-zero value, the ADC will begin operating in automatic conversion
mode (see Automatic Conversion Mode). The Cycle Time table shows how different values provide
various conversion intervals.
4
Alert Hold
0: Alerts will self-clear when the measured voltage moves within the limits by more than the hysteresis
register value.
1: Alerts will not self-clear and are only cleared when a one is written to the alert high flag or the alert
low flag in the Alert Status register.
3
Alert Flag Enable
0: Disables alert status bit [D15] in the Conversion Result register.
1: Enables alert status bit [D15] in the Conversion Result register.
2
Alert Pin Enable
0: Disables the ALERT output pin. The ALERT output will be high impedance when the pin is disabled.
1: Enables the ALERT output pin.
*This bit does not apply to and is a "don't care" for the ADC121C027.
1
Reserved
Always reads zeros. Zeros must be written to this bit.
0
Polarity
This bit configures the active level polarity of the ALERT output pin.
0: Sets the ALERT pin to active low.
1: Sets the ALERT pin to active high.
*This bit does not apply to and is a "don't care" for the ADC121C027.
VLOW -- Alert Limit Register - Under Range
This register holds the lower limit threshold used to determine the alert condition. If the conversion moves lower
than this limit, a VLOW alert is generated.
Pointer Address 03h (Read/Write)
Default Value: 0000h
D15
D14
D13
D12
D11
D10
Reserved
D7
D6
D9
D8
VLOW Limit [11:8]
D5
D4
D3
D2
D1
D0
VLOW Limit [7:0]
Bits
Name
Description
15:12
Reserved
Always reads zeros. Zeros must be written to these bits.
11:0
VLOW Limit
Lower limit threshold. D11 is MSB.
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VHIGH -- Alert Limit Register - Over Range
This register holds the upper limit threshold used to determine the alert condition. If the conversion moves higher
than this limit, a VHIGH alert is generated.
Pointer Address 04h (Read/Write)
Default Value: 0FFFh
D15
D14
D13
D12
D11
Reserved
D7
D10
D9
D8
VHIGH Limit [11:8]
D6
D5
D4
D3
D2
D1
D0
VHIGH Limit [7:0]
Bits
Name
Description
15:12
Reserved
Always reads zeros. Zeros must be written to these bits.
11:0
VHIGH Limit
Upper limit threshold. D11 is MSB.
VHYST -- Alert Hysteresis Register
This register holds the hysteresis value used to determine the alert condition. After a VHIGH or VLOW alert occurs,
the conversion result must move within the VHIGH or VLOW limit by more than this value to clear the alert
condition. Note: If the Alert Hold bit is set in the configuration register, alert conditions will not self-clear.
Pointer Address 05h (Read/Write)
Default Value: 0000h
D15
D14
D13
D12
D11
Reserved
D7
D6
D10
D9
D8
Hysteresis [11:8]
D5
D4
D3
D2
D1
D0
Hysteresis [7:0]
Bits
Name
Description
15:12
Reserved
Always reads zeros. Zeros must be written to these bits.
11:0
Hysteresis
Hysteresis value. D11 is MSB.
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VMIN -- Lowest Conversion Register
This register holds the Lowest Conversion result when in the automatic conversion mode. Each conversion result
is compared against the contents of this register. If the value is lower, it becomes the lowest conversion and
replaces the current value. If the value is higher, the register contents remain unchanged. The lowest conversion
value can be cleared at any time by writing 0FFFh to this register. The value of this register will update
automatically when the automatic conversion mode is enabled, but is NOT updated in the normal mode.
Pointer Address 06h (Read/Write)
Default Value: 0FFFh
D15
D14
D13
D12
D11
D10
Reserved
D7
D9
D8
Lowest Conversion [11:8]
D6
D5
D4
D3
D2
D1
D0
Lowest Conversion [7:0]
Bits
Name
Description
15:12
Reserved
Always reads zeros. Zeros must be written to these bits.
11:0
Lowest Conversion
Lowest conversion result data. D11 is MSB.
VMAX -- Highest Conversion Register
This register holds the Highest Conversion result when in the Automatic mode. Each conversion result is
compared against the contents of this register. If the value is higher, it replaces the previous value. If the value is
lower, the register contents remain unchanged. The highest conversion value can be cleared at any time by
writing 0000h to this register. The value of this register will update automatically when the automatic conversion
mode is enabled, but is NOT updated in the normal mode.
Pointer Address 07h (Read/Write)
Default Value: 0000h
D15
D14
D13
D12
D11
Reserved
D7
D6
D10
D9
D8
Highest Conversion [11:8]
D5
D4
D3
D2
D1
D0
Highest Conversion [7:0]
Bits
Name
Description
15:12
Reserved
Always reads zeros. Zeros must be written to these bits.
11:0
Highest Conversion
Highest conversion result data. D11 is MSB.
22
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SERIAL INTERFACE
The I2C-compatible interface operates in all three speed modes. Standard mode (100kHz) and Fast mode
(400kHz) are functionally the same and will be referred to as Standard-Fast mode in this document. High-Speed
mode (3.4MHz) is an extension of Standard-Fast mode and will be referred to as Hs-mode in this document.
The following diagrams describe the timing relationships of the clock (SCL) and data (SDA) signals. Pull-up
resistors or current sources are required on the SCL and SDA busses to pull them high when they are not being
driven low. A logic zero is transmitted by driving the output low. A logic high is transmitted by releasing the output
and allowing it to be pulled-up externally. The appropriate pull-up resistor values will depend upon the total bus
capacitance and operating speed. The ADC121C021 offers extended ESD tolerance (8kV HBM) for the I2C bus
pins (SCL & SDA) allowing extension of the bus across multiple boards without extra ESD protection.
Basic I2C Protocol
The I2C interface is bi-directional and allows multiple devices to operate on the same bus. The bus consists of
master devices and slave devices which can communicate back and forth over the I2C interface. Master devices
control the bus and are typically microcontrollers, FPGAs, DSPs, or other digital controllers. Slave devices are
controlled by a master and are typically peripheral devices such as the ADC121C021. To support multiple
devices on the same bus, each slave has a unique hardware address which is referred to as the "slave address."
To communicate with a particular device on the bus, the controller (master) sends the slave address and listens
for a response from the slave. This response is referred to as an acknowledge bit. If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled high. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus.
All communication on the bus begins with either a Start condition or a Repeated Start condition. The protocol for
starting the bus varies between Standard-Fast mode and Hs-mode. In Standard-Fast mode, the master
generates a Start condition by driving SDA from high to low while SCL is high. In Hs-mode, starting the bus is
more complicated. Please refer to High-Speed (Hs) Mode for the full details of a Hs-mode Start condition.
A Repeated Start is generated to address a different device or register, or to switch between read and write
modes. The master generates a Repeated Start condition by driving SDA low while SCL is high. Following the
Repeated Start, the master sends out the slave address and a read/write bit as shown in Figure 25. The bus
continues to operate in the same speed mode as before the Repeated Start condition.
All communication on the bus ends with a Stop condition. In either Standard-Fast mode or Hs-Mode, a Stop
condition occurs when SDA is pulled high while SCL is high. After a Stop condition, the bus remains idle until a
master generates another Start condition.
Please refer to the Philips I2C® Specification (Version 2.1 Jan, 2000) for a detailed description of the serial
interface.
SDA
1
2
6
MSB
R/W
Direction
Bit
Acknowledge
from the Device
7-bit Slave Address
SCL
ACK
LSB
MSB
7
8
9
LSB
N/ACK
Data Byte
*Acknowledge
or Not-ACK
1
8
2
Repeated for the Lower Data Byte
and Additional Data Transfers
START or
REPEATED
START
9
STOP
*Note: In continuous mode, this bit must be an ACK from
the data receiver. Immediately preceding a STOP
condition, this bit must be a NACK from the master.
Figure 25. Basic Operation.
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Standard-Fast Mode
In Standard-Fast mode, the master generates a start condition by driving SDA from high to low while SCL is
high. The start condition is always followed by a 7-bit slave address and a Read/Write bit. After these 8 bits have
been transmitted by the master, SDA is released by the master and the ADC121C021 either ACKs or NACKs the
address. If the slave address matches, the ADC121C021 ACKs the master. If the address doesn't match, the
ADC121C021 NACKs the master.
For a write operation, the master follows the ACK by sending the 8-bit register address pointer to the ADC. Then
the ADC121C021 ACKs the transfer by driving SDA low. Next, the master sends the upper 8-bits to the
ADC121C021. Then the ADC121C021 ACKs the transfer by driving SDA low. For a single byte transfer, the
master should generate a stop condition at this point. For a 2-byte write operation, the lower 8-bits are sent by
the master. The ADC121C021 then ACKs the transfer, and the master either sends another pair of data bytes,
generates a Repeated Start condition to read or write another register, or generates a Stop condition to end
communication.
A read operation can take place either of two ways:
If the address pointer is pre-set before the read operation, the desired register can be read immediately following
the slave address. In this case, the upper 8-bits of the register, set by the pre-set address pointer, are sent out
by the ADC. For a single byte read operation, the Master sends a NACK to the ADC and generates a Stop
condition to end communication after receiving 8-bits of data. For a 2-Byte read operation, the Master continues
the transmission by sending an ACK to the ADC. Then the ADC sends out the lower 8-bits of the ADC register.
At this point, the master either sends an ACK to receive more data or sends a NACK followed by a Stop or
Repeated Start. If the master sends an ACK, the ADC sends the next data byte, and the read cycle repeats.
If the ADC121C021address pointer needs to be set, the master needs to write to the device and set the address
pointer before reading from the desired register. This type of read requires a start, the slave address, a write bit,
the address pointer, a Repeated Start (if appropriate), the slave address, and a read bit (refer to Figure 30).
Following this sequence, the ADC sends out the upper 8-bits of the register. For a single byte read operation, the
Master must then send a NACK to the ADC and generate a Stop condition to end communication. For a 2-Byte
write operation, the Master sends an ACK to the ADC. Then, the ADC sends out the lower 8-bits of the ADC
register. At this point, the master sends either an ACK to receive more data, or a NACK followed by a Stop or
Repeated Start. If the master sends an ACK, the ADC sends another pair of data bytes, and the read cycle will
repeat. The number of data words that can be read is unlimited.
High-Speed (Hs) Mode
For Hs-mode, the sequence of events to begin communication differs slightly from Standard-Fast mode.
Figure 26 describes this in further detail. Initially, the bus begins running in Standard-Fast mode. The master
generates a Start condition and sends the 8-bit Hs master code (00001XXX) to the ADC121C021. Next, the
ADC121C021 responds with a NACK. Once the SCL line has been pulled to a high level, the master switches to
Hs-mode by increasing the bus speed and generating a second Repeated Start condition (driving SDA low while
SCL is pulled high). At this point, the master sends the slave address to the ADC121C021, and communication
continues as shown above in the "Basic Operation" Diagram (see Figure 25).
When the master generates a Repeated Start condition while in Hs-mode, the bus stays in Hs-mode awaiting the
slave address from the master. The bus continues to run in Hs-mode until a Stop condition is generated by the
master. When the master generates a Stop condition on the bus, the bus must be started in Standard-Fast mode
again before increasing the bus speed and switching to Hs-mode.
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SDA
NACK
MSB
8-ELW 0DVWHU FRGH ³00001[[[´
7-bit Slave
Address
Not-Acknowledge
from the Device
1
SCL
2
5
6
7
8
9
1
2
Repeated
START
START
Standard-Fast Mode
Hs-Mode
Figure 26. Beginning Hs-Mode Communication
I2C Slave (Hardware) Address
The ADC has a seven-bit hardware address which is also referred to as a slave address. For the VSSOP version
of the ADC121C021, this address is configured by the ADR0 and ADR1 addres selection inputs. For the
ADC121C027, the address is configured by the ADR0 address selection input. ADR0 and ADR1 can be
grounded, left floating, or tied to VA. If desired, ADR0 and ADR1 can be set to VA/2 rather than left floating. The
state of these inputs sets the hardware address that the ADC responds to on the I2C bus (see Table 1). For the
ADC121C021, the hardware address is not pin-configurable and is set to 1010100. The diagrams in
Communicating with the ADC121C021 describes how the I2C controller should address the ADC via the I2C
interface.
Table 1. Slave Addresses
Slave Address
[A6 - A0]
ADC121C027
(SOT)
ADC121C021
(SOT)
ADC121C021
(VSSOP)
ADR0
ALERT
ADR1
ADR0
1010000
Floating
-----------------
Floating
Floating
1010001
GND
-----------------
Floating
GND
1010010
VA
-----------------
Floating
VA
1010100
-----------------
Single Address
GND
Floating
1010101
-----------------
-----------------
GND
GND
1010110
-----------------
-----------------
GND
VA
1011000
-----------------
-----------------
VA
Floating
1011001
-----------------
-----------------
VA
GND
1011010
-----------------
-----------------
VA
VA
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ALERT FUNCTION
The ALERT function is an "out-of-range" indicator. At the end of every conversion, the measured voltage is
compared to the values in the VHIGH and VLOW registers. If the measured voltage exceeds the value stored in
VHIGH or falls below the value stored in VLOW, an alert condition occurs. The Alert condition is indicated in up to
three places. First, the alert condition always causes either or both of the alert flags in the Alert Status register to
go high. If the measured voltage exceeds the VHIGH limit, the Over Range Alert Flag is set. If the measured
voltage falls below the VLOW limit, the Under Range Alert Flag is set. Second, if the Alert Flag Enable bit is set in
the Configuration register, the alert condition also sets the MSB of the Conversion Result register. Third, if the
Alert Pin Enable bit is set in the Configuration register, the ALERT output becomes active (see Figure 27). The
ALERT output (ADC121C021 only) can be configured as an active high or active low output via the Polarity bit in
the Configuration register. If the Polarity bit is cleared, the ALERT output is configured as active low. If the
Polarity bit is set, the ALERT output is configured as active high.
The Over Range Alert condition is cleared when one of the following two conditions is met:
1. The controller writes a one to the Over Range Alert Flag bit.
2. The measured voltage goes below the programmed VHIGH limit minus the programmed VHYST value and the
Alert Hold bit is cleared in the Configuration register. (see Figure 27). If the Alert Hold bit is set, the alert
condition persists and only clears when a one is written to the Over Range Alert Flag bit.
The Under Range Alert condition is cleared when one of the following two conditions is met:
1. The controller writes a one to the Under Range Alert Flag bit.
2. The measured voltage goes above the programmed VLOW limit plus the programmed VHYST value and the
Alert Hold bit is cleared in the Configuration register. If the Alert Hold bit is set, the alert condition persists
and only clears when a one is written to the Under Range Alert Flag bit.
If the alert condition has been cleared by writing a one to the alert flag while the measured voltage still violates
the VHIGH or VLOW limits, an alert condition will occur again after the completion of the next conversion (see
Figure 28).
Alert conditions only occur if the input voltage exceeds the VHIGH limit or falls below the VLOW limit at the samplehold instant. The input voltage can exceed the VHIGH limit or fall below the VLOW limit briefly between conversions
without causing an alert condition.
Measured Voltage
VOLTAGE
VHIGH Limit
VHIGH - VHYST
ALERT pin
(Active Low)
TIME
Figure 27. Alert condition cleared when measured voltage crosses VHIGH - VHYST
Over Range Alert
)ODJ VHW WR ³1´
Measured Voltage
VOLTAGE
VHIGH Limit
VHIGH - VHYST
ALERT pin
(Active Low)
TIME
Figure 28. Alert condition cleared by writing a "1" to the Alert Flag.
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AUTOMATIC CONVERSION MODE
The automatic conversion mode configures the ADC to continually perform conversions without receiving "read"
instructions from the controller over the I2C interface. The mode is activated by writing a non-zero value into the
Cycle Time bits - D[7:5] - of the Configuration register (see Configuration Register). Once the ADC121C021
enters this mode, the internal oscillator is always enabled. The ADC's control logic samples the input at the
sample rate set by the cycle time bits. Although the conversion result is not transmitted by the 2-wire interface, it
is stored in the conversion result register and updates the various status registers of the device.
In automatic conversion mode, the out-of-range alert function is active and updates after every conversion. The
ADC can operate independently of the controller in automatic conversion mode. When the input signal goes "outof-range", an alert signal is sent to the controller. The controller can then read the status registers and determine
the source of the alert condition. Also, comparison and updating of the VMIN and VMAX registers occurs after every
conversion in automatic conversion mode. The controller can occasionally read the VMIN and/or VMAX registers to
determine the sampled input extremes. These register values persist until the user resets the VMIN and VMAX
registers. These two features are useful in system monitoring, peak detection, and sensing applications.
COMMUNICATING WITH THE ADC121C021
The ADC121C021's data registers are selected by the address pointer (see Address Pointer Register). To
read/write a specific data register, the pointer must be set to that register's address. The pointer is always written
at the beginning of a write operation. When the pointer needs to be updated for a read cycle, a write operation
must precede the read operation to set the pointer address correctly. On the other hand, if the pointer is preset
correctly, a read operation can occur without writing the address pointer register. The following timing diagrams
describe the various read and write operations supported by the ADC.
Reading from a 2-Byte ADC Register
The following diagrams indicate the sequence of actions required for a 2-Byte read from an ADC121C021
Register.
1
9
1
9
1
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0 R/W
Start by
Master
Frame 1
Address Byte
from Master
D15 D14 D13 D12 D11 D10 D9
ACK
by
ADC
Frame 2
Data Byte from
ADC
D8
D7
D6
ACK
by
Master
D5
D4
D3
D2
Frame 3
Data Byte from
ADC
D1
D0
N/ACK* Stop
by
by
Master Master
Repeat Frames
2 & 3 for
Continuous Mode
*Note: In continuous mode, this bit must be an ACK. Immediately
preceding a STOP condition, this bit must be a NACK.
Figure 29. (a) Typical Read from a 2-Byte ADC Register with Preset Pointer
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1
9
1
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0 R/W
Frame 1
Address Byte
from Master
SCL
(continued)
SDA
(continued)
0
1
A6
Repeat
Start by
Master
A4
A3
A2
A1
0
0
P2
P1
P0
Ack
by
ADC
1
A0 R/W
9
D15 D14 D13 D12 D11 D10 D9
ACK
by
ADC
Frame 3
Address Byte
from Master
0
Frame 2
Pointer Byte
from Master
9
A5
0
Ack
by
ADC
Start by
Master
1
D8
9
D7
D6
D5
ACK
by
Master
Frame 4
Data Byte from
ADC
D4
D3
D2
D1
Frame 5
Data Byte from
ADC
D0
N/ACK* Stop
by
by
Master Master
Repeat Frames
4 & 5 for
Continuous Mode
*Note: In continuous mode, this bit must be an ACK. Immediately
preceding a STOP condition, this bit must be a NACK.
Figure 30. (b) Typical Pointer Set Followed by Immediate Read of a 2-Byte ADC Register
Reading from a 1-Byte ADC Register
The following diagrams indicate the sequence of actions required for a single Byte read from an ADC121C021
Register.
1
1
9
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0 R/W
D7
D6
D5
ACK
by
ADC
Start by
Master
Frame 1
Address Byte
from Master
D4
D3
D2
D1
D0
Stop
NACK
by
by
Master Master
Frame 2
Data Byte from
ADC
Figure 31. (a) Typical Read from a 1-Byte ADC Register with Preset Pointer
1
9
1
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0
SDA
(continued)
1
A6
Repeat
Start by
Master
9
A5
A4
A3
A2
A1
Frame 3
Address Byte
from Master
0
0
Ack
by
ADC
Frame 1
Address Byte
from Master
SCL
(continued)
0
R/W
Start by
Master
A0 R/W
0
P2
P1
P0
Ack
by
ADC
Frame 2
Pointer Byte
from Master
1
D7
ACK
by
ADC
0
9
D6
D5
D4
D3
D2
D1
Frame 4
Data Byte from
ADC
D0
Stop
NACK
by
by
Master Master
Figure 32. (b) Typical Pointer Set Followed by Immediate Read of a 1-Byte ADC Register
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Writing to an ADC Register
The following diagrams indicate the sequence of actions required for writing to an ADC121C021 Register.
1
9
1
9
1
9
SCL
SDA
A6
Start by
Master
A5
A4
A3
A2
A1
A0
0
R/W
0
0
ACK
by
ADC
Frame 1
Address Byte
from Master
0
0
P2
P1
D7
P0
D6
D5
ACK
by
ADC
Frame 2
Pointer Byte
from Master
D4
D3
D2
D1
Frame 3
Data Byte
from Master
D0
ACK
by
ADC
Stop by
Master
Figure 33. (a) Typical Write to a 1-Byte ADC Register
1
9
1
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0
SDA
(continued)
1
9
D15 D14 D13 D12 D11 D10 D9
Frame 3
Data Byte
from Master
0
0
Ack
by
ADC
Frame 1
Address Byte
from Master
SCL
(continued)
0
R/W
Start by
Master
D8
0
P2
P1
P0
Ack
by
ADC
Frame 2
Pointer Byte
from Master
1
D7
ACK
by
ADC
0
9
D6
D5
D4
D3
D2
D1
D0
Stop
NACK
by
by
Master Master
Frame 4
Data Byte
from Master
Figure 34. (b) Typical Write to a 2-Byte ADC Register
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QUIET INTERFACE MODE
To improve performance at High Speed, operate the ADC in Quiet Interface Mode. This mode provides improved
INL and DNL performance in I2C Hs-Mode (3.4MHz). The Quiet Interface mode provides a maximum throughput
rate of 162ksps. Figure 35 describes how to read the conversion result register in this mode. Basically, the
Master needs to release SCL for at least 1µs before the MSB of every upper data byte. The diagram assumes
that the address pointer register is set to its default value.
Quiet Interface mode will only improve INL and DNL performance in Hs-Mode. Standard and Fast mode
performance is unaffected by the Quiet Interface mode.
Interface Delay
tQuiet 8 1us
1
9
1
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0 R/W
D15 D14 D13 D12 D11 D10 D9
ACK
by
ADC
Start by
Master
Frame 1
Address Byte
from Master
D8
ACK
by
Master
Frame 2
Upper Data Byte
from ADC
Interface Delay
tQuiet 8 1us
SCL
(continued)
SDA
(continued)
1
D7
9
D6
D5
D4
D3
D2
D1
D0
9
D15 D14 D13 D12 D11 D10 D9
ACK
by
Master
Frame 3
Lower Data Byte
from ADC
1
Frame 4
Upper Data Byte
from ADC
D8
1
D7
9
D6
ACK
by
Master
D5
D4
D3
D2
Frame 5
Lower Data Byte
from ADC
D1
D0
Stop
NACK
by
by
Master Master
Repeat Frames
4 and 5 for
Continuous Mode
Figure 35. Reading in Quiet Interface Mode
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APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
A typical application circuit is shown in Figure 36. The analog supply is bypassed with a capacitor network
located close to the ADC121C021. The ADC uses the analog supply (VA) as its reference voltage, so it is very
important that VA be kept as clean as possible. Due to the low power requirements of the ADC121C021, it is
possible to use a precision reference as a power supply.
The bus pull-up resistors (RP) should be powered by the controller's supply. It is important that the pull-up
resistors are pulled to the same voltage potential as VA. This will ensure that the logic levels of all devices on the
bus are compatible. If the controller's supply is noisy, an appropriate bypass capacitor should be added between
the controller's supply pin and the pull-up resistors. For Hs-mode applications, this bypass capacitance will
improve the accuracy of the ADC.
The value of the pull-up resistors (RP) depends upon the characteristics of each particular I2C bus. The I2C
specification describes how to choose an appropriate value. As a general rule-of-thumb, we suggest using a 1kΩ
resistor for Hs-mode bus configurations and a 5kΩ resistor for Standard or Fast Mode bus configurations.
Depending upon the bus capacitance, these values may or may not be sufficient to meet the timing requirements
of the I2C bus specification. Please see the I2C specification for further information.
Regulated Supply
0.1 PF
4.7 PF
5 k:
RP
RP
VDD
Controller
VA
INTERRUPT
ALERT
22:
INPUT
VIN
ADC121C021
470 pF
SDA
SCL
SCL
2
I C BUS ...
GND
SDA
Figure 36. Typical Application Circuit
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BUFFERED INPUT
A buffered input application circuit is shown in Figure 37. The analog input is buffered by a Texas Instruments
LMP7731. The non-inverting amplifier configuration provides a buffered gain stage for a single ended source.
This application circuit is good for single-ended sensor interface. The input must have a DC bias level that keeps
the ADC input signal from swinging below GND or above the supply (+5V in this case).
The LM4132, with its 0.05% accuracy over temperature, is an excellent choice as a reference source for the
ADC121C021.
Unregulated
Supply
LM4132
4.7 PF
0.1 PF
4.7 PF
VA
RS
+
INPUT
LMP7731
VIN
-
ADC121C027
CS
ADDR
GND
SDA
SCL
R1
R2
Figure 37. Buffered Input Circuit
INTELLIGENT BATTERY MONITOR
REF
[LP2980-2.8]
+
R
Low
Battery
Indicator
VA
120 nF
20 kÖ
20 kÖ
VBATT
The ADC121C021 is easily used as an intelligent battery monitor. The simple circuit shown in Figure 38, uses
the ADC121C021, the LP2980 fixed reference, and a resistor divider to implement an intelligent battery monitor
with a window supervisory feature. The window supervisory feature is implemented by the "out of range" alert
function. When the battery is recharging, the Over Range Alert will indicate that the charging cycle is complete
(see Figure 39). When the battery is nearing depletion, the Under Range Alert will indicate that the battery is low
(see Figure 40).
ALERT
VIN ADC121C021
SCL
GND
To Controller...
SDA
Figure 38. Intelligent Battery Monitor Circuit
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Measured
Battery
Voltage
RECHARGE CYCLE
VOLTAGE
VHigh Limit
ALERT pin
(Active Low)
TIME
Figure 39. Recharge Cycle
DISCHARGE CYCLE
VOLTAGE
Measured
Battery
Voltage
VLOW Limit
ALERT pin
(Active Low)
TIME
Figure 40. Discharge Cycle
In addition to the window supervisory feature, the ADC121C021 will allow the controller to read the battery
voltage at any time during operation.
The accurate voltage reading and the alert feature will allow a controller to improve the efficiency of a batterypowered device. During the discharge cycle, the controller can switch to a low-battery mode, safely suspend
operation, or report a precise battery level to the user. During the recharge cycle, the controller can implement an
intelligent recharge cycle, decreasing the charge rate when the battery charge nears capacity.
Trickle Charge Controller
While a battery is discharging, the ADC121C021 can be used to control a trickle charge to keep the battery near
full capacity (see Figure 41). When the alert output is active, the battery will recharge. An intelligent recharge
cycle will prevent over-charging and damaging the battery. With a trickle charge, the battery powered device can
be disconnected from the charger at any time with a full charge.
Measured
Battery Voltage
VOLTAGE
VLOW+VHYST
VLOW Limit
ALERT pin
(Active Low)
TIME
Figure 41. Trickle Charge
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Product Folder Links: ADC121C021 ADC121C021Q ADC121C027
33
ADC121C021, ADC121C021Q, ADC121C027
SNAS415F – JANUARY 2008 – REVISED MARCH 2013
www.ti.com
LAYOUT, GROUNDING, AND BYPASSING
For best accuracy and minimum noise, the printed circuit board containing the ADC121C021 should have
separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes.
Both of these planes should be located on the same board layer. A single, solid ground plane is preferred if
digital return current does not flow through the analog ground area. Frequently a single ground plane design will
utilize a "fencing" technique to prevent the mixing of analog and digital ground current. Separate ground planes
should only be utilized when the fencing technique is inadequate. The separate ground planes must be
connected in one place, preferably near the ADC121C021. Special care is required to ensure that signals do not
pass over power plane boundaries. Return currents must always have a continuous return path below their
traces.
The ADC121C021 power supply should be bypassed with a 4.7µF and a 0.1µF capacitor as close as possible to
the device with the 0.1µF right at the device supply pin. The 4.7µF capacitor should be a tantalum type and the
0.1µF capacitor should be a low ESL type. The power supply for the ADC121C021 should only be used for
analog circuits.
Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the
board. The clock and data lines should have controlled impedances.
34
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Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: ADC121C021 ADC121C021Q ADC121C027
ADC121C021, ADC121C021Q, ADC121C027
www.ti.com
SNAS415F – JANUARY 2008 – REVISED MARCH 2013
REVISION HISTORY
Changes from Revision E (March 2013) to Revision F
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 34
Copyright © 2008–2013, Texas Instruments Incorporated
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Product Folder Links: ADC121C021 ADC121C021Q ADC121C027
35
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADC121C021CIMK/NOPB
ACTIVE
SOT
DDC
6
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 105
X30C
ADC121C021CIMKX/NOPB
ACTIVE
SOT
DDC
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 105
X30C
ADC121C021CIMM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 105
X37C
ADC121C021CIMMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 105
X37C
ADC121C021QIMK/NOPB
ACTIVE
SOT
DDC
6
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 105
X30Q
ADC121C021QIMKX/NOPB
ACTIVE
SOT
DDC
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 105
X30Q
ADC121C027CIMK/NOPB
ACTIVE
SOT
DDC
6
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 105
X31C
ADC121C027CIMKX/NOPB
ACTIVE
SOT
DDC
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 105
X31C
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
13-Sep-2014
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADC121C021, ADC121C021-Q1 :
• Catalog: ADC121C021
• Automotive: ADC121C021-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADC121C021CIMK/NOPB
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SOT
DDC
6
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
ADC121C021CIMKX/NOP
B
SOT
DDC
6
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
ADC121C021CIMM/NOP
B
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADC121C021CIMMX/NO
PB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
SOT
DDC
6
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SOT
DDC
6
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SOT
DDC
6
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SOT
DDC
6
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
ADC121C021QIMK/NOPB
ADC121C021QIMKX/NOP
B
ADC121C027CIMK/NOPB
ADC121C027CIMKX/NOP
B
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADC121C021CIMK/NOPB
SOT
DDC
6
1000
210.0
185.0
35.0
SOT
DDC
6
3000
210.0
185.0
35.0
VSSOP
DGK
8
1000
210.0
185.0
35.0
VSSOP
DGK
8
3500
367.0
367.0
35.0
SOT
DDC
6
1000
210.0
185.0
35.0
SOT
DDC
6
3000
210.0
185.0
35.0
SOT
DDC
6
1000
210.0
185.0
35.0
SOT
DDC
6
3000
210.0
185.0
35.0
ADC121C021CIMKX/NOP
B
ADC121C021CIMM/NOPB
ADC121C021CIMMX/NOP
B
ADC121C021QIMK/NOPB
ADC121C021QIMKX/NOP
B
ADC121C027CIMK/NOPB
ADC121C027CIMKX/NOP
B
Pack Materials-Page 2
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