Catalyst CAT93C56ZD4E-1.8-GT2E 2k-bit microwire serial eeprom Datasheet

H
EE
GEN FR
ALO
CAT93C56/57 (Die Rev. E)
2K-Bit Microwire Serial EEPROM
LE
A D F R E ETM
FEATURES
■ High speed operation: 1MHz
■ Sequential read
■ Low power CMOS technology
■ Power-up inadvertant write protection
■ 1.8 to 5.5 volt operation
■ 1,000,000 Program/erase cycles
■ Selectable x8 or x16 memory organization
■ 100 year data retention
■ Self-timed write cycle with auto-clear
■ Commercial, industrial and automotive
temperature ranges
■ Software write protection
■ RoHS-compliant packages
DESCRIPTION
The CAT93C56/57 are 2K-bit Serial EEPROM memory
devices which are configured as either registers of 16
bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each
register can be written (or read) serially by using the
DI (or DO) pin. The CAT93C56/57 are manufactured
using Catalyst’s advanced CMOS EEPROM floating
gate technology. The devices are designed to endure
1,000,000 program/erase cycles and has a data retention of 100 years. The devices are available in 8-pin DIP,
SOIC, TSSOP and 8-pad TDFN packages.
PIN CONFIGURATION
FUNCTIONAL SYMBOL
CS
SK
1
8
2
DI
DO
3
7
6
5
4
VCC
NC
NC
VCC
1
2
ORG
CS
GND
SK
3
4
SOIC Package (V)
1
2
3
4
CS
SK
DI
DO
8
7
6
5
VCC
SOIC Package (W)
DIP Package (L)
8
7
6
ORG
GND
DO
DI
5
ORG
CS
SK
DI
SOIC Package (X)
VCC
CS
SK
DI
DO
NC
ORG
GND
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
GND
PIN FUNCTIONS
Pin Name
TSSOP Package (Y)
CS
SK
DI
DO
1
2
8
7
3
4
6
5
DO
TDFN Package (ZD4)
VCC
NC
ORG
ORG 6
GND
GND 5
4 DO
Function
CS
Chip Select
SK
Clock Input
VCC 8
1 CS
NC 7
2 SK
DI
Serial Data Input
3 DI
DO
Serial Data Output
VCC
Power Supply
GND
Ground
Bottom View
For Ordering Information details, see page 8.
ORG
Memory Organization
NC
No Connection
Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 pin is
selected. If the ORG pin is left unconnected, then an internal pullup
device will select the x16 organization.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice.
Doc. No. 1088, Rev. O
CAT93C56/57
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias .................. -55°C to +125°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Storage Temperature ........................ -65°C to +150°C
Voltage on any Pin with
Respect to Ground(1) ............. -2.0V to +VCC +2.0V
VCC with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
NEND(3)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Typ
Max
Cycles/Byte
Units
TDR(3)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
VZAP(3)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
ILTH(3)(4)
Latch-Up
JEDEC Standard 17
100
mA
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +5.5V, unless otherwise specified.
Symbol
Parameter
Test Conditions
ICC1
Power Supply Current
(Write)
ICC2
Min
Typ
Max
Units
fSK = 1MHz
VCC = 5.0V
3
mA
Power Supply Current
(Read)
fSK = 1MHz
VCC = 5.0V
500
µA
ISB1
Power Supply Current
(Standby) (x8 Mode)
CS = 0V
ORG=GND
10
µA
ISB2
Power Supply Current
(Standby) (x16Mode)
CS=0V
ORG=Float or VCC
10
µA
ILI
Input Leakage Current
VIN = 0V to VCC
1
µA
ILO
Output Leakage Current
(Including ORG pin)
VOUT = 0V to VCC,
CS = 0V
1
µA
VIL1
Input Low Voltage
4.5V ≤ VCC < 5.5V
-0.1
0.8
V
VIH1
Input High Voltage
4.5V ≤ VCC < 5.5V
2
VCC + 1
V
VIL2
Input Low Voltage
1.8V ≤ VCC < 4.5V
0
VCC x 0.2
V
VIH2
Input High Voltage
1.8V ≤ VCC < 4.5V
VCC x 0.7
VCC+1
V
VOL1
Output Low Voltage
4.5V ≤ VCC < 5.5V
IOL = 2.1mA
0.4
V
VOH1
Output High Voltage
4.5V ≤ VCC < 5.5V
IOH = -400µA
VOL2
Output Low Voltage
1.8V ≤ VCC < 4.5V
IOL = 1mA
VOH2
Output High Voltage
1.8V ≤ VCC < 4.5V
IOH = -100µA
0
2.4
V
0.2
VCC - 0.2
V
V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
Doc. No. 1088, Rev. O
2
CAT93C56/57
PIN CAPACITANCE
Symbol
COUT
CIN
Test
Conditions
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
(2)
(2)
Min
Typ
Max
Units
VOUT=0V
5
pF
VIN=0V
5
pF
INSTRUCTION SET
Instruction
READ
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
Device
Type
93C56(1)
93C57
93C56(1)
93C57
93C56(1)
93C57
93C56(1)
93C57
93C56(1)
93C57
93C56(1)
93C57
93C56(1)
93C57
Start
Bit
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address
Opcode
10
10
11
11
01
01
00
00
00
00
00
00
00
00
Data
x8
A8-A0
A7-A0
A8-A0
A7-A0
A8-A0
A7-A0
x16
A7-A0
A6-A0
A7-A0
A6-A0
A7-A0
A6-A0
11XXXXXXX
11XXXXXX
11XXXXXX
11XXXXX
00XXXXXXX
00XXXXXX
00XXXXXX
00XXXXX
10XXXXXXX
10XXXXXX
10XXXXXX
10XXXXX
01XXXXXXX
01XXXXXX
01XXXXXX
01XXXXX
x8
x16
Comments
Read Address AN– A0
Clear Address AN– A0
D7-D0
D7-D0
D15-D0 Write Address AN– A0
D15-D0
Write Enable
Write Disable
Clear All Addresses
D7-D0
D7-D0
D15-D0 Write All Addresses
D15-D0
A.C. CHARACTERISTICS
Limits
VCC =
1.8V-5.5V
Test
Conditions
Min
Max
VCC =
2.5V-5.5V
Min
Max
VCC =
4.5V-5.5V
Symbol
Parameter
Min
Max
Units
tCSS
CS Setup Time
200
100
50
ns
tCSH
CS Hold Time
0
0
0
ns
tDIS
DI Setup Time
400
200
100
ns
tDIH
DI Hold Time
400
200
100
ns
tPD1
Output Delay to 1
tPD0
Output Delay to 0
tHZ(1)
Output Delay to High-Z
tEW
Program/Erase Pulse Width
tCSMIN
Minimum CS Low Time
1
0.5
0.25
µs
tSKHI
Minimum SK High Time
1
0.5
0.25
µs
tSKLOW
Minimum SK Low Time
1
0.5
0.25
µs
tSV
Output Delay to Status Valid
SKMAX
Maximum Clock Frequency
1
0.5
0.25
µs
CL = 100pF
1
0.5
0.25
µs
(3)
400
200
100
ns
10
10
10
ms
1
DC
250
0.5
DC
500
DC
0.25
µs
1000
kHz
Note:
(1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE
and ERASE commands.
(2) This parameter is tested initially and after a design or process change that affects the parameter.
3
Doc. No. 1088, Rev. O
CAT93C56/57
POWER-UP TIMING (1)(2)
Symbol
tPUR
tPUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Max
1
1
≤ 50ns
0.4V to 2.4V
0.8V, 2.0V
0.2VCC to 0.7VCC
0.5VCC
Units
ms
ms
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 4.5V
1.8V ≤ VCC ≤ 4.5V
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
(3) The input levels and timing reference points are shown in “AC Test Conditions” table.
DEVICE OPERATION
The CAT93C56/57 is a 2048-bit nonvolatile memory
intended for use with industry standard microprocessors. The CAT93C56/57 can be organized as either
registers of 16 bits or 8 bits. When organized as X16,
seven 10-bit instructions for 93C57; seven 11-bit
instructions for 93C56 control the reading, writing and
erase operations of the device. When organized as X8,
seven 11-bit instructions for 93C57; seven 12-bit instructions for 93C56 control the reading, writing and
erase operations of the device. The CAT93C56/57
operates on a single power supply and will generate
on chip, the high voltage required during any write
operation.
DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 7-bit address
(93C57)/ 8-bit address (93C56) (an additional bit when
organized X8) and for write operations a 16-bit data field
(8-bit for X8 organizations).
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C56/
57 will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting out
the data addressed (MSB first). The output data bits will
toggle on the rising edge of the SK clock and are stable
after the specified time delay (tPD0 or tPD1).
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of tCSMIN. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C56/57 can be determined by selecting the device
and polling the DO pin. Since this device features AutoClear before write, it is NOT necessary to erase a
memory location before it is written into.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high)
and polling the DO pin; DO low indicates that the
write operation is not completed, while DO high indicates that the device is ready for the next instruction. If
necessary, the DO pin may be placed back into a high
impedance state during chip select by shifting a dummy
“1” into the DI pin. The DO pin will enter the high
impedance state on the falling edge of the clock (SK).
Placing the DO pin into the high impedance state is
recommended in applications where the DI pin and the
Doc. No. 1088, Rev. O
4
CAT93C56/57
Figure 1. Sychronous Data Timing
tSKLOW
tSKHI
tCSH
SK
tDIS
tDIH
VALID
DI
VALID
tCSS
CS
tDIS
tPD0,tPD1
DO
tCSMIN
DATA VALID
Figure 2. Read Instruction Timing
SK
1
1
1
1
1
AN
AN–1
1
1
1
1
1
1
1
1
1
1
CS
Don't Care
DI
1
1
A0
0
HIGH-Z
DO
Dummy 0
D15 . . . D0
or
D7 . . . D0
Address + 1
D15 . . . D0
or
D 7 . . . D0
Address + 2
D15 . . . D0
or
D 7 . . . D0
Address + n
D15 . . .
or
D7 . . .
Figure 3. Write Instruction Timing
SK
tCSMIN
AN
DI
1
0
AN-1
A0
DN
D0
1
tSV
DO
STANDBY
STATUS
VERIFY
CS
tHZ
BUSY
HIGH-Z
READY
HIGH-Z
tEW
5
Doc. No. 1088, Rev. O
CAT93C56/57
Erase
Erase All
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of tCSMIN. The falling edge of CS will start the self clocking
clear cycle of the selected memory location. The clocking
of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of
the CAT93C56/57 can be determined by selecting the
device and polling the DO pin. Once cleared, the content
of a cleared location returns to a logical “1” state.
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of tCSMIN. The
falling edge of CS will start the self clocking clear cycle
of all memory locations in the device. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C56/57 can be determined by selecting the device
and polling the DO pin. Once cleared, the contents of all
memory bits return to a logical “1” state.
Erase/Write Enable and Disable
Write All
The CAT93C56/57 powers up in the write disable state.
Any writing after power-up or after an EWDS (write
disable) instruction must first be preceded by the EWEN
(write enable) instruction. Once the write instruction is
enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93C56/57
write and clear instructions, and will prevent any
accidental writing or clearing of the device. Data can be
read normally from the device regardless of the write
enable/disable status.
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C56/57 can be determined by
selecting the device and polling the DO pin. It is not
necessary for all memory locations to be cleared before
the WRAL command is executed.
Figure 4. Erase Instruction Timing
SK
STATUS VERIFY
CS
AN
DI
1
1
tCS
A0
AN-1
STANDBY
1
tSV
tHZ
HIGH-Z
DO
BUSY
READY
HIGH-Z
tEW
Doc. No. 1088, Rev. O
6
CAT93C56/57
Figure 5. EWEN/EWDS Instruction Timing
SK
STANDBY
CS
DI
1
0
0
*
* ENABLE=11
DISABLE=00
Figure 6. ERAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
tCS
DI
1
0
0
0
1
tSV
tHZ
HIGH-Z
DO
BUSY
READY
HIGH-Z
tEW
Figure 7. WRAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
tCSMIN
DI
1
0
0
0
DN
1
D0
tSV
tHZ
DO
BUSY
READY
HIGH-Z
tEW
7
Doc. No. 1088, Rev. O
CAT93C56/57
ORDERING INFORMATION
Prefix
Device #
CAT
93C56
Company ID
Suffix
I
V
Product Number
93C56: 2K
93C57: 2K
L
V
W
X
Y
ZD4
-1.8
–G
T3
Temperature Range
I = Industrial (-40°C - 85°C)
A = Automotive (-40°C - 105°C)
E = Extended (-40°C to + 125°C)
Die Revision
93C56: E
93C57: E
Operating Voltage
Blank (Vcc = 2.5V to 5.5V)
1.8 (Vcc = 1.8V to 5.5V)
Package
= PDIP
= SOIC, JEDEC
= SOIC, JEDEC
= SOIC, EIAJ(5)
= TSSOP
= TDFN (3x3mm)
(4)
Rev E
Tape & Reel
T: Tape & Reel
2: 2000/Reel(5)
3: 3000/Reel
Lead Finish
Blank: Matte-Tin
G: NiPdAu
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard finish is NiPdAu.
(3) The device used in the above example is a CAT93C56VI-1.8-GT3 (SOIC, Industrial Temperature, 1.8V to 5.5V Operating Voltage,
NiPdAu, Tape & Reel).
(4) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWE.) For additional
information, please contact your Catalyst sales office.
(5) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT93C56XI-T2.
(6) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
Doc. No. 1088, Rev. O
8
REVISION HISTORY
Date
Revision Comments
05/14/04
L
New Data Sheet Created From CAT93C46/56/57/66/86. Parts
CAT93C56, CAT93C56, CAT93C57, CAT93C66, CAT93C76 and
CAT93C86 have been separtated into single data sheets
10/7/04
M
Updated Instruction Set
03/18/05
N
Updated Description
10/13/06
O
Update Features
Update Pin Configuration
Update Functional Symbol
Update Pin Functions
Update D.C. Operating Characteristics (VCC Range)
Update A.C. Characteristics (VCC Range)
Update Ordering Informations
Copyrights, Trademarks and Patents
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issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
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PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
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OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
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Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
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Publication #:
Revison:
Issue date:
1088
O
10/13/06
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