CXA2647N
RF Signal Processor for CD Players
Description
The CXA2647N is an RF signal processing IC for
compact disc players.
30 pin SSOP (Plastic)
Features
• RF signal processor supporting 6× speed CD
• RF system VCA circuit
• RF system equalizer
• Supports pickups with built-in RF summing
amplifier
• Low current consumption mode (RF off mode)
• ROM/RW switching mode
• Center error amplifier
• Output DC level shift circuit
• TE balance adjustment function
Absolute Maximum Ratings
7
• Supply voltage
VCC
• Storage temperature
Tstg –65 to +150
• Allowable power dissipation
PD
620
Functions
• RF AC summing amplifier, equalizer, VCA
• RF DC summing amplifier
• Focus error amplifier
• Tracking error amplifier
• Center error amplifier
• Automatic power control
• VC buffer amplifier (analog block, digital block)
V
°C
mW
Operating Conditions
• Operating supply voltage range
VCC – GND 3.0 to 3.6
V
DVCC – GND 3.0 to 3.6
V
(0V ≤ VCC – DVCC < 2V)
• Operating temperature
Topr –30 to +85
°C
DC_OFST
RFDCI
RFDC
VC
RFC
VFC
BST
RFG
VCC
CEI
CE
TE_BAL
TE
FEI
FE
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LD
PD
EQ_IN
AC_SUM
GND
A
B
C
D
E
F
SW
DVCC
DVC
RFAC
Pin Configuration
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01997-PS
CXA2647N
RFG
BST
VFC
3
23
24
25
RFAC
EQ_IN
4
RFC
AC_SUM
Block Diagram
26
15
RF off at VCC
AC_SUM
VCA
EQ
30
ROM/
RW
A
6
B
7
C
8
D
9
29 RFDCI
ROM/
RW
28
VC
VOFST VC
DC_OFST
ROM/
RW
RFDC
21 CEI
20
DVC
CE
ROM/
RW
VC
ROM/
RW
VOFST
17 FEI
DVC
ROM/
RW
16
FE
19
TE_BAL
18
TE
VC
VOFST
PD
2
LD
1
VC
ROM/
RW
L: ROM DVC
H: RW
VC
DVC or Hi-Z
Sleep, APC off
APC
VC
VOFST
VC
VCC
DVC
VCC
5
22
–2–
27
14
DVC
12
ROM/
RW
gm
L or H
SW
VC
VC
10
gm
VCC
E
11
GND
F
13 DVCC
CXA2647N
Pin Description
Pin
No.
Symbol
I/O
Description
1
LD
O
APC amplifier output.
2
PD
I
APC amplifier input.
3
EQ_IN
I
RFAC system VCA block and EQ block input.
4
AC_SUM
O
RFAC system RF_SUM output.
5
GND
I
GND.
6
A
I
Signal A input.
7
B
I
Signal B input.
8
C
I
Signal C input.
9
D
I
Signal D input.
10
E
I
Signal E input.
11
F
I
Signal F input.
12
SW
I
Mode switching signal input.
13
DVCC
I
DVCC.
14
DVC
O
DVC output.
15
RFAC
O
RFAC signal output.
16
FE
O
Focus error signal output.
17
FEI
I
FE amplifier virtual ground.
18
TE
O
Tracking error signal output.
19
TE_BAL
I
TE balance adjustment.
20
CE
O
Center error signal output.
21
CEI
I
CE amplifier virtual ground.
22
VCC
I
VCC.
23
RFG
I
RFAC system VCA block low frequency gain adjustment.
24
BST
I
EQ boost level adjustment.
25
VFC
I
EQ cut-off frequency adjustment.
26
RFC
I
EQ cut-off frequency adjustment.
27
VC
O
VC voltage output.
28
RFDC
O
RFDC signal output.
29
RFDCI
I
RFDC amplifier virtual ground.
30
DC_OFST
I
RFDC signal output offset adjustment.
–3–
CXA2647N
Pin Description
Pin
No.
Symbol
I/O
Equivalent circuit
Description
600µA 100µA
10k
1
LD
O
APC amplifier output.
1
1k
10µA 20µA 10µA
2
PD
55k
I
APC amplifier input.
20k
2
20k
3
EQ_IN
I
3
Equalizer circuit input.
1.2k
5k
VC
VC
400µA 400µA
3.4k
4
AC_SUM
O
50
2k
4
RFAC summing amplifier
output.
400µA 400µA 500µA
5
GND
—
—
–4–
GND.
CXA2647N
Pin
No.
6
Symbol
A
I/O
Equivalent circuit
I
Description
10k
6
10k
100µA
100µA
400µA
7
7
B
I
100µA
30k
8
47k
100µA
47k
8
C
RFAC summing amplifier,
RFDC amplifier, focus error
amplifier and center error
amplifier input.
I
50µA
100µA
VC
9
100µA
30k
24k
9
D
I
24k
50µA
100µA
VC
10
E
I
10
Tracking error amplifier input.
11
11
F
100µA
I
VC
200k
200k
12
SW
I
12
200k
VC
13
DVCC
—
14
DVC
O
Digital power supply.
—
100
14
100
CD-ROM/SLEEP/CD-RW
switching input.
ROM when connected to GND,
RW when connected to DVCC,
SLEEP mode when connected
to DVC or Hi-Z.
25
–5–
(DVCC + GND)/2 voltage
output.
CXA2647N
Pin
No.
15
Symbol
RFAC
I/O
Equivalent circuit
O
FE
RFAC amplifier output.
15
100
1.4mA
16
Description
O
Focus error amplifier output.
50k
124
16
VC
50µA
17
FEI
I
18
TE
O
500µA
124
17
18
Tracking error amplifier output.
63k
100µA
500µA
45k
Input for adjusting the tracking
error amplifiers E and F gain
balance with the control
voltage.
19
19
TE_BAL
I
Focus error amplifier gain
adjustment.
The gain is adjusted by the
external resistance value
connected between this pin
and Pin 16.
5k
50µA
VC
20
CE
O
Center error amplifier output.
50k
124
20
VC
50µA
21
CEI
500µA
124
I
–6–
21
Center error amplifier gain
adjustment.
The gain is adjusted by the
external resistance value
connected between this pin
and Pin 20.
CXA2647N
Pin
No.
Symbol
I/O
Equivalent circuit
—
22
VCC
—
23
RFG
I
Description
VCC.
Input for setting the RFAC low
frequency gain with the
control voltage.
19.5k
23
VC
100µA
50µA
24
BST
I
20k
24
VC
Input for adjusting the
equalizer circuit boost level
with the control voltage.
25µA
Input for adjusting the
equalizer circuit cut-off
frequency with the control
voltage.
19k
25
VFC
I
25
VC
100µA
10µA
1.5V
124
26
RFC
I
27
VC
O
26
100
27
100 25
–7–
Input for adjusting the
equalizer circuit cut-off
frequency with the external
resistance.
(VCC + GND)/2 voltage
output.
CXA2647N
Pin
No.
28
Symbol
RFDC
I/O
Equivalent circuit
100µA
O
Description
250µA
RFDC amplifier output.
2k
124
28
VC
1mA
124
29
RFDCI
29
I
RFDC amplifier gain
adjustment.
The gain is adjusted by the
external resistance value
connected between this pin
and Pin 28.
24k
30
30
DC_OFST
VC
I
15k
10k
100µA
–8–
400µA
Input for adjusting RFDC
amplifier offset with the control
voltage.
CXA2647N
Description of Functions
• RFAC
The RF signal input by connecting capacitance to EQ_IN (Pin 3) is equalized, arithmetically amplified and then
output from RFAC (Pin 15).
A
6
B
7
C
8
D
9
AC_SUM
VCC
AC
SUM
Amp
100k
BST VFC
24 25 26 RFC
4
3
VCA
Amp
EQ
15 RFAC
EQ_IN
RFG 23
ROM/RW
Control Bias
VC – 1V to VC + 1V
RFAC OFF when BST = VCC
Low frequency gain (100kHz)
AC_SUM (ABCD to AC_SUM) 13dB
RFAC (EQ_IN to RFAC) ROM: 1.5dB
RW: 13.5dB
When BST (Pin 24) is connected to VCC, the RFAC function is turned off and the low consumption mode is
entered.
If RF (summing signal) is present at the pickup output pin, input the addition output signal to EQ_IN (Pin 3)
coupled by capacitance.
When using a pickup without a summing output function, perform addition with the AC_SUM and then input the
signal to EQ_IN (Pin 3) coupled by capacitance.
ROM/RW switching is done by the VCA block, so either input method can be used without problem.
The RW gain is 12dB higher than the ROM gain.
Gain [dB]
The VCA low frequency gain can be adjusted by the RFG
(Pin 23) voltage control.
The control voltage vs. low frequency gain characteristics
are shown in the graph to the right.
VCA variable range
8
0
–8
VC – 1
VC
VC + 1
Vcnt
[V]
The RFAC pin (Pin 15) is an NPN transistor emitter follower output.
The maximum drive current is approximately 1.4mA.
If the load capacitance distorts the output waveform, connect resistance between the RFAC pin and GND to
increase the drive current.
–9–
CXA2647N
• EQ
The EQ internal block diagram is shown below. The EQ is configured with the filter of the Bessel function of
order 4.
Boost
79.517fc2
Control
LPF1 =
2
S + (17.085fc) S + 79.517fc2
24 BST
Amp
HPF1
In
Control Bias
VC – 1V to VC + 1V
LPF1
LPF2
33kΩ to 100kΩ
S2
S2 + (17.085fc) S + 79.517fc2
LPF2 =
99.963fc2
S2 + (12.412fc) S + 99.963fc2
Out
The boost gain can be adjusted by adjusting the HPF1
gain.
The cut-off frequency is adjusted by the RFC external
resistance value and the VFC control voltage value.
fc Control
RFC 26
HPF1 =
25 VFC
Control Bias
VC – 1V to VC + 1V
RFC resistance value: The cut-off frequency fc of each
filter is adjusted by the Pin 26
external resistance value.
The VFC voltage can be varied
using this fc as the reference.
VFC voltage: fc can be adjusted by the voltage applied
to Pin 25. The cut-off frequency control
characteristics are shown in the graph
below.
The boost gain can be adjusted by the BST (Pin 24)
control voltage.
The control characteristics are shown in the graph
below.
The boost gain stands for the increased gain from the
low frequency gain in the fc frequency.
Gain
1.5fc
Boost
gain
5dB
fc Freq.
fc [Hz]
Boost gain [dB]
8dB
fc
0.5fc
–1dB
VC – 1.0
VC – 1.0
VC
VC + 1.0
BST voltage [V]
VC
VC + 1.0
VFC voltage [V]
RFC pin external resistor value 100kΩ: fc = 1.6MHz
33kΩ: fc = 4.8MHz
• APC (Automatic Power Control)
When the laser diode is driven by a constant current, the optical power output has extremely large negative
temperature characteristics. Therefore, the current must be controlled to maintain the monitor photodiode
output at a constant level. This control is performed by the APC function.
VCC
56k
PD 2
1 LD
10k
55k
10k
10k
1.25V
– 10 –
1k
56k
CXA2647N
• Focus Error
The signals input to the A and C pins and the B and D pins are arithmetically amplified and the focus error
signal is output.
This circuit has ROM/RW switching and offset addition functions.
VC
ROM
100k
RW
16 FE
FEI 17
23.5k
A 6
C 8
B 7
D 9
ROM
VOFST
100k
124
30k
124
50k
30k
30k
ROM
30k
47k
47k
200k
DVC
RW
RW
200k
FE = Gain { (B + D) – (A + C) }
Low frequency gain ROM: 15.5dB
RW: 27.5dB
Cut-off frequency fc (typ.) ROM: 400kHz
RW: 300kHz
• Tracking Error
The signals input to the E and F pins are arithmetically amplified and the tracking error signal is output.
This circuit has ROM/RW switching and offset addition functions.
VC
Control bias
VC – 1V to VC + 1V
TE = Gain (F – E)
TE_BAL 19
ROM
63k
63k ROM
251k RW
Low frequency gain
ROM: 16dB
RW: 28dB
VOFST
11
20k
10
F
E
RW
gm
20k
251k
10k
gm
20k
10k
VC
TE balance adjustment
(F – E) low frequency gain = ±6dB
18 TE
VC
31.5k
Cut-off frequency fc (typ.)
ROM: 200kHz
RW: 150kHz
125.5k
ROM
RW
VC
External resistance value vs. Low frequency gain for E and F input pins
Low frequency gain [dB]
20k
22
15.5
12.5
10k
20k
Resistance value [Ω]
– 11 –
30k
CXA2647N
• VC Buffer
• DVC Buffer
This outputs the VC ((1/2) VCC) voltage.
The maximum output current is approximately ±3mA.
Use this voltage as the analog block VC voltage.
This outputs the DVC ((1/2) DVCC) voltage.
The maximum output current is approximately ±3mA.
Use this voltage as the digital block VC voltage.
The each output DC voltage of FE, TE and CE is
level shifted using the DVC voltage as the reference.
VCC
40k
DVCC
VC 27
25
40k
40k
DVC 14
25
40k
• RFDC
The signals input to the A, B, C and D pins are added, amplified and the RFDC signal is output. ROM/RW
switching, low frequency gain adjustment and output DC voltage adjustment are possible.
30
A 6
B 7
C 8
D 9
ROM
VC
RW
VC
Control bias
VC – 1V to VC + 1V
ROM
RW
24k
96k
15k
10k
RFDCI 29
28 RFDC
124
124
ROM
15k
15k
5.1k
40k
RW
2k
15k
2.4k
VC
3.3k
RFDC = Gain (A + B + C + D)
Low frequency gain ROM: 16.5dB
RW: 28.5dB
Cut-off frequency fc (typ.)
ROM : 15MHz
RW : 6MHz
The gain can be adjusted by the external resistance connected between Pins 28 and 29.
The output voltage offset can be adjusted by controlling the Pin 30 voltage.
– 12 –
CXA2647N
• Center Error
The signals input to the A and D pins and the B and C pins are arithmetically amplified and the center error
signal is output.
ROM/RW switching and offset addition functions are incorporated.
VC
ROM
RW
12k
48k
A 6
200k
30k
D 9
20 CE
CEI 21
124
50k
124
30k
30k
B 7
ROM
C 8
ROM
VOFST
RW
30k
24k
24k
96k
DVC
RW
96k
CE = Gain {(B + C) – (A + D)} signal is arithmetically amplified.
Low frequency gain ROM: 15.5dB
RW: 27.5dB
Cut-off frequency fc (typ.)
ROM: 200kHz
RW: 200kHz
• Output DC Level Shift
The FE, TE and CE output DC voltages are level shifted to the digital VC voltage (DVC).
The reference voltage of this IC is the VC voltage, and only the output reference voltage changes.
The maximum output voltage of each output signal should be kept to the digital VCC voltage (DVCC) or less in
order to protect the DSP IC.
The VC and DVC voltages are arithmetically amplified
30k
and output as the VOFST voltage.
30k
The VOFST voltage serves as the level shift reference
DVC
VOFST
voltage, and is distributed to each block.
VC
15k
VOFST = 2VC –DVC
• SW
This controls the laser (APC) on/off, active/sleep mode, and ROM/RW mode switching.
Switching is controlled by the voltage applied to the SW pin.
Active/Sleep
SW 12
SW
SW low/high condition
Low: GND to DVC – 1.2V
High: DVC + 1.2V to Vcc
ROM/RW
APC ON/OFF
Status of Functions on SW Switching
Item
APC
Active/Sleep
ROM/RW
VCC
ON
Active
RW
VC or Hi-Z
OFF
Sleep
—
GND
ON
Active
ROM
Control
voltage
– 13 –
The VC buffer is always in active mode
even if it enters sleep mode.
In the function block, MODE SW is always
set to active mode.
Symbol
– 14 –
O
O
O
O O
O O
Frequency response Min_H Fac_MinH
Frequency response RF_HiFc Fac_HiFcf
Fac_BSTH
Fac_BSTL
Boost response BST_H
Boost response BST_L
Maximum output voltage H Vac_H
Maximum output voltage L Vac_L
20
21
22
23
24
25
O
O
Fac_MinL
Frequency response Min_L
18
17
19
O
Low frequency gain RW_cnt Gac_RW2
O
O
Gac_RW1
Low frequency gain RW_min
Low frequency gain RF_HiFc Gac_HiFc
O
Low frequency gain ROM_max Gac_ROM3
O
O
Low frequency gain ROM_cnt Gac_ROM2
Low frequency gain RW_max Gac_RW3
16
15
14
13
12
O
O
O
O
O
O
O
O
0.2Vp-p 1.6MHz
70mVp-p 1.6MHz
0.4Vp-p 7.2MHz
0.4Vp-p 2.4MHz
0.4Vp-p 800kHz
0.8Vp-p 100kHz
75mVp-p 100kHz
0.2Vp-p 100kHz
0.35Vp-p 100kHz
0.3Vp-p 100kHz
0.8Vp-p 100kHz
1.4Vp-p 100kHz
–0.85V
0.85V
0V
0V
1.0V
0V
–1.0V
1.0V
0V
–1.0V
0V
–1.0V
1.0V
AC_OfstRW
Offset voltage RW
11
Low frequency gain ROM_min Gac_ROM1
AC_OfstROM
Offset voltage ROM
10
O
SUM maximum output voltage L Vsum_L
9
–0.15V
O O O O
SUM maximum output voltage H Vsum_H
8
0.35V
O O O O
SUM frequency response Fsum
7
6
0.1Vp-p 10MHz
O O O O
Gsum
SUM low frequency gain
0.1Vp-p 100kHz
O O O O
ACSUM_Ofst
O
SUM offset voltage
5
4
3
RFAC EQ
2
Icc_Slp
0V
Current consumption (Sleep)
0V
0V
0V
0V
1.0V
1.0V
–1.0V
1.0V
0V
0V
E19 E23 E24 E25 E30
Icc_Dvcc
0V
E3
Bias conditions
Current consumption (DVCC)
0V
V3
V3
S1 S3-1 S3-2 S6 S7 S8 S9 S10 S11 S12-1 S12-2 S26 S27
amplitude frequency E2
Switch conditions
1.5V
Current consumption (Active, RF On) Icc_ARFon
Measurement item
12
30
17 mA
42 mA
3
4.2 mA
13
15
dB
Pin voltage
Pin voltage
6
–2
3
3
3
–2
6
10
7
7
7
5
10
14
–6
10
5
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
8.5 10.5 dB
5
5
5
1.5
8
12
–8
8
1.5
–6
V
V
0.65 0.85 1.05
V
15 Pin voltage – AC_OfstROM –0.95 –0.75 –0.55 V
15 Pin voltage – AC_OfstROM
15 20 log (Vout/Vin) – Gac_RW2 – Gac_ROM2 –2.5 –0.5 1.5 dB
15 20 log (Vout/Vin) – Gac_RW2 – Gac_ROM2 6.5
15 20 log (Vout/Vin) – Gac_HiFc
15 20 log (Vout/Vin) – Gac_ROM2
15 20 log (Vout/Vin) – Gac_ROM2
15 20 log (Vout/Vin)
15 20 log (Vout/Vin) – Gac_RW2 – Gac_ROM2
15 20 log (Vout/Vin) – Gac_ROM2
15 20 log (Vout/Vin) – Gac_RW2 – Gac_ROM2 –10
15 20 log (Vout/Vin) – Gac_ROM2
15 20 log (Vout/Vin)
–8
–0.45 –0.05 0.35
–0.45 –0.05 0.35
Pin voltage – ACSUM_Ofst –0.55 –0.35 –0.15 V
V
–2.5 –0.5 0.5 dB
11
–0.95 –0.55 –0.15 V
1.8
0.2 0.7 1.2 mA
7
18
Min. Typ. Max. Unit
Pin voltage – ACSUM_Ofst 1.15 1.35 1.55
20 log (Vout/Vin) – Gsum
20 log (Vout/Vin)
Pin voltage
Pin current
Pin current
Pin current
Pin current
Measurement
conditions
15 20 log (Vout/Vin) – Gac_ROM2 –10
15
15
4
4
4
4
4
22
13
22
22
ment pin
Measure-
(VCC = 1.5V, VEE = –1.5V, DVCC = 1.5V, DVEE = –1.5V)
Current consumption (Active, RF Off) Icc_ARFoff
1
RFAC SUM
Measure- Funcment No. tion
Electrical Characteristics
CXA2647N
DC_OfstRW
Offset voltage RW
FE_OfstRW
Offset voltage RW
36
– 15 –
O
O
Frequency response RW1 Ffe_RW1
Frequency response RW2 Ffe_RW2
Maximum output voltage H Vfe_H
Maximum output voltage L Vfe_L
43
44
45
46
O
O
Ffe_ROM2
41
Frequency response ROM2
O
O
42
O
O
Ffe_ROM1
Low frequency gain RW2 Gfe_RW2
Low frequency gain RW1 Gfe_RW1
Low frequency gain ROM2 Gfe_ROM2
Frequency response ROM1
40
39
38
37
O
O
O
O
O
O
O
O
O
FE_OfstROM
Offset voltage ROM
35
O
DC_Ofst1
Offset voltage 1
34
O
O O O O
Maximum output voltage L Vdc_L
33
O
O O O O
Maximum output voltage H Vdc_H
32
Low frequency gain ROM1 Gfe_ROM1
O O O O
O O O O
Frequency response RW Fdc_RW
Gdc_RW
O O O O
31
30
FE
O
O
O
O
O
O
O
O
1kHz
1kHz
25mVp-p 100kHz
25mVp-p 100kHz
0.1Vp-p 200kHz
0.1Vp-p 200kHz
25mVp-p 1kHz
25mVp-p 1kHz
0.1Vp-p
0.1Vp-p
12.5mVp-p 3MHz
50mVp-p 10MHz
12.5mVp-p 100kHz
50mVp-p 100kHz
0V
V3
V3
S1 S3-1 S3-2 S6 S7 S8 S9 S10 S11 S12-1 S12-2 S26 S27
amplitude frequency E2
Switch conditions
O O O O
Low frequency gain RW
Low frequency gain ROM Gdc_ROM
DC_OfstROM
Symbol
Offset voltage ROM
Measurement item
Frequency response ROM Fdc_ROM
29
28
27
26
RFDC
Measure- Funcment No. tion
0.18V
0.18V
0V
–0.25V
0.13V
0V
E3
0V
0V
0V
0V
28
28
28
28
28
28
28
28
ment pin
Measure-
0V
16
16
16
16
16
16
16
16
16
16
16
16
–0.5V 28
0V
E19 E23 E24 E25 E30
Bias conditions
120 mV
120 mV
13
dB
120 mV
120 mV
13
13
Pin voltage
1
1.45
V
dB
dB
dB
dB
dB
dB
–1.45 –1 –0.75 V
0.75
20 log (Vout/Vin) – Gfe_RW2–Gfe_ROM2 –2.5 –0.5 0.5
20 log (Vout/Vin) – Gfe–RW1 –Gfe_ROM1 –2.5 –0.5 0.5
20 log (Vout/Vin) – Gfe_ROM2 –2.5 –0.5 0.5
20 log (Vout/Vin) – Gfe_ROM1 –2.5 –0.5 0.5
12
12
12.5 15.5 18.5 dB
12.5 15.5 18.5 dB
–120 0
–120 0
20 log (Vout/Vin) – Gfe_ROM2 11
Pin voltage
V
–0.67 –0.55 –0.43 V
–1.5 –1.3 –1.1
0.35 0.55 0.75 V
–3 –0.5 0.5 dB
20 log (Vout/Vin) – Gfe_ROM1 11
20 log (Vout/Vin)
20 log (Vout/Vin)
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
20 log (Vout/Vin) – Gdc_RW _Gdc_ROM
20 log (Vout/Vin) – Gdc_ROM –3 –0.5 0.5 dB
12
13.5 16.5 19.5 dB
–120 0
–120 0
Min. Typ. Max. Unit
20 log (Vout/Vin) – Gdc_ROM 11
20 log (Vout/Vin)
Pin voltage
Pin voltage
Measurement
conditions
CXA2647N
TE_OfstRW
Offset voltage RW
– 16 –
CE_OfstRW
Offset voltage RW
Fce_ROM2
Frequency response ROM2
Frequency response RW1 Fce_RW1
Frequency response RW2 Fce_RW2
Maximum output voltage H Vce_H
Maximum output voltage L Vce_L
68
69
70
71
72
67
Fce_ROM1
Low frequency gain RW2 Gce_RW2
Low frequency gain RW1 Gce_RW1
Low frequency gain ROM2 Gce_ROM2
Low frequency gain ROM1 Gce_ROM1
CE_OfstROM
Offset voltage ROM
O
O O
O
O
O
O
O
O O
O O
O O
O O
O
O
O
O
O
O
Maximum output voltage H Vte_H
Maximum output voltage L Vte_L
O O
Frequency response ROM1
66
65
64
63
62
61
60
59
O
O
O
O
O O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
1kHz
1kHz
1kHz
1kHz
25mVp-p 100kHz
25mVp-p 100kHz
0.1Vp-p 100kHz
0.1Vp-p 100kHz
25mVp-p 1kHz
25mVp-p 1kHz
0.1Vp-p
0.1Vp-p
0.1Vp-p 10kHz
0.1Vp-p 10kHz
25mVp-p 100kHz
25mVp-p 100kHz
0.1Vp-p 100kHz
0.1Vp-p 100kHz
25mVp-p 1kHz
25mVp-p 1kHz
0.1Vp-p
0.1Vp-p
0V
V3
V3
S1 S3-1 S3-2 S6 S7 S8 S9 S10 S11 S12-1 S12-2 S26 S27
amplitude frequency E2
Switch conditions
Gte2
Balance gain 2
Balance gain 1
57
58
Frequency response RW2 Fte_RW2
56
Gte1
Frequency response RW1 Fte_RW1
55
Fte_ROM2
Fte_ROM1
Frequency response ROM2
Frequency response ROM1
Low frequency gain RW2 Gte_RW2
Low frequency gain RW1 Gte_RW1
Low frequency gain ROM2 Gte_ROM2
Low frequency gain ROM1 Gte_ROM1
TE_OfstROM
Symbol
Offset voltage ROM
Measurement item
54
53
52
51
50
49
48
CE
47
TE
Measure- Funcment No. tion
0.18V
0.18V
0V
0.18V
0.18V
0V
E3
0V
–1.0V
1.0V
0V
0V
0V
0V
0V
E19 E23 E24 E25 E30
Bias conditions
Measurement
conditions
12
–1
18 20 log (Vout/Vin) – Gte_ROM2 11
18 20 log (Vout/Vin) – Gte_ROM1 –3
–6
6
–4
8
0
0
0
0
13
13
19
19
120 mV
120 mV
12
13
13
dB
dB
20 Pin voltage
20 Pin voltage
1
1.45
V
–1.45 –1 –0.75 V
0.75
20 20 log (Vout/Vin) – Gce_RW2 – Gce_ROM2 –2.7 –1.2 0.3 dB
20 20 log (Vout/Vin) – Gce_RW1– Gce_ROM1 –2.7 –1.2 0.3 dB
20 20 log (Vout/Vin) – Gce_ROM2 –2.7 –1.2 0.3 dB
20 20 log (Vout/Vin) – Gce_ROM1 –2.7 –1.2 0.3 dB
20 20 log (Vout/Vin) – Gce_ROM2 11
12
12.5 15.5 18.5 dB
12.5 15.5 18.5 dB
–120 0
–120 0
–1.45 –1.2 –0.8 V
V
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
350 mV
150 mV
0.8 1.2 1.45
–8
4
20 20 log (Vout/Vin) – Gce_ROM1 11
20 20 log (Vout/Vin)
20 20 log (Vout/Vin)
20 Pin voltage
20 Pin voltage
18 Pin voltage
18 Pin voltage
18 E, F gain difference
18 E, F gain difference
18 20 log (Vout/Vin) – Gte_RW2– Gte_ROM2 –3.5 –1.5
18 20 log (Vout/Vin) – Gte_RW1– Gte_ROM1 –3.5 –1.5
–1
12
18 20 log (Vout/Vin) – Gte_ROM1 11
18 20 log (Vout/Vin) – Gte_ROM2 –3
16
13
18 20 log (Vout/Vin)
16
13
–350 0
–150 0
Min. Typ. Max. Unit
18 20 log (Vout/Vin)
18 Pin voltage
18 Pin voltage
ment pin
Measure-
CXA2647N
79
78
77
76
75
74
DVC AVC
73
APC
Measure- Funcment No. tion
Vapc3
Vapc_off
Iapc_max O
Output voltage 3
APC OFF voltage
Maximum output current
Output voltage
Vdvc
Vavc
Vapc2
Output voltage 2
Output voltage
Switch conditions
O
O
0V
0V
E3
0V
0V
0V
0V
0V
E19 E23 E24 E25 E30
Bias conditions
Vapc1 +
20mV
Vapc1 –
20mV
adj
V3
V3
S1 S3-1 S3-2 S6 S7 S8 S9 S10 S11 S12-1 S12-2 S26 S27
amplitude frequency E2
Vapc1
Symbol
Output voltage 1
Measurement item
14
27
1
1
1
1
1
ment pin
Measure-
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Input at which output voltage = 0V
Measurement
conditions
50 mV
50 mV
0
0
–50
V
–0.25 0.1 0.45
–50
V
1.25 1.45 1.5
V
V
1
–1 –0.75 –0.5
0.5 0.75
50 150 250 mV
Min. Typ. Max. Unit
CXA2647N
– 17 –
CXA2647N
Electrical Characteristics Measurement Circuit
VCC
100k
10k
5.1k
E30
E25 E24 E23
25
24
23
22
E
F
SW
DVCC
DVC
RFAC
4
5
6
7
8
9
10
11
12
13
14
15
S3-1
S1
10k
VEE S6
E2
0.8mA
S7
S8
S9
20k
S11
10k
DVCC DVC
S12-1
S3-2
VEE
TE
CE
20k
S10
FE
VCC
D
3
FEI
RFG
C
2
TE_BAL
BST
B
1
CEI
VFC
A
16
RFC
17
GND
VC
18
AC_SUM
19
RFDC
20
EQ_IN
21
10k
RFDCI
26
10k 100k
PD
27
E19
DC_OFST
28
S26
LD
29
10k
200k
S27
30
VCC
33k
DVC
S12-2
VCC
V3
E3
VEE DVCC
Application Circuit
VCC
RFAC
7
8
9
10
11
12
13
14
15
LD
PD IN
Drive
RF SUM
A
B
C
D
E
F
FE
DVC
6
FEI
DVCC
5
TE
SW
4
TE_BAL
F
3
CE
E
2
CEI
VCC
D
1
VC
RFG
16
C
17
BST
18
B
19
VFC
20
A
21
RFC
22
GND
23
AC_SUM
24
RFDC
25
EQ_IN
26
RFDCI
27
PD
28
FE
OUT
DC_OFST
29
TE
OUT
LD
30
CE
OUT
VCC
VCC
0.1µ
VCC
VCC
VCC
VCC
RFDC
OUT
VC
DVCC DVC
MODE
RFAC
Control
OUT
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 18 –
CXA2647N
A
B
C
D
VCC
23
24
RFAC
RFC
VFC
3
BST
EQ_IN
4
<OP>
<CXA2647N>
VCC
RFG
AC_SUM
VCC
VCC
Connection Example of DP and DSP
25
26
<DSP>
25
RF off at VCC
RFAC
RF
AC_SUM
VCA
VCC
EQ
VC
DC_OFST
A
A
29
6
VC
B
30
ROM/
RW
ROM/
RW
B
7
C
VC
VOFST VC
C
ROM/
RW
8
D
D
VC
28
VC
21
RFDCI
RFDC
RFDC
CEI
9
ROM/
RW
20
DVC
CE
CE
VC
VC
ROM/
RW
VOFST
ROM/
RW
17
16
DVC
FEI
FE
FE
VCC
VC
TE_BAL
19
VOFST
F
11
VC
gm
ROM/
RW
VC
E
TE
E
10
18
gm
PD
2
LD
1
APC
VC
VOFST
VC
VCC
DVC
13
DVCC
VCC
VCC
VC
22
GND
5
27
14
VC
GND
VCC
VC
SW 12
L: ROM DVC
H: RW
VC
DVC or Hi-Z
Sleep, APC off
VCC
L or H
TE
ROM/
RW
VC
VC
DVC
F
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 19 –
CXA2647N
Characteristics Graphs
1. EQ characteristics
(Vcc = 3.0V, DVcc = 3.0V)
Input: Pin 3 EQ_IN
Output: Pin 15 RFAC
1-2. EQ fc control characteristics
1-1. EQ ROM/RW characteristics
25
25
Pin 26 RFC = 100kΩ
Pin 25 VFC = VC
Pin 24 BST = VC
Pin 23 RFG = VC
20
ROM mode
Pin 26 RFC = 100k/33kΩ
Pin 25 VFC = control
Pin 24 BST = VC
Pin 23 RFG = VC
20
15
15
RFC = 100kΩ
VFC = VC + 1V
VFC = VC
VFC = VC – 1V
RW
[dB]
10
[dB]
10
5
RFC = 33kΩ
VFC = VC
VFC = VC + 1V
5
ROM
0
0
–5
–5
–10
1k
10k
100k
1M
10M
–10
10k
100k
[Hz]
30
ROM mode
Pin 26 RFC = 100k/33kΩ
Pin 25 VFC = VC
Pin 24 BST = control
Pin 23 RFG = VC
15
25
RFG = VC + 1V
RFC = 33kΩ
BST = VC + 1V
BST = VC
BST = VC – 1V
RFC = 100kΩ
BST = VC + 1V
BST = VC
BST = VC – 1V
20
15
10
RFG = VC – 1V
5
0
–5
–10
10k
RFG = VC
[dB]
[dB]
5
100M
1-4. EQ gain control characteristics
25
10
10M
[Hz]
1-3. EQ boost control characteristics
20
1M
RW mode
Pin 26 RFC = 100kΩ
Pin 25 VFC = VC
Pin 24 BST = VC
Pin 23 RFG = control
0
–5
100k
1M
10M
100M
[Hz]
1k
10k
100k
[Hz]
– 20 –
1M
10M
CXA2647N
2. AC_SUM characteristics
Input: Pin 6, 7, 8, 9 A, B, C, D
Output: Pin 4 AC_SUM
3. RFDC characteristics
Input: Pin 6, 7, 8, 9 A, B, C, D
Output: Pin 28 RFDC
25
40
Feed back registor 5.1kΩ
between Pin 28 & 29
15
30
10
25
RW
[dB]
35
[dB]
20
5
20
0
15
–5
10
ROM
–10
10k
100k
1M
10M
5
10k
100M
100k
[Hz]
1M
10M
100M
[Hz]
4. TE characteristics
Input: Pin 10 E
Output: Pin 18 TE
3. FE characteristics
Input: Pin 6, 8 A, C
Output: Pin 16 FE
40
40
Input (Pin 10 & 11) registor 200kΩ
Pin 19 TE_BAL = VC
Feed back registor 100kΩ
between Pin 16 & 17
35
35
30
RW
30
RW
[dB]
25
[dB]
25
20
20
ROM
ROM
15
15
10
10
5
5
1k
10k
100k
1M
10M
[Hz]
1k
10k
100k
[Hz]
– 21 –
1M
10M
CXA2647N
3. APC input/output characteristics
Input: Pin 2 PD
Output: Pin 1 LD
3. CE characteristics
Input: Pin 6, 9 A, D
Output: Pin 20 CE
40
3.5
Feed back registor 200kΩ
between Pin 20 & 21
35
3.0
VCC = 3.6V
30
2.5
Output LD [V]
RW
[dB]
25
20
2.0
1.5
ROM
15
1.0
10
0.5
5
VCC = 3.0V
0
1k
10k
100k
1M
10M
[Hz]
0
0.05
0.1
Input PD [V]
– 22 –
0.15
0.2
CXA2647N
Package Outline
Unit: mm
30PIN SSOP (PLASTIC)
+ 0.2
1.25 – 0.1
∗9.7 ± 0.1
0.10
1
A
15
0.65
0.13 M
b=0.22 ± 0.03
0.5 ± 0.2
0.1 ± 0.1
+ 0.03
0.15 – 0.01
b
7.6 ± 0.2
16
∗5.6 ± 0.1
30
DETAIL B : PALLADIUM
NOTE: Dimension "∗" does not include mold protrusion.
0° to 10°
PACKAGE STRUCTURE
DETAIL A
SONY CODE
EIAJ CODE
SSOP-30P-L01
P-SSOP30-5.6x9.7-0.65
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
PALLADIUM PLATING
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.1g
JEDEC CODE
– 23 –
Sony Corporation