AD ADG1206YRUZ-REEL7 Low capacitance, 16- and 8-channel -15 v/12 v icmos multiplexer Datasheet

Low Capacitance, 16- and 8-Channel
±15 V/+12 V iCMOS™ Multiplexers
ADG1206/ADG1207
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
ADG1206
S1A
DA
S8A
D
S1B
DB
S8B
S16
A0 A1 A2 EN
Figure 1.
The ultralow capacitance and exceptionally low charge injection
of these multiplexers make them ideal solutions for data
acquisition and sample-and-hold applications, where low glitch
and fast settling are required. Figure 2 shows that there is
minimum charge injection over the entire signal range of the
device. iCMOS construction also ensures ultralow power
dissipation, making the parts ideally suited for portable and
battery-powered instruments.
1.0
MUX (SOURCE TO DRAIN)
0.9 TA = 25°C
0.8
CHARGE INJECTION (pC)
The iCMOS (industrial CMOS) modular manufacturing
process combines high voltage CMOS (complementary metaloxide semiconductor) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation
of high voltage parts has been able to achieve. Unlike analog ICs
using conventional CMOS processes, iCMOS components can
tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced
package size.
A0 A1 A2 A3 EN
06119-001
Audio and video routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Communication systems
The ADG1206 and ADG1207 are monolithic iCMOS analog
multiplexers comprising sixteen single channels and eight
differential channels, respectively. The ADG1206 switches one
of sixteen inputs to a common output, as determined by the 4bit binary address lines A0, A1, A2, and A3. The ADG1207
switches one of eight differential inputs to a common
differential output, as determined by the 3-bit binary address
lines A0, A1, and A2. An EN input on both devices is used to
enable or disable the device. When disabled, all channels are
switched off. When on, each channel conducts equally well in
both directions and has an input signal range that extends to the
supplies.
1-OF-8
DECODER
1-OF-16
DECODER
APPLICATIONS
GENERAL DESCRIPTION
ADG1207
S1
0.7
0.6
VDD = +15V
VSS = –15V
0.5
0.4
0.3
VDD = +12V
VSS = 0V
0.2
0.1
0
–15
VDD = +5V
VSS = –5V
–10
–5
0
VS (V)
5
10
15
06119-002
<1 pC charge injection over full signal range
1.5 pF off capacitance
33 V supply range
120 Ω on resistance
Fully specified at ±15 V/+12 V
3 V logic-compatible inputs
Rail-to-rail operation
Break-before-make switching action
28-lead TSSOP and 32-lead, 5 mm × 5 mm LFCSP_VQ
Figure 2. Source-to-Drain Charge Injection vs. Source Voltage
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
ADG1206/ADG1207
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................7
Applications....................................................................................... 1
ESD Caution...................................................................................7
Functional Block Diagrams............................................................. 1
Pin Configurations and Function Descriptions ............................8
General Description ......................................................................... 1
Typical Performance Characteristics ........................................... 12
Revision History ............................................................................... 2
Terminology .................................................................................... 16
Specifications..................................................................................... 3
Test Circuits..................................................................................... 17
Dual Supply ................................................................................... 3
Outline Dimensions ....................................................................... 19
Single Supply ................................................................................. 5
Ordering Guide .......................................................................... 19
REVISION HISTORY
7/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG1206/ADG1207
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V, unless otherwise noted. 1
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between
Channels, ∆RON
On Resistance Flatness, RFLAT (On)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
+25°C
−40°C to
+85°C
−40°C to
+125°C
VSS to VDD
120
200
3.5
6
20
64
240
270
10
12
76
83
±0.6
±1
±0.6
±2
±0.6
±2
±0.03
±0.2
±0.05
±0.2
±0.08
±0.2
2.0
0.8
±0.005
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
Transition Time, tTRANSITION
2
Unit
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
VS = ±10 V, IS = −1 mA; see Figure 28
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −1 mA
Ω max
Ω typ
Ω max
VS = −5 V, 0 V, +5 V; IS = −1 mA
nA typ
VD = ±10 V, VS = ∓10 V; see Figure 29
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
Break-Before-Make Time Delay, tBBM
80
130
75
95
85
100
20
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
0.5
−85
−85
0.15
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
−3 dB Bandwidth ADG1206
−3 dB Bandwidth ADG1207
CS (Off )
280
490
1.5
2
11
12
7
9
MHz typ
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
tON (EN)
tOFF (EN)
165
185
105
115
125
140
10
CD (Off ) ADG1206
CD (Off ) ADG1207
Rev. 0 | Page 3 of 20
VS = 1 V, 10 V; VD = 10 V, 1 V; see Figure 29
VS = VD = ±10 V; see Figure 30
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 32
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 37
RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz;
see Figure 38
RL = 50 Ω, CL = 5 pF; see Figure 36
RL = 50 Ω, CL = 5 pF; see Figure 36
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
ADG1206/ADG1207
Parameter
CD, CS (On) ADG1206
CD, CS (On) ADG1207
POWER REQUIREMENTS
IDD
+25°C
13
15
8
10
−40°C to
+85°C
−40°C to
+125°C
0.002
1.0
IDD
260
420
ISS
0.002
VDD/VSS
1
2
1.0
±5/±16.5
Temperature range for Y version is −40°C to +125°C.
Guaranteed by design, not subject to production test.
Rev. 0 | Page 4 of 20
Unit
pF typ
pF max
pF typ
pF max
μA typ
μA max
μA typ
μA max
μA typ
μA max
V min/max
Test Conditions/Comments
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Digital inputs = 0 V, 5 V, or VDD
GND = 0V
ADG1206/ADG1207
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. 1
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between
Channels, ∆RON
On Resistance Flatness, RFLAT (On)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
+25°C
−40°C to
+85°C
−40°C to
+125°C
0 to VDD
300
475
5
16
60
±0.02
±0.2
±0.05
±0.2
±0.08
±0.2
567
625
26
27
±0.6
±1
±0.6
±2
±0.6
±2
2.0
0.8
±0.001
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tBBM
3
100
140
80
100
90
110
25
175
200
120
130
130
155
15
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth ADG1206
−3 dB Bandwidth ADG1207
CS (Off )
CD (Off ) ADG1206
CD (Off ) ADG1207
CD, CS (On) ADG1206
CD, CS (On) ADG1207
0.2
−85
−85
185
300
1.5
2
13
15
9
11
15
17
10
12
Rev. 0 | Page 5 of 20
Unit
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
VS = 0 V to10 V, IS = −1 mA; see Figure 28
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
Ω max
Ω typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
pF typ
pF max
pF typ
pF max
VS = 3 V, 6 V, 9 V; IS = −1 mA
VDD = 13.2 V
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 29
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 29
VS = VD = 1 V or 10 V; see Figure 30
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 32
VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 37
RL = 50 Ω, CL = 5 pF; see Figure 36
RL = 50 Ω, CL = 5 pF; see Figure 36
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
ADG1206/ADG1207
Parameter
POWER REQUIREMENTS
IDD
+25°C
−40°C to
+85°C
−40°C to
+125°C
0.002
1.0
IDD
VDD
1
2
260
420
5/16.5
Temperature range for Y version is −40°C to +125°C.
Guaranteed by design, not subject to production test.
Rev. 0 | Page 6 of 20
Unit
μA typ
μA max
μA typ
μA max
V min/max
Test Conditions/Comments
VDD = 13.2 V
Digital inputs = 0 V or VDD
Digital inputs = 5
VSS = 0 V, GND = 0 V
ADG1206/ADG1207
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog, Digital Inputs 1
Continuous Current, S or D
Peak Current, S or D (Pulsed at 1 ms,
10% Duty Cycle Maximum)
Operating Temperature Ranges
Industrial (Y Version)
Storage
Junction Temperature
28-Lead TSSOP
θJA, Thermal Impedance
θJC, Thermal Impedance
32-Lead LFCSP_VQ
θJA, Thermal Impedance
Reflow Soldering Peak Temperature
(Pb-Free)
1
Rating
35 V
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V
or 30 mA, whichever
occurs first
30 mA
100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating may be applied at any
one time.
–40°C to +125°C
–65°C to +150°C
150°C
97.9°C/W
14°C/W
27.27°C/W
260(+0/−5)°C
Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should
be limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 7 of 20
ADG1206/ADG1207
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
28
D
NC
2
27
VSS
NC
3
26
S8
S16
4
25
S7
S15
5
24
S6
S14
6
23
S5
S13
7
22
S4
S12
8
21
S3
S11
S2
19
S1
S9 11
18
EN
GND 12
17
A0
NC 13
16
A1
A3 14
15
A2
NC = NO CONNECT
32
31
30
29
28
27
26
25
NC = NO CONNECT
Figure 3. ADG1206 Pin Configuration—TSSOP
PIN 1
INDICATOR
ADG1206
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
S8
S7
S6
S5
S4
S3
S2
S1
06119-004
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
9
S10 10
S16
S15
S14
S13
S12
S11
S10
S9
GND
A3
A2
NC
NC
A1
A0
EN
TOP VIEW
(Not to Scale)
06119-003
ADG1206
NC
VDD
NC
D
NC
NC
NC
VSS
VDD
Figure 4. ADG1206 Pin Configuration—5 mm × 5 mm LFCSP_VQ,
Exposed Pad Tied to Substrate, VSS
Table 4. ADG1206 Pin Function Descriptions
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Pin Number
LFCSP_VQ
31
12, 13
26, 27, 28,
30, 32
1
2
3
4
5
6
7
8
9
–
10
11
14
15
16
19
20
21
22
23
24
25
26
27
17
18
19
20
21
22
23
24
25
S1
S2
S3
S4
S5
S6
S7
S8
VSS
28
29
D
TSSOP
1
2
3
Mnemonic
VDD
NC
NC
Description
Most Positive Power Supply Potential.
No Connect.
No Connect.
S16
S15
S14
S13
S12
S11
S10
S9
GND
NC
A3
A2
A1
A0
EN
Source Terminal 16. Can be an input or an output.
Source Terminal 15. Can be an input or an output.
Source Terminal 14. Can be an input or an output.
Source Terminal 13. Can be an input or an output.
Source Terminal 12. Can be an input or an output.
Source Terminal 11. Can be an input or an output.
Source Terminal 10. Can be an input or an output.
Source Terminal 9. Can be an input or an output.
Ground (0 V) Reference.
No Connect.
Logic Control Input.
Logic Control Input.
Logic Control Input.
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are
turned off. When this pin is high, the Ax logic inputs determine which switch is turned on.
Source Terminal 1. Can be an input or an output.
Source Terminal 2. Can be an input or an output.
Source Terminal 3. Can be an input or an output.
Source Terminal 4. Can be an input or an output.
Source Terminal 5. Can be an input or an output.
Source Terminal 6. Can be an input or an output.
Source Terminal 7. Can be an input or an output.
Source Terminal 8. Can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, this pin can be
connected to ground.
Drain Terminal. Can be an input or an output.
Rev. 0 | Page 8 of 20
ADG1206/ADG1207
Table 5. ADG1206 Truth Table
A3
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rev. 0 | Page 9 of 20
On Switch
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
NC
3
26
S8A
S8B
4
25
S7A
S7B
5
24
S6A
S6B
6
23
S5A
S5B
7
22
S4A
S4B
8
21
S3A
S3B
9
20
S2A
S2B 10
19
S1A
S1B 11
18
EN
GND 12
17
A0
NC 13
16
A1
NC 14
15
A2
TOP VIEW
(Not to Scale)
NC = NO CONNECT
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
Figure 5. ADG1207 Pin Configuration—TSSOP
1
2
3
4
5
6
7
8
NC = NO CONNECT
PIN 1
INDICATOR
ADG1207
TOP VIEW
(Not to Scale)
GND
A2
NC
NC
NC
A1
A0
EN
ADG1207
24
23
22
21
20
19
18
17
S8A
S7A
S6A
S5A
S4A
S3A
S2A
S1A
06119-037
DA
27
32
31
30
29
28
27
26
25
28
2
9
10
11
12
13
14
15
16
1
DB
06119-036
VDD
NC
DB
NC
VDD
NC
DA
NC
VSS
ADG1206/ADG1207
Figure 6. ADG1207 Pin Configuration—5 mm × 5 mm LFCSP_VQ
Exposed Pad Tied to Substrate, VSS
Table 6. ADG1207 Pin Function Descriptions
14
15
16
17
18
Pin Number
LFCSP_VQ
29
31
11, 12, 13
1
2
3
4
5
6
7
8
9
26, 28,
30, 32
–
10
14
15
16
19
20
21
22
23
24
25
26
27
17
18
19
20
21
22
23
24
25
S1A
S2A
S3A
S4A
S5A
S6A
S7A
S8A
VSS
28
27
DA
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
Mnemonic
VDD
DB
NC
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
GND
NC
Description
Most Positive Power Supply Potential.
Drain Terminal B. Can be an input or an output.
No Connect.
Source Terminal 8B. Can be an input or an output.
Source Terminal 7B. Can be an input or an output.
Source Terminal 6B. Can be an input or an output.
Source Terminal 5B. Can be an input or an output.
Source Terminal 4B. Can be an input or an output.
Source Terminal 3B. Can be an input or an output.
Source Terminal 2B. Can be an input or an output.
Source Terminal 1B. Can be an input or an output.
Ground (0 V) Reference.
No Connect.
NC
A2
A1
A0
EN
No Connect.
Logic Control Input.
Logic Control Input.
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are
turned off. When this pin is high, the Ax logic inputs determine which switch is turned on.
Source Terminal 1A. Can be an input or an output.
Source Terminal 2A. Can be an input or an output.
Source Terminal 3A. Can be an input or an output.
Source Terminal 4A. Can be an input or an output.
Source Terminal 5A. Can be an input or an output.
Source Terminal 6A. Can be an input or an output.
Source Terminal 7A. Can be an input or an output.
Source Terminal 8A. Can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, this pin can be
connected to ground.
Drain Terminal A. Can be an input or an output.
Rev. 0 | Page 10 of 20
ADG1206/ADG1207
Table 7. ADG1207 Truth Table
A2
X
0
0
0
0
1
1
1
1
A1
X
0
0
1
1
0
0
1
1
A0
X
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
On Switch Pair
None
1
2
3
4
5
6
7
8
Rev. 0 | Page 11 of 20
ADG1206/ADG1207
TYPICAL PERFORMANCE CHARACTERISTICS
200
250
TA = 25°C
180
VDD = +13.5V
VSS = –13.5V
200
TA = +125°C
140
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
160
VDD = +15V
VSS = –15V
VDD = +15V
VSS = –15V
120
VDD = +16.5V
VSS = –16.5V
100
80
60
40
TA = +85°C
150
TA = +25°C
100
TA = –40°C
50
–9 –6 –3
0
3
6
9
SOURCE OR DRAIN VOLTAGE (V)
12
15
18
0
–15
06119-005
0
–18 –15 –12
Figure 7. On Resistance as a Function of VD (VS) for Dual Supply
600
TA = 25°C
VDD = +4.5V
VSS = –4.5V
500
10
15
VDD = 12V
VSS = 0V
TA = +125°C
500
VDD = +5V
VSS = –5V
ON RESISTANCE (Ω)
400
VDD = +5.5V
VSS = –5.5V
300
200
100
TA = +85°C
400
TA = +25°C
300
TA = –40°C
200
–6
–4
–2
0
2
SOURCE OR DRAIN VOLTAGE (V)
4
6
0
06119-006
0
Figure 8. On Resistance as a Function of VD (VS) for Dual Supply
0
1200
400
VDD = 10.8V
VSS = 0V
VDD = +15V
VSS = –15V
VBIAS = +10V/–10V
1000
800
350
VDD = 12V
VSS = 0V
250
VDD = 13.2V
VSS = 0V
200
150
ID (OFF) – +
200
0
–200
IS (OFF) – +
–400
ID (OFF) + –
–800
50
–1000
2
4
6
8
10
SOURCE OR DRAIN VOLTAGE (V)
12
14
Figure 9. On Resistance as a Function of VD (VS) for Single Supply
–1200
06119-007
0
12
IS (OFF) + –
400
–600
100
0
10
ID, IS (ON) + +
600
LEAKAGE (pA)
300
4
6
8
SOURCE OR DRAIN VOLTAGE (V)
Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
450
TA = 25°C
2
06119-009
100
ID, IS (ON) – –
0
20
40
60
80
TEMPERATURE (°C)
100
120
06119-010
ON RESISTANCE (Ω)
–5
0
5
SOURCE OR DRAIN VOLTAGE (V)
Figure 10. On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
600
ON RESISTANCE (Ω)
–10
06119-008
20
Figure 12. ADG1206 Leakage Currents as a Function of Temperature,
Dual Supply
Rev. 0 | Page 12 of 20
ADG1206/ADG1207
6
400
ID (OFF) – +
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
300
CHARGE INJECTION (pC)
LEAKAGE (pA)
4
IS (OFF) + –
200
ID, IS (ON )+ +
100
0
–100
IS (OFF) – +
–200
DEMUX (DRAIN TO SOURCE)
TA = 25°C
ID (OFF) + –
VDD = +5V
VSS = –5V
2
0
VDD = +12V
VSS = 0V
VDD = +15V
VSS = –15V
–2
–4
ID, IS (ON) – –
0
20
40
60
80
TEMPERATURE (°C)
100
120
–6
–15
06119-011
Figure 13. ADG1206 Leakage Currents as a Function of Temperature,
Single Supply
–10
–5
0
VS (V)
15
350
IDD PER CHANNEL
TA = 25°C
300
VDD = +5V
VSS = –5V
160
VDD = +15V
VSS = –15V
140
250
TIME (ns)
120
100
80
60
200
150
VDD = +12V
VSS = 0V
100
VDD = +15V
VSS = –15V
40
50
VDD = +12V
VSS = 0V
0
0
2
4
6
8
10
LOGIC, INX (V)
12
14
16
0
–40
06119-012
20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 14. IDD vs. Logic Level
Figure 17. Transition Time vs. Temperature
0
1.0
MUX (SOURCE TO DRAIN)
0.9 TA = 25°C
–10
–20
0.8
OFF ISOLATION (dB)
0.7
0.6
VDD = +15V
VSS = –15V
0.5
0.4
0.3
VDD = +12V
VSS = 0V
0.2
VDD = +15V
VSS = –15V
TA = 25°C
–30
–40
–50
–60
–70
–80
–90
0.1
–100
VDD = +5V
VSS = –5V
–10
–5
0
VS (V)
5
10
15
06119-013
0
–15
–20
06119-050
180
IDD (µA)
10
Figure 16. Drain-to-Source Charge Injection vs. Source Voltage
200
CHARGE INJECTION (pC)
5
Figure 15. Source-to-Drain Charge Injection vs. Source Voltage
–110
10k
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 18. Off Isolation vs. Frequency
Rev. 0 | Page 13 of 20
1G
06119-016
–400
06119-014
–300
ADG1206/ADG1207
10
0
–10
TA = 25°C
LOAD = 10kΩ
TA = 25°C
–20
1
–40
THD + N (%)
CROSSTALK (dB)
–30
ADJACENT
CHANNELS
–50
–60
–70
VDD = +5V, VSS = –5V, VS = +3.5V rms
VDD = +15V, VSS = –15V, VS = +5V rms
0.1
–80
NON ADJACENT
CHANNELS
–90
100k
1M
10M
100M
1G
FREQUENCY (Hz)
0.01
10
06119-051
–110
10k
100
100k
20
0
TA = 25°C
VDD = +15V
VSS = –15V
TA = 25°C
18
–20
16
CAPACITANCE (pF)
–30
–40
ADJACENT
CHANNELS
–50
–60
–70
–80
14
SOURCE/DRAIN ON
12
10
DRAIN OFF
8
6
4
NON ADJACENT
CHANNELS
–110
10k
100k
1M
10M
100M
2
1G
FREQUENCY (Hz)
SOURCE OFF
0
–15
06119-052
–100
–10
–5
0
5
10
15
06119-054
–90
12
06119-055
CROSSTALK (dB)
10k
Figure 22. THD + N vs. Frequency
Figure 19. ADG1206 Crosstalk vs. Frequency
–10
1k
FREQUENCY (Hz)
06119-020
–100
VBIAS (V)
Figure 23. ADG1206 Capacitance vs. Source Voltage,
±15 V Dual Supply
Figure 20. ADG1207 Crosstalk vs. Frequency
20
–4
–6
18
ADG1207
SOURCE/DRAIN ON
16
CAPACITANCE (pF)
–10
ADG1206
–12
–14
14
DRAIN OFF
12
10
8
6
VDD = 12V
VSS = 0V
TA = 25°C
–16
4
–18
VDD = +15V
VSS = –15V
TA = 25°C
–20
10k
100k
SOURCE OFF
2
1M
10M
100M
FREQUENCY (Hz)
Figure 21. On Response vs. Frequency
1G
0
06119-053
ON RESPONSE (dB)
–8
0
2
4
6
VBIAS (V)
8
10
Figure 24. ADG1206 Capacitance vs. Source Voltage, 12 V Single Supply
Rev. 0 | Page 14 of 20
ADG1206/ADG1207
12
0
VDD = +15V
VSS = –15V
TA = 25°C
10
–10
–20
–30
8
AC PSRR (dB)
DRAIN OFF
6
4
–50
–60
–80
SOURCE OFF
0
–15
–10
–5
0
–90
5
10
15
VBIAS (V)
Figure 25. ADG1207 Capacitance vs. Source Voltage, ±15 V Dual Supply
14
VDD = 12V
VSS = 0V
TA = 25°C
12
SOURCE/DRAIN ON
10
DRAIN OFF
8
6
4
2
0
2
4
6
VBIAS (V)
8
10
12
06119-057
0
SOURCE OFF
Figure 26. ADG1207 Capacitance vs. Source Voltage, 12 V Single Supply
Rev. 0 | Page 15 of 20
–100
100
1k
10k
100k
FREQUENCY (Hz)
Figure 27. AC PSRR vs. Frequency
1M
10M
06119-058
2
CAPACITANCE (pF)
–40
–70
06119-056
CAPACITANCE (pF)
SOURCE/DRAIN ON
TA = 25°C
NO DECOUPLING CAPACITORS
VDD = +15V
VSS = –15V
V p-p = 0.63V
ADG1206/ADG1207
TERMINOLOGY
TBBM
Off time measured between the 80% points of the switches
when switching from one address state to another.
RON
Ohmic resistance between D and S.
ΔRON
Difference between the RON of any two channels.
VINL
Maximum input voltage for Logic 0.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured.
VINH
Minimum input voltage for Logic 1.
IS (Off)
Source leakage current when the switch is off.
IINL (IINH)
Input current of the digital input.
ID (Off)
Drain leakage current when the switch is off.
IDD
Positive supply current.
ID, IS (On)
Channel leakage current when the switch is on.
ISS
Negative supply current.
VD (VS)
Analog voltage on Terminals D and S.
Off Isolation
A measure of unwanted signal coupling through an off channel.
CS (Off)
Channel input capacitance for the off condition.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
CD (Off)
Channel output capacitance for the off condition.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
CD, CS (On)
On switch capacitance.
On Response
The frequency response of the on switch.
CIN
Digital input capacitance.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and the switch on condition.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and the switch off condition.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
ACPSRR (AC Power Supply Rejection Ratio)
Measures the ability of a part to avoid coupling noise and
spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of
signal on the output to the amplitude of the modulation is the
ACPSRR.
Rev. 0 | Page 16 of 20
ADG1206/ADG1207
TEST CIRCUITS
V
A
IDS
ID (ON)
ID (OFF)
A
S
NC
VD
Figure 28. On Resistance
50%
50%
D
A
VD
NC = NO CONNECT
Figure 29. Off Leakage
3V
ADDRESS
DRIVE (VIN)
D
VS
06119-025
VS
S
Figure 30. On Leakage
tr < 20ns
tf < 20ns
VDD
VSS
VDD
VSS
A0
0V
VIN
tTRANSITION
S1
A1
50Ω
VS1
S2 TO S15
A2
A3
tTRANSITION
VS16
S16
ADG12061
90%
2.4V
OUTPUT
OUTPUT
D
EN
GND
300Ω
35pF
1SIMILAR
06119-028
90%
CONNECTION FOR ADG1207.
Figure 31. Address to Output Switching Times, tTRANSITION
3V
ADDRESS
DRIVE (VIN)
VDD
VSS
VDD
VSS
A0
VIN
0V
S1
A1
50Ω
VS
S2 TO S15
A2
A3
S16
80%
ADG12061
80%
OUTPUT
2.4V
OUTPUT
D
EN
GND
300Ω
35pF
1SIMILAR
06119-029
tBBM
CONNECTION FOR ADG1207.
Figure 32. Break-Before-Make Delay, tBBM
3V
ENABLE
DRIVE (VIN)
50%
VDD
VSS
VDD
VSS
A0
50%
S1
A1
A2
0V
VS
S2 TO S16
A3
tOFF (EN)
0.9VO
OUTPUT
ADG12061
0.9VO
VIN
50Ω
1SIMILAR
Figure 33. Enable Delay, tON (EN), tOFF (EN)
Rev. 0 | Page 17 of 20
OUTPUT
D
EN
GND
300Ω
CONNECTION FOR ADG1207.
35pF
06119-030
tON (EN)
06119-027
IS (OFF)
D
06119-026
S
ADG1206/ADG1207
3V
VDD
VSS
VDD
A0
VSS
A1
A2
VIN
A3
ADG12061
VOUT
ΔVOUT
S
D
EN
VS
QINJ = CL × ΔVOUT
GND
VIN
1SIMILAR
CL
1nF
VOUT
06119-031
RS
CONNECTION FOR ADG1207.
Figure 34. Charge Injection
VSS
VDD
VSS
VDD
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
VOUT
S
VDD
S2
GND
VOUT
OFF ISOLATION = 20 log
VS
VOUT
VS
06119-032
RL
50Ω
VSS
VDD
VSS
0.1µF
0.1µF
NETWORK
ANALYZER
AUDIO PRECISION
VDD
VSS
RS
S
50Ω
IN
VS
D
VS
V p-p
D
INSERTION LOSS = 20 log
VOUT
GND
RL
10kΩ
VOUT
06119-035
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
VIN
06119-033
RL
50Ω
GND
VOUT
VS
Figure 37. Channel-to-Channel Crosstalk
0.1µF
S
R
50Ω
GND
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
Figure 35. Off Isolation
VDD
VSS
D
VS
D
VSS
0.1µF
S1
RL
50Ω
50Ω
50Ω
VDD
0.1µF
VSS
0.1µF
06119-034
VDD
0.1µF
Figure 38. THD + Noise
Figure 36. Bandwidth
Rev. 0 | Page 18 of 20
ADG1206/ADG1207
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
1
6.40 BSC
14
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
SEATING
PLANE
0.20
0.09
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 39. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
0.45
BSC
25
4.75
BSC SQ
*EXPOSED
PAD
(TOP VIEW)
PIN 1
INDICATOR
12° MAX
1.00 MAX
0.85 NOM
0.60
0.42
0.24
0.60
0.42
0.24
5.00
BSC SQ
2.85
2.70 SQ
2.55
0.50
BSC
32
1
24
BOTTOM
VIEW
0.50
0.40
0.30
17
16
8
9
3.50 REF
0.80 MAX
0.65 TYP
0.20
MIN
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.05
*COMPLIANT TO JEDEC STANDARDS MO-220
WITH EXCEPTION TO PADDLE ORIENTATION.
Figure 40. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG1206YRUZ 1
ADG1206YRUZ-REEL71
ADG1206YCPZ-REEL71
ADG1207YRUZ1
ADG1207YRUZ-REEL71
ADG1207YCPZ-REEL71
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Description
28-Lead Thin Shrink Small Outline Package [TSSOP]
28-Lead Thin Shrink Small Outline Package [TSSOP]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
28-Lead Thin Shrink Small Outline Package [TSSOP]
28-Lead Thin Shrink Small Outline Package [TSSOP]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Z = Pb-free part.
Rev. 0 | Page 19 of 20
Package Option
RU-28
RU-28
CP-32-2
RU-28
RU-28
CP-32-2
ADG1206/ADG1207
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06119-0-7/06(0)
Rev. 0 | Page 20 of 20