TI1 CSD86336Q3DT Synchronous buck nexfet power block Datasheet

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CSD86336Q3D
SLPS666 – MARCH 2018
CSD86336Q3D Synchronous Buck NexFET™ Power Block
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
The CSD86336Q3D NexFET™ power block is an
optimized design for synchronous buck applications
offering high-current, high-efficiency, and highfrequency capability in a small 3.3-mm × 3.3-mm
outline. Optimized for 5-V gate drive applications, this
product offers a flexible solution capable of providing
a high-density power supply when paired with any 5V gate drive from an external controller/driver.
1
Half-Bridge Power Block
93.0% System Efficiency at 12 A
Up to 20-A Operation
High-Frequency Operation (up to 1.5 MHz)
High-Density SON 3.3-mm × 3.3-mm Footprint
Optimized for 5-V Gate Drive
Low-Switching Losses
Ultra-Low-Inductance Package
RoHS Compliant
Halogen Free
Lead-Free Terminal Plating
Top View
2 Applications
•
•
•
•
Synchronous Buck Converters
– High-Frequency Applications
– High-Current, Low-Duty Cycle Applications
Multiphase Synchronous Buck Converters
POL DC-DC Converters
IMVP, VRM, and VRD Applications
8
VSW
7
VSW
3
6
VSW
4
5
BG
VIN
1
VIN
2
TG
TGR
PGND
(Pin 9)
P0116-01
Device Information(1)
DEVICE
MEDIA
QTY
PACKAGE
SHIP
CSD86336Q3D
13-Inch Reel
2500
CSD86336Q3DT
7-Inch Reel
250
SON
3.30-mm × 3.30-mm
Plastic Package
Tape
and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Power Block Efficiency and Power Loss
VIN
VDD
VDD
BOOT
VIN
ENABLE
PWM
ENABLE
PWM
DRVH
LL
DRVL
TGR
BG
Control
FET
VSW
Sync
FET
PGND
Driver IC
4.0
95
3.6
90
3.2
85
VOUT
CSD86336Q3D
Efficiency (%)
GND
TG
100
2.8
VIN = 12 V
VOUT = 1.3 V
fSW = 500 kHz
VGS = 5 V
LOUT = 950 nH
TJ = 25qC
80
75
70
65
Copyright © 2017, Texas Instruments Incorporated
2.4
2.0
1.6
1.2
60
Power Loss (W)
Typical Circuit
0.8
55
0.4
50
0.0
20
0
2
4
6
8
10
12
14
Output Current (A)
16
18
D000
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD86336Q3D
SLPS666 – MARCH 2018
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
1
1
1
2
3
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
3
3
3
3
4
5
6
8
Absolute Maximum Ratings ......................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Power Block Performance ........................................
Electrical Characteristics – Q1 Control FET .............
Electrical Characteristics – Q2 Sync FET .................
Typical Power Block Device Characteristics.............
Typical Power Block MOSFET Characteristics.........
6.4 Normalized Curves.................................................. 13
6.5 Calculating Power Loss and Safe Operating Area
(SOA) ....................................................................... 14
7
Layout ................................................................... 16
7.1 Recommended Schematic Overview ...................... 16
7.2 Recommended PCB Design Overview ................... 17
8
Device and Documentation Support.................. 19
8.1
8.2
8.3
8.4
8.5
9
Application and Implementation ........................ 11
Mechanical, Packaging, and Orderable
Information ........................................................... 20
9.1
9.2
9.3
9.4
6.1 Application Information............................................ 11
6.2 Power Loss Curves ................................................. 13
6.3 Safe Operating Area (SOA) Curves........................ 13
Receiving Notification of Documentation Updates.. 19
Community Resources............................................ 19
Trademarks ............................................................. 19
Electrostatic Discharge Caution .............................. 19
Glossary .................................................................. 19
Q3D Package Dimensions......................................
Pin Configuration.....................................................
Land Pattern Recommendation ..............................
Stencil Recommendation ........................................
20
20
21
22
4 Revision History
2
DATE
REVISION
NOTES
March 2018
*
Initial release.
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5 Specifications
5.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise noted) (1)
MIN
Voltage
MAX
VIN to PGND
25
VSW to PGND
25
VSW to PGND (10 ns)
UNIT
27
TG to TGR
–8
10
BG to PGND
–8
10
V
Pulsed current rating, IDM (2)
60
A
Power dissipation, PD
6
W
Avalanche
energy, EAS
Sync FET, ID = 40 A, L = 0.1 mH
80
Control FET, ID = 26 A, L = 0.1 mH
34
TJ and TSTG
Operating junction and storage temperature
(1)
(2)
–55
mJ
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
Pulse duration = 50 µS. Duty cycle = 0.01.
5.2 Recommended Operating Conditions
TA = 25°C (unless otherwise noted)
VGS
Gate drive voltage
VIN
Input supply voltage (1)
ƒSW
Switching frequency CBST = 0.1 µF (min)
MIN
MAX
4.5
8
UNIT
V
22
V
1500
Operating current
kHz
20
A
TJ
Operating temperature
125
°C
TSTG
Storage temperature
125
°C
(1)
Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For
reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.
5.3 Thermal Information
TA = 25°C (unless otherwise noted)
THERMAL METRIC
RθJA
MIN
Junction-to-ambient thermal resistance (min Cu) (1)
(1) (2)
MAX
UNIT
105
°C/W
RθJA
Junction-to-ambient thermal resistance (max Cu)
55
°C/W
RθJC
Junction-to-case thermal resistance (top of package) (1)
17
°C/W
RθJC
Junction-to-case thermal resistance (PGND pin) (1)
3.2
°C/W
(1)
(2)
2
2
RθJC is determined with the device mounted on a 1-in (6.45-cm ), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board
design.
Device mounted on FR4 material with 1-in2 (6.45-cm2) Cu.
5.4 Power Block Performance
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PLOSS
Power loss (1)
VIN = 12 V, VGS = 5 V, VOUT = 1.3 V, IOUT = 15 A,
ƒSW = 500 kHz, LOUT = 950 nH, TJ = 25°C
1.8
W
IQVIN
VIN quiescent current (1)
TG to TGR = 0 V, BG to PGND = 0 V, VIN = 12 V
10
µA
(1)
Measurement made with six 10-μF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and
using a high-current 5-V driver IC.
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5.5 Electrical Characteristics – Q1 Control FET
Tj = 25 °C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, IDS = 250 µA
IDSS
Drain-to-source leakage current
VGS = 0 V, VDS = 20 V
25
IGSS
Gate-to-source leakage current
VDS = 0 V, VGS = +10 / –8 V
VGS(th)
Gate-to-source threshold voltage
VDS = VGS, IDS = 250 µA
ZDS(on)
Effective AC on-impedance
VIN = 12 V, VGS = 5 V, VOUT = 1.3 V,
IOUT = 20 A, ƒSW = 500 kHz,
LOUT = 950 nH
9.1
mΩ
gfs
Transconductance
VDS = 2.5 V, IDS = 14 A
40
S
1.1
V
1.5
1
µA
100
nA
1.9
V
DYNAMIC CHARACTERISTICS
CISS
Input capacitance
COSS
Output capacitance
CRSS
Reverse transfer capacitance
RG
Series gate resistance
Qg
Gate charge total (4.5 V)
Qgd
Gate charge – gate-to-drain
Qgs
Gate charge – gate-to-source
Qg(th)
Gate charge at Vth
QOSS
Output charge
td(on)
Turn on delay time
tr
Rise time
td(off)
Turn off delay time
tf
Fall time
VGS = 0 V, VDS = 12.5 V, ƒ = 1 Mhz
380
494
pF
263
342
pF
14.1
18.3
pF
4.0
8.0
Ω
2.9
3.8
nC
0.6
nC
1.4
nC
0.6
nC
VDS = 12.5 V, VGS = 0 V
5.4
nC
5
ns
VDS = 12.5 V, VGS = 4.5 V, IDS = 14 A,
RG = 0 Ω
10
ns
7
ns
2
ns
VDS = 12.5 V, IDS = 14 A
DIODE CHARACTERISTICS
VSD
Diode forward voltage
Qrr
Reverse recovery charge
trr
Reverse recovery time
4
IDS = 14 A, VGS = 0 V
0.86
VDS = 12.5 V, IF = 14 A, di/dt = 300 A/µs
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1.0
V
14.7
nC
15
ns
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5.6 Electrical Characteristics – Q2 Sync FET
Tj = 25 °C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, IDS = 250 µA
IDSS
Drain-to-source leakage current
VGS = 0 V, VDS = 20 V
25
IGSS
Gate-to-source leakage current
VDS = 0 V, VGS = +10 / –8 V
VGS(th)
Gate-to-source threshold voltage
VDS = VGS, IDS = 250 µA
ZDS(on)
Effective AC on-impedance
VIN = 12 V, VGS = 5 V, VOUT = 1.3 V,
IOUT = 20 A, ƒSW = 500 kHz,
LOUT = 950 nH
3.4
mΩ
gfs
Transconductance
VDS = 2.5 V, IDS = 14 A
57
S
1.0
V
1.3
1
µA
100
nA
1.6
V
DYNAMIC CHARACTERISTICS
CISS
Input capacitance
COSS
Output capacitance
CRSS
Reverse transfer capacitance
RG
Series gate resistance
Qg
Gate charge total (4.5 V)
Qgd
Gate charge – gate-to-drain
Qgs
Gate charge – gate-to-source
Qg(th)
Gate charge at Vth
QOSS
Output charge
td(on)
Turn on delay time
tr
Rise time
td(off)
Turn off delay time
tf
Fall time
VGS = 0 V, VDS = 12.5 V, ƒ = 1 Mhz
VDS = 12.5 V, IDS = 14 A
VDS = 12.5 V, VGS = 0 V
VDS = 12.5 V, VGS = 4.5 V, IDS = 14 A,
RG = 0 Ω
728
970
pF
501
664
pF
pF
26
33
0.65
1.3
Ω
5.7
7.4
nC
1.2
nC
2.1
nC
1.0
nC
10.3
nC
4
ns
10
ns
8
ns
2
ns
DIODE CHARACTERISTICS
VSD
Diode forward voltage
Qrr
Reverse recovery charge
trr
Reverse recovery time
IDS = 14 A, VGS = 0 V
VDS = 12.5 V, IF = 14 A, di/dt = 300 A/µs
Max RθJA = 55°C/W
when mounted on 1 in2
(6.45 cm2) of 2-oz
(0.071-mm) thick Cu.
0.82
0.95
nC
18
ns
Max RθJA = 105°C/W
when mounted on
minimum pad area of
2-oz (0.071-mm) thick
Cu.
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25.4
5
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5.7 Typical Power Block Device Characteristics
Test conditions: VIN = 12 V, VDD = 5 V, ƒSW = 500 kHz, VOUT = 1.3 V, LOUT = 0.95 µH, IOUT = 20 A, TJ = 125°C, unless stated
otherwise.
1.05
3.5
1.00
Power Loss, Normalized
4.0
Power Loss (W)
3.0
2.5
2.0
1.5
1.0
0.5
0.95
0.90
0.85
0.80
0.75
0.70
0.0
0
2
4
6
8
10
12
14
Output Current (A)
16
18
20
0.65
-50
-25
0
D001
Figure 1. Power Loss vs Output Current
25
50
75
100
Junction Temperature (qC)
125
150
D002
Figure 2. Power Loss vs Temperature
25
Output Current (A)
20
15
10
5
0
0
20
40
60
80
100
Board Temperature (qC)
120
Figure 3. Typical Safe Operating Area (SOA)
(1)
6
140
D005
(1)
The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with dimensions of 4 in (W)
× 3.5 in (L) × 0.062 in (H) and 6 copper layers of 1-oz copper thickness. See Application and Implementation section for detailed
explanation.
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Typical Power Block Device Characteristics (continued)
1.30
2.9
3.4
1.25
2.4
1.30
2.9
1.20
2.0
1.25
2.4
1.20
2.0
1.15
1.5
1.15
1.5
1.10
1.0
1.10
1.0
1.05
0.5
1.05
0.5
1.00
0.0
-0.5
1.00
0.0
0.95
-0.5
0.95
-1.0
1700
0.90
300
500
700
900 1100 1300
Switching Frequency (kHz)
1500
0
D006
Figure 4. Normalized Power Loss vs Switching Frequency
1.4
0.6
0.5
1.04
0.4
1.03
0.3
1.02
0.2
1.01
0.1
1.00
0.0
1.0
0.0
-1.0
4.3
4.8
Figure 5. Normalized Power Loss vs Input Voltage
1.05
1.1
2.3 2.8 3.3 3.8
Output Voltage (V)
D007
0.7
2.0
1.8
-1.0
18
1.06
1.2
1.3
16
4.9
2.9
0.8
14
0.8
1.3
0.9
8
10
12
Input Voltage (V)
1.07
3.9
1.0
6
1.08
-2.0
5.3
Power Loss, Normalized
Power Loss, Normalized
1.5
4
5.9
SOA Temperature Adj. (qC)
1.6
0.8
0.3
2
0.99
0.98
50
-0.1
200
D008
Figure 6. Normalized Power Loss vs Output Voltage
SOA Temperature Adj. (qC)
0.90
100
SOA Temperature Adj. (qC)
3.9
1.35
Power Loss, Normalized
1.40
SOA Temperature Adj. (qC)
Power Loss, Normalized
Test conditions: VIN = 12 V, VDD = 5 V, ƒSW = 500 kHz, VOUT = 1.3 V, LOUT = 0.95 µH, IOUT = 20 A, TJ = 125°C, unless stated
otherwise.
350
500
650
800
Output Inductance (nH)
950
-0.2
1100
D009
Figure 7. Normalized Power Loss vs Output Inductance
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5.8 Typical Power Block MOSFET Characteristics
100
100
90
90
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
TA = 25°C, unless stated otherwise.
80
70
60
50
40
30
20
VGS = 4.5 V
VGS = 6 V
VGS = 8.0 V
10
80
70
60
50
40
30
20
VGS = 4.5 V
VGS = 6 V
VGS = 8.0 V
10
0
0
0
0.3
0.6
0.9
1.2
1.5
VDS - Drain-to-Source Voltage (V)
1.8
0
0.1
Figure 8. Control MOSFET Saturation
IDS - Drain-to-Source Current (A)
TC = 125° C
TC = 25° C
TC = -55° C
10
1
0.1
0.01
D011
TC = 125° C
TC = 25° C
TC = -55° C
10
1
0.1
0.01
0.001
0
0.5
1
1.5
2
2.5
3
VGS - Gate-to-Source Voltage (V)
3.5
4
0
0.5
D012
1
1.5
2
2.5
VGS - Gate-to-Source Voltage (V)
VDS = 5 V
3
3.5
D013
VDS = 5 V
Figure 10. Control MOSFET Transfer
Figure 11. Sync MOSFET Transfer
8
8
7
7
VGS - Gate-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
0.8
100
0.001
6
5
4
3
2
1
0
6
5
4
3
2
1
0
0
1
2
3
Qg - Gate Charge (nC)
ID = 14 A
4
5
0
1
2
D014
VDD = 12.5 V
Figure 12. Control MOSFET Gate Charge
8
0.7
Figure 9. Sync MOSFET Saturation
100
IDS - Drain-to-Source Current (A)
0.2
0.3
0.4
0.5
0.6
VDS - Drain-to-Source Voltage (V)
D010
3
4
5
6
7
Qg - Gate Charge (nC)
ID = 14 A
8
9
10
D015
VDD = 12.5 V
Figure 13. Sync MOSFET Gate Charge
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Typical Power Block MOSFET Characteristics (continued)
TA = 25°C, unless stated otherwise.
5000
10000
C - Capacitance (pF)
C - Capacitance (pF)
1000
100
10
1000
100
10
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1
1
0
5
10
15
20
VDS - Drain-to-Source Voltage (V)
25
0
5
D016
Figure 14. Control MOSFET Capacitance
10
15
20
VDS - Drain-to-Source Voltage (V)
25
D017
Figure 15. Sync MOSFET Capacitance
1.9
1.7
VGS(th) - Threshold Voltage (V)
VGS(th) - Threshold Voltage (V)
1.6
1.7
1.5
1.3
1.1
0.9
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
-75
-50
-25
0
25
50
75 100
TC - Case Temperature (° C)
125
150
0.7
-75
175
-50
-25
D018
ID = 250 µA
125
150
175
D019
ID = 250 µA
Figure 16. Control MOSFET VGS(th)
Figure 17. Sync MOSFET VGS(th)
20
10
TC = 25° C, I D = 14 A
TC = 125° C, I D = 14 A
18
RDS(on) - On-State Resistance (m:)
RDS(on) - On-State Resistance (m:)
0
25
50
75 100
TC - Case Temperature (° C)
16
14
12
10
8
6
4
2
0
TC = 25° C, I D = 14 A
TC = 125° C, I D = 14 A
9
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
VGS - Gate-to-Source Voltage (V)
9
Figure 18. Control MOSFET RDS(on) vs VGS
10
0
1
2
D020
3
4
5
6
7
8
VGS - Gate-to-Source Voltage (V)
9
10
D021
Figure 19. Sync MOSFET RDS(on) vs VGS
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Typical Power Block MOSFET Characteristics (continued)
TA = 25°C, unless stated otherwise.
1.6
VGS = 4.5 V
VGS = 8.0 V
Normalized On-State Resistance
Normalized On-State Resistance
1.6
1.4
1.2
1
0.8
0.6
-75
-50
-25
0
25
50
75 100
TC - Case Temperature (° C)
ID = 14 A
125
150
VGS = 4.5 V
VGS = 8.0 V
1.4
1.2
1
0.8
0.6
-75
175
125
150
175
D023
VGS = 4.5 V
Figure 21. Sync MOSFET Normalized RDS(on)
100
TC = 25° C
TC = 125° C
10
ISD - Source-to-Drain Current (A)
ISD - Source-to-Drain Current (A)
0
25
50
75 100
TC - Case Temperature (° C)
ID = 14 A
Figure 20. Control MOSFET Normalized RDS(on)
1
0.1
0.01
0.001
0.0001
TC = 25° C
TC = 125° C
10
1
0.1
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
VSD - Source-to-Drain Voltage (V)
1
0
Figure 22. Control MOSFET Body Diode
0.4
0.6
0.8
VSD - Source-to-Drain Voltage (V)
1
D025
Figure 23. Sync MOSFET Body Diode
100
IAV - Peak Avalanche Current (A)
TC = 25q C
TC = 125q C
10
1
0.01
0.2
D024
100
IAV - Peak Avalanche Current (A)
-25
VGS = 4.5 V
100
0.1
TAV - Time in Avalanche (ms)
1
10
TC = 25q C
TC = 125q C
1
0.01
D026
Figure 24. Control MOSFET Unclamped Inductive Switching
10
-50
D022
0.1
TAV - Time in Avalanche (ms)
1
D027
Figure 25. Sync MOSFET Unclamped Inductive Switching
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6 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1 Application Information
6.1.1 Equivalent System Performance
Many of today’s high-performance computing systems require low-power consumption in an effort to reduce
system operating temperatures and improve overall system efficiency. This has created a major emphasis on
improving the conversion efficiency of today’s synchronous buck topology. In particular, there has been an
emphasis in improving the performance of the critical power semiconductor in the power stage of this application
(see Figure 26). As such, optimization of the power semiconductors in these applications, needs to go beyond
simply reducing RDS(ON).
Power Stage
Components
Input
Supply
Power Block
Components
Ci
+
-
Control
FET
Driver
PWM
Driver
Switch
Node
Lo
Sync
FET
Co
IL
Load
Copyright © 2017, Texas Instruments Incorporated
Figure 26. Synchronous Buck Topology
The CSD86336Q3D is part of TI’s power block product family which is a highly optimized product for use in a
synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest
generation silicon which has been optimized for switching performance, as well as minimizing losses associated
with QGD, QGS, and QRR. Furthermore, TI’s patented packaging technology has minimized losses by nearly
eliminating parasitic elements between the control FET and sync FET connections (see Figure 27). A key
challenge solved by TI’s patented packaging technology is the system level impact of Common Source
Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases
switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the
MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system
efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI
and modification of switching loss equations are outlined in Power Loss Calculation With Common Source
Inductance Consideration for Synchronous Buck Converters (SLPA009).
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Application Information (continued)
Input
Supply
RPCB
CESR
LDRAIN
CINPUT
Control
FET
Driver
PWM
CESL
LSOURCE
Switch
Node
Lo
Co
IL
Load
LDRAIN
Sync
FET
Driver
CTOTAL
LSOURCE
Figure 27. Elimination of Common Source Inductance
The combination of TI’s latest generation silicon and optimized packaging technology has created a
benchmarking solution that outperforms industry standard MOSFET chipsets of similar RDS(ON) and MOSFET
chipsets with lower RDS(ON). Figure 28 and Figure 29 compare the efficiency and power loss performance of the
CSD86336Q3D versus industry standard MOSFET chipsets commonly used in this type of application. This
comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The
performance of CSD86336Q3D clearly highlights the importance of considering the effective AC on-impedance
(ZDS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET
RDS(ON) specifications is not an indicator of the actual in-circuit performance when using TI’s power block
technology.
96
4.8
94
4.2
3.6
VGS = 5 V
VIN = 12 V
VOUT = 1.3 V
LOUT = 950 nH
fSW = 500 kHz
TA = 25qC
90
88
86
Power Loss (W)
Efficiency (%)
92
PowerBlock HS/LS RDS(ON) = 9.1 m:/4.6 m:
PowerBlock HS/LS RDS(ON) = 9.1 m:/4.6 m:
PowerBlock HS/LS RDS(ON) = 9.1 m:/3.4 m:
84
VGS = 5 V
VIN = 12 V
VOUT = 1.3 V
LOUT = 950 nH
fSW = 500 kHz
TA = 25qC
3.0
2.4
1.8
1.2
PowerBlock HS/LS RDS(ON) = 9.1 m:/4.6 m:
PowerBlock HS/LS RDS(ON) = 9.1 m:/4.6 m:
PowerBlock HS/LS RDS(ON) = 9.1 m:/3.4 m:
82
0.6
80
0.0
0
2
4
6
8
10
12
14
Output Current (A)
16
18
20
0
2
D030
Figure 28. Efficiency
12
4
6
8
10
12
14
Output Current (A)
16
18
20
D031
Figure 29. Power Loss
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Application Information (continued)
Table 1 compares the traditional DC measured RDS(ON) of CSD86336Q3D versus its ZDS(ON). This comparison
takes into account the improved efficiency associated with TI’s patented packaging technology. As such, when
comparing TI’s power block products to individually packaged discrete MOSFETs or dual MOSFETs in a
standard package, the in-circuit switching performance of the solution must be considered. In this example,
individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC
measured RDS(ON) values that are equivalent to the ZDS(ON) value of CSD86336Q3D in order to have the same
efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged discrete
MOSFETs or dual MOSFETs in a standard package.
Table 1. Comparison of RDS(ON) vs ZDS(ON)
HS
PARAMETER
LS
TYP
MAX
TYP
MAX
Effective AC on-impedance ZDS(ON) (VGS = 5 V)
9.1
—
3.4
—
DC measured RDS(ON) (VGS = 4.5 V)
9.1
11.4
4.6
5.7
The CSD86336Q3D NexFET™ power block is an optimized design for synchronous buck applications using 5-V
gate drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systemscentric environment. System-level performance curves such as power loss, safe operating area (SOA), and
normalized graphs allow engineers to predict the product performance in the actual application.
6.2 Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices.
In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss
performance curves. Figure 1 plots the power loss of the CSD86336Q3D as a function of load current. This curve
is measured by configuring and running the CSD86336Q3D as it would be in the final application (see
Figure 30). The measured power loss is the CSD86336Q3D loss and consists of both input conversion loss and
gate drive loss. Equation 1 is used to generate the power loss curve.
(VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT) = power loss
(1)
The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C
under isothermal test conditions.
6.3 Safe Operating Area (SOA) Curves
The SOA curve in the CSD86336Q3D data sheet provides guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss. Figure 3 outlines the
temperature conditions required for a given load current. The area under the curve dictates the safe operating
area. All the curves are based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L)
× 0.062 in (T) and 6 copper layers of 1-oz copper thickness.
6.4 Normalized Curves
The normalized curves in the CSD86336Q3D data sheet provides guidance on the power loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in
power loss and the secondary Y-axis is the change in system temperature required in order to comply with the
SOA curve. The change in power loss is a multiplier for the power loss curve and the change in temperature is
subtracted from the SOA curve.
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Normalized Curves (continued)
Input Current (IIN)
Gate Drive
Current (IDD)
VDD
A
A
VDD
V
Input Voltage (VIN)
VIN
Gate Drive V
Voltage (VDD)
VIN
BOOT
DRVH
ENABLE
TG
Control
FET
Output Current (IOUT)
VSW
LL
PWM
PWM
DRVL
GND
Driver IC
A
TGR
BG
VOUT
Sync
FET
PGND
Averaging
Circuit
CSD86336Q3D
Averaged Switch
V Node Voltage
(VSW_AVG)
Copyright © 2017, Texas Instruments Incorporated
Figure 30. Typical Application
6.5 Calculating Power Loss and Safe Operating Area (SOA)
The user can estimate power loss and SOA boundaries by arithmetic means (see Design Example). Though the
power loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following
procedure will outline the steps the user should take to predict product performance for any set of system
conditions.
6.5.1 Design Example
Operating conditions:
• Output current = 18.0 A
• Input voltage = 5.0 V
• Output voltage = 1.8 V
• Switching frequency = 750 kHz
• Inductor = 290 nH
6.5.2 Calculating Power Loss
•
•
•
•
•
•
Power loss at 18 A = 3.03 W (Figure 1)
Normalized power loss for input voltage ≈ 1.1 (Figure 5)
Normalized power loss for output voltage ≈ 1.07 (Figure 6)
Normalized power loss for switching frequency ≈ 1.08 (Figure 4)
Normalized power loss for output inductor ≈ 1.0 (Figure 7)
Final calculated power loss = 3.03 W × 1.1 × 1.07 × 1.08 × 1.0 ≈ 3.85 W
6.5.3 Calculating SOA Adjustments
•
•
•
•
•
14
SOA adjustment for input voltage ≈ 1.0°C (Figure 5)
SOA adjustment for output voltage ≈ 0.68°C (Figure 6)
SOA adjustment for switching frequency ≈ 0.75°C (Figure 4)
SOA adjustment for output inductor ≈ 0.02°C (Figure 7)
Final calculated SOA adjustment = 1.0 + 0.68 + 0.75 + 0.02 ≈ 2.45°C
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Calculating Power Loss and Safe Operating Area (SOA) (continued)
In the design example above, the estimated power loss of the CSD86336Q3D would increase to 3.85 W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 2.45°C.
Figure 31 graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 2.45°C. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
Figure 31. Power Block SOA
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7 Layout
7.1 Recommended Schematic Overview
C9
1206
10µF
C 10
1206
10µF
C 11
1206
10µF
C 12
1206
10µF
C 13
1206
10µF
C 14
1206
10µF
GND
GND
GND
GND
GND
GND
GND
GND
Q1
HG
GND
FCCM
VCC
6
7
4
Tgr
Bg
5
Pgnd
6
5
R9
ENABLE
0 0603
+VDD
CSD86336Q3D
GND
C21
10µF
0603
C 19
1210
100µF
Tg
C 17
1210
100µF
3
R 17
0805
PWM PHASE
R16
V_OUT
C 18
1210
100µF
Vsw
L1
9
BOOT
2
LG
7
0
0603
8
9
GND
1
GND
Vsw
C 24
1210
100µF
C20
0.1 µF
U2
4
8
LS
0603
0
3
Vsw
HS
0603
R15
+PWM
GND
Vin
C 16
0603
1
C 15
C8
1206
10µF
GND
C7
1206
10µF
3300pF
C 22
0402
+VIN
470µF
S MT R adial G
There are several critical components that must be used in conjunction with this power block device. Figure 32
shows a portion of a schematic with the critical components needed for proper operation.
• C22: Bypass capacitor for VIN to help with ringing reduction
• C20: Bootstrap capacitor
• C21: Bypass capacitor for VDD
• C7-C14: Bypass capacitors for VIN (minimum of 40 µF)
• C15: Electrolytic capacitor for VIN
• R14, R16: Place holder for gate resistor (optional)
• R15: Place holder for bootstrap resistor (optional)
• R17, C16: Place holder for snubber (optional)
GND
GND
GND
GND
R14
0
0603
Copyright © 2017, Texas Instruments Incorporated
Figure 32. Recommended Schematic
16
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7.2 Recommended PCB Design Overview
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout yields maximum performance in both areas. A brief
description on how to address each parameter follows.
7.2.1 Electrical Performance
The power block has the ability to switch at voltage rates greater than 10 kV/μs. Special care must be taken with
the PCB layout design and placement of the input capacitors, inductor, driver IC and output capacitors.
• The placement of the input capacitors relative to the power block’s VIN and PGND pins should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 33). It
is recommended that one 3.3-nF (or similar), 0402, 50-V ceramic capacitor be placed on the top side of the
board as close as possible to VIN and PGND pins. In addition, a minimum of 40 μF of bulk ceramic
capacitance should be placed as close as possible to the power block in a design. For high-density design,
some of these ceramic capacitors can be placed on the bottom layer of PCB with appropriate number of vias
interconnecting both layers.
• The driver IC should be placed relatively close to the power block gate pins. TG and BG should connect to the
outputs of the driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and should
be connected to the phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap capacitor for
the driver IC will also connect to this pin.
• The switching node of the output inductor should be placed relatively close to the power block VSW pins.
Minimizing the node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level. In the event the switch node waveform exhibits ringing that reaches
undesirable levels, the use of a boost resistor or RC snubber can be an effective way to easily reduce the
peak ring level. The recommended boost resistor value will range between 1.0 Ω to 4.7 Ω depending on the
output characteristics of driver IC used in conjunction with the power block. The RC snubber values can
range from 0.5 Ω to 2.2 Ω for the R and 330 pF to 2200 pF for the C. Please refer to Snubber Circuits:
Theory, Design and Application (SLUP100) for more details on how to properly tune the RC snubber values.
The RC snubber should be placed as close as possible to the VSW node and PGND (see Figure 33 and
Figure 34). (1)
(1)
Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
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Recommended PCB Design Overview (continued)
7.2.2 Thermal Performance
The power block has the ability to utilize the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed in your design. The examples in Figure 33 and Figure 34 use vias with a
10-mil drill hole and a 16-mil capture pad.
• Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
Figure 33. Recommended PCB Layout (Top Down View)
Figure 34. Recommended PCB Layout (Bottom View)
18
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8 Device and Documentation Support
8.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
8.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
8.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
9.1 Q3D Package Dimensions
3.4
3.2
B
A
PIN 1 INDEX AREA
3.4
3.2
C
1.05 MAX
SEATING PLANE
0.05
0.00
0.08 C
1.8 0.1
2X (0.98)
4X (0.2)
(0.2) TYP
EXPOSED
THERMAL PAD
6X 0.65
4
2X
1.95
5
9
SYMM
2.7 0.1
8
1
0.32
0.12
8X
SYMM
8X
0.5
0.4
0.40
0.28
0.1
0.05
C A B
C
4218873/A 10/2016
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical
performance.
9.2 Pin Configuration
20
POSITION
DESIGNATION
Pin 1
VIN
Pin 2
VIN
Pin 3
TG
Pin 4
TGR
Pin 5
BG
Pin 6
VSW
Pin 7
VSW
Pin 8
VSW
Pin 9
PGND
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9.3 Land Pattern Recommendation
(1.8)
2X (0.65)
( 0.2) VIA
TYP
PKG
2X (0.65)
6X (0.65)
(0.22)
1
8
2X (0.34)
6X (0.34)
METAL UNDER
SOLDER MASK
9
PKG
(2.7)
SOLDER MASK
OPENING
3
2X (1.1)
6X (0.65)
5
4
(R0.05) TYP
4X (0.5)
4X (0.2)
2X (1.18)
(3.05)
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
DEFINED
PREFERRED FOR PADS 3-9
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
PADS 1 & 2 (OPTIONAL FOR OTHERS)
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON
PCB Attachment (SLUA271).
3. Vias are optional depending on application, refer to device data sheet. If some or all are implemented,
recommended via locations are shown.
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9.4 Stencil Recommendation
2X (1.63)
PKG
6X (0.65)
2X (0.65)
(0.22)
6X (0.34)
9
1
8
2X (0.34)
2X
(1.19)
METAL UNDER
SOLDER MASK
PKG
3
2X
(0.695)
2X (3.34)
6X (0.65)
5
4
(R0.05) TYP
METAL
TYP
4X (0.22)
4X (0.36)
2X (1.18)
(3.05)
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
22
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PACKAGE OPTION ADDENDUM
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9-Mar-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CSD86336Q3D
PREVIEW
VSON-CLIP
DPB
8
2500
Pb-Free (RoHS
Exempt)
CU SN
Level-1-260C-UNLIM
-55 to 125
86336D
CSD86336Q3DT
PREVIEW
VSON-CLIP
DPB
8
250
Pb-Free (RoHS
Exempt)
CU SN
Level-1-260C-UNLIM
-55 to 125
86336D
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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9-Mar-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Mar-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CSD86336Q3DT
Package Package Pins
Type Drawing
VSONCLIP
DPB
8
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
12.4
Pack Materials-Page 1
3.6
B0
(mm)
K0
(mm)
P1
(mm)
3.6
1.2
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Mar-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD86336Q3DT
VSON-CLIP
DPB
8
250
336.6
336.6
41.3
Pack Materials-Page 2
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