DM74ALS165 8-Bit Parallel In/Serial Out Shift Register January 1986 Revised February 2000 DM74ALS165 8-Bit Parallel In/Serial Out Shift Register General Description Features The DM74ALS165 is an 8-bit serial register that, when clocked, shifts the data toward serial output, QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the SH/LD input. The DM74ALS165 also features a clock inhibit function and a complemented serial output, QH. ■ Complementary outputs ■ Direct overriding load (data) inputs ■ Gated clock inputs ■ Parallel-to-serial data conversion Clocking is accomplished by a LOW-to-HIGH transition of the CLK input while SH/LD is held HIGH and CLK INH is held LOW. The functions of the CLK and CLK INH (clock inhibit) inputs are interchangeable. Since a LOW CLK input and a LOW-to-HIGH transition of CLK INH will also accomplish clocking, CLK INH should be changed to the high level only while the CLK input is HIGH. Parallel loading is inhibited when SH/LD is held HIGH. The parallel inputs to the register are enabled while SH/LD is LOW independently of the levels of CLK, CLK INH, or SER inputs. Ordering Code: Order Number Package Number Package Description DM74ALS165M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS165N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Internal Shift/ Clock Clock Serial Parallel Outputs Load Inhibit A...H QA QB Output QH L X X X a...h a b h H L L X X QA0 QB0 QH0 H L ↑ H X H QAn QGn H L ↑ L X L QAn QGn H ↑ L H X H QAn QGn H ↑ L L X L QAn QGn H H X X X QA0 QB0 QH0 H = HIGH Level (steady-state), L = LOW Level (steady-state) X = Don't Care (any input, including transitions) ↑ = Transition from LOW-to-HIGH level a...h = The level of steady-state input at inputs A through H, respectively QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established QAn, QGn = The level of QA or QG, respectively, before the most recent ↑ transition of the clock © 2000 Fairchild Semiconductor Corporation DS006712 www.fairchildsemi.com DM74ALS165 Logic Diagram Timing Diagram Typical Shift, Load, and Inhibit Sequences www.fairchildsemi.com 2 Supply Voltage 7V Input Voltage 7V 0°C to +70°C Operating Free Air Temperature Range Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. −65°C to +150°C Storage Temperature Range Typical θJA N Package 74.0°C/W M Package 104.0°C/W Recommended Operating Conditions Symbol Parameter Min Typ Max Units 4.5 5 5.5 V LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current 8 mA fCLOCK Clock Frequency tW Pulse Duration VCC Supply Voltage VIH HIGH Level Input Voltage VIL tSU tSU Setup Time Setup Time 2 V 45 CLK HIGH MHz 11 CLK LOW 11 Load 12 SH/LD 10 Data 10 CLK INH ↓ before CLK 11 Serial before CLK 10 tH Hold Time 4 TA Operating Free Air Temperature 0 ns ns ns ns °C 70 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VIK Input Clamp Voltage VCC = 4.5V, II = −18 mA VOH HIGH Level IOH = −0.4 mA Output Voltage VCC = 4.5V to 5.5V LOW Level VCC = 4.5V VOL Min Typ (Note 2) Max Units −1.5 V VCC − 2 Output Voltage V IOL = 4 mA 0.25 0.4 IOL = 8 mA 0.35 0.5 V II Input Current at Max Input Voltage VCC = 5.5V, VI = 7V IIH HIGH Level Input Current VCC = 5.5V, VI = 2.7V 20 µA IIL LOW Level Input Current VCC = 5.5V, VI = 0.4V −0.1 mA IO (Note 3) Output Drive Current VCC = 5.5V, VO = 2.25V ICC Supply Current VCC = 5.5V (Note 4) 0.1 −30 16 mA −112 mA 24 mA Note 2: All typical values are at VCC = 5V, TA = 25°C. Note 3: The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. Note 4: With the outputs open, CLK INH and CLK at 4.5V, and a clock pulse applied to the SH/LD input, ICC is measured first with the parallel inputs at 4.5V, then with the parallel inputs grounded. 3 www.fairchildsemi.com DM74ALS165 Absolute Maximum Ratings(Note 1) DM74ALS165 Switching Characteristics over recommended free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C. Symbol Parameter Input Output Conditions fMAX Maximum Frequency VCC = 4.5V to 5.5V, tPLH Propagation Delay Time CL = 50 pF, LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output www.fairchildsemi.com Min Typ 45 60 Max 4 13 20 4 14 22 MHz Load QH or QH Load QH or QH CLK QH or QH 3 7 13 CLK QH or QH 3 9 14 H QH 3 7 13 H QH 3 9 16 H QH 2 8 15 H QH 3 9 16 RL = 500Ω TA = Min to Max Units ns ns ns ns 4 DM74ALS165 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 5 www.fairchildsemi.com DM74ALS165 8-Bit Parallel In/Serial Out Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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