LVDS Interface ICs 70bit LVDS Distributor BU90RT102 No.10057EAT08 ●Description LVDS Interface IC of ROHM "Serializer" "Deserializer" operates from 8MHz to 150MHz wide clock range, and number of bits range is from 35 to 70. Data is transmitted seven times (7X) stream and reduce cable number by 3(1/3) or less. The ROHM's LVDS has low swing mode to be able to expect further low EMI. Driver and Receiver of 4 bits operate to 250MHz. It can be used for a variety of purposes, home appliances such as LCD-TV, business machines such as decoders, instruments, and medical equipment. ●Features 1) RGB10bits dual channel LVDS Receiver and Transmitter 2) Operating frequency range : 20～135MHz 3) Power down mode supported. 4) Support spread spectrum clock generator. 5) Support reduced swing LVDS for low EMI. 6) Package HTSSOP-C64 ●Applications Digital TV (Signal System) Car Navigation System Copier FA equipment Medical equipment Vending machine, Ticket vending machine www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 1/18 2010.10 - Rev.A Technical Note BU90RT102 ●Absolute Maximum Ratings Parameter Symbol Ratings Unit Supply Voltage VDD -0.3 ~ 4.0 V Input Voltage VIN -0.3 ~ VDD+0.3 V Output Voltage VOUT -0.3 ~ VDD+0.3 V Storage Temperature Range Tstg -55 ~ 125 ℃ ●Recommended Operating Conditions Parameter Symbol Ratings Min Typ Max Unit Supply Voltage VDD 3.0 3.3 3.6 V Operating Temperature Range Topr -20 - 85 ℃ Fin 20 - 135 MHz Fout 20 - 135 MHz Fin 20 - 135 MHz Fout 20 - 135 MHz Fin 40 - 135 MHz Fout 20 - 62.5 MHz Fin 20 - 62.5 MHz Fout 40 - 135 MHz Dual-in/Dual-out Distribution Single-in / Dual-out Dual-in / Single-out www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 2/18 2010.10 - Rev.A Technical Note BU90RT102 ●Block Diagram 1st Link (135MHz Max.) 1st Link (135MHz Max.) LVDS-Rx De-Serialize LVDS-Tx Serialize TA1+/- ~ TE1+/RA1+/- ~ RE1+/- RCLK1 +/- Inter-Link Multiplex & De-Multiplex PLL TCLK1 +/- PLL TCLK2 +/RCLK2 +/PLL LVDS-Rx De-Serialize RA2+/- ~ RE2+/- XRST MODE[1:0] TA2+/- ~ TE2+/- LVDS-Tx Serialize LDO Regulator 2nd Link (135MHz Max.) 2nd Link (135MHz Max.) RS CAP Distribution mode Dual in / Dual out mode 135 MHz 135 MHz Rx Tx Rx Tx 135 MHz 135 MHz 135 MHz Dual in / Single out mode 62 .5 MHz 62 .5 MHz Rx Rx + Tx Rx Tx Rx Tx 135 MHz 135 MHz Single in / Dual out mode 135 MHz 135 MHz Tx Rx Rx - Tx Tx 62. 5MHz 62 .5MHz Fig.1 Block Diagram www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 3/18 2010.10 - Rev.A Technical Note BU90RT102 ●Pin Configuration RS CAP GND VDD RA1RA1+ RB1RB1+ RC1RC1+ RCLK1RCLK1+ RD1RD1+ RE1RE1+ RA2RA2+ RB2RB2+ RC2RC2+ RCLK2RCLK2+ RD2RD2+ RE2RE2+ VDD GND RESERVE1 XRST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Top View 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GND RESERVE2 GND VDD TA1TA1+ TB1TB1+ TC1TC1+ TCLK1TCLK1+ TD1TD1+ TE1TE1+ TA2TA2+ TB2TB2+ TC2TC2+ TCLK2TCLK2+ TD2TD2+ TE2TE2+ VDD GND MODE1 MODE0 Fig.2 Pin Configuration (Top View) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 4/18 2010.10 - Rev.A Technical Note BU90RT102 ●Pin Description Pin Name RA1+/RB1+/RC1+/RD1+/RE1+/RCLK1+/RA2+/RB2+/RC2+/RD2+/RE2+/RCLK2+/TA1+/TB1+/TC1+/TD1+/TE1+/TCLK1+/TA2+/TB2+/TC2+/TD2+/TE2+/TCLK2+/- Pin No. 5,6 7,8 9,10 13,14 15,16 11,12 17,18 19,20 21,22 25,26 27,28 23,24 59,60 57,58 55,56 51,52 49,50 53,54 47,48 45,46 43,44 39,40 37,38 41,42 Type Input LVDS Output XRST 32 Input RS 1 Input MODE1 MODE0 33,34 Input VDD GND 4,29,36,61 3,30,35,62,64 - CAP 2 - 31,63 Input RESERVE1/2 Descriptions Link1 chA LVDS data input Link1 chB LVDS data input Link1 chC LVDS data input Link1 chD LVDS data input Link1 chE LVDS data input Link1 LVDS clock input Link2 chA LVDS data input Link2 chB LVDS data input Link2 chC LVDS data input Link2 chD LVDS data input Link2 chE LVDS data input Link2 LVDS clock input Link1 chA LVDS data output Link1 chB LVDS data output Link1 chC LVDS data output Link1 chD LVDS data output Link1 chE LVDS data output Link1 LVDS clock output Link2 chA LVDS data output Link2 chB LVDS data output Link2 chC LVDS data output Link2 chD LVDS data output Link2 chE LVDS data output Link2 LVDS clock output Power Down H : Normal operation L : Power down (all outputs are Hi-Z) LVDS swing level select H : TYP=350mV L : TYP=200mV CMOS Pixel data mdoe MODE1 MODE0 L L L L H L L H H H - - RCLK2/clkin Hi-z Hi-z clkin - Description Dual-in/Dual-out mode Distribution mode Single-in/Dual-out mode Dual-in/Single-out mode Reserved Power supply pins. Ground pins Decoupling capacitor pin This pin should be connected to external decoupling capacitor. Recommended capacitor is 2.2µF.*1 Reserve pins Must be open *1. Parts list of recommended external decoupling capacitor Size Maker Parts Number [mm] Reference Capacity Capacitance Temperature Tolerance Characteristics Temperature [μF] [%] [℃] [%] Operating Temperature Range [℃] Capacitance Change Voltage [V] Murata GRM155B30G225ME15D 1.0x0.5x0.5 2.2 ±20 B 20 ±10% -25～85 4.0 Murata GRM155R60J225ME15D 1.0x0.5x0.5 2.2 ±20 X5R 25 ±15% -55～85 6.3 TDK C1005X7R1H222KT 1.0x0.5x0.5 2.2 ±20 X7R 25 ±15% -55～125 5.0 Kyocera CM05X5R225K04AH 1.0x0.5x0.5 2.2 ±20 X5R 25 ±15% -55～85 4.0 Kyocera CM05X5R225M04AH 1.0x0.5x0.5 2.2 ±20 X5R 25 ±15% -55～85 4.0 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 5/18 2010.10 - Rev.A Technical Note BU90RT102 ●DC Characteristics Table 1 : LVCMOS DC Characteristics(VDD=3.0V～3.6V, Ta=-20℃～+85℃） Limits Parameter Symbol Unit Min Typ Max Conditions High Level Input Voltage VIH VDD×0.8 - VDD V - Low Level Input Voltage VIL GND - VDD×0.2 V - Input Leak Current IINC -10 - +10 μA Pull-down resistor PDR 20 46 100 KΩ Table 2 : LVDS Receiver DC Characteristics(VDD=3.0V～3.6V, Ta=-20℃～+85℃） Limits Parameter Symbol Unit Min Typ Max 0V VIN VDD - Conditions LVDS-Rx Input Voltage VIN_RX 0.4 - 2.1 V - LVDS-Rx Common Voltage VIC_RX 0.7 1.2 1.8 V - Differential Input High Threshold VTH_RX - - +100 mV VIC_RX=1.2V Differential Input Low Threshold VTL_RX -100 - - mV VIC_RX=1.2V LVDS-Rx Differential Voltage |VID_RX| 100 - 600 mV - LVDS-Rx Input Current VIN_RX -20 - 20 µA - V TH_RX V IC_RX V TL_RX VIN_RX 0V (GND) Fig.3 LVDS Receiver DC Characteristics www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 6/18 2010.10 - Rev.A Technical Note BU90RT102 Table 3 : LVDS Transmitter DC Characteristics(VDD=3.0V～3.6V, Ta=-20℃～+85℃） Limits Parameter Symbol Unit Min Typ Max Conditions 250 350 450 mV 100 200 300 mV ΔVOD - - 35 mV VOC 1.125 1.25 1.375 V Change in VOC between complementary output states ΔVOC - - 35 mV Output Short Circuit Current IOS -60 - - mA VOUT=0V Output Tri-state Current IOZ -10 - +10 μA XRST=0V, VOUT=0V to VDD Differential Output Voltage Change in VOD between complementary output states Common Voltage VOD RL=100Ω Normal swing RS=VDD Reduced swing RS=GND RL=100Ω Diff_N VOD= | V (Diff_P) -V (Diff_N) | VOC= (V (Diff_P) +V (Diff_N)) / 2 0V (GND) Note: Diff_P=TA1+ ~ TA2+ , TCLK1+ ,TCLK2+ Diff_N=TA1- ~ TA2- , TCLK1- ,TCLK2- Fig.4 LVDS Transmitter DC Characteristics www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 7/18 2010.10 - Rev.A Technical Note BU90RT102 ●AC Characteristics Table 4 : Switching Characteristics(VDD=3.3V, Ta=25℃） Parameter Limits Symbol Unit Min Typ Max tCK12 -0.3 tRCP - 0.3 tRCP ns tLT - - 10 ms - 4tRCP+5 - ns - 4tRCP+5 - ns single-in/dual-out - 6tRCP+5 - ns dual-in/single-out - 2.5tRCP+5 - ns Skew Time between RCLK1 and RCLK2 Phase Lock Loop Set Time dual-in/dual-out distribution Data Latency tRIP6 DE Input High Time tDEH 2 tRCP - - ns DE Input Low Time tDEL 2 tRCP - - ns DE Input Period tDEL 4 tRCP Must be 2ntRCP (n=integer) - ns Note: 1) Vdiffrc = (RCLK+)-(RCLK-) (RCLK1+)-(RCLK1-) Vdiffrc=0V tck12 (RCLK2+)-(RCLK2-) Vdiffrc=0V Fig.5 Skew Time between RCLK1 and RCLK2 3.0V VDD RCLK1 +/- VDD×0.8 PD tLT Note: 1) Vdiffrc = (RCLK+)-(RCLK-) TCLKx +/x=1,2 Vdiffrc = 0V Fig.6 Phase Lock Loop Set Time www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 8/18 2010.10 - Rev.A Technical Note BU90RT102 ●LVDS Receiver AC Characteristics Table 5 : Switching Characteristics(VDD=3.3V, Ta=25℃） Parameter Limits Symbol Typ Max 7.4 - 50 ns 7.4 - 50 ns single/dual 7.4 - 25 ns dual/single 16 - 50 ns CLKIN= 75MHz 480 - - ps 250 - - ps CLKIN= 135MHz 220 - - ps CLKIN= 75MHz 480 - - ps 250 - - ps 220 - - ps dual /dual distribution Input Clock Period Differential Input Data Setup Margin Differential Input Data Hold Margin Unit Min tRCP CLKIN= 112MHz CLKIN= 112MHz tRSUP tRHLD CLKIN= 135MHz Differential Input Data Position 6 tRIP6 2 Differential Input Data Position 5 tRIP5 3 Differential Input Data Position 4 tRIP4 4 Differential Input Data Position 3 tTOP3 5 Differential Input Data Position 2 tRIP2 6 Differential Input Data Position 1 tRIP1 7 Differential Input Data Position 0 tRIP0 8 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 9/18 tRCP 7 tRCP 7 tRCP 7 tRCP 7 tRCP 7 tRCP 7 tRCP 7 -tRHLD 2 -tRHLD 3 -tRHLD 4 -tRHLD 5 -tRHLD 6 -tRHLD 7 -tRHLD 8 tRCP 7 tRCP 7 tRCP 7 tRCP 7 tRCP 7 tRCP 7 tRCP 7 2 3 4 5 6 7 8 tRCP 7 tRCP 7 tRCP 7 tRCP 7 tRCP 7 tRCP 7 tRCP 7 +tRSUP ns +tRSUP ns +tRSUP ns +tRSUP ns +tRSUP ns +tRSUP ns +tRSUP ns 2010.10 - Rev.A Technical Note BU90RT102 ●AC Timing Diagram tRIP0 tRIP1 tRIP2 tRIP3 tRIP4 tRIP5 tRIP6 Ryx +/- D<6> D<5> D<4> D<3> D<2> D<1> D<0> tRCP tRCH tRCL RCLKx + RCLKx x=1,2 y=A,B,C,D,E Ry1 +/- skew margin is the one between RCLK1 +/- and Ry1 +/Ry2 +/- skew margin is the one between RCLK2 +/- and Ry2 +/- Fig.7 AC Timing Diagram (1) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 10/18 2010.10 - Rev.A Technical Note BU90RT102 ●LVDS Transmitter AC Characteristics Table 6 : Switching Characteristics(VDD=3.3V, Ta=25℃） Parameter Limits Symbol Typ Max 7.4 - 50 ns 7.4 - 50 ns 16 - 50 ns 7.4 - 25 ns - 0.6 1.5 ns - - 250 ps - - 200 ps CLKOUT=135MHz - - 170 ps CLKOUT=75MHz - - 250 ps - - 200 ps - - 170 ps dual /dual Output Clock Period distribution single/dual tTCP dual/single Differential Output Transition Time tLVT CLKOUT=75MHz Differential Output Setup Time Differential Output Hold Time Unit Min CLKOUT=112MHz CLKOUT=112MHz TTSUP TTHLD CLKOUT=135MHz Differential Output Position 6 tTOP6 2 Differential Output Position 5 tTOP5 3 Differential Output Position 4 tTOP4 4 Differential Output Position 3 tTOP3 5 Differential Output Position 2 tTOP2 6 Differential Output Position 1 tTOP1 7 Differential Output Position 0 tTOP0 8 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 11/18 tTCP 7 tTCP 7 tTCP 7 tTCP 7 tTCP 7 tTCP 7 tTCP 7 - TTHLD 2 - TTHLD 3 - TTHLD 4 - TTHLD 5 - TTHLD 6 - TTHLD 7 - TTHLD 8 tTCP 7 tTCP 7 tTCP 7 tTCP 7 tTCP 7 tTCP 7 tTCP 7 2 3 4 5 6 7 8 tTCP 7 tTCP 7 tTCP 7 tTCP 7 tTCP 7 tTCP 7 tTCP 7 + TTSUP ns + TTSUP ns + TTSUP ns + TTSUP ns + TTSUP ns + TTSUP ns + TTSUP ns 2010.10 - Rev.A Technical Note BU90RT102 ●AC Timing Diagram tTOP0 tTOP1 tTOP2 tTOP 3 tTOP4 tTOP 5 tTOP 6 Tyx +/- D<6> D<5> D<3> D<4> D<2> D<1> D<0> tTCP tTCH tTCL TCLKx + TCLKx x=1,2 y= A,B,C,D,E Ty1 +/- output timing is the one between TCLK 1 +/- and Ty1 +/- . Ty2 +/- output timing is the one between TCLK 2 +/- and Ty2 +/- . Note 80 ％ 80 ％ 1) Vdifft =(Ty+)-(Ty-) =A,B,C,CLK,D,E Vdifft 20 ％ 20 ％ t LVT y=1,2 t LVT Fig.8 AC Timing Diagram (2) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 12/18 2010.10 - Rev.A Technical Note BU90RT102 ●LVDS Data Mapping(1) Dual-in / Dual-out mode LVDS- Rx Input Mapping RCLK1+/ RA1+/ - G1[4] R1[9] R1[8] R1[7] R1[6] R1[5] R1[4] G3[4] R3[9] R3[8] R3[7] R3[6] R3[5] R3[4] RB1+/ - B1[5] B1[4] G1[9] G1[8] G1[7] G1[6] G1[5] B3[5] B3[4] G3[9] G3[8] G3[7] G3[6] G3[5] RC1+/ - DE B1[9] B1[8] B1[7] B1[6] DE B3[9] B3[8] B3[7] B3[6] VSYNC HSYNC VSYNC HSYNC RD1+/ - data11 B1[3] B1[2] G1[3] G1[2] R1[3] R1[2] data11 B3[3] B3[2] G3[3] G3[2] R3[3] R3[2] RE1+/ - data12 B1[1] B1[0] G1[1] G1[0] R1[1] R1[0] data12 B3[1] B3[0] G3[1] G3[0] R3[1] R3[0] RA2+/ - G2[4] R2[9] R2[8] R2[7] R2[6] R2[5] R2[4] G4[4] R4[9] R4[8] R4[7] R4[6] R4[5] R4[4] RB2+/ - B2[5] B2[4] G2[9] G2[8] G2[7] G2[6] G2[5] B4[5] B4[4] G4[9] G4[8] G4[7] G4[6] G4[5] RC2+/ - DE B2[9] B2[8] B2[7] B2[6] DE B4[9] B4[8] B4[7] B4[6] RCLK2+/ - VSYNC HSYNC VSYNC HSYNC RD2+/ - data21 B2[3] B2[2] G2[3] G2[2] R2[3] R2[2] data21 B4[4] B4[2] G4[3] G4[2] R4[3] R4[2] RE2+/ - data22 B2[1] B2[0] G2[1] G2[0] R2[1] R2[0] data22 B4[1] B4[0] G4[1] G4[0] R4[1] R4[0] TA1+/ - G1[4] R1[9] R1[8] R1[7] R1[6] R1[5] R1[4] G3[4] R3[9] R3[8] R3[7] R3[6] R3[5] R3[4] TB1+/ - B1[5] B1[4] G1[9] G1[8] G1[7] G1[6] G1[5] B3[5] B3[4] G3[9] G3[8] G3[7] G3[6] G3[5] TC1+/ - DE B1[9] B1[8] B1[7] B1[6] DE B3[9] B3[8] B3[7] B3[6] LVDS- Tx Output Mapping TCLK1+/ - VSYNC HSYNC VSYNC HSYNC TD1+/ - data11 B1[3] B1[2] G1[3] G1[2] R1[3] R1[2] data11 B3[3] B3[2] G3[3] G3[2] R3[3] R3[2] TE1+/ - data12 B1[1] B1[0] G1[1] G1[0] R1[1] R1[0] data12 B3[1] B3[0] G3[1] G3[0] R3[1] R3[0] TA2+/ - G2[4] R2[9] R2[8] R2[7] R2[6] R2[5] R2[4] G4[4] R4[9] R4[8] R4[7] R4[6] R4[5] R4[4] TB2+/ - B2[5] B2[4] G2[9] G2[8] G2[7] G2[6] G2[5] B4[5] B4[4] G4[9] G4[8] G4[7] G4[6] G4[5] TC2+/ - DE B2[9] B2[8] B2[7] B2[6] DE B4[9] B4[8] B4[7] B4[6] TCLK2+/ - VSYNC HSYNC VSYNC HSYNC TD2+/ - data21 B2[3] B2[2] G2[3] G2[2] R2[3] R2[2] data21 B4[4] B4[2] G4[3] G4[2] R4[3] R4[2] TE2+/ - data22 B2[1] B2[0] G2[1] G2[0] R2[1] R2[0] data22 B4[1] B4[0] G4[1] G4[0] R4[1] R4[0] Fig.9 LVDS Data Mapping(1) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 13/18 2010.10 - Rev.A Technical Note BU90RT102 ●LVDS Data Mapping(2) Distribution Mode Distribution mode,RCLK2+/- must be High-z. LVDS-Rx Input Mapping RCLK1+/ RA 1+/ - G1[4] R1[9] R1[8] R1[7] R1[6] R1[5] R1[4] G2[4] R2[9] R2[8] R2[7] R2[6] R2[5] R2[4] RB 1+/ - B1[5] B1[4] G1[9] G1[8] G1[7] G1[6] G1[5] B2[5] B2[4] G2[9] G2[8] G2[7] G2[6] G2[5] RC 1+/ - DE B1[9] B1[8] B1[7] B1[6] DE B2[9] B2[8] B2[7] B2[6] VSYNC HSYNC VSYNC HSYNC RD 1+/ - data11 B1[3] B1[2] G1[3] G1[2] R1[3] R1[2] data11 B2[3] B2[2] G2[3] G2[2] R2[3] R2[2] RE1+/ - data12 B1[1] B1[0] G1[1] G1[0] R1[1] R1[0] data12 B2[1] B2[0] G2[1] G2[0] R2[1] R2[0] RCLK 2+/ - Hi- z RA 2+/ - no care RB 2+/ - no care RC 2+/ - no care RD 2+/ - no care no care RE 2+/ LVDS -Tx Output Mapping TCLK 1+/ TA 1+/ - G1[4] R1[9] R1[8] R1[7] R1[6] R1[5] R1[4] G2[4] R2[9] R2[8] R2[7] R2[6] R2[5] R2[4] TB 1+/ - B1[5] B1[4] G1[9] G1[8] G1[7] G1[6] G1[5] B2[5] B2[4] G2[9] G2[8] G2[7] G2[6] G2[5] TC 1+/ - DE B1[9] B1[8] B1[7] B1[6] DE B2[9] B2[8] B2[7] B2[6] VSYNC HSYNC VSYNC HSYNC TD 1+/ - data11 B1[3] B1[2] G1[3] G1[2] R1[3] R1[2] data11 B2[3] B2[2] G2[3] G2[2] R2[3] R2[2] TE 1+/ - data12 B1[1] B1[0] G1[1] G1[0] R1[1] R1[0] data12 B2[1] B2[0] G2[1] G2[0] R2[1] R2[0] TA 2+/ - G1[4] R1[9] R1[8] R1[7] R1[6] R1[5] R1[4] G2[4] R2[9] R2[8] R2[7] R2[6] R2[5] R2[4] TB 2+/ - B1[5] B1[4] G1[9] G1[8] G1[7] G1[6] G1[5] B2[5] B2[4] G2[9] G2[8] G2[7] G2[6] G2[5] TC 2+/ - DE B1[9] B1[8] B1[7] B1[6] DE B2[9] B2[8] B2[7] B2[6] TCLK2+/ - VSYNC HSYNC VSYNC HSYNC TD 2+/ - data11 B1[3] B1[2] G1[3] G1[2] R1[3] R1[2] data11 B2[3] B2[2] G2[3] G2[2] R2[3] R2[2] TE 2+/ - data12 B1[1] B1[0] G1[1] G1[0] R1[1] R1[0] data12 B2[1] B2[0] G2[1] G2[0] R2[1] R2[0] (Regardless of the Data Latency ) Fig.10 LVDS Data Mapping(2) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 14/18 2010.10 - Rev.A Technical Note BU90RT102 ●LVDS Data Mapping(3) Single-in / Dual-out mode Single-in / Dual-out mode, RCLK2+/- must be High-z. LVDS-Rx Input Mapping RCLK1+/ RA1+/ - G1[4] R1[9] R1[8] R1[7] R1[6] R1[5] R1[4] G2[4] R2[9] R2[8] R2[7] R2[6] R2[5] R2[4] RB1+/ - B1[5] B1[4] G1[9] G1[8] G1[7] G1[6] G1[5] B2[5] B2[4] G2[9] G2[8] G2[7] G2[6] G2[5] RC1+/ - DE B1[9] B1[8] B1[7] B1[6] DE B2[9] B2[8] B2[7] B2[6] VSYNC HSYNC VSYNC HSYNC RD1+/ - data11 B1[3] B1[2] G1[3] G1[2] R1[3] R1[2] data11 B2[3] B2[2] G2[3] G2[2] R2[3] R2[2] RE1+/ - data12 B1[1] B1[0] G1[1] G1[0] R1[1] R1[0] data12 B2[1] B2[0] G2[1] G2[0] R2[1] R2[0] RCLK 2+/ - Hi- z RA2+/ - no care RB2+/ - no care RC2+/ - no care RD2+/ - no care no care RE2+/ LVDS -Tx Output Mapping TCLK1+/ TA 1+/ - G1[4] R1[9] R1[8] R1[7] R1[6] R1[5] R1[4] TB 1+/ - B1[5] B1[4] G1[9] G1[8] G1[7] G1[6] G1[5] TC 1+/ - DE VSYNC HSYNC B1[9] B1[8] B1[7] B1[6] TD1+/ - data11 B1[3] B1[2] G1[3] G1[2] R1[3] R1[2] TE1+/ - data12 B1[1] B1[0] G1[1] G1[0] R1[1] R1[0] TA 2+/ - G2[4] R2[9] R2[8] R2[7] R2[6] R2[5] R2[4] TB 2+/ - B2[5] B2[4] G2[9] G2[8] G2[7] G2[6] G2[ 5] TC2+/ - DE VSYNC HSYNC B2[9] B2[8] B2[7] B2[6] TD2+/ - data11 B2[3] B2[2] G2[3] G2[2] R2[3] R2[2] TE2+/ - data12 B2[1] B2[0] G2[1] G2[0] R2[1] R2[0] TCLK2+/ - (Regardless of the Data Latency ) Fig.11 LVDS Data Mapping (3) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 15/18 2010.10 - Rev.A Technical Note BU90RT102 ●LVDS Data Mapping(4) Dual-in / Single-out mode LVDS-Rx Input Mapping RCLK1+/ RA1+/ - G1[4] R1[9] R1[8] R1[7] R1[6] R1[5] R1[4] RB1+/ - B1[5] B1[4] G1[9] G1[8] G1[7] G1[6] G1[5] RC1+/ - DE VSYNC HSYNC B1[9] B1[8] B1[7] B1[6] RD1+/ - data11 B1[3] B1[2] G1[3] G1[2] R1[3] R1[2] RE1+/ - data12 B1[1] B1[0] G1[1] G1[0] R1[1] R1[0] RA 2+/ - G2[4] R2[9] R2[8] R2[7] R2[6] R2[5] R2[4] RB 2+/ - B2[5] B2[4] G2[9] G2[8] G2[7] G2[6] G2[5] RC 2+/ - DE VSYNC HSYNC B2[9] B2[8] B2[7] B2[6] RD 2+/ - data11 B2[3] B2[2] G2[3] G2[2] R2[3] R2[2] RE 2+/ - data12 B2[1] B2[0] G2[1] G2[0] R2[1] R2[0] RCLK2+/ - LVDS-Tx Output Mapping TCLK1+/ TA1+/ - G1[4] R1[9] R1[8] R1[7] R1[6] R1[5] R1[4] G2[4] R2[9] R2[8] R2[7] R2[6] R2[5] R2[4] TB1+/ - B1[5] B1[4] G1[9] G1[8] G1[7] G1[6] G1[5] B2[5] B2[4] G2[9] G2[8] G2[7] G2[6] G2[5] TC1+/ - DE B1[9] B1[8] B1[7] B1[6] DE B2[9] B2[8] B2[7] B2[6] VSYNC HSYNC VSYNC HSYNC TD1+/ - data11 B1[3] B1[2] G1[3] G1[2] R1[3] R1[2] data11 R2[3] R2[2] R2[3] R2[2] R2[3] R2[2] TE1+/ - data12 B1[1] B1[0] G1[1] G1[0] R1[1] R1[0] data12 R2[1] R2[0] R2[1] R2[0] R2[1] R2[0] TCLK 2+/ - Hi- z TA 2+/ - no care TB 2+/ - no care TC 2+/ - no care TD 2+/ - no care no care TE 2+/ - ( Regardless of the Data Latency ) Fig.12 LVDS Data Mapping(4) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 16/18 2010.10 - Rev.A Technical Note BU90RT102 ●Application Circuit BU90RT102 2.2µF CAP LDO 100Ω 100Ω LVDS Tx LVDS Rx LVDS Tx LVDS Rx LVDS Tx LVDS Rx LOGIC LVDS Tx LVDS Rx OPEN RESERVE 2 RESERVE１ Fig.13 Application circuit example V DD ● 10[µF] ● 0.1[µF] To VDD 0.01[µF] Fig.14 Filtering capacitor of power line www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 17/18 2010.10 - Rev.A Technical Note BU90RT102 ●Ordering part number B U 9 Part No. 0 R T 1 0 2 - Part No. 90RT102 E 2 Packaging and forming specification E2: Embossed tape and reel Package HTSSOP-C64 HTSSOP-C64 <Tape and Reel information> 17.2±0.1 (MAX 17.94 include BURR) 4.45 REF Embossed carrier tape (with dry pack) Quantity 2000pcs 1.0±0.2 0.45±0.15 3.05 REF 1 Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 32 1PIN MARK +0.05 0.145 -0.03 0.1±0.05 S 0.9±0.05 1.1MAX 0.85 Tape 33 6.1± 0.1 8.1± 0.2 64 +6 4 -4 0.5 +0.05 0.22 -0.04 0.08 S 0.08 M 1pin (Unit : mm) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. Reel 18/18 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2010.10 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. 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