Cirrus CS5461A Single phase, bi-directional power/energy ic Datasheet

CS5461A
Single Phase, Bi-directional Power/Energy IC
Features
Description
The CS5461A is an integrated power measurement device which combines two ∆Σ
analog-to-digital converters, power calculation
• On-chip Functions:
engine, energy-to-frequency converter, and a
- Instantaneous Voltage, Current, and Power
serial interface on a single chip. It is designed to
- IRMS and VRMS, Apparent and Active (Real) Power
accurately measure instantaneous current and
- Energy-to-pulse Conversion for Mechanical
voltage, and calculate VRMS, IRMS, instantaCounter/Stepper Motor Drive
neous power, apparent power, and active power
- System Calibrations and Phase Compensation
for single-phase, 2- or 3-wire power metering
- Temperature Sensor
applications.
• Energy Data Linearity: ±0.1% of Reading over
1000:1 Dynamic Range
- Voltage Sag Detect
The CS5461A is optimized to interface to shunt
resistors or current transformers for current measurement, and to resistive dividers or potential
transformers for voltage measurement.
• Meets Accuracy Spec for IEC, ANSI, & JIS.
• Low Power Consumption
• Current Input Optimized for Sense Resistor.
The CS5461A features a bi-directional serial interface for communication with a processor, and
a programmable energy-to-pulse output function. Additional features include on-chip
functionality to facilitate system-level calibration,
temperature sensor, voltage sag detection, and
phase compensation.
• GND-referenced Signals with Single Supply
• On-chip 2.5 V Reference (25 ppm/°C typ)
• Power Supply Monitor
• Simple Three-wire Digital Serial Interface
• “Auto-boot” Mode from Serial E2PROM.
• Power Supply Configurations:
ORDERING INFORMATION:
VA+ = +5 V; AGND = 0 V; VD+ = +3.3 V to +5 V
RESET
VA+
IIN+
IIN-
PGA
See Page 41.
4th Order ∆Σ
Modulator
VD+
Digital
Filter
HPF
Option
MODE
CS
VREFIN
Power
Calculation
Engine
Temperature
Sensor
x1
SDI
Serial
Interface
SDO
SCLK
INT
VIN+
VIN-
VREFOUT
x10
Voltage
Reference
AGND
http://www.cirrus.com
2nd Order ∆Σ
Modulator
Power
Monitor
PFMON
Digital
Filter
System
Clock
HPF
Option
Clock
Generator
/K
XIN
XOUT CPUCLK
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
E-to-F
E1
E2
E3
Calibration
DGND
AUG ‘05
DS661F1
CS5461A
TABLE OF CONTENTS
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3. Characteristics & Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Voltage and Current Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Power Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Linearity Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.1 Voltage Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.2 Current Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 High-pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Performing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4 Energy Pulse Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4.1 Normal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4.2 Alternate Pulse Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4.3 Mechanical Counter Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4.4 Stepper Motor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4.5 Pulse Output E3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4.6 Anti-creep for the Pulse Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4.7 Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5 Voltage Sag-detect Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.6 On-chip Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.7 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.8 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.9 Power-down States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.10 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.11 Event Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.11.1 Typical Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.12 Serial Port Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.12.1 Serial Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.13 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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CS5461A
6. Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Current and Voltage DC Offset Register ( IDCoff ,VDCoff ) . . . . . . . . . . . . . .
6.3 Current and Voltage Gain Register ( Ign ,Vgn ) . . . . . . . . . . . . . . . . . . . . . .
6.4 Cycle Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5 PulseRateE1,2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 Instantaneous Current, Voltage and Power Registers ( I , V , P ) . . . . . . . .
6.7 Active (Real) Power Registers ( PActive ) . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8 IRMS and VRMS Registers ( IRMS , VRMS ) . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9 Power Offset Register ( Poff ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10 Status Register and Mask Register ( Status , Mask ) . . . . . . . . . . . . . . . .
6.11 Current and Voltage AC Offset Register ( VACoff , IACoff ) . . . . . . . . . . . . .
6.12 PulseRateE3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13 Temperature Register ( T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14 System Gain Register ( SYSGain ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.15 Pulsewidth Register ( PW ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16 Voltage Sag Duration Register ( VSAGDuration ) . . . . . . . . . . . . . . . . . . . .
6.17 Voltage Sag Level Register ( VSAGLevel ) . . . . . . . . . . . . . . . . . . . . . . . .
6.18 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.19 Temperature Gain Register ( TGain ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.20 Temperature Offset Register ( Toff ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.21 Apparent Power Register ( S ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7. System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Channel Offset and Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.1 Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.1.1 Duration of Calibration Sequence . . . . . . . . . . . . . . . . . . . . .
7.1.2 Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.2.1 DC Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . .
7.1.2.2 AC Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . .
7.1.3 Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.3.1 AC Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . .
7.1.3.2 DC Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . .
7.1.4 Order of Calibration Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Phase Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Active Power Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8. Auto-boot Mode Using E2PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 Auto-Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Auto-Boot Data for E2PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 Suggested E2PROM Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
26
26
26
27
27
27
27
27
28
29
29
29
29
30
30
30
31
32
32
32
33
33
33
33
33
33
34
34
34
35
35
35
35
36
36
36
36
9. Basic Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10. Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . .
13. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
40
41
41
41
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CS5461A
LIST OF FIGURES
Figure 1. CS5461A Read and Write Timing Diagrams ............................................................... 11
Figure 2. Data Flow..................................................................................................................... 13
Figure 3. Normal Format on pulse outputs E1 and E2 ................................................................ 16
Figure 4. Alternate Pulse Format on E1 and E2 .......................................................................... 17
Figure 5. Mechanical Counter Format on E1 and E2 .................................................................. 17
Figure 6. Stepper Motor Format on E1 and E2 ............................................................................ 18
Figure 7. Voltage Sag Detect ...................................................................................................... 19
Figure 8. Oscillator Connection................................................................................................... 20
Figure 9. Calibration Data Flow .................................................................................................. 33
Figure 10. System Calibration of Offset. ..................................................................................... 33
Figure 11. System Calibration of Gain ........................................................................................ 34
Figure 12. Example of AC Gain Calibration ................................................................................ 34
Figure 13. Another Example of AC Gain Calibration .................................................................. 34
Figure 14. Typical Interface of E2PROM to CS5461A ................................................................ 36
Figure 15. Typical Connection Diagram (Single-phase, 2-wire – Direct Connect to Power Line)37
Figure 16. Typical Connection Diagram (Single-phase, 2-wire – Isolated from Power Line)...... 38
Figure 17. Typical Connection Diagram (Single-phase, 3-wire).................................................. 38
Figure 18. Typical Connection Diagram (Single-phase, 3-wire – No Neutral Available)............. 39
LIST OF TABLES
Table 1. Current Channel PGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2. E1 and E2 Pulse Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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CS5461A
1. OVERVIEW
The CS5461A is a CMOS monolithic power measurement device with a computation engine and an energy-to-frequency pulse output. The CS5461A combines a programmable-gain amplifier, two ∆Σ analog-to-digital converters (ADCs), system calibration and a computation engine on a single chip.
The CS5461A is designed for power measurement applications and is optimized to interface to a current-sense resistor or transformer for current measurement, and to a resistive divider or potential transformer for voltage measurement. The voltage and current channels provide programmable gains to
accommodate various input levels from a wide variety of sensing elements. With single +5 V supply on
VA+/AGND, both of the CS5461A’s input channels can accommodate common mode as well as signal
levels between (AGND - 0.25 V) and VA+.
Additionally, the CS5461A is equipped with a computation engine that calculates IRMS, VRMS, apparent
power and active (real) power. To facilitate communication to a microprocessor, the CS5461A includes a
simple three-wire serial interface which is SPI™ and Microwire™ compatible. The CS5461A provides
three outputs for energy registration. E1 and E2 are designed to directly drive a mechanical counter or
stepper motor, or interface to a microprocessor. The pulse output E3 is designed to assist with meter calibration.
DS661F1
5
CS5461A
2. PIN DESCRIPTION
Crystal Out
XOUT
CPU Clock Output
CPUCLK
Positive Digital Supply
VD+
Digital Ground
DGND
Serial Clock
SCLK
Serial Data Ouput
SDO
Chip Select
CS
Mode Select
MODE
Differential Voltage Input
VIN+
Differential Voltage Input
VINVoltage Reference Output VREFOUT
Voltage Reference Input
VREFIN
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
XIN
SDI
E2
E1
INT
RESET
E3
PFMON
IIN+
IINVA+
AGND
Crystal In
Serial Data Input
Energy Output 2
Energy Output 1
Interrupt
Reset
High Frequency Energy Output
Power Fail Monitor
Differential Current Input
Differential Current Input
Positive Analog Supply
Analog Ground
Clock Generator
Crystal Out
Crystal In
1,24
CPU Clock Output
XOUT, XIN - The output and input of an inverting amplifier. Oscillation occurs when connected to
a crystal, providing an on-chip system clock. Alternatively, an external clock can be supplied to
the XIN pin to provide the system clock for the device.
2
CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.
Serial Clock Input
5
SCLK - A Schmitt Trigger input pin. Clocks data from the SDI pin into the receive buffer and out of
the transmit buffer onto the SDO pin when CS is low.
Serial Data Output
6
SDO -Serial port data output pin.SDO is forced into a high impedance state when CS is high.
Chip Select
7
CS - Low, activates the serial port interface.
Mode Select
8
MODE - High, enables the “auto-boot” mode. The mode pin is pulled low by an internal resistor.
High Frequency Energy
Output
18
E3 - Active low pulses with an output frequency proportional to the active power. Used to assist in
system calibration.
Reset
19
RESET - A Schmitt Trigger input pin. Low activates Reset, all internal registers (some of which
drive output pins) are set to their default states.
Interrupt
20
INT - Low, indicates that an enabled event has occurred.
Control Pins and Serial Data I/O
Energy Output
Serial Data Input
21,22
23
E1, E2 - Active low pulses with an output frequency proportional to the active power. Indicates if
the measured energy is negative.
SDI - Serial port data input pin. Data will be input at a rate determined by SCLK.
Analog Inputs/Outputs
Differential Voltage Inputs
9,10
Differential Current Inputs
15,16
Voltage Reference Output
11
VREFOUT - The on-chip voltage reference output. The voltage reference has a nominal magnitude of 2.5 V and is referenced to the AGND pin on the converter.
Voltage Reference Input
12
VREFIN - The input to this pin establishes the voltage reference for the on-chip modulator.
VIN+, VIN- - Differential analog input pins for the voltage channel.
IIN+, IIN- - Differential analog input pins for the current channel.
Power Supply Connections
Positive Digital Supply
3
VD+ - The positive digital supply.
Digital Ground
4
DGND - Digital Ground.
Positive Analog Supply
14
VA+ - The positive analog supply.
Analog Ground
13
AGND - Analog ground.
Power Fail Monitor
17
PFMON - The power fail monitor pin monitors the analog supply. If PFMON’s voltage threshold is
not met, a Low-Supply Detect (LSD) bit is set in the status register.
6
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CS5461A
3. CHARACTERISTICS & SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter
Positive Digital Power Supply
Positive Analog Power Supply
Voltage Reference
Specified Temperature Range
Symbol
VD+
VA+
VREFIN
TA
Min
3.135
4.75
-40
Typ
5.0
5.0
2.5
-
Max
5.25
5.25
+85
Unit
V
V
V
°C
ANALOG CHARACTERISTICS
•
•
•
•
Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VA+ = VD+ = 5 V ±5%; AGND = DGND = 0 V; VREFIN = +2.5 V. All voltages with respect to 0 V.
MCLK = 4.096 MHz.
Parameter
Symbol
Min
Typ
Max
Unit
-
±0.1
-
-
±0.1
±0.2
±3.0
-
%
%
%
%
%
-
±0.1
-
%
Linearity Performance
Active Power Accuracy
(Note 1)
Current RMS Accuracy
(Note 1)
Voltage RMS Accuracy
(Note 1)
All Gain Ranges
Input Range 0.1% - 100%
All Gain Ranges
Input Range 1.0% - 100%
Input Range 0.3% - 1.0%
Input Range 0.1% - 0.3%
All Gain Ranges
Input Range 5% - 100%
PActive
(DC, 50, 60 Hz)
All Gain Ranges
CMRR
80
-0.25
-
VA+
dB
V
IRMS
VRMS
Analog Inputs (Both Channels)
Common Mode Rejection
Common Mode + Signal
Analog Inputs (Current Channel)
Differential Input Range
[(IIN+) - (IIN-)]
(Gain = 10)
(Gain = 50)
IIN
-
500
100
-
mVP-P
mVP-P
Total Harmonic Distortion
Crosstalk with Voltage Channel at Full Scale
Input Capacitance
(Gain = 50)
(50, 60 Hz)
(Gain = 10)
(Gain = 50)
THD
80
30
-
94
-115
32
52
-
22.5
4.5
dB
dB
pF
pF
kΩ
µVrms
µVrms
-
4.0
±0.4
-
(Note 2)
OD
GE
µV/°C
%
{(VIN+) - (VIN-)}
VIN
-
500
-
mVP-P
Total Harmonic Distortion
Crosstalk with Current Channel at Full Scale
(50, 60 Hz)
Input Capacitance
All Gain Ranges
Effective Input Impedance
Noise (Referred to Input)
THD
IC
EII
NV
65
2
-
75
-70
0.2
-
140
dB
dB
pF
MΩ
µVrms
Offset Drift (Without the high-pass Filter)
Gain Error
OD
GE
-
16.0
±3.0
-
µV/°C
%
Effective Input Impedance
Noise (Referred to Input)
Offset Drift (Without the high-pass filter)
Gain Error
(Gain = 10)
(Gain = 50)
IC
EII
NI
Analog Inputs (Voltage Channel)
Differential Input Range
DS661F1
(Note 2)
7
CS5461A
ANALOG CHARACTERISTICS (Continued)
Parameter
Symbol
Min
Typ
Max
Unit
T
-
±5
-
°C
Power Supply Currents (Active State)
IA+
ID+ (VA+ = VD+ = 5 V)
ID+ (VA+ = 5 V, VD+ = 3.3 V)
PSCA
PSCD
PSCD
-
1.3
2.9
1.7
-
mA
mA
mA
Power Consumption
Active State (VA+ = VD+ = 5 V)
(Note 3)
Active State (VA+ = 5 V, VD+ = 3.3 V)
Stand-By State
Sleep State
Power Supply Rejection Ratio
(DC, 50 and 60 Hz)
(Note 4)
Voltage Channel
Current Channel
PFMON Low-voltage Trigger Threshold
(Note 5)
PFMON High-voltage Power-On Trip Point
(Note 6)
PC
-
21
12
8
10
28
16.5
-
mW
mW
mW
µW
PSRR
45
70
2.3
-
65
75
2.45
2.55
2.7
dB
dB
V
V
Temperature Channel
Temperature Accuracy
Power Supplies
PMLO
PMHI
1. Applies when the HPF option is enabled.
2. Applies before system calibration.
3. All outputs unloaded. All inputs CMOS level.
4. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV (zero-to-peak) (60 Hz)
sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input
channels are shorted to AGND. Then the CS5461A is commanded to continuous conversion acquisition mode, and
digital output data is collected for the channel under test. The (zero-to-peak) value of the digital sinusoidal output
signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal voltage (measured
in mV) that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output.
This voltage is then defined as Veq. PSRR is then (in dB):
⎧ 150 ⎫
PSRR = 20 ⋅ log ⎨ ---------- ⎬
⎩ V eq ⎭
5. When voltage level on PFMON is sagging, and LSD bit is at 0, the voltage at which LSD bit is set to 1.
6. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on PFMON at
which the LSD bit can be permanently reset back to 0.
VOLTAGE REFERENCE
Parameter
Symbol
Min
Typ
Max
Unit
VREFOUT
+2.4
+2.5
+2.6
V
Reference Output
Output Voltage
Temperature Coefficient
(Note 7)
TCVREF
-
25
60
ppm/°C
Load Regulation
(Note 8)
∆VR
-
6
10
mV
VREFIN
+2.4
+2.5
+2.6
V
Input Capacitance
-
4
-
pF
Input CVF Current
-
25
-
nA
Reference Input
Input Voltage Range
Notes: 7. The voltage at VREFOUT is measured across the temperature range. From these measurements the following
formula is used to calculate the VREFOUT Temperature Coefficient:.
( ( V R E F O VU RT E F O- UV TR E F O U T
MAX
AVG
M IN )
(
8
=
(T
A
M AX
1
- T A M IN
(
8.
VREF
( 1 .0
x 10
6
(
TC
Specified at maximum recommended output of 1 µA, source or sink.
DS661F1
CS5461A
DIGITAL CHARACTERISTICS
•
•
•
•
Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
MCLK = 4.096 MHz.
Parameter
Symbol
Min
Typ
Max
Unit
2.5
4.096
20
MHz
40
-
60
%
60
%
Master Clock Characteristics
Master Clock Frequency
Internal Gate Oscillator (Note 10) MCLK
Master Clock Duty Cycle
CPUCLK Duty Cycle
(Note 11 and 12)
40
Filter Characteristics
Phase Compensation Range
(Voltage Channel, 60 Hz)
Input Sampling Rate
Digital Filter Output Word Rate
DCLK = MCLK/K
(Both Channels)
High-pass Filter Corner Frequency
OWR
-3 dB
Full Scale Calibration Range (Referred to Input)
(Note 13) FSCR
Channel-to-channel Time-shift Error
(Note 14)
-2.8
-
+2.8
°
-
DCLK/8
-
Hz
-
DCLK/1024
-
Hz
-
0.5
-
Hz
25
-
100
%F.S.
1.0
µs
Input/Output Characteristics
High-level Input Voltage
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
VIH
Low-level Input Voltage (VD = 5 V)
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
VIL
Low-level Input Voltage (VD = 3.3 V)
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
VIL
High-level Output Voltage
Iout = +5 mA
Low-level Output Voltage
Iout = -5 mA
0.6 VD+
(VD+) - 0.5
0.8 VD+
-
-
V
V
V
-
-
0.8
1.5
0.2 VD+
V
V
V
-
-
0.48
0.3
0.2 VD+
V
V
V
VOH
(VD+) - 1.0
-
-
V
VOL
-
-
0.4
V
Iin
-
±1
±10
µA
3-state Leakage Current
IOZ
-
-
±10
µA
Digital Output Pin Capacitance
Cout
-
5
-
pF
Input Leakage Current
(Note 15)
Notes: 9. All measurements performed under static conditions.
10.
11.
12.
13.
14.
15.
DS661F1
If a crystal is used, then XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is used,
XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between 2.5 MHz - 5.0 MHz.
If external MCLK is used, then the duty cycle must be between 45% and 55% to maintain this specification.
The frequency of CPUCLK is equal to MCLK.
The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is limited by the
full-scale signal applied to the channel input.
Configuration Register bits PC[6:0] are set to “0000000”.
The MODE pin is pulled low by an internal resistor.
9
CS5461A
SWITCHING CHARACTERISTICS
•
•
•
•
Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.
Parameter
Symbol
Min
Typ
Max
Unit
Rise Times
(Note 16)
Any Digital Input Except SCLK
SCLK
Any Digital Output
trise
-
50
1.0
100
-
µs
µs
ns
Fall Times
(Note 16)
Any Digital Input Except SCLK
SCLK
Any Digital Output
tfall
-
50
1.0
100
-
µs
µs
ns
XTAL = 4.096 MHz (Note 17)
tost
-
60
-
ms
SCLK
-
-
2
MHz
t1
t2
200
200
-
-
ns
ns
CS Falling to SCLK Rising
t3
50
-
-
ns
Data Set-up Time Prior to SCLK Rising
t4
50
-
-
ns
Data Hold Time After SCLK Rising
t5
100
-
-
ns
CS Falling to SDO Driving
t6
-
20
50
ns
SCLK Falling to New Data Bit (hold time)
t7
-
20
50
ns
CS Rising to SDO Hi-Z
t8
-
20
50
ns
Start-up
Oscillator Start-Up Time
Serial Port Timing
Serial Clock Frequency
Serial Clock
Pulse Width High
Pulse Width Low
SDI Timing
SDO Timing
Auto-Boot Timing
Serial Clock
Pulse Width Low
Pulse Width High
t9
t10
8
8
MCLK
MCLK
MODE setup time to RESET Rising
t11
50
ns
RESET rising to CS falling
t12
48
MCLK
CS falling to SCLK rising
t13
100
SCLK falling to CS rising
t14
CS rising to driving MODE low (to end auto-boot sequence).
t15
50
ns
SDO guaranteed setup time to SCLK rising
t16
100
ns
8
MCLK
16
MCLK
Notes: 16. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
17.
10
Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external
clock source.
DS661F1
CS5461A
t3
CS
t1
t2
SC LK
H ig h B y te
LSB
MSB
MSB-1
LSB
MSB
LSB
MSB
C o m m a n d T im e 8 S C L K s
MSB-1
t5
MSB-1
LSB
MSB
SDI
MSB-1
t4
M id B y te
L o w B y te
SDI Write Timing (Not to Scale)
CS
t1
t8
LSB
MSB-1
LSB
MSB
L o w B y te
MSB-1
LSB
UNKNOW N
MSB-1
MSB
SDO
M id B y t e
MSB
H ig h B y t e
t6
t7
t2
LSB
MSB-1
SDI
MSB
SC LK
C o m m a n d T im e 8 S C L K s
SYNC0 or SYNC1
Com m and
SYNC0 or SYNC1
Com m and
SYNC0 or SYNC1
Com m and
SDO Read Timing (Not to Scale)
t11
t15
MODE
( IN P U T )
RESET
( IN P U T )
CS
t14
t12
t7
t13
(O U T P U T )
SCLK
(O U T P U T )
t10
SDO
t16
t9
t4
t5
STOP bit
(O U T P U T )
SDI
( IN P U T )
Last 8
B it s
D a ta fro m E E P R O M
Auto-Boot Sequence Timing (Not to Scale)
Figure 1. CS5461A Read and Write Timing Diagrams
DS661F1
11
CS5461A
ABSOLUTE MAXIMUM RATINGS
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Parameter
DC Power Supplies
Input Current, Any Pin Except Supplies
Symbol
Min
Typ
Max
Unit
(Notes 18 and 19)
Positive Digital
Positive Analog
VD+
VA+
-0.3
-0.3
-
+6.0
+6.0
V
V
(Notes 20, 21, 22)
IIN
-
-
±10
mA
IOUT
-
-
100
mA
PD
-
-
500
mW
Output Current, Any Pin Except VREFOUT
Power Dissipation
(Note 23)
Analog Input Voltage
All Analog Pins
VINA
- 0.3
-
(VA+) + 0.3
V
Digital Input Voltage
All Digital Pins
VIND
-0.3
-
(VD+) + 0.3
V
Ambient Operating Temperature
TA
-40
-
85
°C
Storage Temperature
Tstg
-65
-
150
°C
Notes: 18. VA+ and AGND must satisfy {(VA+) - (AGND)} ≤ + 6.0 V.
19.
20.
21.
22.
23.
12
VD+ and AGND must satisfy {(VD+) - (AGND)} ≤ + 6.0 V.
Applies to all pins including continuous over-voltage conditions at the analog input pins.
Transient current of up to 100 mA will not cause SCR latch-up.
Maximum DC input current for a power supply pin is ±50 mA.
Total power dissipation, including all input currents and output currents.
DS661F1
CS5461A
VDCoff* Vgn *
V ACoff*
V*
Digital Filter
VOLTAGE
x10
2nd Order
∆Σ
Modulator
DELAY
REG
SINC 3
X
IIR
HPF
Option
+
+
Σ
N
X
X
Poff *
6
Σ
PulseRateE1,2 *
÷N
X
+
PC6 PC5 PC4 PC3 PC2 PC1 PC0
SYSGain *
X
Configuration Register *
+
P*
CURRENT
PGA
4th Order
∆Σ
Modulator
SINC 3
DELAY
REG
X
IIR
HPF
Option
Digital Filter
X
X
+
I gn*
Σ
X
÷N
√
V RMS *
E3
PActive*
X
S*
E1
E2
Energy-to-pulse
÷N
+
Σ
+
Σ
I RMS *
+
IACoff*
I*
Figure 2. Data Flow.
The CS5461A is a dual-channel analog-to-digital converter (ADC) followed by a computation engine that performs power calculations and energy-to-pulse
conversion. The flow diagram for the two data paths is
depicted in Figure 2. The analog inputs are structured
with two dedicated channels, voltage and current, then
optimized to simplify interfacing to sensing elements.
The voltage-sensing element introduces a voltage
waveform on the voltage channel input VIN± and is subject to a gain of 10x. A second-order, delta-sigma modulator samples the amplified signal for digitization.
Simultaneously, the current-sensing element introduces
a voltage waveform on the current channel input IIN±
and is subject to the two selectable gains of the programmable gain amplifier (PGA). The amplified signal is
sampled by a fourth-order, delta-sigma modulator for
digitization. Both converters sample at a rate of
MCLK/8, the over-sampling provides a wide dynamic
range and simplified anti-alias filter design.
4.1 Digital Filters
The decimating digital filters on both channels are Sinc3
filters followed by 4th-order, IIR filters. The single-bit
data is passed to the low-pass decimation filter and output at a fixed word rate. The output word is passed to
the IIR filter to compensate for the magnitude roll-off of
the low-pass filtering operation.
An optional digital High-pass Filter (HPF in Figure 2) removes any DC component from the selected signal
path. By removing the DC component from the voltage
and/or the current channel, any DC content will also be
removed from the calculated active power as well. With
both HPFs enabled, the DC component will be removed
from the calculated VRMS and IRMS as well as the apparent power.
DS661F1
N
Σ
IDCoff*
* DENOTES REGISTER NAME.
4. THEORY OF OPERATION
+
N
PulseRateE3 *
+
Energy-to-pulse
Σ
Σ
√
4.2 Voltage and Current Measurements
The digital filter output word is then subject to a DC offset adjustment and a gain calibration (See Section 7.
System Calibration on page 33). The calibrated measurement is available to the user by reading the instantaneous voltage and current registers.
The Root Mean Square (RMS) calculations are performed on N instantaneous voltage and current samples, Vn and In respectively (where N is the cycle count),
using the formula:
N–1
I RMS =
∑
I
n
n=0
-------------------N
and likewise for VRMS, using Vn. IRMS and VRMS are accessible by register reads, which are updated once every cycle count (referred to as a computational cycle).
4.3 Power Measurements
The instantaneous voltage and current samples are
multiplied to obtain the instantaneous power (see Figure 2). The product is then averaged over N conversions to compute active power and used to drive energy
pulse outputs E1, E2 and E3. Output E3 provides a uniform pulse stream that is proportional to the active power and is designed for system calibration.
To generate a value for the accumulated active energy
over the last computation cycle, the active power can be
multiplied by the time duration of the computation cycle.
13
CS5461A
The apparent power is the combination of the active
power and reactive power, without reference to an impedance phase angle, and is calculated by the
CS5461A using the following formula:
S = V RMS × I RMS
The apparent power is registered once every computation cycle.
4.4 Linearity Performance
The linearity of the VRMS, IRMS, and active power measurements (before calibration) will be within ±0.1% of
reading over the ranges specified, with respect to the in-
14
put voltage levels required to cause full-scale readings
in the IRMS and VRMS registers. Refer to Linearity Performance Specifications on page 7.
Until the CS5461A is calibrated, the accuracy of the
CS5461A (with respect to a reference line-voltage and
line-current level on the power mains) is not guaranteed
to within ±0.1%. See Section 7. System Calibration on
page 33. The accuracy of the internal calculations can
often be improved by selecting a value for the Cycle
Count Register that will cause the time duration of one
computation cycle to be equal to (or very close to) a
whole-number of power-line cycles (and N must be
greater than or equal to 4000).
DS661F1
CS5461A
5. FUNCTIONAL DESCRIPTION
5.1 Analog Inputs
The CS5461A is equipped with two fully differential input channels. The inputs VIN± and IIN± are designated
as the voltage and current channel inputs, respectively.
The full-scale differential input voltage for the current
and voltage channel is ±250 mVP.
5.1.1 Voltage Channel
The output of the line-voltage resistive divider or transformer is connected to the VIN+ and VIN- input pins of
the CS5461A. The voltage channel is equipped with a
10x, fixed-gain amplifier. The full-scale signal level that
can be applied to the voltage channel is ±250 mV. If the
input signal is a sine wave the maximum RMS voltage
at a gain 10x is:
250mV P
--------------------- ≅ 176.78mV
2
5.1.2 Current Channel
The output of the current-sense resistor or transformer
is connected to the IIN+ and IIN- input pins of the
CS5461A. To accommodate different current-sensing
elements, the current channel incorporates a Programmable Gain Amplifier (PGA) with two programmable input gains. Configuration Register bit Igain (See Table 1)
defines the two gain selections and corresponding maximum input-signal level.
Maximum Input Range
0
±250 mV
10x
1
±50 mV
50x
Table 1. Current Channel PGA Configuration
For example, if Igain=0, the current channel’s PGA gain
is set to 10x. If the input signals are pure sinusoids with
zero phase shift, the maximum peak differential signal
on the current or voltage channel is ±250 mVP. The input-signal levels are approximately 70.7% of maximum
peak voltage producing a full-scale energy pulse registration equal to 50% of absolute maximum energy pulse
registration. This will be discussed further in Section 5.4
Energy Pulse Output on page 16.
The Current Gain Register also allows for an additional
programmable gain of up to 4x. If an additional gain is
DS661F1
5.2 High-pass Filters
By removing the offset from either channel, no error
component will be generated at DC when computing the
active power. By removing the offset from both channels, no error component will be generated at DC when
computing VRMS, IRMS, and apparent power. Configuration Register bits VHPF and IHPF activate the HPF in
the voltage and current channel respectively.
5.3 Performing Measurements
The CS5461A performs measurements of instantaneous voltage (Vn) and current (In), and calculates instantaneous power (Pn) at an Output Word Rate (OWR)
of
RMS
which is approximately 70.7% of maximum peak voltage. The voltage channel is also equipped with a Voltage Gain Register, allowing for an additional
programmable gain of up to 4x.
Igain
applied to the voltage and/or current channel, the maximum input range should be adjusted accordingly.
( MCLK ⁄ K )
OWR = ----------------------------1024
where K is the clock divider setting in the Configuration
Register.
The RMS voltage (VRMS), RMS current (IRMS), and active power (PActive) are computed using N instantaneous samples of Vn, In and Pn respectively, where N is
the value in the Cycle Count Register (N) and is referred
to as a “computation cycle”. The apparent power (S) is
the product of VRMS and IRMS. A computation cycle is
derived from the master clock (MCLK), with frequency:
OWR
Computation Cycle = --------------N
Under default conditions & with K = 1, N = 4000, and
MCLK = 4.096 MHz – the OWR = 4000 Hz and the
Computation Cycle = 1 Hz.
All measurements are available as a percentage of full
scale. The format for signed registers is a two’s complement, normalized value between -1 and +1. The format
for unsigned registers is a normalized value between 0
and 1. A register value of
23
(2 – 1)
------------------------ = 0.99999988
23
2
represents the maximum possible value.
At each instantaneous measurement, the CRDY bit will
be set (logic 1) in the Status Register, and the INT pin
will become active if the CRDY bit is unmasked in the
Mask Register. At the end of each computation cycle,
the DRDY bit will be set in the Status Register, and the
15
CS5461A
INT pin will become active if the DRDY bit is unmasked
in the Mask Register. When these bits are set, they
must be cleared (logic 0) by the user before they can be
asserted again.
If the Cycle Count Register (N) is set to 1, all output calculations are instantaneous, and DRDY, like CRDY, will
indicate when instantaneous measurements are finished. Some calculations are inhibited when the cycle
count is less than 2.
5.4 Energy Pulse Output
The CS5461A provides three output pins for energy registration. The E1 and E2 pins provide a simple interface
which energy can be registered. These pins are designed to directly connect to a stepper motor or electromechanical counter. E1 and E2 pins can be set to one
of four pulse output formats, Normal, Alternate, Stepper
Motor, or Mechanical Counter. Table 2 defines the
pulse output format, which is controlled by bits ALT in
the Configuration Register, and MECH and STEP in the
Control Register.
ALT
STEP
MECH
FORMAT
0
0
0
Normal
0
X
1
Mechanical Counter
0
1
0
Stepper Motor
1
X
1
Alternate Pulse
Table 2. E1 and E2 Pulse Output Format
The E3 pin is designated for system calibration, the
pulse rate can be selected to reach a frequency of
512 kHz.
The pulse output frequency of E1 and E2 is directly proportional to the active power calculated from the input
signals. To calculate the output frequency on E1 and
E2, the following transfer function can be utilized:
P o s itiv e E n e rg y B u rs t
VIN × VGAIN × IIN × IGAIN × PF × PulseRateE 1, 2
FREQ E = -----------------------------------------------------------------------------------------------------------------------------------------------2
VREFIN
FREQE = Average frequency of E1 and E2 pulses [Hz]
VIN = rms voltage across VIN+ and VIN- [V]
VGAIN = Voltage channel gain
IIN = rms voltage across IIN+ and IIN- [V]
IGAIN = Current channel gain
PF = Power Factor
PulseRateE1,2 = Maximum frequency on E1 and E2 [Hz]
VREFIN = Voltage at VREFIN pin [V]
With MCLK = 4.096 MHz, PF = 1, and default settings,
the pulses will have an average frequency equal to the
frequency setting in the PulseRateE1,2 Register when
the input signals applied to the voltage and current
channels cause full-scale readings in the instantaneous
voltage and current registers. When MCLK/K is not
equal to 4.096 MHz, the user should scale the
PulseRateE1,2 Register
by
a
factor
of
4.096 MHz/(MCLK/K) to get the actual pulse rate output.
5.4.1 Normal Format
The Normal format is the default. Figure 3 illustrates the
output format on pins E1 and E2. The E1 pin outputs active-low pulses with a frequency proportional to the active power. The E2 pin is the energy direction indicator.
Positive energy is represented by a pulse on the E1 pin
while the E2 pin remains high. Negative energy is represented by synchronous pulses on both the E1 pin and
the E2 pin.
The PulseRateE1,2 Register defines the average frequency on output pin E1, when full-scale input signals
are applied to the voltage and current channels. The
maximum pulse frequency from the E1 pin
N e g a tiv e E n e rg y B u rs t
td ur
E1
. . .
. . .
E2
. . .
. . .
Figure 3. Normal Format on pulse outputs E1 and E2
16
DS661F1
CS5461A
FREQE
tPW
E1 ...
...
...
E2 ...
Figure 4. Alternate Pulse Format on E1 and E2
is (MCLK/K)/16. The pulse duration (tdur) is an integer
multiple of MCLK cycles, approximately equal to:
t dur ( sec )
PulseRateE 1, 2
1
≅ -------------------------------------------PulseRateE 1, 2 × 8
The maximum pulse duration (tdur) is determined by the
sampling rate and the minimum is defined by the maximum pulse frequency. The tdur limits are:
1
1
----------------------------------< t dur ( sec ) < ----------------------------------------(MCLK/K)/16 × 8
(MCLK/K)/1024 × 8
The Pulse Width Register (PW) does not affect the normal format.
5.4.2 Alternate Pulse Format
Setting bits MECH = 1 and STEP = 0 in the Control
Register and ALT = 1 in the Configuration Register configures the E1 and E2 pins for alternating pulse format
output (see Figure 4). Each pin produces alternating active-low pulses with a pulse duration (tPW) defined by
the Pulse Width Register (PW):
t PW ( ms )
=
PW
The pulse frequency (FREQE) is determined by the
PulseRateE1,2 Register and can be calculated using the
transfer function. The energy direction is not defined in
the alternate pulse format.
5.4.3 Mechanical Counter Format
Setting bits MECH = 1 and STEP = 0 in the Control
Register and bit ALT = 0 in the Configuration Register
enables E1 and E2 for mechanical counters and similar
discrete counting instruments. When energy is negative, pulses appear on E2 (see Figure 5). When energy
is positive, the pulses appear on E1. The pulse width is
defined by the Pulsewidth Register and will limit the output pulse frequency (FREQE). By default, PW = 512
samples, if MCLK = 4.096 MHz and K = 1 then
tPW = 128 ms. To ensure that pulses will occur, the
PulseRateE1,2 Register must be set to an appropriate
value.
Setting bits STEP = 1 and MECH = 0 in the Control
Register and bit ALT = 0 in the Configuration Register
configures the E1 and E2 pins for stepper motor format.
When the accumulated active power equals the defined
tPW
FREQE
E2
1
< ----------t
5.4.4 Stepper Motor Format
PW
----------------------------------------(MCLK/K)/1024
If MCLK = 4.096 MHz, K = 1, and PW = 1 then
tPW = 0.25 ms. To ensure that pulses occur on the E1
E1
and E2 output pins when full-scale input signals are applied to the voltage and current channels, then:
...
...
...
...
Positive Energy
Negative Energy
Figure 5. Mechanical Counter Format on E1 and E2
DS661F1
17
CS5461A
tedg e
E1
...
...
E2
...
...
P o s it iv e E n e r g y
N e g a t iv e E n e r g y
Figure 6. Stepper Motor Format on E1 and E2
energy level, the energy output pins (E1 and E2) alternate changing states (see Figure 6). The duration
(tedge) between the alternating states is defined by the
transfer function:
t
edge
( sec )
=
1
---------------------FREQ E
The direction the motor will rotate is determined by the
order of the state changes. When energy is positive, E1
will lead E2. When energy is negative, E2 will lead E1.
The Pulse Width Register (PW) does not affect the stepper motor format.
5.4.5 Pulse Output E3
The pulse output E3 is designed to assist with meter calibration. The pulse-output frequency of E3 is directly
proportional to the active power calculated from the input signals. E3 pulse frequency is derived using a simular transfer function as E1, but is set by the value in the
PulseRateE3 Register.
The E3 pin outputs negative and positive energy, but
has no energy direction indicator.
5.4.6 Anti-creep for the Pulse Outputs
Anti-creep allows the measurement element to maintain
an energy level, such that when the magnitude of the
accumulated active power is below this level, no energy
pulses are output. Anti-creep is enabled by setting bit
FAC in the Control Register for E3 and bit EAC in the
Control Register for E1 and E2.
For low-frequency pulse output formats (i.e. mechanical
counter and stepper motor formats), the active power is
accumulated over time. When a designated energy level is reached (determined by the transfer function) a
pulse is generated on E1 and/or E2. If active power with
alternating polarity occurs during the accumulation period (e.g. random noise at zero power levels), the accuracy of the registered energy will be maintained.
For high-frequency pulse output formats (i.e. normal
and alternate pulse formats), the active power is accumulated over time until a ±8x buffer is defined. Then,
when the designated energy level is reached, a pulse is
18
generated on E1 and/or E2. For pulse outputs with high
frequencies and power levels close to zero, the extended buffer prevents random noise from being registered
as active energy.
5.4.7 Design Examples
EXAMPLE #1:
The maximum rated levels for a power line meter are
250 V rms and 20 A rms. The required number of pulses per second on E1 is 100 pulses per second (100 Hz),
when the levels on the power line are 220 V rms and
15 A rms.
With a 10x gain on the voltage and current channel the
maximum input signal is 250 mVP (see Section 5.1 Analog Inputs on page 15). To prevent over-driving the
channel inputs, the maximum rated rms input levels will
register 0.6 in VRMS and IRMS by design. Therefore the
voltage level at the channel inputs will be 150 mV rms
when the maximum rated levels on the power lines are
250 V rms and 20 A rms.
Solving for PulseRateE1,2 using the transfer function:
PulseRateE
1, 2
2
FREQ × VREFIN
E
= ------------------------------------------------------------------VIN × VGAIN × IIN × PF
Therefore with PF = 1 and
VIN = 220V × ( ( 150mV ) ⁄ ( 250V ) ) = 132mV
IIN = 15A × ( ( 150mV ) ⁄ ( 20A ) ) = 112.5mV
the PulseRateE1,2 Register is set to:
2
100 × 2.5
PulseRateE = ----------------------------------------------------------------- = 420.8754Hz
0.132 × 10 × 0.1125 × 10
EXAMPLE #2:
The required number of pulses per unit energy present
on E1 is specified to be 500 pulses per kWhr, given that
the line voltage is 250 Vrms and the line current is
20 Arms. In such a situation, the stated line voltage and
current do not determine the appropriate PulseRateE1,2
setting. To achieve full-scale readings in the instanta-
DS661F1
CS5461A
neous voltage and current registers, a 250 mV, DC-level signal is applied to the channel inputs.
As in example #1, the voltage and current channel gains
are 10x, and the voltage level at the channel inputs will
be 150 mV rms when the levels on the power lines are
250 V rms and 20 A rms. In order to achieve
500 pulse-per-kW Hr
per
unit-energy,
the
PulseRateE1,2 Register setting is determined using the
following equation:
PulseRateE
1, 2
(VSAGDuration). The voltage sag level is specified as the
average of the absolute instantaneous voltage. Voltage
sag duration is specified in terms of ADC cycles.
500pulses
1Hr
1kW
250mV
250mV
= ------------------------------ × ---------------- × ------------------- × ------------------------- × ------------------------kWHr
3600s 1000W ⎛ 150mV⎞ ⎛ 150mV⎞
------------------------------------⎝ 250V ⎠ ⎝ 20A ⎠
Level
Duration
Therefor, the PulseRateE1,2 Register is approximately
1.929 Hz. The PulseRateE1,2 Register cannot be set to
a frequency of exactly 1.929 Hz. The closest setting is
0x00003E = 1.9375 Hz.
To improve the accuracy, either gain register can be
programmed to correct for the round-off error. This value would be calculated as
Vgn or Ign
=
PulseRateE
----------------------------------1.929
≅ 1.00441 =
0x404830
If (MCLK/K) is not equal to 4.096 MHz, the
PulseRateE1,2 Register must be scaled by a correction
factor of:
4.096MHz
---------------------------(MCLK/K)
× PulseRateE1, 2
Therefore if (MCLK/K) = 3.05856 MHz the value of
PulseRateE1,2 Register is
PulseRateE
1, 2
=
4.096
--------------------3.05856
× 1.929Hz ≅ 2.583Hz
5.5 Voltage Sag-detect Feature
Status bit VSAG in the Status Register, indicates a voltage sag occurred in the power line voltage. For a voltage sag condition to be identified, the absolute value of
the instantaneous voltage must be less than the voltage
sag level for more than half of the voltage sag duration
(see Figure 7).
To activate Voltage Sag detect, a voltage sag level must
be specified in the Voltage Sag Level Register
(VSAGLevel), and a voltage sag duration must be specified in the Voltage Sag Duration Register
DS661F1
Figure 7. Voltage Sag Detect
5.6 On-chip Temperature Sensor
The on-chip temperature sensor is designed to assist in
characterizing the measurement element over a desired
temperature range. Once a temperature characterization is performed, the temperature sensor can then be
utilized to assist in compensating for temperature drift.
Temperature measurements are performed during continuous conversions and stored in the Temperature
Register. The Temperature Register (T) default is Celsius scale (oC). The Temperature Gain Register (Tgain)
and Temperature Offset Register (Toff) are constant values allowing for temperature scale conversions.
The temperature update rate is a function of the number
of ADC samples. With MCLK = 4.096 MHz and K = 1
the update rate is:
2240 samples
----------------------------------------(MCLK/K)/1024
=
0.56 sec
The Cycle Count Register (N) must be set to a value
greater than one. Status bit TUP in the Status Register,
indicates when the Temperature Register is updated.
The Temperature Offset Register sets the zero-degree
measurement. To improve temperature measurement
accuracy, the zero-degree offset should be adjusted after the CS5461A is initialized. Temperature offset calibration is achieved by adjusting the Temperature Offset
Register (Toff) by the differential temperature (∆T) measured from a calibrated digital thermometer and the
CS5461A temperature sensor. A one-degree adjustment to the Temperature Register (T) is achieved by
19
CS5461A
adding 2.737649x10-4 to the Temperature Offset Register (Toff). Therefore,
T off = T off
+ ( ∆T × 2.737649 ⋅ 10
–4
)
if Toff = -0.09104831 and ∆T = -7.0 (oC), then
T
off
= – 0.09104831
+ ( – 7.0 × 2.737649 ⋅ 10–4 )
= – 0.09296466
or 0xF419BC (2’s compliment notation) is stored in the
Temperature Offset Register (Toff).
To convert the Temperature Register (T) from a Celsius
scale (oC) to a Fahrenheit scale (oF) utilize the formula
9 o
F = --- ( C + 17.7778 )
5
o
Applying the above relationship to the CS5461A temperature measurement algorithm
T〈
o
9
F〉 = ( --5
× Tgain ) [ T 〈
o
C〉 + ( T off
The CS5461A has two power-down states, stand-by
and sleep. In the stand-by state all circuitry except the
voltage reference and crystal oscillator is turned off. To
return the device to the active state a power-up command is sent to the device.
In sleep state all circuitry except the instruction decoder
is turned off. When the power-up command is sent to
the device, a system initialization is performed (see
Section 5.8 System Initialization on page 20).
5.10 Oscillator Characteristics
The XIN and XOUT pins are the input and output of an
inverting amplifier configured as an on-chip oscillator,
as shown in Figure 8. The oscillator circuit is designed
XOUT
–4
+ ( 17.7778 × 2.737649 ⋅ 10 ) ) ]
If Toff = -0.09296466 and Tgain = 23.799 for a Celsius
scale, then the modified values are Toff = -0.08809772
(0xF4B937) and Tgain = 42.8382 (0x55AD29) for a
Fahrenheit scale.
5.7 Voltage Reference
The CS5461A is specified for operation with a +2.5 V
reference between the VREFIN and AGND pins. To utilize the on-chip 2.5 V reference, connect the VREFOUT
pin to the VREFIN pin of the device. The VREFIN pin
can be used to connect external filtering and/or references.
5.8 System Initialization
Upon powering up, the digital circuitry is held in reset
until the analog voltage reaches 4.0 V. At that time, an
eight-XIN-clock-period delay is enabled to allow the oscillator to stabilize. The CS5461A will then initialize.
A hardware reset is initiated when the RESET pin is asserted with a minimum pulse width of 50 ns. The
RESET signal is asynchronous, with a Schmitt-trigger
input. Once the RESET pin is de-asserted, an
eight-XIN-clock-period delay is enabled.
A software reset is initiated by writing the command of
0x80. After a hardware or software reset, the internal
registers (some of which drive output pins) will be reset
to their default values. Status bit DRDY in the Status
Register, indicates the CS5461A is in its active state
and ready to receive commands.
20
5.9 Power-down States
C1
Oscillator
Circuit
XIN
C2
DGND
C1 = C2 = 22 pF
Figure 8. Oscillator Connection
to work with a quartz crystal. To reduce circuit cost, two
load capacitors C1 and C2 are integrated in the device,
from XIN to DGND, and XOUT to DGND. PCB trace
lengths should be minimized to reduce stray capacitance. To drive the device from an external clock
source, XOUT should be left unconnected while XIN is
driven by the external circuitry. There is an amplifier between XIN and the digital section which provides
CMOS-level signals. This amplifier works with sinusoidal inputs so there are no problems with slow edge
times.
The CS5461A can be driven by an external oscillator
ranging from 2.5 to 20 MHz, but the K divider value must
be set such that the internal MCLK will run somewhere
between 2.5 MHz and 5 MHz. The K divider value is set
with the K[3:0] bits in the Configuration Register. As an
example, if XIN = MCLK = 15 MHz, and K is set to 5,
then DCLK is 3 MHz, which is a valid value for DCLK.
DS661F1
CS5461A
5.11 Event Handler
5.12 Serial Port Overview
The INT pin is used to indicate that an internal error or
event has taken place in the CS5461A. Writing a logic 1
to any bit in the Mask Register allows the corresponding
bit in the Status Register to activate the INT pin. The interrupt condition is cleared by writing a logic 1 to the bit
that has been set in the Status Register.
The CS5461A incorporates a serial port transmit and receive buffer with a command decoder that interprets
one-byte (8 bits) commands as they are received. There
are four types of commands; instructions, synchronizing, register writes and register reads (See Section 5.13
Commands on page 22).
The behavior of the INT pin is controlled by the IMODE
and IINV bits of the Configuration Register.
Instructions are one byte in length and will interrupt any
instruction currently executing. Instructions do not affect
register reads currently being transmitted.
IMODE
IINV
INT Pin
0
0
Active-low Level
0
1
Active-high Level
1
0
Low Pulse
1
1
High Pulse
Table 3. Interrupt Configuration
If the interrupt output signal format is set for either falling
or rising edge, the duration of the INT pulse will be at
least one DCLK cycle (DCLK = MCLK/K).
5.11.1 Typical Interrupt Handler
The steps below show how interrupts can be handled.
INITIALIZATION:
1) All Status bits are cleared by writing 0xFFFFFF to
the Status Register.
2) The condition bits which will be used to generate
interrupts are then set to logic 1 in the Mask Register.
3) Enable interrupts.
INTERRUPT HANDLER ROUTINE:
4) Read the Status Register.
5) Disable all interrupts.
6) Branch to the proper interrupt service routine.
7) Clear the Status Register by writing back the read
value in step 4.
8) Re-enable interrupts.
9) Return from interrupt service routine.
This handshaking procedure ensures that any new interrupts activated between steps 4 and 7 are not lost
(cleared) by step 7.
DS661F1
Synchronizing commands are one byte in length and
only affect the serial interface. Synchronizing commands do not affect operations currently in progress.
Register writes must be followed by three bytes of data.
register reads can return up to four bytes of data.
Commands and data are transferred most-significant bit
(MSB) first. Figure 1 on page 11, defines the serial port
timing and required sequence necessary to write to and
read from the serial port receive and transmit buffer, respectively. While reading data from the serial port, commands and data can be simultaneously written. Starting
a new register read command while data is being read
will terminate the current read in progress. This is acceptable if the remainder of the current read data is not
needed. During data reads, the serial port requires input
data. If a new command and data is not sent, SYNC0 or
SYNC1 must be sent.
5.12.1 Serial Port Interface
The serial port interface is a “4-wire” synchronous serial
communications interface. The interface is enabled to
start excepting SCLKs when CS (Chip Select) is asserted. SCLK (Serial bit-clock) is a Schmitt-trigger input that
is used to strobe the data on SDI (Serial Data In) into the
receive buffer and out of the transmit buffer onto SDO
(Serial Data Out).
If the serial port interface becomes unsynchronized with
respect to the SCLK input, any attempt to clock valid
commands into the serial interface may result in unexpected operation. The serial port interface must then be
re-initialized by one of the following actions:
-
Drive the CS pin high, then low.
Hardware Reset (drive RESET pin low, for at
least 10 µs).
- Issue the Serial Port Initialization Sequence,
which is 3 (or more) SYNC1 command bytes
(0xFF) followed by one SYNC0 command byte
(0xFE).
If a resynchronization is necessary, it is best to re-initialize the part either by hardware or software reset (0x80),
as the state of the part may be unknown.
21
CS5461A
5.13 Commands
All commands are 8-bits in length. Any byte that is not listed in this section is invalid. Commands that write to registers must be followed by 3 bytes of data. Commands that read data can be chained with other commands (e.g., while
reading data, a new command can be sent which can execute during the original read). All commands except register reads, register writes, and SYNC0 & SYNC1 will abort any currently executing commands.
5.13.1 Start Conversions
B7
1
B6
1
B5
1
B4
0
B3
C3
B2
0
B1
0
B0
0
Initiates acquiring measurements and calculating results. The device has two modes of acquisition.
C3
Modes of acquisition/measurement
0 = Perform a single computation cycle
1 = Perform continuous computation cycles
5.13.2 SYNC0 and SYNC1
B7
1
B6
1
B5
1
B4
1
B3
1
B2
1
B1
1
B0
SYNC
The serial port can be initialized by asserting CS or by sending three or more consecutive SYNC1 commands followed by a SYNC0 command. The SYNC0 or SYNC1 can also be sent while sending data out.
SYNC
0 = Last byte of a serial port re-initialization sequence.
1 = Used during reads and serial port initialization.
5.13.3 Power-Up/Halt
B7
1
B6
0
B5
1
B4
0
B3
0
B2
0
B1
0
B0
0
If the device is powered-down, Power-Up/Halt will initiate a power on reset. If the part is already powered-on, all
computations will be halted.
5.13.4 Power-down and Software Reset
B7
1
B6
0
B5
0
B4
S1
B3
S0
B2
0
B1
0
B0
0
To conserve power the CS5461A has two power-down states. In stand-by state all circuitry, except the analog/digital
clock generators, is turned off. In the sleep state all circuitry, except the instruction decoder, is turned off. Bringing
the CS5461A out of sleep state requires more time than out of stand-by state, because of the extra time needed to
re-start and re-stabilize the analog oscillator.
S[1:0]
22
Power-down state
00 = Software Reset
01 = Halt and enter stand-by power saving state. This state allows quick power-on
10 = Halt and enter sleep power saving state.
11 = Reserved
DS661F1
CS5461A
5.13.5 Register Read/Write
B7
0
B6
W/R
B5
RA4
B4
RA3
B3
RA2
B2
RA1
B1
RA0
B0
0
The Read/Write informs the command decoder that a register access is required. During a read operation, the addressed register is loaded into an output buffer and clocked out by SCLK. During a write operation, the data is
clocked into an input buffer and transferred to the addressed register upon completion of the 24th SCLK.
W/R
Write/Read control
0 = Read
1 = Write
RA[4:0]
Register address bits (bits 5 through 1) of the read/write command.
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
21
23
24
26
28
29
30
31
RA[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01110
01111
10000
10001
10010
10011
10100
10101
10111
11000
11010
11100
11101
11110
11111
Name
Config
IDCoff
Ign
VDCoff
Vgn
Cycle Count
PulseRateE1,2
I
V
P
PActive
IRMS
VRMS
Poff
Status
IACoff
VACoff
PulseRateE3
T
SYSGain
PW
VSAGDuration
VSAGLevel
Mask
Ctrl
TGain
Toff
S
Description
Configuration
Current DC Offset
Current Gain
Voltage DC Offset
Voltage Gain
Number of A/D conversions used in one computation cycle (N)).
Sets the E1 and E2 energy-to-frequency output pulse rate.
Instantaneous Current
Instantaneous Voltage
Instantaneous Power
Active (Real) Power
RMS Current
RMS Voltage
Power Offset
Status
Current AC (RMS) Offset
Voltage AC (RMS) Offset
Sets the E3 energy-to-frequency output pulse rate.
Temperature
System Gain
Pulse width register for mechanical counter output mode
Voltage Sag Duration
Voltage Sag Level Threshold
Interrupt Mask
Control
Temperature Sensor Gain
Temperature Sensor Offset
Apparent Power
Note: For proper operation, do not attempt to write to unspecified registers.
DS661F1
23
CS5461A
5.13.6 Calibration
B7
1
B6
1
B5
0
B4
CAL4
B3
CAL3
B2
CAL2
B1
CAL1
B0
CAL0
The CS5461A can perform system calibrations. Proper input signals must be applied to the current and voltage
channel before performing a designated calibration.
CAL[4:0]*
Designates calibration to be performed
01001 = Current channel DC offset
01010 = Current channel DC gain
01101 = Current channel AC offset
01110 = Current channel AC gain
10001 = Voltage channel DC offset
10010 = Voltage channel DC gain
10101 = Voltage channel AC offset
10110 = Voltage channel AC gain
11001 = Current and Voltage channel DC offset
11010 = Current and Voltage channel DC gain
11101 = Current and Voltage channel AC offset
11110 = Current and Voltage channel AC gain
*Values for CAL[4:0] not specified should not be used.
24
DS661F1
CS5461A
6. REGISTER DESCRIPTION
1.
2.
“Default” => bit status after power-on or reset
Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits.
6.1 Configuration Register
Address: 0
23
PC6
22
PC5
21
PC4
20
PC3
19
PC2
18
PC1
17
PC0
Igain
16
15
EWA
14
13
12
IMODE
11
IINV
10
EPP
9
EOP
8
EDP
7
ALT
6
VHPF
5
IHPF
4
iCPU
3
K3
2
K2
1
K1
0
K0
Default = 0x000001
PC[6:0]
Phase compensation. A 2’s complement number which sets a delay in the voltage channel relative to the current channel. When MCLK = 4.096 MHz and K = 1, the phase adjustment range
is approximately ±2.8 degrees with each step approximately 0.04 degrees (assuming a power
line frequency of 60 Hz). If (MCLK/K) is not 4.096 MHz, the values for the range and step size
should be scaled by the factor 4.096 MHz / (MCLK/K). Default setting is 0000000 = 0.0215 degree phase delay at 60 Hz (when MCLK = 4.096 MHz).
Igain
Sets the gain of the current PGA.
0 = Gain is 10x (default)
1 = Gain is 50x
EWA
Allows the E1 and E2 pins to be configured as open-collector output pins.
0 = Normal outputs (default)
1 = Only the pull-down device of the E1 and E2 pins are active
IMODE, IINV
Interrupt configuration bits. Select the desired pin behavior for indication of an interrupt.
00 = Active-low level (default)
01 = Active-high level
10 = High-to-low pulse
11 = Low-to-high pulse
EPP
Allows the E1 and E2 pins to be controlled by the EOP and EDP bits.
0 = Normal operation of the E1 and E2 pins. (default)
1 = EOP and EDP bits defines the E1 and E2 pins.
EOP
EOP defines the value of the E1 pin when EPP = 1.
0 = Logic level low (default)
EDP
EDP defines the value of the E2 pin when EPP = 1.
0 = Logic level low (default)
ALT
Alternate pulse format, E1 and E2 becomes active low alternating pulses with an output frequency proportional to the active power.
0 = Normal (default), Mechanical Counter or Stepper Motor Format
1 = Alternate Pulse Format, also MECH = 1
VHPF (IHPF)
Enables the high-pass filter on the voltage (current) channel.
0 = High-pass filter disabled (default)
1 = High-pass filter enabled
DS661F1
25
CS5461A
iCPU
Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals
are sampled, the logic driven by CPUCLK should not be active during the sample edge.
0 = Normal operation (default)
1 = Minimize noise when CPUCLK is driving rising-edge logic
K[3:0]
Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal
clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range between 1 and 16. A value of “0000” will set K to 16 (not zero). K = 1 at reset.
6.2 Current and Voltage DC Offset Register ( IDCoff ,VDCoff )
Address: 1 (Current DC Offset); 3 (Voltage DC Offset)
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
Default = 0x000000
The DC Offset registers (IDCoff,VDCoff) are initialized to 0.0 on reset. When DC Offset calibration is performed, the
register is updated with the DC offset measured over a computation cycle. DRDY will be asserted at the end of
the calibration. This register may be read and stored for future system offset compensation. The value is represented in two's complement notation and in the range of -1.0 ≤ IDCoff, VDCoff < 1.0, with the binary point to the
right of the MSB.
6.3 Current and Voltage Gain Register ( Ign ,Vgn )
Address: 2 (Current Gain); 4 (Voltage Gain)
MSB
21
LSB
20
2-1
2-2
2-3
2-4
2-5
2-6
.....
2-16
2-17
2-18
2-19
2-20
2-21
2-22
Default = 0x400000 = 1.000
The gain registers (Ign,Vgn) are initialized to 1.0 on reset. When either a AC or DC Gain calibration is performed,
the register is updated with the gain measured over a computation cycle. DRDY will be asserted at the end of
the calibration. This register may be read and stored for future system gain compensation. The value is in the
range 0.0 ≤ Ign,Vgn < 3.9999, with the binary point to the right of the second MSB.
6.4 Cycle Count Register
Address: 5
MSB
223
LSB
222
221
220
219
218
217
216
.....
26
25
24
23
22
21
20
Default = 0x000FA0 = 4000
Cycle Count, denoted as N, determines the length of one computation cycle. During continuous conversions,
the computation cycle frequency is (MCLK/K)/(1024∗N). A one second computational cycle period occurs when
MCLK = 4.096 MHz, K = 1, and N = 4000.
26
DS661F1
CS5461A
6.5 PulseRateE1,2 Register
Address: 6
MSB
218
LSB
217
216
215
214
213
212
211
.....
21
20
2-1
2-2
2-3
2-4
2-5
Default = 0xFA000 = 32000.00 Hz
PulseRateE1,2 sets the frequency of the E1 and/or E2 pulses. The smallest valid frequency is 2-4 with 2-5 incremental steps. A pulse rate higher than (MCLK/K)/8 will result in a pulse rate setting of (MCLK/K)/8. The value
is represented in unsigned notation, with the binary point to the right of bit 5.
6.6 Instantaneous Current, Voltage and Power Registers ( I , V , P )
Address: 7 (Instantaneous Current); 8 (Instantaneous Voltage); 9 (Instantaneous Power)
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
I and V contain the instantaneous measured values for current and voltage, respectively. The instantaneous
voltage and current samples are multiplied to obtain Instantaneous Power (P). The value is represented in two's
complement notation and in the range of -1.0 ≤ I, V, P < 1.0, with the binary point to the right of the MSB.
6.7 Active (Real) Power Registers ( PActive )
Address: 10
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
The instantaneous power is averaged over each computation cycle (N conversions) to compute Active Power
(PActive). The value is represented in two's complement notation and in the range of -1.0 ≤ PActive< 1.0, with the
binary point to the right of the MSB.
6.8 IRMS and VRMS Registers ( IRMS , VRMS )
Address: 11 (IRMS); 12 (VRMS)
MSB
2-1
LSB
2-2
2-3
2-4
2-5
2-6
2-7
2-8
.....
2-18
2-19
2-20
2-21
2-22
2-23
2-24
IRMS and VRMS contain the Root Mean Square (RMS) value of I and V, calculated over each computation cycle.
The value is represented in unsigned binary notation and in the range of 0.0 ≤ IRMS, VRMS < 1.0, with the binary
point to the left of the MSB.
6.9 Power Offset Register ( Poff )
Address: 14
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
Default = 0x000000
Power Offset (Poff) is added to the instantaneous power being accumulated in the Pactive register and can be
used to offset contributions to the energy result that are caused by undesirable sources of energy that are inherent in the system. The value is represented in two's complement notation and in the range of -1.0 ≤ Poff < 1.0,
with the binary point to the right of the MSB.
DS661F1
27
CS5461A
6.10 Status Register and Mask Register ( Status , Mask )
Address: 15 (Status); 26 (Mask)
23
DRDY
22
21
20
CRDY
19
18
17
IOR
16
VOR
15
14
IROR
13
VROR
12
EOR
11
10
9
8
7
TUP
6
TOD
5
4
VOD
3
IOD
2
LSD
1
VSAG
0
IC
Default =
0x000001 (Status Register), 0x000000 (Mask Register)
The Status Register indicates status within the chip. In normal operation, writing a '1' to a bit will cause the bit
to reset. Writing a '0' to a bit will not change it’s current state.
The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in a Mask bit will allow the
corresponding bit in the Status Register to activate the INT pin when the status bit is asserted.
DRDY
Data Ready. During conversions, this bit will indicate the end of computation cycles. For calibrations, this bit indicates the end of a calibration sequence.
CRDY
Conversion Ready. Indicates a new conversion is ready. This will occur at the output word rate.
IOR
Current Out of Range. Set when the Instantaneous Current Register overflows.
VOR
Voltage Out of Range. Set when the Instantaneous Voltage Register overflows.
IROR
IRMS Out of Range. Set when the IRMS Register overflows.
VROR
VRMS Out of Range. Set when the VRMS Register overflows.
EOR
Energy Out of Range. Set when PACTIVE overflows.
TUP
Temperature Updated. Indicates the Temperature Register has updated.
TOD
Modulator oscillation detected on the temperature channel. Set when the modulator oscillates
due to an input above full scale.
VOD (IOD)
Modulator oscillation detected on the voltage (current) channel. Set when the modulator oscillates due to an input above full scale. The level at which the modulator oscillates is significantly
higher than the voltage (current) channel’s differential input voltage range.
Note:
LSD
Low Supply Detect. Set when the voltage at the PFMON pin falls below the low-voltage threshold (PMLO), with respect to AGND pin. The LSD bit cannot be reset until the voltage at PFMON
pin rises back above the high-voltage threshold (PMHI).
VSAG
Indicates a voltage sag has occurred. See Section 5.5 Voltage Sag-detect Feature on page 19.
IC
28
The IOD and VOD bits may be ‘falsely’ triggered by very brief voltage spikes from the
power line. This event should not be confused with a DC overload situation at the inputs, when the IOD and VOD bits will re-assert themselves even after being cleared,
multiple times.
Invalid Command. Normally logic 1. Set to logic 0 if an invalid command is received or the Status Register has not been successfully read.
DS661F1
CS5461A
6.11 Current and Voltage AC Offset Register ( VACoff , IACoff )
Address: 16 (Current AC Offset); 17 (Voltage AC Offset)
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
Default = 0x000000
The AC Offset Registers (VACoff, IACoff) are initialized to zero on reset, allowing for uncalibrated normal operation.
AC Offset Calibration updates these registers. This sequence lasts approximately (6N + 30) ADC cycles (where
N is the value of the Cycle Count Register). DRDY will be asserted at the end of the calibration. These values
may be read and stored for future system AC offset compensation. The value is represented in two's complement notation and in the range of -1.0 ≤ VACoff, IACoff < 1.0, with the binary point to the right of the MSB.
6.12 PulseRateE3 Register
Address: 18
MSB
218
LSB
217
216
215
214
213
212
211
.....
21
20
2-1
2-2
2-3
2-4
2-5
Default = 0xFA0000 = 32000.00 Hz
PulseRateE3 sets the frequency of the E3 pulses. The register’s smallest valid frequency is 2-4 with 2-5 incremental steps. A pulse rate higher than (MCLK/K)/8 will result in a pulse rate setting of (MCLK/K)/8. The value
is represented in unsigned notation, with the binary point to the right of bit #5.
6.13 Temperature Register ( T )
Address: 19
MSB
-(27)
LSB
26
25
24
23
22
21
20
.....
2-10
2-11
2-12
2-13
2-14
2-15
2-16
T contains measurements from the on-chip temperature sensor. Measurements are performed during continuous conversions, with the default the Celsius scale (oC). The value is represented in two's complement notation
and in the range of -128.0 ≤ T < 128.0, with the binary point to the right of the eighth MSB.
6.14 System Gain Register ( SYSGain )
Address: 20
MSB
-(21)
LSB
20
2-1
2-2
2-3
2-4
2-5
2-6
.....
2-16
2-17
2-18
2-19
2-20
2-21
2-22
Default = 0x500000 = 1.25
System Gain (SYSGain) determines the one’s density of the channel measurements. Small changes in the modulator due to temperature can be fine adjusted by changing the system gain. The value is represented in two's
complement notation and in the range of -2.0 < SYSGain < 2.0, with the binary point to the right of the second
MSB.
DS661F1
29
CS5461A
6.15 Pulsewidth Register ( PW )
Address: 21
MSB
223
LSB
222
221
220
219
218
217
216
.....
26
25
24
23
22
21
20
Default = 0x000200 = 512 sample periods
PW sets the pulsewidth of E1 and E2 pulses in Alternate Pulse and Mechanical Counter format. The width is a
function of number of sample periods. The default corresponds to a pulsewidth of
512 samples/[(MCLK/K)/1024] = 128 msec with MCLK = 4.096 MHz and K = 1. The value is represented in unsigned notation.
6.16 Voltage Sag Duration Register ( VSAGDuration )
Address: 23
MSB
0
LSB
222
221
220
219
218
217
216
.....
26
25
24
23
22
21
20
Default = 0x000000
Voltage Sag Duration (VSAGDuration) defines the number of instantaneous voltage measurements utilized to determine a voltage level sag event (VSAGLEVEL). Setting this register to zero will disable Voltage Sag-detect. The
value is represented in unsigned notation.
6.17 Voltage Sag Level Register ( VSAGLevel )
Address: 24
MSB
0
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
Default = 0x000000
Voltage Sag Level (VSAGLevel) defines the voltage level that the magnitude of input samples, averaged over the
sag duration, must fall below in order to register a sag condition. This value is represented in unsigned notation
and in the range of 0 ≤ VSAGLevel < 1.0, with the binary point to the right of the MSB.
30
DS661F1
CS5461A
6.18 Control Register
Register Address: 28
23
22
21
20
19
18
17
16
15
14
13
12
11
10
FAC
9
EAC
8
STOP
7
6
MECH
5
4
INTOD
3
2
NOCPU
1
NOOSC
0
STEP
Default = 0x000000
FAC
Determines if anti-creep is enabled for pulse output E3.
0 = Disable anti-creep (default)
1 = Enabled anti-creep
EAC
Determines if anti-creep is enabled for pulse output E1 and/or E2.
0 = Disable anti-creep (default)
1 = Enabled anti-creep
STOP
Terminates the auto-boot sequence.
0 = Normal (default)
1 = Stop sequence
MECH
Mechanical Counter Format, E1 or E2 becomes active low pulses with an output frequency proportional to the active power
0 = Normal (default) or Stepper Motor Format
1 = Mechanical Counter Format, also ALT = 0
INTOD
Converts INT output pin to an open drain output.
0 = Normal (default)
1 = Open drain
NOCPU
Saves power by disabling the CPUCLK pin.
0 = Normal (default)
1 = Disables CPUCLK
NOOSC
Saves power by disabling the crystal oscillator.
0 = Normal (default)
1 = Oscillator circuit disabled
STEP
Stepper Motor Format, E1 and E2 becomes active low pulses with an output frequency proportional to the active power
0 = Normal Format (default)
1 = Stepper Motor Format, also MECH = 0 and ALT = 0
DS661F1
31
CS5461A
6.19 Temperature Gain Register ( TGain )
Address: 29
MSB
26
LSB
25
24
23
22
21
20
2-1
.....
2-11
2-12
2-13
2-14
2-15
2-16
2-17
Default = 0x34E2E7 = 26.443169
Sets the temperature channel gain. Temperature gain (TGain) is utilized to convert from one temperature scale
to another. The Celsius scale (oC) is the default. Values are represented in unsigned notation and in the range
of 0 ≤ TGain < 128, with the binary point to the right of the seventh MSB.
6.20 Temperature Offset Register ( Toff )
Address: 30
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
Default = 0xF3E7D0 = -0.094488
Temperature offset (Toff) is used to remove the temperature channel’s offset at the zero degree reading. Values
are represented in two's complement notation and in the range of -1.0 ≤ Toff < 1.0, with the binary point to the
right of the MSB.
6.21 Apparent Power Register ( S )
Address: 31
MSB
2-1
LSB
2-2
2-3
2-4
2-5
2-6
2-7
2-8
.....
2-18
2-19
2-20
2-21
2-22
2-23
2-24
Apparent power (S) is the product of the VRMS and IRMS. The value is represented in unsigned binary notation
and in the range of 0.0 ≤ S < 1.0, with the binary point to the left of the MSB.
32
DS661F1
CS5461A
7. SYSTEM CALIBRATION
7.1 Channel Offset and Gain Calibration
The CS5461A provides digital DC offset and gain compensation that can be applied to the instantaneous voltage and current measurements, and AC offset
compensation to the voltage and current RMS calculations.
Since the voltage and current channels have independent offset and gain registers, system offset and/or
gain can be performed on either channel without the
calibration results from one channel affecting the other.
calibrations, the sequence takes at least 6N + 30 ADC
cycles to complete, (about 6 computation cycles). As N
is increased, the accuracy of calibration results will increase.
7.1.2 Offset Calibration Sequence
For DC- and AC offset calibrations, the VIN± pins of the
voltage and IIN± pins of the current channels should be
connected to their ground-reference level.
See Figure 10.
External
Connections
The computational flow of the calibration sequences are
illustrated in Figure 9. The flow applies to both the voltage channel and current channel.
+
0V +-
7.1.1 Calibration Sequence
The CS5461A must be operating in its active state and
ready to accept valid commands. Refer to Section 5.13
Commands on page 22. The calibration algorithms are
dependent on the value N in the Cycle Count Register
(see Figure 9). Upon completion, the results of the calibration are available in their corresponding register. The
DRDY bit in the Status Register will be set. If the DRDY
bit is to be output on the INT pin, then DRDY bit in the
Mask Register must be set. The initial values stored in
the AC gain and offset registers do affect the calibration
results.
7.1.1.1 Duration of Calibration Sequence
The value of the Cycle Count Register (N) determines
the number of conversions performed by the CS5461A
during a given calibration sequence. For DC offset and
gain calibrations, the calibration sequence takes at least
N + 30 conversion cycles to complete. For AC offset
CM +-
+
AIN+
XGAIN
-
AIN-
-
Figure 10. System Calibration of Offset.
The AC offset registers must be set to the default
(0x000000).
7.1.2.1 DC Offset Calibration Sequence
Channel gain should be set to 1.0 when performing DC
offset calibration. Initiate a DC offset calibration. The DC
offset registers are updated with the negative of the average of the instantaneous samples taken over a computational cycle. Upon completion of the DC offset
calibration the DC offset is stored in the corresponding
DC offset register. The DC offset value will be added to
each instantaneous measurement to cancel out the DC
to V*, I* Registers
In
Modulator
Filter
+
N
+
X
X
+
DC Offset*
Gain*
Inverse
-1
Σ
÷N
+
√
+
+
VRMS*, IRMS*
Registers
N
Σ
AC Offset*
÷N
-1
X
X
0.6
RMS
* Denotes readable/writable register
Figure 9. Calibration Data Flow
DS661F1
33
CS5461A
component present in the system during conversion
commands.
7.1.2.2 AC Offset Calibration Sequence
Corresponding offset registers IACoff and/or VACoff
should be cleared prior to initiating AC offset calibrations. Initiate an AC offset calibration. The AC offset registers are updated with an offset value that reflects the
RMS output level. Upon completion of the AC offset calibration the AC offset is stored in the corresponding AC
offset register. The AC offset register value is subtracted from each successive VRMS and IRMS calculation.
A typical rms calibration value which allows for reasonable over-range margin would be 0.6 or 60% of the voltage and current channel’s maximum input voltage level.
Two examples of AC gain calibration and the updated
digital output codes of the channel’s instantaneous data
registers are shown in Figures 12 and 13. Figure 13
Before AC Gain Calibration (Vgn Register = 1)
Sinewave
+
XG AIN
CM
+
-
-0.92
-1.0000...
VRMS Register = 230/√2 x 1/250 ≈ 0.65054
After AC Gain Calibration (Vgn Register changed to approx. 0.9223)
Sinewave
IN-
Instantaneous Voltage
Register Values
-250 mV
External
Connections
IN+
0.92
-230 mV
When performing gain calibrations, a reference signal
should be applied to the VIN± pins of the voltage and
IIN± pins of the current channels that represents the desired maximum signal level. Figure 11 shows the basic
setup for gain calibration.
R eference
+
Signal
-
0.9999...
230 mV
INPUT
0V
SIGNAL
7.1.3 Gain Calibration Sequence
+
250 mV
250 mV
0.92231
230 mV
0.84853
INPUT
0V
SIGNAL
Instantaneous Voltage
Register Values
-230 mV
-0.84853
-250 mV
-0.92231
VRMS Register = 0.600000
-
Figure 12. Example of AC Gain Calibration
Figure 11. System Calibration of Gain
For gain calibrations, there is an absolute limit on the
RMS voltage levels that are selected for the gain-calibration input signals. The maximum value that the gain
registers can attain is 4. Therefore, if the signal level of
the applied input is low enough that it causes the
CS5461A to attempt to set either gain register higher
than 4, the gain calibration result will be invalid and all
CS5461A results obtained while performing measurements will be invalid.
If the channel gain registers are initially set to a gain other then 1.0, AC gain calibration should be used.
7.1.3.1 AC Gain Calibration Sequence
The corresponding gain register should be set to 1.0,
unless a different initial gain value is desired. Initiate an
AC gain calibration. The AC gain calibration algorithm
computes the RMS value of the reference signal applied
to the channel inputs. The RMS register value is then divided into 0.6 and the quotient is stored in the corresponding
gain
register.
Each
instantaneous
measurement will be multiplied by its corresponding AC
gain value.
34
Before AC Gain Calibration (Vgain Register = 1)
250 mV
0.9999...
230 mV
0.92
DC Signal
Instantaneous Voltage
Register Values
INPUT 0 V
SIGNAL
-1.0000...
-250 mV
230 = 0.92
VRMS Register = 250
After AC Gain Calibration (Vgain Register changed to approx. 0.65217)
250 mV
0.65217
230 mV
0.6000
DC Signal
INPUT
0V
SIGNAL
Instantaneous Voltage
Register Values
-0.65217
-250 mV
VRMS Register = 0.600000
Figure 13. Another Example of AC Gain Calibration
shows that a positive (or negative), DC-level signal can
be used even though an AC gain calibration is being exDS661F1
CS5461A
ecuted. However, an AC signal should not be used for
DC gain calibration.
7.1.3.2 DC Gain Calibration Sequence
Initiate a DC gain calibration. The corresponding gain
register is restored to default (1.0). The DC gain calibration algorithm averages the channel’s instantaneous
measurements over one computation cycle (N samples). The average is then divided into 1.0 and the quotient is stored in the corresponding gain register
After the DC gain calibration, the instantaneous register
will read at full-scale whenever the DC level of the input
signal is equal to the level of the DC calibration signal
applied to the inputs during the DC gain calibration.The
HPF option should not be enabled if DC gain calibration
is utilized.
7.1.4 Order of Calibration Sequences
1. If the HPF option is enabled, then any dc component that may be present in the selected signal path
will be removed and a DC offset calibration is not required. However, if the HPF option is disabled the
DC offset calibration sequence should be performed.
When using high-pass filters, it is recommended
that the DC offset register for the corresponding
channel be set to zero. When performing DC offset
calibration, the corresponding gain channel should
be set to one.
2. If an ac offset exist, in the VRMS or IRMS calculation,
then the AC offset calibration sequence should be
performed.
3. Perform the gain calibration sequence.
4. Finally, if an AC offset calibration was performed
(step 2), then the AC offset may need to be adjusted
to compensate for the change in gain (step 3). This
DS661F1
can be accomplished by restoring zero to the AC
offset register and then perform an AC offset calibration sequence. The adjustment could also be
done by multiplying the AC offset register value that
was calculated in step 2 by the gain calculated in
step 3 and updating the AC offset register with the
product.
7.2 Phase Compensation
The CS5461A is equipped with phase compensation to
cancel out phase shifts introduced by the measurement
element. Phase Compensation is set by bits PC[6:0] in
the Configuration Register.
The default value of PC[6:0] is zero. With
MCLK = 4.096 MHz and K = 1, the phase compensation has a range of ±2.8 degrees when the input signals
are 60 Hz. Under these conditions, each step of the
phase compensation register (value of one LSB) is approximately 0.04 degrees. For values of MCLK other
than 4.096 MHz, the range and step size should be
scaled by 4.096 MHz/(MCLK/K). For power-line frequencies other than 60Hz, the values of the range and
step size of the PC[6:0] bits can be determined by converting the above values from angular measurement
into time-domain (seconds), and then computing the
new range and step size (in degrees) with respect to the
new line frequency.
7.3 Active Power Offset
The Power Offset Register can be used to offset system
power sources that may be resident in the system, but
do not originate from the power-line signal. These
sources of extra energy in the system contribute undesirable and false offsets to the power and energy measurement results. After determining the amount of stray
power, the Power Offset Register can be set to cancel
the effects of this unwanted energy.
35
CS5461A
8. AUTO-BOOT MODE USING E2PROM
When the CS5461A MODE pin is asserted (logic 1), the
CS5461A auto-boot mode is enabled. In auto-boot
mode, the CS5461A downloads the required commands and register data from an external serial
E2PROM, allowing the CS5461A to begin performing
energy measurements.
8.1 Auto-Boot Configuration
operation, when the auto-boot initialization sequence is
running. Any of the valid commands can be used.
8.2 Auto-Boot Data for E2PROM
Below is an example code set for an auto-boot sequence. This code is written into the E2PROM by the user. The serial data for such a sequence is shown below
in single-byte, hexidecimal notation:
A typical auto-boot serial connection between the
CS5461A and a E2PROM is illustrated in Figure 14. In
auto-boot mode, the CS5461A’s CS and SCLK are configured as outputs. The CS5461A asserts CS, provides
a clock on SCLK, and sends a read command to the
E2PROM on SDO. The CS5461A reads the user-specified commands and register data presented on the SDI
pin. The E2PROM’s programmed data is utilized by the
CS5461A to change the designated registers’ default
values and begin registering energy.
VD+
EOUT1
EOUT2
5K
Mech. Counter
or
Stepper Motor
EEPROM
CS5461A
SCK
SCLK
MODE
- 40 00 00 61
Write Configuration Register, turn high-pass filters
on, set K=1.
- 44 7F C4 A9
Write value of 0x7FC4A9 to Current Gain
Register.
- 48 FF B2 53
Write value of 0xFFB253 to Voltage Gain
Register.
- 4C 00 7D 00
Set PulseRateE1,2 Register to 1000 Hz.
- 74 00 00 04
Unmask bit #2 (LSD) in the Mask Register).
- E8
Start continuous conversions
- 78 00 01 00
Write STOP bit to Control Register, to terminate
auto-boot initialization sequence.
SDI
SO
SDO
SI
5K
CS
CS
8.3 Suggested E2PROM Devices
Connector to Calibrator
Figure 14. Typical Interface of E2PROM to CS5461A
Figure 14 also shows the external connections that
would be made to a calibrator device, such as a PC or
custom calibration board. When the metering system is
installed, the calibrator would be used to control calibration and/or to program user-specified commands and
calibration values into the E2PROM. The user-specified
commands/data will determine the CS5461A’s exact
36
Several industry-standard, serial E2PROMs that will
successfully run auto-boot with the CS5461A are listed
below:
•
•
•
Atmel AT25010, AT25020 or AT25040
National Semiconductor NM25C040M8 or NM25020M8
Xicor X25040SI
These types of serial E2PROMs expect a specific 8-bit
command (00000011) in order to perform a memory
read. The CS5461A has been hardware programmed to
transmit this 8-bit command to the E2PROM at the beginning of the auto-boot sequence.
DS661F1
CS5461A
9. BASIC APPLICATION CIRCUITS
Figure 16 shows the same single-phase, two-wire system with complete isolation from the power lines. This
isolation is achieved using three transformers: a general
purpose transformer to supply the on-board DC power;
a high-precision, low-impedance voltage transformer
with very little roll-off/phase-delay, to measure voltage;
and a current transformer to sense the line current.
Figure 15 shows the CS5461A configured to measure
power in a single-phase, 2-wire system while operating
in a single-supply configuration. In this diagram, a shunt
resistor is used to sense the line current and a voltage
divider is used to sense the line voltage. In this type of
shunt resistor configuration, the common-mode level of
the CS5461A must be referenced to the line side of the
power line. This means that the common-mode potential of the CS5461A will track the high-voltage levels, as
well as low-voltage levels, with respect to earth ground
potential. Isolation circuitry is required when an earthground-referenced communication interface is connected.
Figure 17 shows a single-phase, 3-wire system. In
many 3-wire residential power systems within the United States, only the two line terminals are available (neutral is not available). Figure 18 shows the CS5461A
configured to meter a three-wire system with no neutral
available.
10 kΩ
5 kΩ
120 VAC
N
L
500 Ω
10 Ω
500
470 µF
470 nF
0.1 µF
0.1 µF
14
VA+
3
VD+
CS5461A
9
CVCVdiff
R1
R V-
10
VIN-
2
1
4.096 MHz
RESET
C Idiff
CS
SDI
C I+
16
12
11
0.1 µF
Note:
Indicates common (floating) return.
XIN
Optional
Clock
Source
24
IIN-
C I-
R Shunt
R I+
17
CV+
15
R I-
PFMON
CPUCLK
XOUT
IIN+
SDO
SCLK
INT
VREFIN
VREFOUT
AGND
13
E2
E1
19
7
23
6
5
ISOLATION
R2
VIN+
Serial
Data
Interface
20
22
21
DGND
4
Mech. Counter
or
Stepper Motor
Figure 15. Typical Connection Diagram (Single-phase, 2-wire – Direct Connect to Power Line)
DS661F1
37
CS5461A
10 kΩ
5 kΩ
120 VAC
N
L
Voltage
Transformer
200 Ω
10 Ω
200 Ω
0.1 µF
0.1µF
12 VAC
14
VA+
200µF
12 VAC
3
VD+
CS5461A
M:1
9
1kΩ
RV+
CVdiff
RV-
1kΩ
10
Low Phase-Shift
Potential Transformer
RI-
N:1
15
1kΩ
XIN
VIN-
IIN-
RESET
1kΩ
16
RI+
12
11
0.1 µF
4.096 MHz
Optional
Clock
Source
24
19
7
CS
23
SDI
6
SDO
5
SCLK
20
INT
CIdiff
RBurden
Current
Transformer
17
PFMON
2
CPUCLK
1
XOUT
VIN+
IIN+
VREFIN
VREFOUT
Serial
Data
Interface
22
E2
21
E1
DGND
4
AGND
13
Mech. Counter
or
Stepper Motor
Figure 16. Typical Connection Diagram (Single-phase, 2-wire – Isolated from Power Line)
240 VAC
120 VAC
L1
5 kΩ
120 VAC
N
L2
500 Ω
500 Ω
10 Ω
470 µF
470 nF
0.1 µF
Earth
Ground
R2
0.1 µF
14
VA+
3
VD+
CS5461A
9
R3
10 kΩ
17
PFMON
2
CPUCLK
1
XOUT
VIN+
CIdiff
R4
R1
10
VIN16 IIN+
1kΩ
XIN
R I+
RESET
RBurden
C Idiff
1kΩ
15
R I-
0.1 µF
IIN-
12
VREFIN
11
VREFOUT
AGND
13
4.095 MHz
Optional
Clock
Source
24
19
7
CS
23
SDI
6
SDO
5
SCLK
20
INT
E2
E1
Serial
Data
Interface
22
21
DGND
4
Mech. Counter
or
Stepper Motor
Figure 17. Typical Connection Diagram (Single-phase, 3-wire)
38
DS661F1
CS5461A
5 kΩ
240 VAC
L1
L2
500 Ω
1 kΩ
10 Ω
470 µF
235 nF
10 kΩ
0.1 µF
0.1 µF
14
VA+
3
VD+
CS5461A
9
CV+
R2
CI+
R V-
CVdiff
10
16
1kΩ
VINIIN+
17
PFMON
2
CPUCLK
1
XOUT
XIN
4.096 MHz
Optional
Clock
Source
24
R I+
RBurden
RESET
CIdiff
1kΩ
15
R I-
0.1 µF
Note:
Indicates common (floating) return.
IIN-
12
VREFIN
11
VREFOUT
AGND
13
CS
SDI
SDO
SCLK
INT
E2
E1
19
7
23
6
5
ISOLATION
R1
VIN+
Serial
Data
Interface
20
22
21
DGND
4
Mech. Counter
or
Stepper Motor
Figure 18. Typical Connection Diagram (Single-phase, 3-wire – No Neutral Available)
DS661F1
39
CS5461A
10.PACKAGE DIMENSIONS
24L SSOP PACKAGE DRAWING
N
D
E11
A2
E
e
b2
SIDE VIEW
A
∝
A1
L
END VIEW
SEATING
PLANE
1 2 3
TOP VIEW
DIM
A
A1
A2
b
D
E
E1
e
L
∝
MIN
-0.002
0.064
0.009
0.311
0.291
0.197
0.022
0.025
0°
INCHES
NOM
-0.006
0.068
-0.323
0.307
0.209
0.026
0.03
4°
MAX
0.084
0.010
0.074
0.015
0.335
0.323
0.220
0.030
0.041
8°
MIN
-0.05
1.62
0.22
7.90
7.40
5.00
0.55
0.63
0°
MILLIMETERS
NOM
-0.13
1.73
-8.20
7.80
5.30
0.65
0.75
4°
NOTE
MAX
2.13
0.25
1.88
0.38
8.50
8.20
5.60
0.75
1.03
8°
2,3
1
1
JEDEC #: MO-150
Controlling Dimension is Millimeters.
Notes: 3. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch
and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.
Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in
excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more
than 0.07 mm at least material condition.
5. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
4.
40
DS661F1
CS5461A
11. ORDERING INFORMATION
Model
CS5461A-IS
CS5461A-ISZ (lead free)
Temperature
Package
-40 to +85 °C
24-pin SSOP
12. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number
Peak Reflow Temp
MSL Rating*
Max Floor Life
CS5461A-IS
240 °C
2
365 Days
CS5461A-ISZ (lead free)
260 °C
3
7 Days
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
13. REVISION HISTORY
Revision
Date
Changes
A1
DEC 2004
Advance Release
PP1
FEB 2005
Initial Preliminary Release
F1
AUG 2005
Final version Updated with most-recent characterization data. MSL data added.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
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to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
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does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
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SPI is a trademark of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
DS661F1
41