TI1 DS90C3202 3.3v 8 mhz to 135 mhz dual fpd-link receiver Datasheet

DS90C3202
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SNLS191D – APRIL 2005 – REVISED APRIL 2013
DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver
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FEATURES
DESCRIPTION
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The DS90C3202 is a 3.3V single/dual FPD-Link 10bit color receiver is designed to be used in Liquid
Crystal Display TVs, LCD Monitors, Digital TVs, and
Plasma Display Panel TVs. The DS90C3202 is
designed to interface between the digital video
processor and the display device using the lowpower, low-EMI LVDS (Low Voltage Differential
Signaling) interface. The DS90C3202 converts up to
ten LVDS data streams back into 70 bits of parallel
LVCMOS/LVTTL data. The receiver can be
programmed with rising edge or falling edge clock.
Optional wo-wire serial programming allows fine
tuning in development and production environments.
With an input clock at 135 MHz, the maximum
transmission rate of each LVDS line is 945 Mbps, for
an aggregate throughput rate of 9.45 Gbps (945
Mbytes/s). This allows the dual 10-bit LVDS Receiver
to support resolutions up to HDTV.
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2
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Up to 9.45 Gbit/s data throughput
8 MHz to 135 MHz input clock support
Supports up to QXGA panel resolutions
Supports HDTV panel resolutions and frame
rates up to 1920 x 1080p
LVDS 30-bit, 24-bit or 18-bit color data inputs
Supports single pixel and dual pixel interfaces
Supports spread spectrum clocking
Two-wire serial communication interface
Programmable clock edge and control strobe
select
Power down mode
+3.3V supply voltage
128-pin TQFP Package
Compliant to TIA/EIA-644-A-2001 LVDS
Standard
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
DS90C3202
SNLS191D – APRIL 2005 – REVISED APRIL 2013
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Block Diagram
7
RXOA-/+
RXOA[6:0]
7
RXOB-/+
RXOB[6:0]
7
LVDS INPUT
RXOD-/+
RXOE-/+
RXEA-/+
RXEB-/+
LVCMOS/LVTTL OUTPUT <69:0>
RXOC[6:0]
LVDS SERIAL-TO-LVTTL PARALLEL
RXOC-/+
7
RXOD[6:0]
7
RXOE[6:0]
7
RXEA[6:0]
7
RXEB[6:0]
7
RXEC-/+
RXEC[6:0]
7
RXED-/+
RXED[6:0]
7
RXEE-/+
RXEE[6:0]
PLL
RCLKIN-/+
RCLKOUT
RFB
PWDNB
MODE0
MODE1
S2CLK
S2DAT
Figure 1. Receiver Block Diagram
Typical Application Diagram
Host
(PC, Graphics Board, Video Processor)
LVDS
Display
(LCD Monitor, LCD TV, Digital TV)
5 Pairs
DE
DE
Pixel Data
Pixel Data
5 Pairs
Clock
Video
Source
HSYNC
VSYNC
DS90C3201
FPD-Link
Transmitter
DS90C3202
FPD-Link
Receiver
LVDS Clock
Clock
Digital
Display
HSYNC
VSYNC
2-Wire Serial
Interface
Figure 2. LCD Panel Application Diagram
Functional Description
The DS90C3201 and DS90C3202 are a dual 10-bit color Transmitter and Receiver FPD-Link chipset designed to
transmit data at clocks speeds from 8 to 135 MHz. DS90C3201 and DS90C3202 are designed to interface
between the digital video processor and the display using a LVDS interface. The DS90C3201 transmitter
serializes 2 channels of video data (10-bit each for RGB for each channel, totaling 60 bits) and control signals
(HSYNC, VSYNC, DE and two user-defined signals) along with clock signal to 10 channels of LVDS signals and
transmits them. The DS90C3202 receiver converts 10 channels of LVDS signals into parallel signals and outputs
2
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2 channels of video data (10-bit each for RGB for each channel, totaling 60 bits) and control signals (HSYNC,
VSYNC, DE and two user-defined signals) along with clock signal. The dual high speed LVDS channels supports
single pixel in-single pixel out and dual pixel in-dual pixel out transmission modes. The FPD-Link chipset is
suitable for a variety of display applications including LCD Monitors, LCD TV, Digital TV, and DLP TV, and
Plasma Display Panels.
Using a true 10-bit color depth system, the 30-bit RGB color produces over 1.07 billion colors to represent High
Definition (HD) displays in their most natural color, surpassing the maximum 16.7 million colors achieved by 6/8bit color conventionally used for large-scale LCD televisions and LCD monitors.
LVDS RECEIVER
The LVDS Receiver receives input RGB video data and control signal timing.
SELECTABLE OUTPUT DATA STROBE
The Receiver output data edge strobe can be latched on the rising or falling edges of clock signal. The dedicated
RFB pin is used to program output strobe select on the rising edge of RCLK or the falling edge of RCLK.
2-WIRE SERIAL COMMUNICATION INTERFACE
Optional Two-Wire serial interface programming allows fine tuning in development and production environments.
The Two-Wire serial interface provides several capabilities to reduce EMI and to customize output timing. These
capabilities are selectable/programmable via Two-Wire serial interface: Programmable Skew Rates, Progress
Turn On Function, Input/Output Channel Control.
PROGRAMMABLE SKEW RATES
Programmable edge rates allow the LVCMOS/LVTTL Data and Clock outputs to be adjusted for better
impedance matching for noise and EMI reduction. The individual output drive control registers for Rx data out
and Rx clock out are programmable via Two-Wire serial interface.
PROGRESS TURN ON FUNCTION
Progress Turn On (PTO) function aligns the two output channels of LVCMOS/LVTLL in either a non-skew data
format (simultaneous switching) or a skewed data format (staggered). The skewed format delays the selected
channel data and staggers the outputs. This reduces the number of outputs switching simultaneously, which
lowers EMI radiation and minimizes ground bounce. Feature is controlled via Two-Wire serial interface.
INPUT/OUTPUT CHANNEL CONTROL
Full independent control for input/output channels can be disabled to minimize power supply line noise and
overall power dissipation. Feature is configured via Two-Wire serial interface
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1)
−0.3V to +4V
Supply Voltage (VDD)
LVCMOS/LVTTL Input Voltage
−0.3V to (VDD + 0.3V)
LVCMOS/LVTTL Output Voltage
−0.3V to (VDD + 0.3V)
LVDS Receiver Input Voltage
−0.3V to (VDD + 0.3V)
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Lead Temperature (Soldering, 10 seconds)
+260°C
Maximum Package Power Dissipation Capacity at 25°C
128 TQFP Package
1.4W
Package Derating
25.6mW/°C above +25°C
ESD Rating:
HBM, 1.5kΩ, 100pF
> 2 kV
EIAJ, 0Ω, 200pF
(1)
> 200 V
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Recommended Operating Conditions
Min
Supply Voltage (VDD)
Operating Free Air
Temperature (TA)
Nom
Max
Unit
3.15
3.3
3.6
V
0
+25
+70
°C
Supply Noise Voltage (VP-P)
±100
mVp-p
Receiver Input Range
0
VDD
V
Input Clock Frequency (f)
8
135
MHz
4
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Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CMOS/TTL DC SPECIFICATIONS (Rx outputs, control inputs and outputs)
VIH
High Level Input Voltage
2.0
VDD
V
VIL
Low Level Input Voltage
0
0.8
V
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
Rx clock out
IOH = −4 mA
Rx data out
IOH = −2 mA
Rx clock out
IOL = +4 mA
Rx data out
IOL = +2 mA
VCL
Input Clamp Voltage
ICL = −18 mA
IIN
Input Current
VIN = VDD
VIN = 0V
IOS
Output Short Circuit Current
2.4
V
0.4
−0.8
V
−1.5
V
+10
µA
−10
µA
VOUT = 0V
−120
mA
+100
mV
LVDS RECEIVER DC SPECIFICATIONS
VTH
Differential Input High Threshold VCM = +1.2V
VTL
Differential Input Low Threshold
VIN
Input Voltage Range (Singleended)
|VID|
Differential Input Voltage
VCM
Differential Common Mode
Voltage
IIN
Input Current
−100
mV
0
VDD
V
0.200
0.600
V
VDD−0.1
V
VIN = +2.4V, VDD = 3.6V
±10
µA
VIN = 0V, VDD = 3.6V
±10
µA
0.2
1.2
RECEIVER SUPPLY CURRENT
ICCRW
ICCRG
ICCRZ
Receiver Supply Current, Worst
Case
(Figure 4 , Figure 6)
CL = 8 pF,
f = 8 MHz
Worst Case Pattern,
f = 135 MHz
Default Register Settings
Receiver Supply Current,
Incremental Test Pattern
(Figure 5 , Figure 6)
CL = 8 pF,
f = 8 MHz
Worst Case Pattern,
f = 135 MHz
Default Register Settings
Receiver Supply Current, Power PDWNB = Low,
Down
Receiver Outputs stay low during
Powerdown mode,
Default Register Settings
65
130
mA
375
550
mA
55
120
mA
245
400
mA
2
mA
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Receiver Switching Characteristics (1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
CLHT
Parameter
Condition or
Reference
Min
Typ
Max
Unit
LVCMOS/LVTTL Low-to-High Transition Time, CL
= 8pF, (Figure 7) (2)
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
Rx clock out
1.45
2.10
ns
Rx data out
2.40
3.50
ns
LVCMOS/LVTTL High-to-Low Transition Time, CL
= 8pF, (Figure 7) (2)
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
Rx clock out
1.35
2.20
ns
Rx data out
2.40
3.60
ns
CLHT
Programmable
adjustment
LVCMOS/LVTTL Low-to-High Transition Time, CL
= 8pF, (Figure 7) (2)
Register addr 28d/1ch,
bit [2] (RCLK)=1b (Default),
bit [1] (RXE) =1b (Default),
bit [0] (RXO) =1b (Default)
Rx clock out
2.45
ns
Rx data out
3.40
ns
CHLT
Programmable
adjustment
LVCMOS/LVTTL High-to-Low Transition Time, CL
= 8pF, (Figure 7) (2)
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
Rx clock out
2.35
ns
Rx data out
3.40
ns
RCOP
RCLK OUT Period (Figure 13, Figure 14)
RCOH
RCLK OUT High Time (Figure 13 , Figure 14)
RCOL
RSRC
RHRC
RxOUT Hold to RCLK OUT (Figure 13 , Figure 14)
Register addr 29d/1dh [2:1]= 00b (Default)
RSRC/RHRC
Programmable
Adjustment
Register addr 29d/1dh [2:1] = 01b, (Figure 15, Figure 16)
RSRC increased from default by 1UI
RHRC decreased from default by 1UI
CHLT
(2)
8–135 MHz
7.4
T
125
ns
Rx clock out
0.4T
0.5T
0.6T
ns
RCLK OUT Low Time (Figure 13 , Figure 14)
Rx clock out
0.4T
0.5T
0.6T
ns
RxOUT Setup to RCLK OUT (Figure 13, Figure 14)
Register addr 29d/1dh [2:1]= 00b (Default)
(2) (3)
2.60
0.5T
ns
3.60
0.5T
ns
+1UI / -1UI
ns
(4)
-1UI / +1UI
ns
Register addr 29d/1dh [2:1] = 11b, (Figure 15 Figure 16)
RSRC increased from default by 2UI
RHRC decreased from default by 2UI
(4)
+2UI / -2UI
ns
Receiver Phase Lock Loop Set (Figure 8)
RPDD
Receiver Powerdown Delay (Figure 9)
RPDL
Receiver Propagation Delay — Latency (Figure 10)
RITOL
Receiver Input Tolerance
(Figure 12 Figure 18) (2) (4)
6
(4)
Register addr 29d/1dh [2:1] = 10b, (Figure 15 Figure 16)
RSRC decreased from default by 1UI
RHRC increased from default by 1UI
RPLLS
(1)
(2)
(3)
(4)
(2) (3)
VCM = 1.25V,
VID = 350mV
10
ms
100
ns
4*RCLK
ns
0.25
UI
Typical values are given for VDD = 3.3V and T A = +25°C.
Specification is ensured by characterization.
A Clock Unit Symbol (T) is defined as 1/ (Line rate of RCLK). E.g. For Line rate of RCLK at 85MHz, 1 T = 11.76ns
A Unit Interval (UI) is defined as 1/7th of an ideal clock period (RCLK/7). E.g. For an 11.76ns clock period (85MHz), 1 UI = 1.68ns
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Two-Wire Serial Communication Interface
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
400
kHz
fSC
S2CLK Clock Frequency
SC:LOW
Clock Low Period
RP = 4.7KΩ, CL = 50pF
1.5
SC:HIGH
Clock High Period
RP = 4.7KΩ, CL = 50pF
0.6
SCD:TR
S2CLK and S2DAT Rise Time
RP = 4.7KΩ, CL = 50pF
SCD:TF
S2CLK and S2DAT Fall Time
RP = 4.7KΩ, CL = 50pF
SU:STA
Start Condition Setup Time
RP = 4.7KΩ, CL = 50pF
0.6
us
HD:STA
Start Condition Hold Time
RP = 4.7KΩ, CL = 50pF
0.6
us
HD:STO
Stop Condition Hold Time
RP = 4.7KΩ, CL = 50pF
0.6
us
SC:SD
Clock Falling Edge to Data
RP = 4.7KΩ, CL = 50pF
0
us
SD:SC
Data to Clock Rising Edge
RP = 4.7KΩ, CL = 50pF
0.1
us
SCL:SD
S2CLK Low to S2DAT Data Valid
RP = 4.7KΩ, CL = 50pF
0.1
BUF
Bus Free Time
RP = 4.7KΩ, CL = 50pF
13
us
us
0.3
us
0.3
us
0.9
us
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AC Timing Diagrams
SCD:TF
SCD:TR
fSC
SC:LOW
SC:HIGH
|
S2CLK
HD:STO
HD:STA
|
S2DAT
Data in
|
SU:STA
SC:SD
|
SD:SC
|
S2DAT
Data out
SCL:SD
Figure 3. Two-Wire Serial Communication Interface Timing Diagram
Figure 4. “Worst Case” Test Pattern
TCLKIN
TXOA, TXEA
TXOB, TXEB
TXOC, TXEC
TXOD, TXED
TXOE, TXEE
Figure 5. Incremental Test Pattern
600
Worst Case
(max)
500
ICC (mA)
400
Worst Case
(typ)
300
200
100
Incr. Pattern
(max)
0
0
20
40
60
80
Incr. Pattern
(typ)
100 120 140 160
FREQUENCY (MHz)
Figure 6. Typical and Max ICC with Worse Case and Incremental Pattern
8
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AC Timing Diagrams (continued)
Figure 7. LVCMOS/LVTTL Output Load and Transition Times
2V
PWDNB
3.15V
VDD
| |
RPLLS
RCLK IN
2V
RCLKOUT
Figure 8. Receiver Phase Lock Loop Wake-up Time
1.5V
PWDNB
| | |
Low
RCLK IN
RPDD
RCLKOUT
Low
+
RCLKIN
+
Rx IN
-
Rx OUT
RPDL
1.5V
|
RCLKOUT
(RFB=1)
VDIFF =
0V
| | | | |
Figure 9. Powerdown Delay
Figure 10. Receiver Propagation Delay
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AC Timing Diagrams (continued)
RCLKOUT
RxOUT
RFB = 0
RFB = 1
Figure 11. RFB: LVTTL Level Programmable Strobe Select
Sampling
Window
Ideal Bit Start
RITOL
(Left)
Ideal Bit Stop
RITOL
(Right)
Ideal Strobe Position
tBIT
( )
2
tBIT
(1UI)
RITOL ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
Please see AN-1217 (SNLA053) for more details.
Cycle-to-cycle jitter is less than 100 ps (worse case estimate).
ISI is dependent on interconnect length; may be zero.
Figure 12. Receiver Input Tolerance and Sampling Window
RCOP
RCOH
RCOL
RFB=0
RCLK OUT
VDD/2
VDD/2
RFB=1
RSRC
RXOA,B,C,D,E[6:0]
RXEA,B,C,D,E[6:0]
RHRC
VDD/2
VDD/2
Register address 29d/1dh bit [2:1] = 00b
Figure 13. Receiver RSRC and RHRC Output Setup/Hold Time — PTO Disabled
10
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AC Timing Diagrams (continued)
RCOP
RCOL
RCOH
RFB=0
RCLK OUT
VDD/2
VDD/2
RFB=1
RXEB,D[6:0]
RXOA,C,E[6:0]
VDD/2
RXEA,C,E[6:0]
RXOB,D[6:0]
VDD/2
VDD/2
1/2 UI
1/2 UI
RegisterAddress 29d/1dh bit [2:1] = 00b
Figure 14. Receiver RSRC and RHRC Output Setup/Hold Time — PTO Enabled
RCOP
RCOL
RCOH
RFB=0
RCLK OUT
VDD/2
Balanced RSRC / RHRC
Register addr 29d/1dh bit[2:1]=00b (default)
VDD/2
RFB=1
RCLK OUT
RSRC
VDD/2
+1 UI
RCLK OUT
VDD/2
RSRC
RHRC
VDD/2
VDD/2
RSRC Decreased by 1UI, RHRC Increased by 1UI
Register addr 29d/1dh bit[2:1]=10b
VDD/2
+1 UI
VDD/2
+2 UI
RXOA,B,C,D,E[6:0]
RXEA,B,C,D,E[6:0]
RSRC Increased by 1UI, RHRC Decreased by 1UI
Register addr 29d/1dh bit[2:1]=01b
-1 UI
RHRC
RSRC
-1 UI
RCLK OUT
RHRC
VDD/2
RSRC Increased by 2UI, RHRC Decreased by 2UI
Register addr 29d/1dh bit[2:1]=11b
-2 UI
VDD/2
Figure 15. Receiver RSRC and RHRC Output Setup/Hold Time Adjustment — PTO Disabled
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AC Timing Diagrams (continued)
RCOP
RFB=0
RCLK OUT
Balanced RSRC / RHRC
Register addr 29d/1dh bit[2:1]=00b (default)
VDD/2
VDD/2
RFB=1
RCLK OUT
RCLK OUT
RCLK OUT
VDD/2
VDD/2
VDD/2
RXEB,D[6:0]
RXOA,C,E[6:0]
VDD/2
RXEA,C,E[6:0]
RXOB,D[6:0]
VDD/2
Additional +0.5 UI RSRC on
RXEA,C,E[6:0]; RXOB,D[6:0]
RSRC
RHRC
RHRC
RSRC
RSRC
VDD/2
RSRC Decreased by 1UI, RHRC Increased by 1 UI
Register addr 29d/1dh bit[2:1]=10b
VDD/2
VDD/2
RHRC
RSRC Increased by 1UI, RHRC Decreased by 1 UI
Register addr 29d/1dh bit[2:1]=01b
RSRC Increased by 2UI, RHRC Decreased by 2 UI
Register addr 29d/1dh bit[2:1]=11b
VDD/2
VDD/2
-0.5 UI Less RHRC on
RXEA,C,E[6:0]; RXOB,D[6:0]
Figure 16. Receiver RSRC and RHRC Output Setup/Hold Time Adjustment — PTO Enabled
12
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AC Timing Diagrams (continued)
RCLK IN
VDIFF = 0V
VDIFF = 0V
(Differential)
Previous
cycle
Current
Cycle
Next
cycle
RXOA+/-
OA1-1
OA0-1
OA6
OA5
OA4
OA3
OA2
OA1
OA0
RXOB+/-
OB1-1
OB0-1
OB6
OB5
OB4
OB3
OB2
OB1
OB0
RXOC+/-
OC1-1
OC0-1
OC6
OC5
OC4
OC3
OC2
OC1
OC0
RXOD+/-
OD1-1
OD0-1
OD6
OD5
OD4
OD3
OD2
OD1
OD0
RXOE+/-
OE1-1
OE0-1
OE6
OE5
OE4
OE3
OE2
OE1
OE0
RXEA+/-
EA1-1
EA0-1
EA6
EA5
EA4
EA3
EA2
EA1
EA0
RXEB+/-
EB1-1
EB0-1
EB6
EB5
EB4
EB3
EB2
EB1
EB0
RXEC+/-
EC1-1
EC0-1
EC6
EC5
EC4
EC3
EC2
EC1
EC0
RXED+/-
ED1-1
ED0-1
ED6
ED5
ED4
ED3
ED2
ED1
ED0
RXEE+/-
EE1-1
EE0-1
EE6
EE5
EE4
EE3
EE2
EE1
EE0
Figure 17. LVDS Input Mapping
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AC Timing Diagrams (continued)
RCLK IN
VDIFF = 0V
VDIFF = 0V
(Differential)
Previous
cycle
Current
Cycle
Next
cycle
RXOA+/-
OA1
OA0
RXOB+/-
OB1
OB0
RXOC+/-
OC1
OC0
RXOD+/-
OD1
OD0
RXOE+/-
OE1
OE0
RXEA+/-
EA1
EA0
RXEB+/-
EB1
EB0
RXEC+/-
EC1
EC0
RXED+/-
ED1
ED0
RXEE+/-
EE1
EE0
RITOL 1 min
RITOL 1 max
RITOL 0 min
RITOL 0 max
RITOL 6 min
RITOL 6 max
RITOL 5 min
RITOL 5 max
RITOL 4 min
RITOL 4 max
RITOL 3 min
RITOL 3 max
RITOL 2 min
RITOL 2 max
Figure 18. Receiver RITOL Min and Max
14
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VDD4
RXOD2
RXOD1
RXOD3
RXOD5
RXOD4
RXOC0
RXOD6
RXOC2
RXOC1
RXOC4
RXOC3
RXOC6
RXOC5
RXOB1
RXOB0
RXOB2
RXOB3
RXOB5
RXOB4
VDDR2
RXOB6
VSSR2
RXOA1
RXOA0
RXOA2
RXOA3
RXOA4
RXOA5
RXOA6
VSS5
VDD5
PIN ASSIGNMENTS
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
RESRVD
97
64
MODE1
98
63
RXOD0
VSSL
99
62
RXOE6
VDDL
100
61
RXOE5
RXOA-
101
60
RXOE4
VSS4
RXOA+
102
59
RXOE3
RXOB-
103
58
RXOE2
RXOB+
104
57
RXOE1
RXOC-
105
56
RXOE0
RXOC+
106
55
VDD3
RXOD-
107
54
VSS3
RXOD+
108
53
RXEA6
RXOE-
109
52
RXEA5
RXOE+
110
51
RXEA4
VSSL
111
50
RXEA3
49
RXEA2
DS90C3202
VSSL
112
VDDL
113
VDDL
114
RCLKIN-
115
46
VDD2
RCLKIN+
116
45
VSS2
48
RXEA1
47
RXEA0
RXEA-
117
44
RCLKOUT
RXEA+
118
43
VDDR1
39
RXEB4
RXED-
123
38
RXEB3
RXED+
124
37
RXEB2
RXEE-
125
36
RXEB1
RXEE+
126
35
RXEB0
MODE0
127
34
RXEC6
RFB
128
33
VDD1
VSS1
RXEC5
RXEC4
RXEC3
RXEC1
RXEC2
RXEC0
VDDR0
VSSR0
RXED6
RXED4
RXED5
RXED2
RXED3
RXED1
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RXED0
8
VSS0
7
VDD0
6
RXEE6
5
RXEE5
4
RXEE4
3
RXEE2
2
RXEE3
1
RXEE1
122
RXEE0
RXEB5
RXEC+
PWDNB
40
VDDP0
121
VSSP0
RXEB6
RXEC-
VSSP1
VSSR1
41
VDDP1
42
120
S2CLK
119
S2DAT
RXEBRXEB+
Figure 19. DS90C3202 Receiver
DS90C3202 PIN DESCRIPTIONS
Pin No.
Pin Name
I/O
1
S2DAT
I/OP
Digital
Pin Type
Two-wire Serial Interface – Data
Description
2
S2CLK
I/P
Digital
Two-wire Serial Interface – Clock
3
VDDP1
VDD
PLL
Power supply for PLL circuitry
4
VSSP1
GND
PLL
Ground pin for PLL circuitry
5
VSSP0
GND
PLL
Ground pin for PLL circuitry
6
VDDP0
VDD
PLL
Power supply for PLL circuitry
7
PWDNB
I/P
LVTTL I/P (pulldown)
Powerdown Bar (Active LOW)
0 = DEVICE DISABLED
1 = DEVICE ENABLED
8
RXEE0
O/P
LVTTL O/P
LVTTL level data output
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DS90C3202 PIN DESCRIPTIONS (continued)
16
Pin No.
Pin Name
I/O
9
RXEE1
O/P
LVTTL O/P
Pin Type
LVTTL level data output
Description
10
RXEE2
O/P
LVTTL O/P
LVTTL level data output
11
RXEE3
O/P
LVTTL O/P
LVTTL level data output
12
RXEE4
O/P
LVTTL O/P
LVTTL level data output
13
RXEE5
O/P
LVTTL O/P
LVTTL level data output
14
RXEE6
O/P
LVTTL O/P
LVTTL level data output
15
VSS0
GND
LVTTL O/P PWR
Ground pin for LVTTL outputs and digital circuitry
16
VDD0
VDD
LVTTL O/P PWR
Power supply pin for LVTTL outputs and digital
circuitry
17
RXED0
O/P
LVTTL O/P
LVTTL level data output
18
RXED1
O/P
LVTTL O/P
LVTTL level data output
19
RXED2
O/P
LVTTL O/P
LVTTL level data output
20
RXED3
O/P
LVTTL O/P
LVTTL level data output
21
RXED4
O/P
LVTTL O/P
LVTTL level data output
22
RXED5
O/P
LVTTL O/P
LVTTL level data output
23
RXED6
O/P
LVTTL O/P
LVTTL level data output
24
VSSR0
GND
RX LOGIC
Ground pin for logic
25
VDDR0
VDD
RX LOGIC
Power supply for logic
26
RXEC0
O/P
LVTTL O/P
LVTTL level data output
27
RXEC1
O/P
LVTTL O/P
LVTTL level data output
28
RXEC2
O/P
LVTTL O/P
LVTTL level data output
29
RXEC3
O/P
LVTTL O/P
LVTTL level data output
30
RXEC4
O/P
LVTTL O/P
LVTTL level data output
31
RXEC5
O/P
LVTTL O/P
LVTTL level data output
32
VSS1
GND
LVTTL O/P PWR
Ground pin for LVTTL outputs and digital circuitry
33
VDD1
VDD
LVTTL O/P PWR
Power supply pin for LVTTL outputs and digital
circuitry
34
RXEC6
O/P
LVTTL O/P
LVTTL level data output
35
RXEB0
O/P
LVTTL O/P
LVTTL level data output
36
RXEB1
O/P
LVTTL O/P
LVTTL level data output
37
RXEB2
O/P
LVTTL O/P
LVTTL level data output
38
RXEB3
O/P
LVTTL O/P
LVTTL level data output
39
RXEB4
O/P
LVTTL O/P
LVTTL level data output
40
RXEB5
O/P
LVTTL O/P
LVTTL level data output
41
RXEB6
O/P
LVTTL O/P
LVTTL level data output
42
VSSR1
GND
RX LOGIC
Ground pin for logic
43
VDDR1
VDD
RX LOGIC
Power supply for logic
44
RCLKOUT
O/P
LVTTL O/P
LVTTL level clock output
45
VSS2
GND
LVTTL O/P PWR
Ground pin for LVTTL outputs and digital circuitry
46
VDD2
VDD
LVTTL O/P PWR
Power supply pin for LVTTL outputs and digital
circuitry
47
RXEA0
O/P
LVTTL O/P
LVTTL level data output
48
RXEA1
O/P
LVTTL O/P
LVTTL level data output
49
RXEA2
O/P
LVTTL O/P
LVTTL level data output
50
RXEA3
O/P
LVTTL O/P
LVTTL level data output
51
RXEA4
O/P
LVTTL O/P
LVTTL level data output
52
RXEA5
O/P
LVTTL O/P
LVTTL level data output
53
RXEA6
O/P
LVTTL O/P
LVTTL level data output
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DS90C3202 PIN DESCRIPTIONS (continued)
Pin No.
Pin Name
I/O
54
VSS3
GND
LVTTL O/P PWR
Pin Type
Ground pin for LVTTL outputs and digital circuitry
Description
55
VDD3
VDD
LVTTL O/P PWR
Power supply pin for LVTTL outputs and digital
circuitry
56
RXOE0
O/P
LVTTL O/P
LVTTL level data output
57
RXOE1
O/P
LVTTL O/P
LVTTL level data output
58
RXOE2
O/P
LVTTL O/P
LVTTL level data output
59
RXOE3
O/P
LVTTL O/P
LVTTL level data output
60
RXOE4
O/P
LVTTL O/P
LVTTL level data output
61
RXOE5
O/P
LVTTL O/P
LVTTL level data output
62
RXOE6
O/P
LVTTL O/P
LVTTL level data output
63
RXOD0
O/P
LVTTL O/P
LVTTL level data output
64
VSS4
GND
LVTTL O/P PWR
Ground pin for LVTTL outputs and digital circuitry
65
VDD4
VDD
LVTTL O/P PWR
Power supply pin for LVTTL outputs and digital
circuitry
66
RXOD1
O/P
LVTTL O/P
LVTTL level data output
67
RXOD2
O/P
LVTTL O/P
LVTTL level data output
68
RXOD3
O/P
LVTTL O/P
LVTTL level data output
69
RXOD4
O/P
LVTTL O/P
LVTTL level data output
70
RXOD5
O/P
LVTTL O/P
LVTTL level data output
71
RXOD6
O/P
LVTTL O/P
LVTTL level data output
72
RXOC0
O/P
LVTTL O/P
LVTTL level data output
73
RXOC1
O/P
LVTTL O/P
LVTTL level data output
74
RXOC2
O/P
LVTTL O/P
LVTTL level data output
75
RXOC3
O/P
LVTTL O/P
LVTTL level data output
76
RXOC4
O/P
LVTTL O/P
LVTTL level data output
77
RXOC5
O/P
LVTTL O/P
LVTTL level data output
78
RXOC6
O/P
LVTTL O/P
LVTTL level data output
79
RXOB0
O/P
LVTTL O/P
LVTTL level data output
80
RXOB1
O/P
LVTTL O/P
LVTTL level data output
81
RXOB2
O/P
LVTTL O/P
LVTTL level data output
82
RXOB3
O/P
LVTTL O/P
LVTTL level data output
83
RXOB4
O/P
LVTTL O/P
LVTTL level data output
84
RXOB5
O/P
LVTTL O/P
LVTTL level data output
85
RXOB6
O/P
LVTTL O/P
LVTTL level data output
86
VDDR2
VDD
RX LOGIC
Power supply for logic
87
VSSR2
GND
RX LOGIC
Ground pin for logic
88
RXOA0
O/P
LVTTL O/P
LVTTL level data output
89
RXOA1
O/P
LVTTL O/P
LVTTL level data output
90
RXOA2
O/P
LVTTL O/P
LVTTL level data output
91
RXOA3
O/P
LVTTL O/P
LVTTL level data output
92
RXOA4
O/P
LVTTL O/P
LVTTL level data output
93
RXOA5
O/P
LVTTL O/P
LVTTL level data output
94
RXOA6
O/P
LVTTL O/P
LVTTL level data output
95
VDD5
VDD
LVTTL O/P PWR
Power supply pin for LVTTL outputs and digital
circuitry
96
VSS5
GND
LVTTL O/P PWR
Ground pin for LVTTL outputs and digital circuitry
97
RESRVD
I/P
LVTTL I/P (pulldown)
Tie to VSS for correct functionality
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DS90C3202 PIN DESCRIPTIONS (continued)
18
Pin No.
Pin Name
I/O
98
MODE1
I/P
Pin Type
Description
Digital (pulldown)
“ODD” Bank Enable
0 = LVTTL ODD OUTPUTS DISABLED
(Data Output Low)
1 = LVTTL ODD OUTPUTS ENABLED
99
VSSL
GND
LVDS PWR
Ground pin for LVDS
100
VDDL
VDD
LVDS PWR
Power supply pin for LVDS
101
RXOA-
I/P
LVDS I/P
Negative LVDS differential data input
102
RXOA+
I/P
LVDS I/P
Positive LVDS differential data input
103
RXOB-
I/P
LVDS I/P
Negative LVDS differential data input
104
RXOB+
I/P
LVDS I/P
Positive LVDS differential data input
105
RXOC-
I/P
LVDS I/P
Negative LVDS differential data input
106
RXOC+
I/P
LVDS I/P
Positive LVDS differential data input
107
RXOD-
I/P
LVDS I/P
Negative LVDS differential data input
108
RXOD+
I/P
LVDS I/P
Positive LVDS differential data input
109
RXOE-
I/P
LVDS I/P
Negative LVDS differential data input
110
RXOE+
I/P
LVDS I/P
Positive LVDS differential data input
111
VSSL
GND
LVDS PWR
Ground pin for LVDS
112
VSSL
GND
LVDS PWR
Ground pin for LVDS
113
VDDL
VDD
LVDS PWR
Power supply pin for LVDS
114
VDDL
VDD
LVDS PWR
Power supply pin for LVDS
115
RCLKIN-
I/P
LVDS I/P
Negative LVDS differential clock input
116
RCLKIN+
I/P
LVDS I/P
Positive LVDS differential clock input
117
RXEA-
I/P
LVDS I/P
Negative LVDS differential data input
118
RXEA+
I/P
LVDS I/P
Positive LVDS differential data input
119
RXEB-
I/P
LVDS I/P
Negative LVDS differential data input
120
RXEB+
I/P
LVDS I/P
Positive LVDS differential data input
121
RXEC-
I/P
LVDS I/P
Negative LVDS differential data input
122
RXEC+
I/P
LVDS I/P
Positive LVDS differential data input
123
RXED-
I/P
LVDS I/P
Negative LVDS differential data input
124
RXED+
I/P
LVDS I/P
Positive LVDS differential data input
125
RXEE-
I/P
LVDS I/P
Negative LVDS differential data input
126
RXEE+
I/P
LVDS I/P
Positive LVDS differential data input
127
MODE0
I/P
Digital (pulldown)
“EVEN” Bank Enable
0 = LVTTL EVEN OUTPUTS DISABLED
(Data Output Low)
1 = LVTTL EVEN OUTPUTS ENABLED
128
RFB
I/P
Digital (pulldown)
Rising Falling Bar (Figure 11)
0 = FALLING EDGE DATA STROBE
1 = RISING EDGE DATA STROBE
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APPLICATION INFORMATION
Two-Wire Serial Communication Interface Description
The DS90C3202 operates as a slave on the Serial Bus, so the S2CLK line is an input (no clock is generated by
the DS90C3202) and the S2DAT line is bi-directional. DS90C3202 has a fixed 7bit slave address. The address is
not user configurable in anyway.
A zero in front of the register address is required. For example, to access register 0x0Fh, “0F” is the correct way
of accessing the register.
COMMUNICATING WITH THE DS90C3202 CONTROL REGISTERS
There are 32 data registers (one byte each) in the DS90C3202, and can be accessed through 32 addresses. All
registers are predefined as read only or read and write. The DS90C3202 slave state machine does not require
an internal clock and it supports only byte read and write. Page mode is not supported. The 7bit binary address
is 0111110 All seven bits are hardwired internally.
Reading the DS90C3202 can take place either of three ways:
1. If the location latched in the data register addresses is correct, then the read can simply consist of a slave
address byte, followed by retrieving the data byte.
2. If the data register address needs to be set, then a slave address byte, data register address will be sent
first, then the master will repeat start, send the slave address byte and data byte to accomplish a read.
3. When performing continuous read operations, another write (or read) instruction in between reads needs to
be completed in order for the two-wire serial interface module to read repeatedly.
SDA Line
Register
Address
Slave Address
A A A
2 1 0 0
S
A A A
2 1 0 1
S
AC
K
Bus Activity:
DS90C3202
AC
K
Slave Address
P
AC
K
AC
K
Stop
Start
Bus Activity:
Master
Start
The data byte has the most significant bit first. At the end of a read, the DS90C3202 can accept either
Acknowledge or No Acknowledge from the Master (No Acknowledge is typically used as a signal for the slave
that the Master has read its last byte).
Data
Figure 20. Byte Read
The master must generate a Start by sending the 7-bit slave address plus a 0 first, and wait for acknowledge
from DS90C3202. When DS90C3202 acknowledges (the 1st ACK) that the master is calling, the master then
sends the data register address byte and waits for acknowledge from the slave. When the slave acknowledges
(the 2nd ACK), the master repeats the “Start” by sending the 7-bit slave address plus a 1 (indicating that READ
operation is in progress) and waits for acknowledge from DS90C3202. After the slave responds (the 3rd ACK),
the slave sends the data to the bus and waits for acknowledge from the master. When the master acknowledges
(the 4th ACK), it generates a “Stop”. This completes the “ READ”.
SDA Line
Register
Address
Slave
Address
S
Bus Activity:
DS90C3202
Stop
Bus Activity:
Master
Start
A Write to the DS90C3202 will always include the slave address, data register address byte, and a data byte.
Data
A A A
2 1 0 0
P
AC
K
AC
K
AC
K
Figure 21. Byte Write
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The master must generate a “Start” by sending the 7-bit slave address plus a 0 and wait for acknowledge from
DS90C3202. When DS90C3202 acknowledges (the 1st ACK) that the master is calling, the master then sends
the data register address byte and waits for acknowledge from the slave. When the slave acknowledges (the 2nd
ACK), the master sends the data byte and wait for acknowledge from the slave. When the slave acknowledges
(the 3rd ACK), the master generates a “ Stop”. This completes the “WRITE”.
DS90C3202 Two-Wire Serial Interface Register Table
Address
R/W
RESET
Bit #
0d/0h
R
PWDN
[7:0]
Vender ID low byte[7:0] = 05h
0000_0101
1d/1h
R
PWDN
[7:0]
Vender ID high byte[15:8] =13h
0001_0011
2d/2h
R
PWDN
[7:0]
Device ID low byte[7:0] = 28h
0010_1000
3d/3h
R
PWDN
[7:0]
Device ID high byte 15:8] = 67h
0110_0111
4d/4h
R
PWDN
[7:0]
Device revision [7:0] = 00h to begin with
0000_0000
5d/5h
R
PWDN
[7:0]
Low frequency limit, 8Mhz = 8h
0000_1000
6d/6h
R
PWDN
[7:0]
High frequency limit 135Mhz = 87h =
0000_0000_1000_0111
1000_0111
7d/7h
R
PWDN
[7:0]
Reserved
0000_0000
8d/8h
R
PWDN
[7:0]
Reserved
0000_0000
Default Value
9d/9h
R
PWDN
[7:0]
Reserved
0000_0000
10d/ah
R
PWDN
[7:0]
Reserved
0000_0000
11d/bh
R
PWDN
[7:0]
Reserved
0000_0000
20d/14h
R/W
None
[7:0]
Reserved
0000_0000
21d/15h
R/W
None
[7:0]
Reserved
0000_0000
22d/16h
R/W
None
[7:3]
Reserved
0000_0000
[2:0]
LVDS input skew control for CLK channel,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Tsetup improvement
23d/17h
R/W
None
[7]
Reserved
[6:4]
[3]
24d/18h
R/W
None
[7]
[3]
None
LVDS input skew control for RXO channel C,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
0000_0000
LVDS input skew control for RXO channel D,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
Reserved
[2:0]
R/W
LVDS input skew control for RXO channel B,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
Reserved
[6:4]
25d/19h
0000_0000
Reserved
[2:0]
[7]
LVDS input skew control for RXO channel E,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
Reserved
[6:4]
[3]
0000_0000
LVDS input skew control for RXO channel A,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
Reserved
[2:0]
20
Description
LVDS input skew control for RXE channel A,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
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Address
R/W
RESET
Bit #
26d/1ah
R/W
None
[7]
[6:4]
[3]
R/W
None
[7]
[3]
29d/1dh
30d/1eh
R/W
R/W
R/W
None
None
None
0000_0000
LVDS input skew control for RXE channel B,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
LVDS input skew control for RXE channel C,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
Reserved
[6:4]
28d/1ch
Default Value
Reserved
[2:0]
27d/1bh
Description
Reserved
0000_0000
LVDS input skew control for RXE channel D,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment
Reserved
[2:0]
LVDS input skew control for RXE channel E,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
[7:3]
Reserved
0000_0000
[2]
LVTTL output transition time control for CLK
0: Tr/Tf = 1.0ns (default)
1: Tr/Tf = 1.5ns
[1]
LVTTL output transition time control for RXE
0: Tr/Tf = 1.5ns (default)
1: Tr/Tf = 2.5ns
[0]
LVTTL output transition time control for RXO
0: Tr/Tf = 1.5ns (default)
1: Tr/Tf = 2.5ns
[7:3]
Reserved
[2:1]
LVTTL output setup and hold time control
00: balanced setup and hold time (default)
01: setup time is increased from default position by 1UI &
hold time is reduced from default position by 1UI
10: setup time is decreased from default position by 1UI &
hold time is reduced from default position by 1UI
11: setup time is increased from default position by 2UI &
hold time is increased from default position by 2UI
[0]
LVTTL output PTO control
1: PTO disabled, all outputs setup time are only controlled
by contents of [2:1]
0: PTO enabled (default)
Group1: CLK to latch Data is re-assigned earlier by 0.5UI
respect to the normal centered position if only PTO option
enabled; but PTO option and (Tsetup or Thold) adjustment
can co-exist
Group2: CLK to latch Data stays as the normal centered
position if only PTO option enabled; but PTO option and
(Tsetup or Thold) adjustment can co-exist
[7:5]
Reserved
[4]
I/O disable control for RXE channel A,
1: disable, 0: enable (default)
[3]
I/O disable control for RXE channel B,
1: disable, 0: enable (default)
[2]
I/O disable control for RXE channel C,
1: disable, 0: enable (default)
[1]
I/O disable control for RXE channel D,
1: disable, 0: enable (default)
[0]
I/O disable control for RXE channel E,
1: disable, 0: enable (default)
0000_0000
0000_0000
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Product Folder Links: DS90C3202
21
DS90C3202
SNLS191D – APRIL 2005 – REVISED APRIL 2013
22
www.ti.com
Address
R/W
RESET
Bit #
Description
Default Value
31d/1fh
R/W
None
[7:6]
11; LVTTL Outputs available as long as "NO CLK" is at
HIGH regardless PLL lock or not
10; LVTTL Outputs available after 1K of CLK cycles
detected & PLL generated strobes are within 0.5UI respect
to REFCLK
01; LVTLL Outputs available after 2K of CLK cycles
detected
00: default ; LVTTL Outputs available after 1K of CLK cycles
detected
0000_0000
[5]
0: default; to select the size of wait counter between 1K or
2K, default is 1K
[4]
I/O disable control for RXO channel A,
1: disable, 0: enable (default)
[3]
I/O disable control for RXO channel B,
1 disable, 0: enable (default)
[2]
I/O disable control for RXO channel C,
1: disable, 0: enable (default)
[1]
I/O disable control for RXO channel D,
1: disable, 0: enable (default)
[0]
I/O disable control for RXO channel E,
1: disable, 0: enable (default)
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Product Folder Links: DS90C3202
DS90C3202
www.ti.com
SNLS191D – APRIL 2005 – REVISED APRIL 2013
REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
Page
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Product Folder Links: DS90C3202
23
PACKAGE OPTION ADDENDUM
www.ti.com
12-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
DS90C3202VS/NOPB
ACTIVE
Package Type Package Pins Package
Drawing
Qty
TQFP
PDT
128
90
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
CU SN
Level-3-260C-168 HR
(4)
0 to 70
DS90C3202VS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
MECHANICAL DATA
MPQF013 – NOVEMBER 1995
PDT (S-PQFP-G128)
PLASTIC QUAD FLATPACK
0,23
0,13
0,40
96
0,05 M
65
97
64
128
33
1
0,13 NOM
32
12,40 TYP
Gage Plane
14,05
SQ
13,95
16,10
SQ
15,90
0,05 MIN
0,25
0°– 5°
0,75
0,45
1,05
0,95
Seating Plane
0,08
1,20 MAX
4087726/A 11/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
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