SSRAM AS5SP512K36 Plastic Encapsulated Microcircuit 18Mb, 512K x 36, Synchronous SRAM Pipeline Burst, Single Cycle Deselect FEATURES Synchronous Operation in relation to the input Clock 2 Stage Registers resulting in Pipeline operation On chip address counter (base +3) for Burst operations Self-Timed Write Cycles On-Chip Address and Control Registers Byte Write support Global Write support On-Chip low power mode [powerdown] via ZZ pin Interleaved or Linear Burst support via Mode pin Three Chip Enables for ease of depth expansion without Data Contention. Two Cycle load, Single Cycle Deselect Asynchronous Output Enable (OE\) Three Pin Burst Control (ADSP\, ADSC\, ADV\) 3.3V Core Power Supply 3.3V/2.5V IO Power Supply JEDEC Standard 100 pin TQFP Package Available in Industrial, Enhanced, and MilTemperature Operating Ranges RoHs compliant options available 100-PIN TQFP PINOUT (3-CHIP ENABLE) Fast Access Times Parameter Cycle Time Clock Access Time Output Enable Access Time Symbol tCYC tCD tOE 200Mhz 5.0 3.1 3.1 166Mhz 6.0 3.5 3.5 133Mhz 7.5 4.0 4.0 Units ns ns ns Block Diagram OE\ ZZ GENERAL DESCRIPTION The AS5SP512K36 is a 18Mb High Performance Synchronous Pipeline Burst SRAM, available in multiple temperature screening levels, fabricated using High Performance CMOS technology and is organized as a 512K x 36 array. It integrates address and control registers, a two (2) bit burst address counter supporting four (4) double-word transfers. Writes are internally self-timed and synchronous to the rising edge of clock. CLK CE1\ CE2 I/O Gating and Control CE3\ BWE\ BWx\ CONTROL BLOCK GW\ ADV\ ADSC\ ADSP\ MODE A0-Ax AS5SP512K36 Rev. 3.0 10/13 BURST CNTL. Address Registers Row Decode Memory Array x36 SBP ❑ Synchronous Pipeline Burst ❋ Two (2) cycle load ❋ One (1) cycle de-select ❋ One (1) cycle latency on Mode change Output Register Output Driver DQx, DQPx Input Register Column Decode The AS5SP512K36 includes advanced control options including Global Write, Byte Write as well as an asynchronous output enable. Burst Cycle controls are handled by three (3) input pins, ADV\, ADSP\ and ADSC\. Burst operation can be initiated with either the Address Status Processor (ADSP\) or Address Status controller (ADSC\) inputs. Subsequent burst addresses are generated internally in the system’s burst sequence control block and are controlled by the Address Advance (ADV\) control input. Micross Components reserves the right to change products or specifications without notice. 1 SSRAM AS5SP512K36 Pin Descriptions Clock CLK Input Address A0, A1 Sync Input 37, 36 Address A Sync Input(s) Chip Enable Chip Enable Global Write Enable Byte Write Enable Output Enable CE1\, CE3\ CE2 GW\ BWa\, BWb\, BWc\, BWd\ BWE\ OE\ Input Address Status Controller ADSC\ Sync Input 85 Address Status Processor ADSP\ Sync Input 84 Address Advance ADV\ Sync Input 83 Power-Down ZZ Input 64 Data Parity Input/Outputs DQPa, DQPb, DQPc, DQPd Sync Input/ Output 51, 80, 1, 30 Data Input/Outputs Sync DQa, DQb, DQc, Input/ DQd Output Burst Mode Power Supply [Core] Ground [Core] MODE VDD VSS Input Supply Supply Power Supply I/O VDDQ Supply I/O Ground VSSQ Supply No Connection(s) NC NA Byte Enables 89 Synchronous clock. Low order, synchronous address inputs and burst counter address inputs. 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 43, 42 Sync Input 98, 92 Sync Input 97 Sync Input 88 Synchronous address inputs Active low chip enables. Active high chip enable. Active low global write enable. Write to all bits. Sync Input 93, 94, 95, 96 Active low byte write enables. Write to byte segments. Sync Input 87 Active low byte write function enable. Active low asynchronous output enable. When asserted LOW, address is captured in the address registers and A0A1 are loaded into the burst counter when ADSP\ and ADSC\ are both asserted, only ADSP\ is recognized. 86 When asserted LOW, address is captured in the address registers, A0-A1 is registered in the burst counter. When both ADSP\ and ADSC\ or both asserted, only ADSP\ is recognized. ADSP\ is ignored when CE1\ is HIGH. When asserted LOW, address in burst counter is incremented on rising edge of clock. Asynchronous, non-time critical Power-down Input control. Places the chip into an ultra low power mode, with data preserved. 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29 31 91, 15, 41, 65 90, 17, 40, 67 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 14, 16, 38, 39, 66 Synchronous parity on input/output. Synchronous data input/output. Interleaved or linear burst mode control. Core power supply. Core power supply ground. Isolated input/output buffer supply. Isolated input/output buffer ground. No connections to internal silicon. Logic Block Diagram A0, A1, A ADDRESS REGISTER 2 A [1:0] MODE ADV CLK Q1 BURST COUNTER CLR AND LOGIC ADSC Q0 ADSP BW D DQ D , DQP D BYTE WRITE REGISTER DQ D ,DQP D BYTE WRITE DRIVER BW C DQ C , DQP C BYTE WRITE REGISTER DQ C , DQP C BYTE WRITE DRIVER DQ B , DQP B BYTE WRITE REGISTER DQ B , DQP B BYTE WRITE DRIVER BW B BW A BWE ZZ AS5SP512K36 Rev. 3.0 10/13 ENABLE REGISTER SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS E DQs DQP A DQP B DQP C DQP D DQ A , DQP A BYTE WRITE DRIVER DQ A , DQP A BYTE WRITE REGISTER GW CE 1 CE 2 CE 3 OE MEMORY ARRAY INPUT REGISTERS PIPELINED ENABLE SLEEP CONTROL Micross Components reserves the right to change products or specifications without notice. 2 SSRAM AS5SP512K36 Functional Description cycle. Consecutive single cycle READS are supported. Once the SRAM is deselected by use of the Chip Enable(s) and either ADSP\ or ADSC\, its outputs will tri-state immediately. Micross Components AS5SP512K36 Synchronous SRAM is manufactured to support today’s High Performance platforms utilizing the industry’s leading processor elements including those of Intel and Motorola. The AS5SP512K36 supports Synchronous SRAM READ and WRITE operations as well as Synchronous Burst READ/WRITE operations. All inputs with the exception of OE\, MODE and ZZ are synchronous in nature and registered on the rising edge of input clock (CLK). The type, start and duration of Burst Mode operations is controlled by MODE, ADSC\, ADSP\ and ADV\. All synchronous accesses, including the Burst accesses, are enabled via the use of the multiple enable pins, and wait state insertion is supported and controlled via the use of the Address Advance (ADV\). A Single ADSP\ controlled WRITE operation is initiated when both of the following conditions are satisfied at the rising edge of Clock: [1] ADSP\ is asserted LOW, and [2] Chip Enable(s) are asserted ACTIVE. The WRITE controls: Global Write, Byte Write Enable (GW\, BWE\) the individual Byte Writes (BWa\, BWb\, BWc\, BWd\), and ADV\ are ignored on the first machine cycle. ADSP\ triggered WRITE accesses require two (2) machine cycles to complete. If Global Write is asserted LOW on the second Clock (CLK) rise, data will be written into the selected address location. If GW\ is HIGH (inactive) then the WRITE operation is controlled by BWE\ and one or more of the Byte Write controls (BWa\, BWb\, BWc\ and BWd\). All WRITES that are initiated in this device are internally self timed. The AS5SP512K36 supports both Interleaved and Linear Burst modes. The AS5SP512K36 supports Byte WRITE operations via the Byte Write Enable (BWE\) and the Byte Write Select pin(s) (BWa\, BWb\, BWc\, BWd\). Global Writes are supported via the Global Write Enable (GW\). Global Write Enable will override the Byte Write inputs and will perform a Write to all 36 Data Bits. A Single ADSC\ controlled WRITE operation is initiated at the rising edge of Clock when the following conditions are satisfied: [1] ADSC\ is asserted LOW, [2] ADSP\ is de-asserted (HIGH), [3] Chip Enable(s) are asserted (TRUE or Active), and [4] the appropriate combination of the WRITE inputs (GW\, BWE\, BWx\) are asserted (ACTIVE). ADSC\ triggered WRITE accesses require a single clock (CLK) machine cycle to complete. The ADV\ pin is ignored during this cycle. The AS5SP512K36 provides ease of producing very dense arrays via the multiple Chip Enable input pins and Asynchronous Output Enable. Single Cycle Access Operations A Single READ operation is initiated at the rising edge of Clock when all of the following conditions are satisfied: [1] ADSP\ or ADSC\ is asserted LOW, [2] Chip Enables are all asserted active, and [3] the WRITE signals (GW\, BWE\) are HIGH. ADSP\ is ignored if CE1\ is HIGH. The address presented to the Address inputs is stored within the Address Registers and Address Counter/Advancement Logic and presented to the array core. The corresponding data of the addressed location is propagated to the Output Registers and passed to the data bus on the next rising clock via the Output Buffers. The time at which the data is presented to the Data bus is as specified by either the Clock to Data valid specification or the Output Enable to Data Valid spec for the device speed grade chosen. The only exception occurs when the device is emerging from a deselected to selected state where its outputs are tristated in the first machine cycle and controlled by its Output Enable (OE\) on following AS5SP512K36 Rev. 3.0 10/13 Deep Power-Down Mode (SLEEP) The AS5SP512K36 has a Deep Power-Down mode and is controlled by the Asynchronous ZZ pin. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, Data integrity is guaranteed. For the device to be placed successfully into this operational mode the device must be deselected and the Chip Enables, ADSP\ and ADSC\ remain inactive for the duration of tZZREC after the ZZ input returns LOW. Accesses pending when entering “sleep” mode are not considered valid. Micross Components reserves the right to change products or specifications without notice. 3 SSRAM AS5SP512K36 Synchronous Truth Table (1, 2) CE1\ H L L L L L L L X H X H X H X H CE2 X L X L X H H H X X X X X X X X CE3\ X X H X H L L L X X X X X X X X ADSP\ X L L H H L H H H X H X H X H X ADSC\ L X X L L X L L H H H H H H H H ADV\ X X X X X X X X L L L L H H H H WT / RD X X X X X X WT RD RD RD WT WT RD RD WT WT CLK Address Accessed NA NA NA NA NA External Address External Address External Address Next Address Next Address Next Address Next Address Current Address Current Address Current Address Current Address Operation Not Selected Not Selected Not Selected Not Selected Not Selected Begin Burst, READ Begin Burst, WRITE Begin Burst, READ Continue Burst, READ Continue Burst, READ Continue Burst, WRITE Continue Burst, WRITE Suspend Burst, READ Suspend Burst, READ Suspend Burst, WRITE Suspend Burst, WRITE Notes: 1. X = Don’t Care 2. WT= WRITE operation in WRITE TABLE, RD= READ operation in WRITE TABLE Burst Sequence Tables Burst Control Pin [MODE] First Address State HIGH Case 1 A1 0 0 1 1 Fourth Address Burst Control Pin [MODE] First Address A0 State LOW Capacitance Interleaved Burst Case 2 A1 A0 0 0 1 0 0 1 1 1 1 0 1 0 Linear Burst Case 2 A1 A0 0 1 1 0 1 0 1 0 Case 1 A0 A1 0 0 1 1 Fourth Address 0 1 0 1 Case 3 A1 Case 4 A0 A1 1 1 0 0 0 1 0 1 1 1 0 0 Case 3 A1 A0 BW\ H L L L L L X A1 0 1 0 1 Max. 6 8 Units pF pF A0 1 0 0 1 1 0 1 0 Asynchronous Truth Table BWa\ X H L H H L X BWb\ X H H L H L X BWc\ X H H H L L X BWd\ X H H H L L X Operation READ READ WRITE Byte [A] WRITE Byte [B] WRITE Byte [C], [D] WRITE ALL Bytes WRITE ALL Bytes Absolute Maximum Ratings Parameter Symbol Min. -0.3 Voltage on VDD Pin VDD Voltage on VDDQ Pins VDDQ Voltage on Input Pins VIN -0.3 Voltage on I/O Pins VIO -0.3 Power Dissipation PD Storage Temperature tSTG -65 Operating Temperatures /IT -40 [Screening Levels] /ET -40 /XT -55 Operation Power-Down (SLEEP) READ WRITE De-Selected ZZ H L L L L OE\ X L H X X I/O Status High-Z DQ High-Z Din, High-Z High-Z AC Test Loads Absolute Maximum Ratings* Figure 1 Max. Units 4.6 V VDD V VDD+0.3 V VDDQ+0.3 V 1.6 150 85 105 125 Output Rt = 50 ohm Zo=50 ohm Diagram [A] W C Vt= Termination Voltage Rt= Termination Resistor R R 30 pF Vt= 1.50v for 3.3v VDDQ Vt= 1.25v for 2.5v VDDQ C R C R= 317 [email protected] Figure 2 R= 1667 [email protected] R C *Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum conditions for any duration or segment of time may affect device reliability. AS5SP512K36 Rev. 3.0 10/13 Symbol CI CIO Case 4 A0 1 1 0 0 Write Table GW\ H H H H H H L 1 0 1 0 Parameter Input Capacitance Input/Output Capacitance Output 3.3/2.5v 5 pF R= 351 [email protected] R= 1538 [email protected] Diagram [B] Micross Components reserves the right to change products or specifications without notice. 4 SSRAM AS5SP512K36 DC Electrical Characteristics (VDD = 3.3v ± 5%, VDDQ = 3.3V/2.5V ± 5%, VDDQ ≤ VDD) [1, 2] TA=Min. and Max temperatures of Screening level chosen VDD VDDQ VoH Symbol Parameter Power Supply Voltage I/O Supply Voltage Output High Voltage VoL Output Low Voltage Test Conditions 3.3v 2.5v 3.3v 2.5v 3.3v 2.5v 3.3v 2.5v VDD=Min., IOH=-4mA VDD=Min., IOH=-1mA VDD=Min., IOL=8mA VDD=Min., IOL=1mA VIH Input High Voltage VIL Input Low Voltage IIL IZ IOL IDD Input Leakage (except ZZ) Mode Pin VDD=Max., VIN=VSS to VDD Input Leakage, ZZ pin Output Leakage Operating Current Output Disabled, VOUT=VSSQ to VDDQ Automatic CE, Power Down Current - TTL inputs CMOS Standby 0.8 0.7 5 30 5 475 425 375 Units V V V V V V V V V V uA uA uA mA mA mA 250 225 200 200 mA mA mA mA 2 1.7 -5 -30 -5 Notes 4 3 3 Max VDD, De-Selected, 5.0ns Cycle, 200 Mhz 6.0ns Cycle, 166 Mhz 7.5ns Cycle, 133 Mhz VIN>=VIH or VIN</=VIL f=1/tCYC ISB2 Max 3.630 VDD 0.4 0.4 5.0ns Cycle, 200 Mhz 6.0ns Cycle, 166 Mhz 7.5ns Cycle, 133 Mhz VDD=Max., f=Max., IOH=0mA ISB1 Min 3.465 2.375 2.4 2 Max. VDD, Device deselected, VIN </=0.3V or VIN>/=VDDQ-0.3V f=1/tCYC Thermal Resistance Parameter ȺJA ȺJC Description ThermalResistance (JunctiontoAmbient) ThermalResistance (JunctiontoCase) TestConditions Testconditionsfollowstandardtest methodsandproceduresfor measuringthermalimpedance,per EIA/JESD51 DQ DQC Package Package Unit 28.66 30.2 o 4.08 6.5 o C/W C/W Notes: [1] [2] [3] [4] AS5SP512K36 Rev. 3.0 10/13 All Voltages referenced to VSS (Logic Ground) Overshoot: VIH(AC) < VDD +1.5V (Pulsewidth less than tCYC/2) Undershoot: VIL(AC) > -2V (Pulsewidth less than tCYCLZ) tPower-up: Assumes a linear amp from OV to VDD(MIN) within zooms. During this time VIH VDD and VDDQ VDD MODE and ZZ pins have internal pull-up resistors VDDQ should never exceed VDD, VDD and VDDQ can be connected together Micross Components reserves the right to change products or specifications without notice. 5 SSRAM AS5SP512K36 AC Switching Characteristics (VDD = 3.3v ± 5%, VDDQ = 3.3V/2.5V ± 5%, VDDQ ≤ VDD) [1] TA=Min. and Max temperatures of Screening level chosen Parameter Clock (CLK) Cycle Time Clock (CLK) High Time Clock (CLK) Low Time Clock Access Time Clock (CLK) High to Output Low-Z Clock High to Output High-Z Output Enable to Data Valid Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Address Set-up to CLK High Address Hold from CLK High Address Status Set-up to CLK High Address Status Hold from CLK High Address Advance Set-up to CLK High Address Advance Hold from CLK High Chip Enable Set-up to CLK High (CEx\, CE2) Chip Enable Hold from CLK High (CEx\, CE2) Data Set-up to CLK High Data Hold from CLK High Write Set-up to CLK High (GW\, BWE\, BWx\) Write Hold from CLK High (GW\, BWE\, BWX\) ZZ High to Power Down ZZ Low to Power Up -30 [200Mhz] Min. Max. 5.00 2.00 2.00 3.10 1.00 1.25 3.00 3.10 1.25 0.00 3.00 1.40 0.40 1.40 0.40 1.40 0.40 1.40 0.40 1.40 0.40 1.40 0.40 2 2 Symbol tCYC tCH tCL tCD tCLZ tCHZ tOE tOH tOELZ tOEHZ tAS tAH tASS tASH tADVS tADVH tCES tCEH tDS tDH tWES tWEH tPD tPU -35 [166Mhz] Min. Max. 6.00 2.20 2.20 3.50 1.00 1.25 3.50 3.50 1.25 0.00 3.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 2 2 -40 [133Mhz] Min. Max. 7.50 2.50 2.50 4.00 1.00 1.25 3.50 4.00 1.25 0.00 3.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 2 2 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cycles cycles Notes to Switching Specifications: 1. 2. 3. AS5SP512K36 Rev. 3.0 10/13 Configuration signal mode is static and must not change during normal operation. Guaranteed but not 100% tested. This parameter is periodically sampled. Tested with load in Figure 2. Micross Components reserves the right to change products or specifications without notice. 6 Notes 2,3 2,3 2,3 2,3 SSRAM AS5SP512K36 AC SWITCHING WAVEFORMS Write Cycle Timing Single Write Burst Write tCYC Pipelined Write tCH CLK tASS tASH tCL ADSP\ ADSP\ Ignored with CE1\ inactive ADSC\ tASS ADSC\ Initiated Write tASH ADV\ tADVS tADVH A1 Ax ADV\ Must be Inactive for ADSP\ Write A3 A2 tAS tAH GW\ tWES tWEH tWEH tWES BWE\, BWx\ tCES tCEH CE1\ Masks ADSP\ CE1\ CE2 CE3\ OE\ tDS tDH DQx,DQPx W1 W2a W2b W2c W2d W3 DON'T CARE UNDEFINED AS5SP512K36 Rev. 3.0 10/13 Micross Components reserves the right to change products or specifications without notice. 7 SSRAM AS5SP512K36 AC SWITCHING WAVEFORMS Read Cycle Timing Single Read Burst Read tCYC tCH Pipelined Read tCL CLK tASS ADSP\ Ignored with CE1\ Inactive tASH ADSP\ ADSC\ Initiated Read ADSC\ Suspend Burst ADV\ tADVS tADVH Ax A2 A1 tAS A3 tAH GW\ tWES tWEH BWE\, BWx\ tCES CE1\ Masks ADSP\ tCEH CE1\ Unselected with CE2 CE2 CE3\ OE\ tOEHZ tOE tCD DQx,DQPx R1 tOH R2a R2b R2c R2d R3a DON'T CARE UNDEFINED AS5SP512K36 Rev. 3.0 10/13 Micross Components reserves the right to change products or specifications without notice. 8 SSRAM AS5SP512K36 AC SWITCHING WAVEFORMS Read/Write Cycle Timing Single Cycle Deselected Burst Read tCYC tCH tCL Pipedlined Read CLK tASS tASH ADSP\ ADSC\ ADV\ tADVS tADVH tAS Ax A1R A2W A3W A4R A5R tAH GW\ tWES tWEH BWE\, BWx\ tCES tCEH tCES tCEH CE1\ Unselected CE1\ CE2 CE3\ OE\ tOEHZ tOE DQx,DQPx DON'T CARE A1O tOH A2I A4O [a] A3I tOELZ A4O [c] A4O [d] tCHZ tCD I/O disabled within 1 clock cycle after deselect UNDEFINED AS5SP512K36 Rev. 3.0 10/13 A4O [b] Micross Components reserves the right to change products or specifications without notice. 9 SSRAM AS5SP512K36 POWER DOWN (SLEEP MODE) The device is placed in this SLEEP mode via the use of the ZZ pin, an asynchronous control pin which when asserted, places the array into the lower power or Power Down mode. Awakening the array or leaving the Power Down (SLEEP) mode is done so by de-asserting the ZZ pin . While in the Power Down or Snooze mode, Data integrity is guaranteed. Accesses pending when the device entered the mode are not considered valid nor is the completion of the operation guaranteed. The device must be de-selected prior to entering the Power Down mode, all Chip Enables, ADSP\ and ADSC\ must remain inactive for the duration of ZZ recovery time (tZZREC). ZZ MODE ELECTRICAL CHARACTERISTICS Parameter Power Down (SNOOZE) Mode ZZ Active (Signal HIGH) to Power Down ZZ Inactive (Signal Low) to Power Up Symbol Test Conditon IDDzz ZZ >/- VDD - 0.2V tZZS ZZ >/- VDD - 0.2V tZZR ZZ </- 0.2V ZZ MODE TIMING DIAGRAM [1, 2] Min. Max. 165 2 tCYC 2 tCYC Units mA ns ns ORDERING INFORMATION TQFP Device Number AS5SP512K36DQ-30/IT AS5SP512K36DQ-35/IT AS5SP512K36DQ-40/IT AS5SP512K36DQ-30/ET AS5SP512K36DQ-35/ET AS5SP512K36DQ-40/ET AS5SP512K36DQ-35/XT AS5SP512K36DQ-40/XT CLK ADSP\ HIGH ADSC\ AVAILABLE PROCESSES IT = Industrial Temperature Range ET = Enhanced Temperature Range XT = Military Temperature Range HIGH CE1\, CE3\ CE2 Configuration 512Kx36, 3.3vCore/3.3,2.5vIO 512Kx36, 3.3vCore/3.3,2.5vIO 512Kx36, 3.3vCore/3.3,2.5vIO 512Kx36, 3.3vCore/3.3,2.5vIO 512Kx36, 3.3vCore/3.3,2.5vIO 512Kx36, 3.3vCore/3.3,2.5vIO 512Kx36, 3.3vCore/3.3,2.5vIO 512Kx36, 3.3vCore/3.3,2.5vIO tCD (ns) 3.1 3.5 4.0 3.1 3.5 4.0 3.5 4.0 Clock (Mhz) 200 166 133 200 166 133 166 133 -40oC to +85oC -40oC to +105oC -55oC to +125oC LOW ZZ tZZS IDD 1. 2. tZZREC IDDzz Device must be deselected when entering ZZ mode. See Synchronous Truth table for all signal conditions to deselect device. I/O’s are in three-state when exiting ZZ sleep mode. AS5SP512K36 Rev. 3.0 10/13 Micross Components reserves the right to change products or specifications without notice. 10 SSRAM AS5SP512K36 MECHANICAL DEFINITION 100-Pin TQFP (Package Designator DQ) AS5SP512K36 Rev. 3.0 10/13 Micross Components reserves the right to change products or specifications without notice. 11 SSRAM AS5SP512K36 DOCUMENT TITLE Plastic Encapsulated Microcircuit , 18Mb, 512K x 36, Synchronous SRAM Pipeline Burst, Single Cycle Deselect REVISION HISTORY Rev # 2.5 History updated max ratings & DC Electrical Characteristics Release Date September 2008 Status Release 2.6 Updated Micross Information October 2010 Release 2.7 Changed ADV\ description text from HIGH to LOW on page 2, Edited ADV\ Write Cycle Timing drawing on page 7 November 2010 Release 2.8 Added copper lead frame and RoHS May 2011 compliant options, Updated IDDzz, pg 10 from 35mA to 165mA, Updated logic block diagram on page 2. Changed tCLZmin from 1.25ns to 1.0ns. Corrected -30 tOH from 1.65ns to 1.25ns. Changed: Spec Device From To IDD 5ns Cycle 350 475 mA 6ns Cycle 300 425 mA 7.5ns Cycle 275 375 mA ISB1 5ns Cycle 160 250 mA 6ns Cycle 150 225 mA 7.5ns Cycle 140 200 mA All 70 200 mA ISB2 ISB3 All 80 250 mA Deleted ISB4 Specification Release 2.9 Added Thermal Resistance for DQC package, page 5. September 2011 Release 3.0 Removed Cu-lead frame option October 2013 Release AS5SP512K36 Rev. 3.0 10/13 Micross Components reserves the right to change products or specifications without notice. 12