Burr-Brown DIR1701E Digital audio interface receiver Datasheet

DIR1701
SLAS331 – APRIL 2001
DIGITAL AUDIO INTERFACE RECEIVER
FEATURES
D Standard Digital Audio Interface Receiver
D
D
D
D
D
D
D
D
DESCRIPTION
(EIAJ1201)
Sampling Rate: 32/44.1/48/88.2/96 kHz
Recover 128 / 256 / 384 / 512 fs System Clock
Very Low Jitter System Clock Output (80ps
Typically)
On-Chip Master Clock Oscillator, Only an
External 12.000 MHz or 16.000 MHz Crystal Is
Required
Selectable Output PCM Audio Data Format
Output User Bit Data, Flag Signals, and
Channel Status Data With Block Start Signal
Single + 3.3-V Power Supply
Package: 28 SSOP
APPLICATIONS
D AV Receiver
D MD Player
D DAC Unit
The DIR1701 is a digital audio interface receiver
(DIR) which receives and decodes audio data up
to 96 kHz according to the AES/EBU, IEC958,
S/PDIF, and EIAJCP340/1201 consumer and
professional format interface standards. The
DIR1701 demultiplexes the channel status bit and
user bit directly to serial output pins, and has
dedicated output pins for the most important
channel status bits.
The significant advantages of the DIR1701 are
96 kHz sampling rate capability and Low-jitter
clock recovery by the Sampling Period Adaptive
Controlled Tracking (SpAct) system. Input signal
is reclocked with the patented Sampling period
Adaptive controlled tracking system for maximum
quality. These two features are required for recent
consumer and professional audio instruments, in
which the DIR has an interface to any kind of
delta-sigma type ADC/DAC with 96 kHz sampling
rate.
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate
precaustions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SpAct and Burr-Brown are trademarks of Texas Instruments.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
DIR1701
SLAS331 – APRIL 2001
DIR1701
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ADFLG
BRATE0
BRATE1
SCKO
VDD
DGND
XTO
XTI
CKTRNS
LRCKO
BCKO
DOUT
SCF0
SCF1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TEST
UNLOCK
FMT1
FMT0
VCC
AGND
FILT
RST
DIN
BRSEL
BFRAME
EMFLG
URBIT
CSBIT
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER
DIR1701E
SSOP–28
324†
OPERATION
TEMPERATURE
RANGE
PACKAGE
MARKING
–25°C
° to +85°C
°
DIR1701E
ORDERING
NUMBER}
TRANSPORT
MEDIA
DIR1701E
Rails
DIR1701E/2K
Tape and Reel
† TI equivalent no. 4040065.
‡ Models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000
pieces of DIR1701E/2K will get a single 2000-piece tape and reel.
block diagram
VDD VCC
BRSEL SCF
FMT
XTI
SCKO
OSC
XTO
BCKO
OSC
Selector
PLL1
LRCKO
Audio Clock
and Data
Generator
100 MHz
DIN
PLL2
SpAct
S/PDIF
DECODER
ADFLG
wrclk
rdclk
2
UNLOCK CKTRNS
2
URBIT
CSBIT
EMFLG
FIFO
BRATE
DOUT
BFRAME
FILT
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RST
DGND
AGND
DIR1701
SLAS331 – APRIL 2001
Terminal Functions
TERMINAL
NAME
PIN
DESCRIPTIONS
I/O
ADFLG
1
O
Audio data or digital data flag
BRATE0
2
O
BRATE1
3
O
fs rate flag 0 (32k, 44.1k, 48k, and 88k / 96k)
fs rate flag 1 (32k, 44.1k, 48k, and 88k / 96k)
SCKO
4
O
System clock output
VDD
DGND
5
–
Digital power supply, +3.3 V
6
–
Digital ground
XTO
7
O
Crystal oscillator output
XTI
8
I
Crystal oscillator input, external clock input
CKTRNS
9
O
Clock transition status output
LRCKO
10
O
Audio latch enable (LRCK, fs) output
BCKO
11
O
Audio bit clock output
DOUT
12
O
Audio serial data output
SCF0
13
I
System clock frequency select (128/256/384/512 fs) (see Note 1)
SCF1
14
I
System clock frequency select (128/256/384/512 fs) (see Note 1)
CSBIT
15
O
Channel status bit output (see Note 2)
URBIT
16
O
User bit output (see Note 2)
EMFLG
17
O
Emphasis flag
BFRAME
18
O
Block start clock (B-frame)
BRSEL
19
I
Default bit rate select (32 / 44.1 / 48 / 88.2 / 96k) (see Note 1)
DIN
20
I
S/PDIF data digital input (see Note 4)
RST
21
I
Reset input, active LOW (see Note 3)
FILT
22
–
External filter
AGND
23
–
Analog ground
VCC
FMT0
24
–
Analog power supply, +3.3V
25
I
Audio data format select (see Note 1)
FMT1
26
I
Audio data format select (see Note 1)
UNLOCK
27
O
PLL unlock or parity error flag
TEST
28
I
Should be connected to DGND (see Note 1)
NOTES: 1.
2.
3.
4.
Schmitt trigger input with internal pulldown (TYP 51 kΩ), 5 V tolerant.
Serial outputs are utilized for both consumer and professional application.
Schmitt trigger input with internal pullup (TYP 51 kΩ), 5 V tolerant.
CMOS level input with internal pulldown (TYP 51 kΩ), 5 V tolerant.
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DIR1701
SLAS331 – APRIL 2001
absolute maximum ratings†
Supply voltage, VCC, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
Supply voltage differences, VCC, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V
Ground voltage differences, AGND, DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V
Digital input voltage:
Digital input pins except XTI . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (6.5 V + 0.3 V)
XTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VDD + 0.3 V)
Input current (Any pins except supplies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead temperature (soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C, 5 sec
Package temperature (IR reflow, peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235°C, 10 sec
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4
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DIR1701
SLAS331 – APRIL 2001
electrical characteristics, all specifications at TA = 25°C, VCC = VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DIGITAL INPUT/OUTPUT
VIH (5)
VIL (5)
VIH2 (6)
VIL2 (6)
VIH3 (7)
VIL3 (7)
VOH (8)
VOL (8)
VOH (9)
2
MAX
UNIT
5.5
70%VDD
Input logic level
30%VDD
5.5
70%VDD
VDC
30%VDD
Output logic level
Input leakage current
IIH(6)
IIL(6)
fs(12)
TYP
0.8
VOL (9)
IIH(10)
IIL(10)
IIH(11)
IIL(11)
MIN
IO = 1 mA
IO = –2 mA
VDD–0.4
IO = 2 mA
IO = –4 mA
VDD–0.4
0.5
VDC
0.5
VIN = VDD
VIN = 0 V
65
–10
VIN = VDD
VIN = 0 V
–100
10
–10
VIN = VDD
VIN = 0 V
Input sampling frequency
10
–65
–10
10
–10
10
32
SCKO
System clock frequency
tj
SCKO clock jitter
128/256/
384/512 fs
80
SCKO duty cycle
50%
4.096
XTI clock accuracy
100
–500
See
Table 3
µ
µA
96
kHz
49.152
MHz
ps RMS
500
ppm
S/PDIF INPUT
Duty cycle
Jitter
VIN = 1.5 V,
VIN = 1.5 V
fs = 96 kHz
15%
85%
20
ns p-p
3.3
3.6
VDC
3.4
4.7
26
36
POWER SUPPLY REQUIREMENTS
VDD, VCC
ICC (VCC)
IDD (VDD)
PD
Voltage range
3
Supply current (see Note 13)
Power dissipation
100
mA
mW
POWER SUPPLY REQUIREMENTS
Operation temperature
θJA
NOTES: 5.
6.
7.
8.
9.
10.
11.
12.
13.
Thermal resistance
–25
28-pin SSOP
85
100
°C
°C/W
TTL compatible, except pins 8, 20: XTI, DIN.
Pin 8: XTI (CMOS logic level).
Pin 20: DIN (CMOS logic level).
Pins 1–3, 9, 17–18, 27: ADFLG, BRATE0, BRATE1, CKTRNS, EMFLG, BFRAME, UNLOCK.
Pins 4, 10–12, 15–16: SCKO, LRCKO, BCKO, DOUT, CSBIT, URBIT.
Pins 13–14, 19–20, 25–26, 28: SCF0, SCF1, BRSEL, DIN, FMT0, FMT1, CKSEL.
Pin 21: RST
fs is defined as the incoming audio sampling frequency per channel.
No load connected to SCKO, LRCKO, BCKO, DOUT, CSBIT, URBIT. Power supply current varies according to the system clock
frequency.
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5
DIR1701
SLAS331 – APRIL 2001
basic operation theory
The DIR1701 has two PLLs, PLL1 and PLL2. The SpAct (Sampling Period Adaptive Controlled Tracking)
system is a newly developed clock recovery architecture, giving very low jitter clock from S/PDIF data input. The
DIR1701 requires a system clock input for operation of SpAct; internal PLL1 provides a 100 MHz execution
clock. The system clock can be obtained by either connecting a suitable crystal resonator at the XTI/XTO pins
or applying an external clock input at the XTI pin as shown in Figure 1. Internal PLL2 generates the system clock
SCKO by using the output signal of the SpAct frequency estimator.
When the S/PDIF input signal ceases, SCKO holds the latest tracked frequency. Also, the DIR1701 indicates
the unlocked state by a HIGH level output at the UNLOCK pin. When the S/PDIF signal restarts, the PLL will
lock in around 1ms with very low jitter, using the SpAct estimator. Then the DIR1701 indicates the locked status
by a LOW level output at the UNLOCK pin. In this status, the BRATE pins indicate the actual bit rate of the
incoming S/PDIF signal.
C1
External Clock
Crystal
XTI
XTAL
OSC
CIR
R1
XTI
Open
XTO
XTO
C2
R1 = 1 MΩ,
C1, C2 = 10 TO 33 pF
XTAL
OSC
CIR
DIR1701
DIR1701
Crystal Resonator Connection
External Clock Input
Figure 1. System Clock Connections
system clock output
The primary function of the DIR1701 is to recover audio data and a low jitter clock from a digital audio
transmission line. The clocks that can be generated are SCKO (128/256/384/512 fS, shown in Table 1), BCKO
(64 fS), and LRCKO (1 fS). SCKO is the output of the voltage controlled oscillator (VCO) in an analog PLL. The
PLL function consists of a VCO, phase and frequency detector, and a external second-order loop filter. The
closed-loop transfer function, which specifies the PLL jitter attenuation characteristics, is shown in Figure 2.
The crystal frequency should be defined for internal PLL by connecting the BRSEL pin to one of the output pins
BFRAME or CSBIT as shown in Table 2. A 12 MHz crystal resonator can be used for 128fS (CSBIT), 256fS
(OPEN) and 384fS (BFRAME). And a 16 MHz crystal resonator is used for 512fS (BFRAME). The system clock
frequency can be set by control data at SCF0, SCF1 pin (shown in Table 3); this data must be stable before reset
is applied.
Table 4 shows the state of the system and the condition of audio clocks and flags. Required accuracy of system
clock by either crystal resonator or external clock input is ±500 ppm.
Table 1. Generated System Clock (SCKO) Frequencies
SAMPLING
RATE
6
128 fS
256 fS
32 kHz
4.096 MHz
8.192 MHz
12.288 MHz
16.384 MHz
44.1 kHz
5.6448 MHz
11.2896 MHz
16.9344 MHz
22.5792 MHz
48 kHz
6.144 MHz
12.288 MHz
18.432 MHz
24.576 MHz
88.2kHz
11.2896 MHz
22.5792 MHz
33.8688 MHz
45.1584 MHz
96 kHz
12.288 MHz
24.576 MHz
36.864 MHz
49.152 MHz
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384 fS
512 fS
DIR1701
SLAS331 – APRIL 2001
system clock output (continued)
5
Magnitude Response – dB
0
–5
–10
–15
–20
–25
–30
100
1k
10 k
f – Frequency – Hz
100 k
Figure 2. Jitter Attenuator Characteristics With Specified Loop Filter
Table 2. Selectable Crystal Oscillators
SYSTEM CLOCK fS
CRYSTAL
BRSEL CONNECTED TO
128
12 MHz
CSBIT
256
12 MHz
OPEN or DGND
384
12 MHz
BFRAME
512
16 MHz
BFRAME
Table 3. System Clock Selection
SCF1
SCF0
SYSTEM CLOCK
LOW
LOW
128 fS
LOW
HIGH
256 fS
HIGH
LOW
384 fS
HIGH
HIGH
512 fS
Table 4. System Clock and Data Output Operation
CONDITIONS
CLOCK AND DATA OUTPUTS
S/PDIF DATA
SCKO
BCKO
LRCKO
DOUT
BRATE
UNLOCK
CS. UR BIT
AD. EMFLG
After RESET
Unknown
(128, 256, 384, 512 fS)
Unknown
(64 fS)
Unknown
(1 fS)
MUTE
LOW
HIGH
LOW
LOW
YES
PLL
(128, 256, 384, 512 fS)
DETECT
LOW
DATA
DATA
HOLD†
(128, 256, 384, 512 fS)
PLL
(1 fS)
HOLD†
(1 fS)
DATA
NO
PLL
(64 fS)
HOLD†
(64 fS)
MUTE
HOLD†
HIGH
HOLD†
HOLD†
† Holds the latest tracked frequency.
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DIR1701
SLAS331 – APRIL 2001
SCKO timing
tSCKH
H
2V
SCKO
0.8 V
L
tSCKL
SCKO Clock Pulse Width High
SCKO Clock Pulse Width Low
System Clock Pulse
Cycle Time†
tSCKH
tSCKL
7 ns (min)
7 ns (min)
† 1/128 fS, 1/256 fS, 1/384 fS or 1/512 fS.
bit rate detection
By using the SpAct frequency estimator (not the S/PDIF channel status bit), the DIR1701 detects automatically
the sample rate of an incoming S/PDIF signal and indicates the frequency at the BRATE pins.
Table 5 lists the frequency ranges reported. Except for 88.2 and 96 kHz, these sample rates are the same as
the channel status bit defined in the S/PDIF specifications. When the bit-rate is 88.2 or 96 kHz the indicator
shows the same HL value. This state is not defined in the S/PDIF specifications.
Table 5. Incoming Sample Frequency Bits
SAMPLING RATE
BRATE1
BRATE0
32 kHz
HIGH
HIGH
44.1 kHz
LOW
LOW
48 kHz
LOW
HIGH
88.2 kHz
HIGH
LOW
96 kHz
HIGH
LOW
timing specification for PLL operation
lock-up time
PLL
Condition
Unlock
Lock
DIN Start
PLL Status
Indicator Pin
Site UNLOCK
H
L
tINT< 1 ms
Figure 3. PLL Lock Up Timing
8
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DIR1701
SLAS331 – APRIL 2001
relation between audio-data-output timing and PLL condition indicator timing
When the analog PLL is still unlocked and the S/PDIF signal starts, after at least ten rising edges, the S/PDIF
decoder can detect the incoming S/PDIF signal. The DOUT pin becomes LOW (MUTE) until the analog PLL
locks. This MUTE period tINT is less than 1 ms (the analog PLL lockup time is less than 0.5 ms). When the
decoder detects that incoming S/PDIF signal has stopped, UNLOCK goes HIGH at the next LRCKO transition.
SCKO keeps its frequency at the latest tracked bit rate.
When S/PDIF signal is not present after removal of reset, the frequency of the DIR1701 audio clocks (SCKO,
BCKO, LRCKO) is not known.
Unlock
Lock
PLL
Condition
H
UNLOCK
L
LRCKO
BCKO
DOUT
Mute
1
31
2
32
Mute
Figure 4. Relation Between Audio Data Output Timing and UNLOCK Flag Timing
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DIR1701
SLAS331 – APRIL 2001
unlock flag minimum pulse width time
CASE-A when PLL is unlocked
When the PLL is unlocked, the UNLOCK flag pin is HIGH and the audio data output DOUT becomes LOW
(MUTE). The MUTE period, tUNL, is at least 200 ms. In this period, SCKO, BCKO, and LRCKO frequency hold
the latest tracked frequency.
If an S/PDIF signal is connected again in this unlock period, the bit rate is changed to the incoming signal
frequency, after at least 1 ms (before the UNLOCK flag goes LOW). The CKTRNS pin indicates validity of SCKO.
When CKTRNS is HIGH, the frequency of SCKO, BCKO, and LRCKO is in transition between states.
tUNL>200 ms
UNLOCK
H
L
LRCKO
CKTRANS
S/PDIF Signal Bit Rate
S/PDIF Signal Starts Again
New Bit Rate
BCKO
tTRNS < 1 ms
DOUT
1
Mute
Figure 5. UNLOCK Flag Minimum Pulse Width Time for PLL Unlocked
10
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2
DIR1701
SLAS331 – APRIL 2001
unlock flag minimum pulse width time (continued)
CASE-B when parity error occurs
When a parity error occurs in one subframe interval, UNLOCK becomes HIGH during this sub-frame then
returns LOW at the next arriving subframe.
During this subframe with parity error, the data output will hold the previous data of each channel.
CASE-B When Parity Error Occurs
H
UNLOCK
L
LRCKO
BCKO
DOUT
24
1
24
1
2
Same as The Previous Data
Figure 6. UNLOCK Timing for Parity Error
PCM audio interface
The DIR1701 can produce 16-bit or 24-bit output data in standard format and 24-bit output data in IIS format.
The PCM audio interface format of the DIR1701 is selected using the format pins FMT1, FMT0. Table 6 shows
the FMT pin configuration.
Table 6. Audio Output Data Format Select
FMT1
FMT0
LOW
LOW
16 bit MSB first, Right justified
AUDIO DATA FORMAT
LOW
HIGH
24 bit MSB first, Right justified
HIGH
LOW
24 bit MSB first, Left justified
HIGH
HIGH
24 bit IIS
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DIR1701
SLAS331 – APRIL 2001
PCM audio interface (continued)
Standard Data Format; L–Channel = HIGH, R–Channel = LOW
1/fS
LRCKO
R–Channel
L–Channel
BCKO
Right Justified
Audio Data Word = 16–Bit
1 2
DOUT 14 15 16
DOUT 22 23 24
1 2
23 24
23 24
LSB
MSB
1 2
LSB
MSB
LSB
1 2
LSB
MSB
15 16
MSB
23 24
1 2
Left Justified
Audio Data Word = 24–Bit
DOUT
LSB
MSB
Right Justified
Audio Data Word = 24–Bit
1 2
15 16
23 24
LSB
MSB
IIS Data Format; L–Channel = LOW, R–Channel = HIGH
1/fS
LRCKO
L–Channel
R–Channel
BCKO
Audio Data Word = 24–Bit
DOUT
1 2
MSB
23 24
LSB
1 2
MSB
Figure 7. Audio Data Output Format
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23 24
LSB
1
DIR1701
SLAS331 – APRIL 2001
PCM audio interface (continued)
50% of VDD
SCHO
tSL
tLS
50% of VDD
LRCHO
tBCH
tBCL
tLB
50% of VDD
BCHO
tBCY
tBL
50% of VDD
DOUT
tDS
tDH
PARAMETERS
MIN
MAX
UNITS
tSL
tLS
SCKO rising edge to LRCKO edge
11
ns
LRCKO edge to SCKO rising edge
5
ns
tBCY
tBCL
BCKO pulse cycle time
BCKO pulse width low
78
ns
tBCH
tBL
BCKO pulse width high
78
ns
BCKO rising edge to LRCKO edge
78
ns
tLB
tDS
LRCKO edge to BCKO rising edge
78
ns
DOUT setup time
78
ns
tDH
DOUT hold time
78
ns
64 fS
Figure 8. Audio Data Output Timing
dedicated output pins for both professional and consumer applications
The DIR1701 has parallel output pins for both professional and consumer applications. In professional mode
de-emphasis flag EMFLG indicates a 50/15-µs time constant pre-emphasis. Professional mode is set when Bit
0 of CSBIT Byte 0 is HIGH. When Bits 2 to 4 of CSBIT Byte 0 is 110, the EMFLG becomes HIGH. In other cases,
EMFLG is LOW. Audio/non-audio flag ADFLG indicates S/PDIF data mode, i.e., Bit 1 of CSBIT Byte 0. When
ADFLG is LOW, S/PDIF data includes PCM audio signal. In other cases, ADFLG is HIGH.
In consumer mode EMFLG indicates 2-channel audio with a 50/15-µs time constant pre-emphasis. Consumer
mode is set when Bit 0 of CSBIT Byte 0 is LOW. When Bits 3 to 5 of CSBIT Byte 0 is 100, EMFLG becomes
HIGH. In other cases, EMFLG is LOW. The ADFLG signal indicates whether S/PDIF includes digital data, such
as AC-3 or not. When Bit 1 of CSBIT Byte 0 is HIGH, the incoming S/PDIF includes non-audio signal. In other
cases, ADFLG is LOW.
These dedicated output pins are checked for only L-ch CS information. The DIR1701 does not support CRC
check function in professional mode. As for other flags, CS bit and user-bit for professional and consumer
applications, are directly supplied by serial mode at CSBIT (pin 15) and URBIT (pin 16). These pins indicate
L-ch and R-ch information sequentially.
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DIR1701
SLAS331 – APRIL 2001
dedicated output pins for both professional and consumer applications (continued)
Audio data and clock timing are described below. The serial output data starts after 16±8 BCKO clocks from
when the corresponding subframe arrives. When B subframe arrives, BFRAME pin becomes HIGH during
1/fs x 32 (s), then BFRAME returns to LOW after 32 frames.
S/PDIF
1/fS (S)
Frame 0
B
W
M
Frame 1
W
M
Frame 191
W
Frame 0
B
16 ± 8 BCKO Delay
64 BCKO
URBIT/CSBIT/UNLOCK etc.
L0
R0
L1
R1
L191
LRCKO
BFRAME
1/fS x 32 (S)
1/fS x 192 (S)
LRCKO
BCKO
DOUT
64 1 2 3
Figure 9. Timing Chart for Audio Data and Channel Status
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DIR1701
SLAS331 – APRIL 2001
reset sequence
The DIR1701 requires external reset operation after power on. Figure 10 shows the reset sequence after power
on. The DIR1701 is ready for receiving S/PDIF signal when the internal reset sequence has finished and
CKTRNS goes to LOW. BFRAME, EMFLG, URBIT and CSBIT pins are used for configuration during the period
from the rising edge of RST to the falling edge of CKTRNS. S/PDIF signal is accepted after CKTRNS goes to
LOW. The minimum pulse width of RST, tRST is 100 ns. The RST delay after the power supply reaches 3 V should
be at least 10 ms. All of the output pins except CKTRNS and UNLOCK are LOW during RST LOW.
3V
VDD, VCC
XTI
Stable
Unstable
XTO
DIR1701 Ready
Internal PLL ON
tSTT > 10 ms
RST
BFRAME,
EMFLG,
VRBIT,
CSBIT
LOW
HIGH
tRST > 100 ns
12.5XTI Clock
Chip Status Information
LOW
LOW
Unknown
Valid
1160XTI Clock
CKTRNS
HIGH
< 5 fs
S/PDIF Acceptable
DIN
< 1 ms
UNLOCK
HIGH
NOTE: SCF0 and SCF1 should be settled during RST assertion. The change of SCF0 and SCF1 is not permitted during normal operation. When
the change is needed, the reset sequence must be started by asserting RST again.
Figure 10. After Power ON
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15
DIR1701
SLAS331 – APRIL 2001
typical circuit connection
1
2
Bit Rate Indicator
3
4
5
3.3 V VDD
+
C1
C3
6
7
R1
C5
8
9
C6
10
11
12
13
System Clock
Frequency Select
(128,256,348, 512 fs)
14
ADFLG
BRATE0
UNLOCK
BRATE1
FMT1
SCKO
FMT0
VDD
DGND
NOTES: A.
B.
C.
D.
16
VCC
AGND
XTO
FILT
XTI
RST
CKTRNS
DIN
LRCKO
BRSEL
BCKO
BFRAME
DOUT
EMFLG
SCF0
URBIT
SCF1
CSBIT
28
27
26
Data Format Select
25
24
23
22
21
20
C7
R2
C4
+
3.3 V VCC
C2
C8
Reset (Active LOW)
Receiver Circuit
19
18
17
16
15
BRSEL Connection Depends Upon
Crystal Resonator Frequency.
Audio Data
Processor
C1 , C2:
C3 , C4:
C5 , C6:
C7:
C8:
R1:
R2:
TEST
Bypass Capacitor, 1 µF to 10 µF
Bypass Capacitor, 0.01 µF to 0.1 µF
OSC Capacitor, 10 to 33 pF
Loop Filter Capacitor, 0.022 µF
Ripple Capacitor, 0.0022 µF
OSC Resistor, 1 MΩ
Loop Filter Resistor, 6.8 kΩ
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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®
PACKAGE DRAWING
MPDS072
DIR1701
SLAS331 – APRIL 2001
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18
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