AD AD8401AR 8-bit, 4-channel data acquisition system Datasheet

a
FEATURES
2 ms ADC with T/H
4-Channel MUX
AD899 Compatible
+5 Volt Operation
On-Chip Reference
4 ms Voltage Output DAC
Fast Bus Access Time—75 ns
APPLICATIONS
Servo Controls
Digitally Controlled Calibration
Process Control Equipment
8-Bit, 4-Channel Data
Acquisition System
AD8401
FUNCTIONAL BLOCK DIAGRAM
A0 A1
VI N A
VIN B
VI N C
M
U
X
The AD8401 is a complete data acquisition and control system
containing ADC, DAC, 4-channel MUX, and internal voltage
reference. Built using CBCMOS, this monolithic circuit offers
the user a complete system with very high package density and
reliability.
The converter is a successive approximation ADC with T/H,
and is capable of operating with conversion times as short as
2 µs. Analog input bandwidth is 200 kHz, and DAC output voltage settling time is less than 4 µs, making the AD8401 capable
of controlling servo loops with speed and precision.
T/H
8-BIT
DAC
8-BIT ADC
VI N D
VOUT
1.25 REF
RS
INT
BUSY
ST
DAC REG
AD8401
CONTROL LOGIC
ADC REG
DGND
GENERAL DESCRIPTION
VDD (+5.0V)
RD
CLK
CS
WR
DATA I/O
(8 BITS)
AG DAC
AG ADC
The input multiplexer addressing is designed for direct interface
to the AD899 hard-disk drive, read-channel device with no extra
hardware or special software. Analog input range levels are likewise compatible with the AD899.
The AD8401 is designed to operate from a single +5 volt supply, which will give an ADC input range of 0 V to 3.0 V, and
DAC output range of 0 V to 2.5 V.
The AD8401 is offered in the SOIC-28 surface mount package,
and is guaranteed to operate over the extended industrial temperature range of –40°C to +85°C.
The 8-bit data interface provides both read and write operation
for parallel bus interfaces to microcontrollers and DSP processors. An external 5 MHz clock sets the 2 µs conversion rate.
Slower clocks reduce the conversion time and the internal power
dissipation. The standard control lines: Reset, Busy, Interrupt,
Read and Write complete the handshaking signals for microprocessor communication. A start trigger ST input allows precise sampling intervals in synchronous sampling applications.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD8401–SPECIFICATIONS
(@ VDD = +5.0 V 6 5%, AGDAC = AGADC = 0.0 V; fCLK = 5 MHz; –408C ≤ TA ≤ +858C,
ADC ELECTRICAL CHARACTERISTICS unless otherwise noted)
Parameter
Symbol
STATIC PERFORMANCE
Resolution
Total Unadjusted Error
Relative Accuracy
Differential Nonlinearity
Offset Error
N
TUE
INL
DNL
VOSE
Full-Scale Error
Min
8
TA = +25°C
TA = Full Temp Range
TA = +25°C
TA = Full Temp Range
TA = +25°C
AE
∆Full-Scale/∆VDD
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio
Total Harmonic Distortion
Intermodulation Distortion
Frequency Response
Track/Hold Acquisition Time
Conditions
0 to 200 kHz
0
–500
VIN = 0 V
VIN = VDD
CS, RD, RS, ST
tC
+1
+1
+4
+6
+4
+6
1
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
dB
dB
dB
dB
ns
3
+500
10
1.6
40
10
LOGIC OUTPUTS (Applies to Outputs DB0–DB7, INT, BUSY)
Logic Output Low Voltage
VOL
IOL = 1.6 mA
Logic Output High Voltage
VOH
IOH = 200 µA
Output Leakage Current
IOZ
CS = 1 (Except INT & BUSY)
Output Capacitance
COZ
CS = 1 (Except INT & BUSY)
CONVERSION TIME
Units
44
48
60
0.1
200
tAQ
ICKL
ICKH
IL
Max
±3
–1
–1
–4
–6
–4
–6
SNR
THD
IMD
ANALOG INPUTS (Applies to Inputs A, B. C, D)
Unipolar Input Range
VIN
Input Current
IIN
Input Capacitance
CIN
LOGIC INPUTS
Clock Input Current Low
Clock Input Current High
Input Leakage Current
Typ
0.4
mA
µA
µA
10
10
V
V
µA
pF
2
µs
4.0
External Clock
V
µA
pF
Specifications subject to change without notice.
Table I. Multiplexer Address Input Decode
A1
A0
Input Selected
0
0
1
1
0
1
0
1
VINA
VINB
VINC
VIND
–2–
REV. 0
AD8401
(@ VDD = +5.0 V 6 5%, AGDAC = AGADC = 0.0 V; RL = 2 kV, CL = 100 pF
DAC; –408C ≤ TA ≤ +858C, unless otherwise noted)
DAC ELECTRICAL CHARACTERISTICS to AG
Parameter
Symbol
STATIC PERFORMANCE
Resolution
Total Unadjusted Error
Relative Accuracy
Differential Nonlinearity
Offset Error
N
TUE
INL
DNL
VOSE
Full-Scale Error
AE
∆Full-Scale/∆VDD
Load Regulation at Full-Scale
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio
Total Harmonic Distortion
SNR
THD
ANALOG OUTPUT
Output Voltage Range
OVR
Conditions
Min
8
TA = +25°C
TA = Full Temp Range
TA = +25°C
TA = Full Temp Range
TA = +25°C
POWER REQUIREMENTS
Positive Supply Current
tS
tPOS
tNEG
–1
–1
–2
–2.5
–3
–4
–0.5
–0.2
2.4
–10
To ± 1/2 LSB of Final Value
10% to 90%
90% to 10%
No Load
Specifications subject to change without notice.
REV. 0
Units
+1
+1
+2
+2.5
+3
+4
+0.5
+0.2
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
±2
0
f = 50 kHz
IDD
Max
44
48
LOGIC INPUTS (Applies to DB0–DB7, CS, WR, RD, RS)
Logic Input Low Voltage
VIL
Logic Input High Voltage
VIH
Input Leakage Current
IL
Input Capacitance
CIL
AC CHARACTERISTICS
Voltage Output Settling Time
Positive Full-Scale Change
Negative Full-Scale Change
DAC Glitch Impulse
Digital Feedthrough
VIN to VOUT Isolation
Typ
–3–
dB
dB
+2.5
V
0.8
V
V
µA
pF
10
10
2
1
2
15
1
60
4
2
4
µs
µs
µs
nV s
nV s
dB
13
mA
AD8401
(@ VDD = +5.0 V 6 5%, AGDAC = AGADC = 0.0 V; fCLK = 5 MHz; –408C ≤ TA ≤ +858C,
TIMING ELECTRICAL SPECIFICATIONS unless otherwise noted)
Parameters1, 2, 3
Symbol
DAC TIMING (See Figure 8 Timing Diagram)
WR Pulse Width
CS to WR Setup Time
CS to WR Hold Time
Data Setup Time
Data Hold Time
t1
t2
t3
t4
t5
50
0
0
60
0
ADC TIMING (See Figures 6 and 7 Timing Diagrams)
ST Pulse Width
ST to BUSY Delay
BUSY to INT Delay
BUSY to CS Delay
CS to RD Setup Time
RD Pulse Width4
CS to RD Hold Time
Data Access after RD
Data Access after RD
Bus Relinquish after RD
RD to INT Delay
RD to BUSY Delay
Data Valid after BUSY
Data Valid after BUSY
t6
t7
t8
t9
t10
t11
t12
t13
t13
t14
t15
t16
t17
t17
40
Condition
Min
Typ
Max
ns
ns
ns
ns
ns
110
30
CL = 20 pF
CL = 100 pF
Units
0
0
75
0
10
10
10
75
135
70
85
110
90
135
CL = 20 pF
CL = 100 pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
All input control signals are specified with t R = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2
t13 and t17 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross either 0.8 V or 2.4 V.
3
t14 is defined as the time required for the data line to change 0.5 V when loaded with the circuit of Figure 2.
4
t15 is determined by t 13.
+5V
+5V
3kΩ
DBN
3kΩ
DBN
DBN
CL
3kΩ
CL
10pF
10pF
3kΩ
DGND
DGND
a. High Z to VOH
DBN
DGND
DGND
a. VOH to High Z
b. High Z to VOL
b. VOL to High Z
Figure 2. Load Circuits for Bus Relinquish Time Test
Figure 1. Load Circuits for Data Access Time Test
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . +8 V
Input Voltages . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Package Power Dissipation . . . . . . . . . . . . . . (TJ max–TA)/θJA
Thermal Resistance θJA
28-Lead SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . 53°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range (TJ max) . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . +300°C
ORDERING GUIDE
Model*
Temperature
Range
AD8401AR
–40°C to +85°C
AD8401Chips +25°C
Package
Description
Package
Option
28-Lead SOIC
Die
SOL-28
*The AD8401 contains 1257 transistors.
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8401 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
AD8401
PIN CONFIGURATION
28
DICE CHARACTERISTICS
1
A0
VDD
1
AG DAC
2
27
VIN A
VOUT
3
26
VIN B
NC
4
25
VIN C
A1
5
24
VIN D
RS
6
23
AGADC
DB7
7
AD8401AR
22
CLK
DB6
8
Top View
(Not to Scale)
21
INT
DB5
9
20
BUSY
DB4 10
19
ST
DB3 11
18
RD
7
DB2 12
17
CS
8
13
16
WR
9
DB1 14
15
DB0
10
3
28
2
27
26
25
24
23
22
5
21
6
DGND
20
19
18
11
12
13
14
15
16
17
NC = NO CONNECT
Die Size 91 X 121 mil = 11,011 sq mil
PIN DESCRIPTIONS
Pin#
Name
Description
1
VDD
Positive Supply. Nominal value +5 volts. This pad requires 2 bonds for die assembly.
The substrate is common with VDD.
2
AGDAC
Analog Ground for the DAC. There is a separate analog ground for the ADC.
3
VOUT
Voltage Output from the DAC.
4
NC
No Connect.
5
A1
Address Input that controls multiplexer. See Table I for address decode.
6
RESET (RS)
Active Low Digital Input that clears the DAC register to zero, setting the DAC to minimum scale. It also asynchronously clears the INT line of the ADC.
7–12, 14, 15
DB7 to DB0
Digital I/O Lines. DB7 (7) is the Most Significant Bit (MSB), for both the ADC and
the DAC, and DB0 (15) is the Least Significant Bit (LSB).
13
DGND
Digital Ground.
16
WR
Rising Edge Triggered Write Input. Used to load data into the DAC register.
17
CS
Chip Select. Active Low Input
18
RD
Active Low Read Input. When this input is active, ADC data can be read from the
part. RD going low starts the ADC conversion.
19
ST
Falling Edge Triggered Start Input. Used for applications requiring precise sample timing. The falling edge of ST starts the conversion and sets the BUSY low. The ST is not
gated by CS.
20
BUSY
ADC Active Low, Status Output. When the ADC is performing a conversion, the
BUSY output is low.
21
INT
Active Low Output. The Interrupt output notifies the system that the ADC has completed its conversion. INT goes high on the rising edge of CS or RD. It will also be
forced high when RESET is asserted.
22
CLK
External Clock Input Pin. Accepts a TTL or 5 V CMOS input logic levels.
23
AGADC
Analog ADC Ground
27–24
VINA, B, C, D
Four Analog Inputs
28
A0
Address input that controls multiplexer. See Table I for address decode.
REV. 0
–5–
AD8401
Figure 4 shows the wave forms for a conversion cycle. The track
and hold begins holding the input voltage VIN approximately
50 ns after the falling edge of the Start command. The MSB decision is made approximately 50 ns after the second falling edge
of the CLK. If tX is greater than 50 ns, then the falling edge of
the CLK will be seen as the first falling clock edge. If tX is less
than 50 ns, the first MSB conversion will not occur until one
clock cycle later. The following bits will each be converted in a
similar manner 50 ns after each CLK edge until all eight bits
have been converted. After the end of conversion the contents of
the ADC SAR register are transferred to the output data latch,
the track and hold is returned to the track mode, INT goes low
and the SAR is reset.
OPERATION
The AD8401 is a complete data acquisition and control system.
It contains the DAC, a four channel input multiplexer, a track/
hold, an ADC, as well as an internal bandgap reference. It interfaces to the microcontroller via an 8-bit digital I/O port.
D/A CONVERTER SECTION
The DAC is an 8-bit voltage mode DAC with an output that
swings from AGDAC to the 1.25 volt bandgap voltage. It uses an
R-2R ladder fed by PNP current sources which allow the output
to swing to ground so that the DAC operates in a unipolar mode.
AMPLIFIER SECTION
The DAC’s output is buffered by an internal high speed op
amp. The op amps output range is set at 0 V to 2.5 V. The op
amp has a 500 ns typical settling time to 0.2% for positive
slewing signals. There are differences in settling time for negative slewing signals. Signals going to zero volts will settle slightly
slower to ground than is seen in the positive direction.
CS , RD
OR ST
BUSY
100ns
TYP
50ns TYP
VIN
50ns TYP
VDD
CLK
tx
MSB DECISION
DB7
20Ω
VOUT
LSB DECISION
DB0
Figure 4. Operating Waveforms Using the External Clock
20Ω
n-CH
ANALOG INPUT
The analog inputs of the AD8401 are fed into resistor voltage
divider networks with a typical value of 8.5 kΩ. The amplifiers
driving these inputs must have an output resistance low enough
to drive these nodes without losing accuracy. Taps from the
voltage dividers are connected to the track and hold amplifier by
the multiplexer switches.
AG DAC
Figure 3. Equivalent Amplifier Output Stage
Current sinking capability is also limited near zero volts in single
supply operation. Figure 3 provides an equivalent amplifier output stage schematic.
INTERNAL REFERENCE
5kΩ
An on-chip bandgap is provided as a voltage reference to both
the DAC and the ADC. This reference is internal to the
AD8401 and is not accessible to the user. It is laser trimmed for
both absolute accuracy and temperature coefficients. The reference is internally buffered by a separate control amplifier for both
the DAC and ADC to improve isolation between the converters.
VINA
3.57kΩ
MUX
T/H
VIND
5kΩ
3.57kΩ
AGADC
DIGITAL I/O
The 8-bit parallel data I/O port on the AD8401 provides access
to both the DAC and the ADC. This port is TTL/CMOS compatible with three-state outputs that are ESD protected.
Figure 5. Equivalent Analog Input Circuit
TRACK-AND-HOLD AMPLIFIER
The data format is binary. This data coding applies to both the
DAC and the ADC. See the applications information section.
Following the resistive divider at the input of the AD8401 is a
track-and-hold amplifier that captures input signals accurately
up to the 200 kHz Nyquist frequency of the ADC. To attain this
performance the T/H amplifier must have a much greater bandwidth than the signal of interest. Because of this the user must
be careful to band limit the input signal to avoid aliasing high
frequency components and noise into the passband.
ADC SECTION
A fast successive approximation ADC is used to attain a conversion time of 2 microseconds. Start of conversion is initiated by
CS and RD. Following a Start command the BUSY signal will
become active and another Start command should not be given
until the conversion is complete.
The track-and-hold amplifier is internally controlled by the Start
command and is not directly available to the user. After the
Start command signal the track-and-hold is placed into the hold
mode; it returns to the track mode after the conversion is
complete.
The RESET (RS) input does not affect A/D conversion, but the
INT (Interrupt or conversion complete) which normally goes
active low at the end of a conversion will be forced high by
RESET asynchronously.
–6–
REV. 0
AD8401
CLOCK
t9
The AD8401 uses an external clock that is TTL or 5 V CMOS
compatible. The external clock speed is 5 MHz and the duty
cycle may vary from 30% to 70%. The external clock can be
continuously operated between conversions.
CS
t10
t12
t 11
RD
t16
DIGITAL INTERFACE: ADC TIMING AND CONTROL
Two basic ADC operating modes are available with the
AD8401. The first mode uses the Start (ST) pin to trigger a
synchronized A/D conversion. As soon as the ST pin is asserted,
the T/H switches from tracking to the hold mode capturing the
present analog input-voltage sample. With the T/H holding the
analog sample the successive-approximation analog-to-digital
conversion is completed on that sample value. At the end of
conversion the T/H returns to the tracking mode. This mode of
conversion is ideal for digital signal processing applications
where precise interval sampling is necessary to minimize errors
due to sampling uncertainty or jitter. A precise clock source can
be used to drive the ST input.
The second mode of conversion is started by the RD and CS inputs going low, after which the BUSY line puts the microprocessor into a WAIT state until end of conversion. Mode 2 is
asserted by connecting the ST pin to logic high. The major advantage of this interface is that a single Read Instruction will
start and complete a new analog-to-digital conversion without
the need for carefully tailored software delays that often are not
portable when software routines are taken to a different processor running at a different clock speed.
t6
BUSY
t15
t8
INT
t13
DATA
t17
HIGH Z
OLD DATA
t14
NEW DATA
Figure 7. Mode 2, ADC Interface Timing
Mode 2 Interface
This interface mode can be used with microprocessors that can
be put into a WAIT state for at least 2 microseconds. The ST
pin must be tied to logic high for proper operation. The microprocessor begins a conversion by executing a READ instruction
that asserts the CS and RD pins at the AD8401’s decoded address. The AD8401 BUSY output then goes low, forcing the
microprocessor’s READY (or WAIT) line into a WAIT state.
The analog input signal is captured by the T/H on the falling
edge of RD. When the conversion is complete (8 clocks later),
the BUSY line returns high, and then the µP completes its
READ of the new data now on the digital output port of the
AD8401. Note that while conversion is in progress the ADC
places the results from the last conversion (Old Data) on the
data bus. The Figure 7 timing diagram details the applicable
timing specification requirements.
ST
DIGITAL INTERFACE: DAC TIMING AND CONTROL
t7
tCONVERT
BUSY
t8
INT
t9
t15
CS
t10
t12
t11
RD
t14
t13
DATA
HIGH Z
Table II. DAC Register Logic
DATA VALID
Figure 6. Mode 1, ADC Interface Timing
Mode 1 Interface
As shown in Figure 6, the falling edge of the ST pulse initiates a
conversion and puts the T/H amplifier into the hold mode. The
BUSY signal goes low during the whole A/D conversion time
and returns high signaling end of conversion. The INT line can
be used to interrupt the microprocessor. When the microprocessor performs a READ to access the AD8401 data, the rising
edges of CS or RD will reset the INT output to high after the t15
timing specification. INT can also be used to externally trigger a
pulse that activates the CS and RD and places the new data into
a buffer or First In First Out FIFO memory. The microprocessor can then load a series of readings from this buffer memory at
a convenient time. Care must be taken not to have the ST input
high when RD is brought low; otherwise, the AD8401 will not
operate properly. Also triggering the ST line a second time before conversion is complete will cause erroneous readings.
REV. 0
Table II shows the truth table for DAC operation. The internal
8-bit DAC register contents are loaded from the data bus when
both WR and CS are asserted. The DAC register determines the
D/A converter analog-output voltage. The WR input is a positive edge triggered input that loads the bus data into the DAC
register subject to the data setup and data hold timing requirements. When CS and WR are low, the DAC register contents
will not change with changing data bus values. Figure 8 provides
the detail timing diagram for write cycle operation.
CS
WR
RS
DAC Function
H
L
L
`
X
H
L
`
L
X
H
H
H
H
L
No Effect
No Effect
DAC Register Updated
DAC Register Updated
DAC Register Loaded with all Zeros
CS
t2
t3
t1
WR
t4
DATA
VALID DATA
Figure 8. Write Cycle Timing
–7–
t5
AD8401
An active low pulse, at any time, on the RESET pin asynchronously forces all DAC register bits to zero. The DAC output
voltage becomes zero volts and stays at that value until a new
data word is loaded into the DAC register with a new WR command. The equivalent input logic for the DAC register loading
is shown in Figure 9.
TO DAC LADDER
CS
D0
WR
D7
DAC REGISTER
RESET
INPUT DATA
Figure 9. Equivalent DAC Register Control Logic
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
120
110
SS = 300 UNITS
T A = +25°C
100
0.5
90
80
UNITS
LINEARITY ERROR – LSB
VDD = +5V
TA = +25°C
0
70
60
50
40
–0.5
30
20
10
–0.1
0
64
128
192
0
–4.5
256
–3.5
DIGITAL INPUT CODE – DECIMAL
–1.5 –0.5
0.5
1.5
2.5
FULL SCALE ERROR – LSB
3.5
4.5
Figure 12. ADC Full-Scale Error Histogram
Figure 10. ADC Linearity Error vs. Digital Code
1.0
2.5
2.0
ADC FULL-SCALE ERROR – LSB
VDD = +5V
TA = +25°C
LINEARITY ERROR – LSB
–2.5
0.5
0
–0.5
V DD = +5V
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–0.1
0
64
128
192
–3.0
–50
256
–25
0
25
50
75
100
TEMPERATURE – °C
DIGITAL INPUT CODE – DECIMAL
Figure 11. DAC Linearity Error vs. Digital Code
Figure 13. ADC Full-Scale Error vs. Temperature
–8–
REV. 0
AD8401
240
220
T A = +25°C
200
V DD = +5V
T A = +25°C
2.5
SS = 300 UNITS
180
R L TO GND
OUTPUT VOLTAGE – Volts
160
UNITS
140
120
100
80
60
40
2.0
1.5
1.0
R L TO V DD
0.5
20
0
–4
–3
–2
–1
0
1
2
3
0
4
10
100
FULL SCALE ERROR – LSB
1k
10k
100k
LOAD RESISTANCE – Ω
Figure 14. DAC Full-Scale Error Histogram
Figure 17. DAC Output Swing vs. Load Resistance
3.0
DAC FULL SCALE ERROR – LSB
2.5
V DD = +5V
2.0
3
1.5
2
1.0
1
5V
100
x +3σ
0.5
90
VOUT
0
0
5V
–0.5
0
0
–1.0
5V
10
0%
x – 3σ
–1.5
5V
WR
x
DATA
0
1V
–2.0
–2.5
–50
5V
1µS
TIME – 1µs/DIV
–25
0
25
50
75
100
Figure 18. DAC Output Slew Rate Positive Transition
TEMPERATURE – °C
Figure 15. DAC Full-Scale Error vs. Temperature
4
DAC FULL SCALE OUT CHANGE – LSB
5V
V DD = +5V
3
3
100
SS = 135 UNITS
2
2
VOUT
1
1
x +3σ
0
0
5V
5V
WR
x
–1
0
0
10
0%
x – 3σ
–2
DATA
0
1V
5V
1µS
–3
TIME – 1µs/DIV
–4
Figure 19. DAC Output Slew Rate Negative Transition
–5
0
100
200
300
400
500
BURN-IN TIME @ 150°C – HOURS
Figure 16. DAC Full-Scale Out Change vs Time
Accelerated by Burn-In
REV. 0
90
–9–
AD8401
10.0
500mV
VIN = +2.4V
9.5
90
V DD = +5V
TA = +25°C
SUPPLY CURRENT – mA
VOUT – 0.5V /DIV
100
CL = 1000pF
10
0%
20µS
9.0
V DD = +5.25V
8.5
8.0
7.5
7.0
V DD = +4.75V
TIME – 20µs /DIV
6.5
Figure 20. DAC Output Swing with Capacitive Load
6.0
–50
–25
0
25
50
75
100
TEMPERATURE – °C
POWER SUPPLY REJECTION – dB
Figure 21. Supply Current vs. Temperature
TA = +25°C
OUTPUT = FULL SCALE
VDD = 5V ± 200mV
60
40
20
0
1k
10k
100k
1M
FREQUENCY – Hz
Figure 22. Power Supply Rejection Ratio vs. Frequency
–10–
REV. 0
AD8401
APPLICATIONS INFORMATION
The software programming needs to format data as defined by
the transfer equations and Code Tables that follow.
DAC Transfer Equation
V OUT = 2.500 ×
D
255
= 2.500 ×
for a 2.50 V full scale
256
256
where D is the decimal value 0 through 255 of the 8-bit data
word.
Table III. DAC Unipolar Code
Nominal
Analog
DAC Register Contents
General Transfer
Decimal
Binary
Equation
255
1111 1111
255
2.500 ×
256
2.490 V
129
1000 0001
2.500 ×
129
256
1.260 V
128
1000 0000
2.500 ×
128
256
1.250 V
0111 1111
2.500 ×
127
256
1.240 V
1
0000 0001
1
2.500 ×
256
0.010 V
0
0000 0000
2.500 ×
0
256
0.000 V
127
Output VOUT
The nominal output voltages listed in the Code Table are subject to the static performance specifications. The INL, ZeroScale and Full-Scale errors describe the total specified variation
that will be encountered from part to part. One LSB of error for
the 2.5 V FS range is 9.766 millivolts (= 2.50/256).
Although separate AGNDs exist for both the DAC and ADC to
minimize crosstalk, writing data to the DAC while the ADC is
performing a conversion may result in an incorrect conversion
from the ADC due to signal interaction between the DAC and
ADC. Therefore, to ensure correct operation of the ADC, the
DAC register should not be updated while the ADC is converting.
The AD8401 is configured for an input range of +3.0 volts Full
Scale. The nominal transfer characteristic for this range is plotted in Figure 23. The output coding is natural binary with one
LSB equal to 11.72 millivolts. Note that the first code transition
between 0 LSB and 1 LSB occurs at 5.8 mV, one half of the
11.72 mV LSB step size. The last code transition occurs at Full
Scale minus 1.5 LSBs, which is a 2.982 V input.
The AD8401 is easily interfaced to most microprocessors by using either address bits or address decode to select the appropriate multiplexer channel. Figure 24 shows how easily the AD8401
interfaces to the AD899. No additional hardware is required.
OUTPUT
CODE
FULL SCALE
TRANSITION
11111111
11111110
11111101
1LSB = FS
256
00000011
00000010
FS – 1LSB
00000001
00000000
1
2
3
FS
VIN INPUT VOLTAGE – LSBs
Figure 23. ADC 0 V to +3 V Input Transfer Characteristic
REV. 0
–11–
AD8401
ADDRESS BUS
VDD (+5.0V)
A1
C1857–18–10/93
A0
A1
A0
A
B
C
D
1.25V REF
AD8401
VIN A
VIN B
VIN C
VIN D
T/H
8-BIT ADC
VOUT
8-BIT DAC
AD899
RESET
INT
DAC REG
CONTROL LOGIC
ADC REG
WR
CS
RD
CLOCK
DGND
ST
BUSY
DATA I/O
(8 BITS)
AG DAC
AG ADC
Figure 24. AD8401 Interface to the AD899 Read-Channel Hard Disk Drive Circuit
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Wide-Body SO
(SOL-28)
15
1
14
PIN 1
0.0500
(1.27)
BSC
0.0291 (0.74)
x 45°
0.0098 (0.25)
8°
0.0192 (0.49)
0°
SEATING 0.0125 (0.32)
0.0138 (0.35)
PLANE 0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
PRINTED IN U.S.A.
0.0118 (0.30)
0.0040 (0.10)
0.1043 (2.65)
0.0926 (2.35)
0.4193 (10.65)
0.3937 (10.00)
28
0.2992 (7.60)
0.2914 (7.40)
0.7125 (18.10)
0.6969 (17.70)
–12–
REV. 0