March 2005 Preliminary Information AS7C3256A-8 ® 3.3V 32K X 8 CMOS SRAM (Common I/O) Features • Easy memory expansion with CE and OE inputs • TTL-compatible, three-state I/O • 28-pin JEDEC standard packages - 300 mil SOJ - 8 × 13.4 mm TSOP 1 • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA • Organization: 32,768 words × 8 bits • High speed - 8 ns address access time - 5 ns output enable access time • Very low power consumption: ACTIVE - 216mW max @ 8 ns • Very low power consumption: STANDBY - 7.2 mW max CMOS I/O Logic block diagram Pin arrangement 28-pin TSOP 1 (8×13.4 mm) VCC 28-pin SOJ (300 mil) Input buffer 256 X 128 X 8 Array (262,144) Sense amp I/O7 Row decoder A0 A1 A2 A3 A4 A5 A6 A7 I/O0 Column decoder OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AS7C3256A WE Control circuit 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AS7C3256A GND 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 OE CE A A A A A A A 8 9 10 11 12 13 14 Selection guide -8 Unit Maximum address access time 8 ns Maximum output enable access time 5 ns Maximum operating current 60 mA Maximum CMOS standby current 2 mA 3/22/05; v.1.0 Alliance Semiconductor P. 1 of 9 Copyright © Alliance Semiconductor. All rights reserved. AS7C3256A-8 ® Functional description The AS7C3256A is a 3.3V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 3.3V operation without sacrificing performance or operating margins. The device enters standby mode when CE is high. CMOS standby mode consumes 7.2 mW. Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Equal address access and cycle time (tAA, tRC, tWC) of 8 ns with output enable access time (tOE) of 5 ns are ideal for highperformance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible. Operation is from a single 3.3 ±0.3V supply. The AS7C3256A is packaged in high volume industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on VCC relative to GND Vt1 –0.5 +5.0 V Voltage on any pin relative to GND Vt2 –0.5 VCC + 0.5 V Power dissipation PD – 1.0 W Storage temperature (plastic) Tstg –65 +150 oC Ambient temperature with VCC applied Tbias –55 +125 o DC current into outputs (low) IOUT – 20 C mA Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE Data Mode H X X High Z Standby (ISB, ISB1) L H H High Z Output disable (ICC) L H L DOUT Read (ICC) L L X DIN Write (ICC) Key: X = Don’t care, L = Low, H = High 3/22/05; v.1.0 Alliance Semiconductor P. 2 of 9 AS7C3256A-8 ® Recommended operating conditions Parameter Symbol Min Typical Max Unit Supply voltage VCC 3.0 3.3 3.6 V Input voltage VIH** VIL* 2.0 – VCC+0.5 V -0.5 – 0.8 V 70 o Ambient operating temperature commercial TA 0 – C * VIL min = –1.0V for pulse width less than 5ns. ** V max = V + 2.0V for pulse width less than 5ns. IH CC DC operating characteristics (over the operating range)1 -8 Parameter Sym Test conditions Min Max Unit Input leakage current |ILI| VCC = Max, Vin = GND to VCC – 1 µA Output leakage current |ILO| VCC = Max, VOUT = GND to VCC – 1 µA VCC = Max, CE ≤ VIL f = fMax, IOUT = 0mA – 60 mA – 30 mA Operating power supply ICC current ISB Standby power supply current Output voltage VCC = Max, CE > VIH f = fMax ISB1 VCC = Max, CE > VCC–0.2V VIN < 0.2V or VIN > VCC–0.2V, f = 0 – 2.0 mA VOL IOL = 8 mA, VCC = Min – 0.4 V VOH IOH = –4 mA, VCC = Min 2.4 – V Capacitance (f = 1MHz, Ta = room temperature, VCC = NOMINAL)4 Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE, WE, OE Vin = 0V 5 pF I/O capacitance CI/O I/O Vin = Vout = 0V 7 pF 3/22/05; v.1.0 Alliance Semiconductor P. 3 of 9 AS7C3256A-8 ® Read cycle (over the operating range)2,8 -8 Parameter Symbol Min Max Unit Notes Read cycle time tRC 8 – ns Address access time tAA – 8 ns 2 Chip enable (CE) access time tACE – 8 ns 2 Output enable (OE) access time tOE – 5 ns Output hold from address change tOH 3 – ns 4 CE LOW to output in low Z tCLZ 3 – ns 3,4 CE HIGH to output in high Z tCHZ – 3 ns 3,4 OE LOW to output in low Z tOLZ 0 – ns 3,4 OE HIGH to output in high Z tOHZ – 3 ns 3,4 Power up time tPU 0 – ns 3,4 Power down time tPD – 10 ns 3,4 Key to switching waveforms Rising input Falling input Undefined output/don’t care Read waveform 1 (address controlled)2,5,6,8 tRC Address tOH tAA Dout Data valid Read waveform 2 (CE controlled)2,5,7,8 tRC1 CE tOE OE tOLZ tOHZ tCHZ tACE Dout Data valid tCLZ Supply current 3/22/05; v.1.0 tPU tPD 50% Alliance Semiconductor ICC ISB 50% P. 4 of 9 AS7C3256A-8 ® Write cycle (over the operating range)9 -8 Parameter Symbol Min Max Unit Notes Write cycle time tWC 8 – ns Chip enable to write end tCW 8 – ns Address setup to write end tAW 8 – ns Address setup time tAS 0 – ns Write pulse width tWP 7 – ns Write recovery time tWR 0 – ns Address hold from end of write tAH 0 – ns Data valid to write end tDW 5 – ns Data hold time tDH 0 – ns 3,4 Write enable to output in high Z tWZ – 5 ns 3,4 Output active from write end tOW 3 – ns 3,4 Write waveform 1 (WE controlled)9 tWC tAW tAH Address tWR tWP WE tAS tDW Din tDH Data valid tWZ tOW Dout Write waveform 2 (CE controlled)9 tAW tWC tAH Address tAS tWR tCW CE tWP WE tWZ Din tDW tDH Data valid Dout 3/22/05; v.1.0 Alliance Semiconductor P. 5 of 9 AS7C3256A-8 ® AC test conditions - Output load: see Figure B Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. +3.3V +3.0V GND 90% 10% 90% 2 ns 10% Figure A: Input pulse Dout 350Ω Thevenin equivalent 320Ω C10 Dout 168Ω +1.72V GND Figure B: Output load Notes 1 2 3 4 5 6 7 8 9 10 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. For test conditions, see AC Test Conditions, Figures A, B. These parameters are specified with CL = 5pF, as in Figures B. Transition is measured ±500mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. All write cycle timings are referenced from the last valid address to the first transitioning address. C=30pF, except on High Z and Low Z parameters, where C=5pF. 3/22/05; v.1.0 Alliance Semiconductor P. 6 of 9 AS7C3256A-8 ® Package diagrams 28-pin SOJ D e 28-pin SOJ Min Max in inches B A A1 E1 E2 Seating Plane b Pin 1 c A2 E 28-pin TSOP1 b A A1 A2 B b c D E E1 E2 e 0.148 0.105 0.032 0.020 0.010 0.730 0.275 0.305 0.340 0.050 BSC e 28-pin TSOP1 8×13.4 mm Min Max c L A2 D Hd α E 3/22/05; v.1.0 0.128 0.026 0.095 0.026 0.016 0.007 0.720 0.255 0.295 0.330 Alliance Semiconductor A A1 A A1 A2 b c D e E Hd L α 1.00 1.20 0.05 0.15 0.91 1.05 0.17 0.27 0.10 0.20 11.70 11.90 0.55 nominal 7.90 8.10 13.20 13.60 0.50 0.70 0° 5° P. 7 of 9 AS7C3256A-8 ® Ordering information Temperature Package 8 ns Plastic SOJ, 300 mil Commercial AS7C3256A-8JC TSOP 8x13.4mm Commercial AS7C3256A-8TC Note: Add suffix ‘N’to the above part number for lead free parts. (Ex. AS7C3256A-8JCN) Part numbering system AS7C 3 Voltage: SRAM prefix 3 = 3.3V supply 3/22/05; v.1.0 256A –XX X Packages: Device number Access time J = SOJ 300 mil T = TSOP 8x13.4mm Alliance Semiconductor C Temperature range: C = 0 oC to 70 0C X N= Lead Free Part P. 8 of 9 ® AS7C3256A-8 ® Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C3256A-8 Preliminary Information Document Version: v.1.0 www.alsc.com © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. 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