TI DAC7821IPWR 12-bit, parallel input, multiplying digital-to-analog converter Datasheet

DA
DAC7821
C7
821
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SBAS365A – OCTOBER 2005 – REVISED FEBRUARY 2006
12-Bit, Parallel Input, Multiplying
Digital-to-Analog Converter
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2.5 V to 5.5 V Supply Operation
Fast Parallel Interface:
17ns Write Cycle
Update Rate of 20.4 MSPS
10 MHz Multiplying Bandwidth
±10 V Reference Input
Low Glitch Energy: 5 nV-s
Extended Temperature Range:
–40°C to +125°C
20-Lead QFN and 20-Lead TSSOP Packages
12-Bit Monotonic
±1 LSB INL
4-Quadrant Multiplication
Power-On Reset with Brownout Detection
Readback Function
Industry-Standard Pin Configuration
APPLICATIONS
•
•
•
•
•
•
•
•
Portable Battery-Powered Instruments
Waveform Generators
Analog Processing
Programmable Amplifiers and Attenuators
Digitally-Controlled Calibration
Programmable Filters and Oscillators
Composite Video
Ultrasound
DESCRIPTION
The DAC7821 is a CMOS 12-bit current output
digital-to-analog converter (DAC). This device
operates from a single 2.5 V to 5.5 V power supply,
making it suitable to battery-powered and many other
applications.
This DAC operates with a fast parallel interface. Data
readback allows the user to read the contents of the
DAC register via the DB pins. On power-up, the
internal register and latches are filled with zeroes and
the DAC outputs are at zero scale.
The
DAC7821
offers
excellent
4-quadrant
multiplication characteristics, with large signal
multiplying bandwidth of 10 MHz. The applied
external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback
resistor (RFB) provides temperature tracking and
full-scale voltage output when combined with an
external current-to-voltage precision amplifier.
The DAC7821 is available in a 20-lead TSSOP
package as well as a small 20-lead QFN package
(available Q2 2006).
VDD
VREF
R
DAC7821
RFB
IOUT1
12-Bit
R-2R DAC
Power-On
Reset
IOUT2
DAC Register
Input Latch
CS
R/W
Control
Logic
Parallel Bus
DB0
DB11
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
DAC7821
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SBAS365A – OCTOBER 2005 – REVISED FEBRUARY 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
PRODUCT
PACKAGE
PACKAGE
DESIGNATOR
DAC7821
20-TSSOP
PW
–40°C to +125°C
DAC7821
DAC7821
20-QFN (2)
RGP
–40°C to +125°C
DAC7821
(1)
(2)
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
DAC7821IPW
70, Tube
DAC7821IPWR
2000, Tape and Reel
DAC7821IRGPT
250, Tape and Reel
DAC7821IRGPR
3000, Tape and Reel
For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or
refer to our web site at www.ti.com.
Available 2Q 2006.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
DAC7821
UNIT
–0.3 to +7.0
V
Digital input voltage to GND
–0.3 to VDD + 0.3
V
VOUT to GND
–0.3 to VDD + 0.3
V
Operating temperature range
–40 to +125
°C
Storage temperature range
–65 to +150
°C
Junction temperature (TJ max)
+150
°C
ESD Rating, HBM
3000
V
ESD Rating, CDM
1000
V
VDD to GND
(1)
2
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
DAC7821
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SBAS365A – OCTOBER 2005 – REVISED FEBRUARY 2006
ELECTRICAL CHARACTERISTICS
VDD = +2.5 V to +5.5 V; IOUT1 = Virtual GND; IOUT2 = 0V; VREF = +10 V; TA = full operating temperature. All specifications
–40°C to +125°C, unless otherwise noted.
DAC7821
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
12
Bits
Relative accuracy
±1
LSB
Differential nonlinearity
±1
LSB
±10
nA
Output leakage current
Data = 000h, TA = +25°C
Output leakage current
Data = 000h, TA = TMAX
Full-scale gain error
All ones loaded to DAC register
±5
Full-scale tempco
Output capacitance
Code dependent
±20
nA
±10
mV
±5
ppm/°C
30
pF
REFERENCE INPUT
VREF range
15
V
Input resistance
–15
8
10
12
kΩ
RFB resistance
8
10
12
kΩ
0.6
V
0.8
V
LOGIC INPUTS AND OUTPUT (1)
Input low voltage
VIL VDD = +2.7V
Input high voltage
VIH VDD = +2.7V
2.1
V
VIH VDD = +5V
2.4
V
VIL VDD = +5V
Input leakage current
Input capacitance
IIL
10
µA
CIL
10
pF
5.5
V
POWER REQUIREMENTS
VDD
2.7
IDD (normal operation)
Logic inputs = 0 V
5
µA
VDD = +4.5 V to +5.5 V
VIH = VDD and VIL = GND
0.8
5
µA
VDD = +2.5 V to +3.6 V
VIH = VDD and VIL = GND
0.4
2.5
µA
Reference multiplying BW
VREF = 7 VPP, Data = FFFh
10
MHz
DAC glitch impulse
VREF = 0 V to 10 V,
Data = 7FFh to 800h to 7FFh
5
nV-s
Feedthrough error VOUT/VREF
Data = 000h, VREF = 100kHz
–70
dB
2
nV-s
AC CHARACTERISTICS
Output voltage settling time
0.2
Digital feedthrough
µs
Total harmonic distortion
–105
dB
Output spot noise voltage
18
nV/√Hz
(1)
Specified by design and characterization; not production tested.
3
DAC7821
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SBAS365A – OCTOBER 2005 – REVISED FEBRUARY 2006
TIMING INFORMATION
R/W
t1
t6
t2
t2
t7
t3
CS
t4
t5
DATA VALID
DATA
t8
t9
DATA VALID
TIMING REQUIREMENTS: 2.5 V to 4.5 V
At tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; VDD = +2.5 V to +4.5 V, VREF = +10 V,
IOUT2 = 0 V. All specifications –40°C to +125°C, unless otherwise noted.
DAC7821
PARAMETER (1)
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t1
R/W to CS setup time
0
ns
t2
R/W to CS hold time
0
ns
t3
CS low time (write cycle)
10
ns
t4
Data setup time
6
ns
t5
Data hold time
0
ns
t6
R/W high to CS low
5
ns
t7
CS min high time
9
ns
t8
Data access time
t9
Bus relinquish time
20
40
ns
5
10
ns
Ensured by design; not production tested.
TIMING REQUIREMENTS: 4.5 V to 5.5 V
At tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; VDD = +4.5 V to +5.5 V, VREF = +10 V,
IOUT2 = 0 V. All specifications –40°C to +125°C, unless otherwise noted.
DAC7821
PARAMETER (1)
(1)
4
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t1
R/W to CS setup time
0
ns
t2
R/W to CS hold time
0
ns
t3
CS low time (write cycle)
10
ns
t4
Data setup time
6
ns
t5
Data hold time
0
ns
t6
R/W high to CS low
5
ns
t7
CS min high time
7
ns
t8
Data access time
t9
Bus relinquish time
Ensured by design; not production tested.
10
20
ns
5
10
ns
DAC7821
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SBAS365A – OCTOBER 2005 – REVISED FEBRUARY 2006
IOUT2
IOUT1
RFB
VREF
VDD
19
18
17
16
IOUT1
1
20
RFB
IOUT2
2
19
VREF
GND
3
18
VDD
DB11 (MSB)
4
17
R/W
GND
1
15
R/W
DB10
5
16
CS
DB11
2
14
CS
DB10
3
13
DB0
7
14
DB1
DB9
4
12
DB1
DB7
8
13
DB2
DB8
5
11
DB2
DB6
9
12
DB3
7
8
DB5
10
11
DB4
DB6
DB5
QFN-20
TSSOP-20
10
DB8
DB3
DB0 (LSB)
9
15
DB4
6
6
DAC7821
DB9
DB7
DAC7821
(1)
20
DEVICE INFORMATION
(1)
QFN-20 package available 2Q 2006.
TERMINAL FUNCTIONS
TERMINAL
TSSOP
NO.
QFN
NO.
NAME
1
19
IOUT1
DAC current output.
2
20
IOUT2
DAC analog ground. This pin is normally tied to the analog ground of the system.
3
1
GND
Ground pin.
4–15
2–13
DB11 – DB0
16
14
CS
Chip select input. Active low. Used in conjunction with R/W to load parallel data to the input
latch or read data from the DAC register. Rising edge of CS loads data.
17
15
R/W
Read/Write. When low, use in conjunction with CS to load parallel data. When high, use with
CS to read back contents of DAC register.
18
16
VDD
Positive power supply input. These parts can be operated from a supply of 2.5 V to 5.5 V.
19
17
VREF
DAC reference voltage input.
20
18
RFB
DAC feedback resistor pin. Establish voltage output for the DAC by connecting to external
amplifier output.
DESCRIPTION
Parallel data bits 11 to 0.
5
DAC7821
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SBAS365A – OCTOBER 2005 – REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS: VDD = +5 V
At TA = +25°C, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
TA = +25°C
VREF = +10 V
0.8
0.6
0.6
0.4
DNL (LSB)
INL (LSB)
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-0.8
-1.0
512
1024
1536
2048
2560
3072
3584
4095
0
512
1024
1536
2048
2560
3072
3584
Digital Input Code
Digital Input Code
Figure 1.
Figure 2.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
4095
1.0
TA = -40°C
VREF = +10 V
0.8
0.6
TA = -40°C
VREF = +10 V
0.8
0.6
0.4
DNL (LSB)
0.4
INL (LSB)
0
-0.2
-0.6
0
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536
2048
2560
3072
3584
4095
0
512
1024
1536
2048
2560
3072
3584
Digital Input Code
Digital Input Code
Figure 3.
Figure 4.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
4095
1.0
TA = +125°C
VREF = +10 V
0.8
0.6
TA = +125°C
VREF = +10 V
0.8
0.6
0.4
DNL (LSB)
0.4
INL (LSB)
0.2
-0.4
-1.0
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
6
TA = +25°C
VREF = +10 V
0.8
512
1024
1536
2048
2560
3072
3584
4095
0
512
1024
1536
2048
2560
Digital Input Code
Digital Input Code
Figure 5.
Figure 6.
3072
3584
4095
DAC7821
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SBAS365A – OCTOBER 2005 – REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, unless otherwise noted.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
REFERENCE MULTIPLYING BANDWIDTH
3.0
6
0
-6
-12
-18
-24
-30
-36
-42
-48
-56
-60
-66
-72
-78
-84
-90
-96
-102
VDD = 5.0 V
Attenuation (dB)
Supply Current (mA)
2.5
0xFFF
0x800
0x400
0x200
0x100
0x080
0x040
0x020
0x010
0x008
0x004
0x002
0x001
2.0
1.5
1.0
VDD = 3.0 V
VDD = 2.5 V
0.5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0x000
10
100
10k
1k
Logic Input Voltage (V)
100k
10M
1M
Figure 8.
MIDSCALE DAC GLITCH
MIDSCALE DAC GLITCH
Output Voltage (50mV/div)
Figure 7.
Output Voltage (50mV/div)
100M
Bandwidth (Hz)
Code 2047 to 2048
DAC Update
Code 2048 to 2047
DAC Update
Time (50ns/div)
Time (50ns/div)
Figure 9.
Figure 10.
DAC SETTLING TIME
GAIN ERROR
vs TEMPERATURE
0
VOUT = IOUT x 100 W
-0.2
Small Signal Settling
Gain Error (mV)
Output Voltage (%)
90
10
-0.4
DAC Update
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
Time (20 ns/div)
--2.0
VREF = +10 V
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Figure 11.
Figure 12.
7
DAC7821
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SBAS365A – OCTOBER 2005 – REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, unless otherwise noted.
SUPPLY CURRENT
vs TEMPERATURE
2.0
0.2
VREF = +10 V
0.18
1.6
Leakage Current (nA)
Quiescent Current (mA)
1.8
LEAKAGE CURRENT
vs TEMPERATURE
1.4
1.2
1.0
VDD = +5.0 V
0.8
0.6
0.4
0.14
0.12
0.10
0.08
0.06
0.04
VDD = +2.5 V
0.2
0.02
0
0
-40
-20
0
20
40
60
Temperature (°C)
Figure 13.
8
0.16
80
100
120
-40
-20
0
20
40
60
Temperature (°C)
Figure 14.
80
100
120
DAC7821
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SBAS365A – OCTOBER 2005 – REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS: VDD = +2.5 V
At TA = +25°C, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
TA = +25°C
VREF = +10 V
0.8
0.6
0.6
0.4
DNL (LSB)
INL (LSB)
0.4
0.2
0
-0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
0
512
1024
1536
2048
2560
3072
3584
4095
0
512
1024
1536
2048
2560
3072
3584
Digital Input Code
Digital Input Code
Figure 15.
Figure 16.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
4095
1.0
TA = -40°C
VREF = +10 V
0.8
0.6
TA = -40°C
VREF = +10 V
0.8
0.6
0.4
DNL (LSB)
0.4
INL (LSB)
0.2
-0.4
-1.0
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536
2048
2560
3072
3584
4095
0
512
1024
1536
2048
2560
3072
3584
Digital Input Code
Digital Input Code
Figure 17.
Figure 18.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
4095
1.0
TA = +125°C
VREF = +10 V
0.8
0.6
TA = +125°C
VREF = +10 V
0.8
0.6
0.4
DNL (LSB)
0.4
INL (LSB)
TA = +25°C
VREF = +10 V
0.8
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536
2048
2560
3072
3584
4095
0
512
1024
1536
2048
2560
Digital Input Code
Digital Input Code
Figure 19.
Figure 20.
3072
3584
4095
9
DAC7821
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SBAS365A – OCTOBER 2005 – REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS: VDD = +2.5 V (continued)
At TA = +25°C, unless otherwise noted.
MIDSCALE DAC GLITCH
Output Voltage (50mV/div)
Output Voltage (50mV/div)
MIDSCALE DAC GLITCH
Code 2047 to 2048
Code 2048 to 2047
DAC Update
2.0
1.8
DAC Update
Time (50ns/div)
Time (50ns/div)
Figure 21.
Figure 22.
GAIN ERROR
vs TEMPERATURE
LEAKAGE CURRENT
vs TEMPERATURE
0.2
VREF = +10 V
0.18
Leakage Current (nA)
Gain Error (mV)
1.6
1.4
1.2
1.0
0.8
0.6
0.14
0.12
0.10
0.08
0.06
0.4
0.04
0.2
0.02
0
0
-40
-20
0
20
40
60
Temperature (°C)
Figure 23.
10
0.16
80
100
120
-40
-20
0
20
40
60
Temperature (°C)
Figure 24.
80
100
120
DAC7821
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SBAS365A – OCTOBER 2005 – REVISED FEBRUARY 2006
THEORY OF OPERATION
The DAC7821 is a single channel current output, 12-bit digital-to-analog converter (DAC). The architecture,
illustrated in Figure 25, is an R-2R ladder configuration with the three MSBs segmented. Each 2R leg of the
ladder is either switched to IOUT1 or the IOUT2 terminal. The IOUT1 terminal of the DAC is held at a virtual GND
potential by the use of an external I/V converter op amp. The R-2R ladder is connected to an external reference
input VREF that determines the DAC full-scale current. The R-2R ladder presents a code-independent load
impedance to the external reference of 10 kΩ ±20%. The external reference voltage can vary over a range of
–15 V to +15 V, thus providing bipolar IOUT current operation. By using an external I/V converter and the
DAC7821 RFB resistor, output voltage ranges of –VREF to VREF can be generated.
R
R
R
R
VREF
2R
2R
2R
2R
2R
RFB
IOUT1
IOUT2
DB11
(MSB)
DB10
DB9
DB0
(LSB)
Figure 25. Equivalent R-2R DAC Circuit
When using an external I/V converter and the DAC7821 RFB resistor, the DAC output voltage is given by
Equation 1:
V OUT V REF CODE
4096
(1)
Each DAC code determines the 2R leg switch position to either GND or IOUT. Because the DAC output
impedance as seen looking into the IOUT1 terminal changes versus code, the external I/V converter noise gain
will also change. Because of this, the external I/V converter op amp must have a sufficiently low offset voltage
such that the amplifier offset is not modulated by the DAC IOUT1 terminal impedance change. External op amps
with large offset voltages can produce INL errors in the transfer function of the DAC7821 as a result of offset
modulation versus DAC code.
For best linearity performance of the DAC7821, an op amp with a low input offset voltage (OPA277) is
recommended (see Figure 26). This circuit allows VREF swinging from –10 V to +10 V.
VDD
VDD
VREF
DAC7821
GND
15V
RFB
IOUT1
IOUT2
V+
OPA277
VOUT
V-15V
Figure 26. Voltage Output Configuration
11
DAC7821
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SBAS365A – OCTOBER 2005 – REVISED FEBRUARY 2006
APPLICATION INFORMATION
Stability Circuit
For a current-to-voltage design (see Figure 27), the DAC7821 current output (IOUT) and the connection with the
inverting node of the op amp should be as short as possible and according to correct printed circuit board (PCB)
layout design. For each code change, there is a step function. If the gain bandwidth product (GBP) of the op amp
is limited and parasitic capacitance is excessive at the inverting node, then gain peaking is possible. Therefore,
for circuit stability, a compensation capacitor C1 (1 pF to 5 pF typ) can be added to the design, as shown in
Figure 27.
VDD
U1
VDD
VREF
RFB
C1
IOUT1
VREF
VOUT
IOUT2
GND
U2
Figure 27. Gain Peaking Prevention Circuit with Compensation Capacitor
Positive Voltage Output Circuit
As Figure 28 illustrates, in order to generate a positive voltage output, a negative reference is input to the
DAC7821. This design is suggested instead of using an inverting amp to invert the output as a result of resistor
tolerance errors. For a negative reference, VOUT and GND of the reference are level-shifted to a virtual ground
and a –2.5 V input to the DAC7821 with an op amp.
+2.5 V Reference
VDD
VIN
VOUT
GND
VDD
VREF
OPA277
RFB
C1
DAC7821 IOUT1
-2.5V
GND
IOUT2
OPA277
VOUT
0 < VOUT < +2.5 V
Figure 28. Positive Voltage Output Circuit
Bipolar Output Section
The DAC7821, as a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the
full-scale output IOUT is the inverse of the input reference voltage at VREF.
Some applications require full 4-quadrant multiplying capabilities or bipolar output swing. As shown in Figure 29,
external op amp U4 is added as a summing amp and has a gain of 2X that widens the output span to 5 V. A
4-quadrant multiplying circuit is implemented by using a 2.5 V offset of the reference voltage to bias U4.
According to the circuit transfer equation given in Equation 2, input data (D) from code 0 to full-scale produces
output voltages of VOUT = –2.5 V to VOUT = +2.5 V.
V OUT 12
0.5 D 2 1 V
N
REF
(2)
DAC7821
www.ti.com
SBAS365A – OCTOBER 2005 – REVISED FEBRUARY 2006
APPLICATION INFORMATION (continued)
External resistance mismatching is the significant error in Figure 29.
10 kW
10 kW
C2
VDD
VDD
+2.5 V
(+10 V)
5 kW
RFB
VREF DAC7821 IOUT1
GND
IOUT2
U4
OPA277
C1
VOUT
U2
OPA277
-2.5 V £ VOUT £ +2.5 V
(-10 V £ VOUT £ +10 V)
Figure 29. Bipolar Output Circuit
Programmable Current Source Circuit
A DAC7821 can be integrated into the circuit in Figure 30 to implement an improved Howland current pump for
precise voltage-to-current conversions. Bidirectional current flow and high voltage compliance are two features of
the circuit. With a matched resistor network, the load current of the circuit is shown by Equation 3:
R2R3R1
I L V REF D
R3
(3)
The value of R3 in the previous equation can be reduced to increase the output current drive of U3. U3 can drive
±20 mA in both directions with voltage compliance limited up to 15 V by the U3 voltage supply. Elimination of the
circuit compensation capacitor C1 in the circuit is not suggested as a result of the change in the output
impedance ZO, according to Equation 4:
R1R3R1R2
Z O R1R2R3 R1 R2R3
(4)
As shown in Equation 4, with matched resistors, ZO is infinite and the circuit is optimum for use as a current
source. However, if unmatched resistors are used, ZO is positive or negative with negative output impedance
being a potential cause of oscillation. Therefore, by incorporating C1 into the circuit, possible oscillation problems
are eliminated. The value of C1 can be determined for critical applications; for most applications, however, a
value of several pF is suggested.
R2¢
15 kW
C1
10 pF
R1¢
150 kW
VDD
U3
OPA277
VDD
VREF
RFB
U1
DAC7821 IOUT1
GND
IOUT2
R3¢
50 W
U2
OPA277
R1
150 kW
R2
15 kW
VOUT
R3
50 W
IL
LOAD
Figure 30. Programmable Bidirectional Current Source Circuit
13
DAC7821
www.ti.com
SBAS365A – OCTOBER 2005 – REVISED FEBRUARY 2006
APPLICATION INFORMATION (continued)
Parallel Interface
Data is loaded to the DAC7821 as a 12-bit parallel word. The bi-directional bus is controlled with CS and R/W,
allowing data to be written to or read from the DAC register. To write to the device, CS and R/W are brought low,
and data available on the data lines fills the input register. The rising edge of CS latches the data and transfers
the latched data-word to the DAC register. The DAC latches are not transparent; therefore, a write sequence
must consist of a falling and rising edge on CS in order to ensure that data is loaded to the DAC register and its
analog equivalent is reflected on the DAC output.
To read data stored in the device, R/W is held high and CS is brought low. Data is loaded from the DAC register
back to the input register and out onto the data line, where it can be read back to the controller.
Cross-Reference
The DAC7821 has an industry-standard pinout. Table 1 provides the cross-reference information.
Table 1. Cross-Reference
(1)
14
PRODUCT
INL (LSB)
DNL (LSB)
SPECIFIED
TEMPERATURE
RANGE
DAC7821
±1
±1
–40°C to +125°C
20-Lead TSSOP
TSSOP-20
AD5445
DAC7821
±1
±1
–40°C to +125°C
20-Lead QFN (1)
QFN-20
AD5445
Available 2Q 2006.
PACKAGE
DESCRIPTION
PACKAGE
OPTION
CROSSREFERENCE PART
PACKAGE OPTION ADDENDUM
www.ti.com
3-Apr-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DAC7821IPW
ACTIVE
TSSOP
PW
20
78
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC7821IPWG4
ACTIVE
TSSOP
PW
20
78
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC7821IPWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC7821IPWRG4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC7821IRGPR
PREVIEW
QFN
RGP
20
3000
TBD
Call TI
Call TI
DAC7821IRGPT
PREVIEW
QFN
RGP
20
250
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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