TI1 CY74FCT646ATSOCT 8-bit registered transceivers with 3-state output Datasheet

CY54FCT646T, CY74FCT646T
8-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS031A – JULY 1994 – REVISED OCTOBER 2001
D
D
D
D
D
D
D
D
D
D
Function, Pinout, and Drive Compatible
With FCT and F Logic
Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
Ioff Supports Partial-Power-Down Mode
Operation
Matched Rise and Fall Times
Fully Compatible With TTL Input and
Output Logic Levels
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Independent Register for A and B Buses
CY54FCT646T
– 48-mA Output Sink Current
– 12-mA Output Source Current
CY74FCT646T
– 64-mA Output Sink Current
– 32-mA Output Source Current
3-State Outputs
description
CY54FCT646T . . . D PACKAGE
CY74FCT646T . . . Q OR SO PACKAGE
(TOP VIEW)
CPAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
CPBA
SBA
G
B1
B2
B3
B4
B5
B6
B7
B8
CY54FCT646T . . . L PACKAGE
(TOP VIEW)
DIR
SAB
CPAB
NC
VCC
CPBA
SBA
D
4 3
A1
A2
A3
NC
A4
A5
A6
5
2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
G
B1
B2
NC
B3
B4
B5
B6
GND
NC
B8
B7
A7
A8
19
11
The ’FCT646T devices consist of a bus
12
13
14
15
16
17
18
transceiver circuit with 3-state, D-type flip-flops,
and control circuitry arranged for multiplexed
transmission of data directly from the input bus or
from the internal registers. Data on the A or B bus
NC – No internal connection
is clocked into the registers as the appropriate
clock pin goes to a high logic level. Output-enable (G) and direction (DIR) inputs control the transceiver function.
In the transceiver mode,data present at the high-impedance port can be stored in either the A or B register, or
in both. Select controls (SAB, SBA) can multiplex stored and real-time (transparent mode) data. DIR determines
which bus receives data when G is low. In the isolation mode (G is high), A data can be stored in the B register
and/or B data can be stored in the A register.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CY54FCT646T, CY74FCT646T
8-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS031A – JULY 1994 – REVISED OCTOBER 2001
PIN DESCRIPTION
NAME
DESCRIPTION
A
Data register A inputs, data register B outputs
B
Data register B inputs, data register A outputs
CPAB, CPBA
Clock-pulse inputs
SAB, SBA
Output data-source-select inputs
DIR, G
Output-enable inputs
ORDERING INFORMATION
SPEED
(ns)
PACKAGE†
TA
QSOP – Q
Tape and reel
5.4
CY74FCT646CTQCT
Tube
5.4
CY74FCT646CTSOC
Tape and reel
5.4
CY74FCT646CTSOCT
Tape and reel
6.3
CY74FCT646ATQCT
Tube
6.3
CY74FCT646ATSOC
Tape and reel
6.3
CY74FCT646ATSOCT
Tape and reel
9
CY74FCT646TQCT
Tube
9
CY74FCT646TSOC
Tape and reel
9
CY74FCT646TSOCT
LCC – L
Tube
6
CY54FCT646CTLMB
CDIP – D
Tube
7.7
CY54FCT646ATDMB
Tube
7.7
CY54FCT646ATLMB
Tube
11
SOIC – SO
QSOP – Q
–40°C to 85°C
SOIC – SO
QSOP – Q
SOIC – SO
–55°C
55°C to 125°C
ORDERABLE
PART NUMBER
LCC – L
TOP-SIDE
MARKING
FCT646C
FCT646C
FCT646A
FCT646A
FCT646
FCT646
CY54FCT646TLMB
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
DATA I/O‡
INPUTS
G
DIR
CPAB
CPBA
SAB
H
X
H or L
H or L
X
H
X
↑
↑
X
L
L
X
X
X
L
L
X
H or L
X
L
H
X
X
L
L
H
H or L
X
H
SBA
OPERATION
OR FUNCTION
A1–A8
B1–B8
X
Input
Input
Isolation
X
Input
Input
Store A and B data
L
Output
Input
Real-time B data to A bus
H
Output
Input
Stored B data to A bus
X
Input
Output
Real-time A data to B bus
X
Input
Output
Stored A data to B bus
H = High logic level, L = Low logic level, ↑ = Low-to-high transition, X = Don’t care
‡ The data output functions can be enabled or disabled by various signals at the G or DIR inputs. Data input
functions always are enabled, i.e., data at the bus pins is stored on every low-to-high transition of the
clock inputs.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CY54FCT646T, CY74FCT646T
8-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
21
G
L
3
DIR
L
1
CPAB
X
23
CPBA
X
2
SAB
X
BUS B
BUS A
BUS A
BUS B
SCCS031A – JULY 1994 – REVISED OCTOBER 2001
22
SBA
L
21
G
L
3
DIR
H
3
DIR
H
L
X
1
CPAB
↑
X
↑
23
CPBA
X
↑
↑
2
SAB
L
2
SAB
X
X
X
22
SBA
X
BUS B
BUS A
BUS A
21
G
L
L
H
23
CPBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
1
CPAB
X
22
SBA
X
X
X
STORAGE FROM
A AND/OR B
21
G
L
L
3
DIR†
L
H
1
CPAB
X
H or L
23
CPBA
H or L
X
2
SAB
X
H
22
SBA
H
X
TRANSFER STORED DATA
TO A AND/OR B
† Cannot transfer data to A bus and B bus simultaneously.
Figure 1. Bus-Management Functions
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
CY54FCT646T, CY74FCT646T
8-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS031A – JULY 1994 – REVISED OCTOBER 2001
logic diagram (positive logic)
G
DIR
CPBA
SBA
CPAB
SAB
21
3
23
22
1
2
One of Eight Channels
D
C
A1
4
20
B1
D
C
To Seven Other Channels
Pin numbers shown are for the Q and SO packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance, θJA (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CY54FCT646T, CY74FCT646T
8-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS031A – JULY 1994 – REVISED OCTOBER 2001
recommended operating conditions (see Note 2)
CY54FCT646T
CY74FCT646T
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
0.8
V
High-level output current
–12
–32
mA
IOL
TA
Low-level output current
48
64
mA
85
°C
High-level input voltage
2
Operating free-air temperature
–55
2
125
–40
V
V
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
CY54FCT646T, CY74FCT646T
8-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS031A – JULY 1994 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
CY54FCT646T
TYP† MAX
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.75 V,
IIN = –18 mA
IIN = –18 mA
VCC = 4.5 V,
IOH = –12 mA
IOH = –32 mA
VCC = 4
4.75
75 V
MIN
–0.7
–1.2
–0.7
2.4
2.4
Vhys
All inputs
II
VCC = 5.5 V,
VCC = 5.25 V,
VIN = VCC
VIN = VCC
5
IIH
VCC = 5.5 V,
VCC = 5.25 V,
VIN = 2.7 V
VIN = 2.7 V
±1
IIL
VCC = 5.5 V,
VCC = 5.25 V,
VIN = 0.5 V
VIN = 0.5 V
±1
IOZH
VCC = 5.5 V,
VCC = 5.25 V,
VOUT = 2.7 V
VOUT = 2.7 V
10
IOZL
VCC = 5.5 V,
VCC = 5.25 V,
VOUT = 0.5 V
VOUT = 0.5 V
–10
IOS‡
VCC = 5.5 V,
VCC = 5.25 V,
VOUT = 0 V
VOUT = 0 V
VCC = 0 V,
VCC = 5.5 V,
VOUT = 4.5 V
VIN ≤ 0.2 V,
∆ICC
ICCD¶
0.3
0.3
0.2
0.55
0.2
±1
±1
10
–10
–120
–225
–60
–120
±1
VIN ≥ VCC – 0.2 V
VIN ≥ VCC – 0.2 V
0.1
0.5
V
V
5
VIN ≤ 0.2 V,
VCC = 5.5 V, VIN = 3.4 V§, f1 = 0, Outputs open
VCC = 5.25 V,
3.3
0.55
IOL = 64 mA
–60
V
V
2
IOH = –15 mA
IOL = 48 mA
VCC = 4.5 V,
VCC = 4.75 V,
ICC
–1.2
UNIT
3.3
VOL
Ioff
CY74FCT646T
TYP† MAX
MIN
–225
±1
0.2
0.1
0.2
0.5
2
µA
µA
µA
µA
µA
mA
µA
mA
2
mA
VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open
VCC = 5.5 V, One input switching at 50% duty cycle,
Outputs open, G = DIR = GND, SAB = SBA = GND,
VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
VCC = 5.25 V, One input switching at 50% duty cycle,
Outputs open, G = DIR = GND, SAB = SBA = GND,
VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
0.06
0.12
mA/
MHz
0.06
0.12
† Typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or
sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged
shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence
of parameter tests, IOS tests should be performed last.
§ Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND
¶ This parameter is derived for use in total power-supply calculations.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CY54FCT646T, CY74FCT646T
8-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS031A – JULY 1994 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
CY54FCT646T
TYP† MAX
TEST CONDITIONS
VCC = 5.5
5 5 V,
V
f0 = 10 MHz,
Outputs open,
open
G = DIR = GND,
SAB = SBA = GND
IC#
VCC = 5
5.25
25 V
V,
f0 = 10 MHz,
Outputs open,
open
G = DIR = GND,
SAB = SBA = GND
MIN
CY74FCT646T
TYP† MAX
MIN
One bit
switching
at f1 = 5 MHz
at 50% duty
cycle
VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
0.7
1.4
VIN = 3.4 V or GND
1.2
3.4
Eight bits
switching
at f1 = 5 MHz
at 50% duty
cycle
VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
2.8
5.6||
VIN = 3.4 V or GND
5.1
14.6||
One bit
switching
at f1 = 5 MHz
at 50% duty
cycle
VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
0.7
1.4
VIN = 3.4 V or GND
1.2
3.4
Eight bits
switching
at f1 = 5 MHz
at 50% duty
cycle
VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
2.8
5.6||
VIN = 3.4 V or GND
5.1
14.6||
UNIT
mA
mA
Ci
Co
# IC
= ICC + ∆ICC × DH × NT + ICCD(f0/2 + f1 × N1)
Where:
IC
= Total supply current
ICC = Power-supply current with CMOS input levels
∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V)
DH
= Duty cycle for TTL inputs high
NT
= Number of TTL inputs at DH
ICCD = Dynamic current caused by an input transition pair (HLH or LHL)
f0
= Clock frequency for registered devices, otherwise zero
f1
= Input signal frequency
N1
= Number of inputs changing at f1
All currents are in milliamperes and all frequencies are in megahertz.
|| Values for these conditions are examples of the ICC formula.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
6
10
6
10
pF
8
12
8
12
pF
7
CY54FCT646T, CY74FCT646T
8-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS031A – JULY 1994 – REVISED OCTOBER 2001
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)
CY54FCT646T
MIN
tw
tsu
Pulse duration
th
Hold time, data after CPAB↑ or CPBA↑
Setup time, data before CPAB↑ or CPBA↑
MAX
CY54FCT646AT
MIN
MAX
CY54FCT646CT
MIN
MAX
UNIT
6
5
5
ns
4.5
2
2
ns
2
1.5
1.5
ns
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)
CY74FCT646T
MIN
MAX
CY74FCT646AT
MIN
MAX
CY74FCT646CT
MIN
MAX
UNIT
tw
tsu
Pulse duration
6
5
5
ns
Setup time, data before CPAB↑ or CPBA↑
4
2
2
ns
th
Hold time, data after CPAB↑ or CPBA↑
2
1.5
1.5
ns
switching characteristics over operating free-air temperature range (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPZH
tPZL
DIR
A or B
tPHZ
tPLZ
G and DIR
A or B
tPLH
tPHL
CPAB or CPBA
A or B
tPLH
tPHL
SBA or SAB
A or B
CY54FCT646T
CY54FCT646AT
CY54FCT646CT
MIN
MAX
MIN
MAX
MIN
MAX
2
11
2
7.7
1.5
6
2
11
2
7.7
1.5
6
2
15
2
10.5
1.5
8.9
2
15
2
10.5
1.5
8.9
2
11
2
7.7
1.5
7.7
2
11
2
7.7
1.5
7.7
2
10
2
7
1.5
6.3
2
10
2
7
1.5
6.3
2
12
2
8.4
1.5
7
2
12
2
8.4
1.5
7
UNIT
ns
ns
ns
ns
ns
switching characteristics over operating free-air temperature range (see Figure 2)
8
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPZH
tPZL
DIR
A or B
tPHZ
tPLZ
G and DIR
A or B
tPLH
tPHL
CPAB or CPBA
A or B
tPLH
tPHL
SBA or SAB
A or B
POST OFFICE BOX 655303
CY74FCT646T
CY74FCT646AT
CY74FCT646CT
MIN
MAX
MIN
MAX
MIN
MAX
1.5
9
1.5
6.3
1.5
5.4
1.5
9
1.5
6.3
1.5
5.4
1.5
14
1.5
9.8
1.5
7.8
1.5
14
1.5
9.8
1.5
7.8
1.5
9
1.5
6.3
1.5
6.3
1.5
9
1.5
6.3
1.5
6.3
1.5
9
1.5
6.3
1.5
5.7
1.5
9
1.5
6.3
1.5
5.7
1.5
11
1.5
7.7
1.5
6.2
1.5
11
1.5
7.7
1.5
6.2
• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
ns
ns
CY54FCT646T, CY74FCT646T
8-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS031A – JULY 1994 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
7V
From Output
Under Test
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
Open
TEST
GND
CL = 50 pF
(see Note A)
500 Ω
S1
500 Ω
S1
Open
7V
Open
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
500 Ω
LOAD CIRCUIT FOR
3-STATE OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
tsu
3V
1.5 V
Input
1.5 V
th
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
1.5 V
1.5 V
VOL
tPHL
Out-of-Phase
Output
tPLZ
≈3.5 V
1.5 V
tPZH
VOH
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
Output
Waveform 1
(see Note B)
tPLH
1.5 V
1.5 V
tPZL
VOH
In-Phase
Output
3V
Output
Control
Output
Waveform 2
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
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9
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9222301M3A
ACTIVE
LCCC
FK
28
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629222301M3A
5962-9222303M3A
ACTIVE
LCCC
FK
28
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629222303M3A
CY54FCT
646ATLMB
5962-9222303MLA
ACTIVE
CDIP
JT
24
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9222303ML
A
CY54FCT646ATDM
B
5962-9222305M3A
ACTIVE
LCCC
FK
28
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629222305M3A
CY54FCT
646CTLMB
CY54FCT646ATDMB
ACTIVE
CDIP
JT
24
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9222303ML
A
CY54FCT646ATDM
B
CY54FCT646ATLMB
ACTIVE
LCCC
FK
28
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629222303M3A
CY54FCT
646ATLMB
CY54FCT646CTLMB
ACTIVE
LCCC
FK
28
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629222305M3A
CY54FCT
646CTLMB
CY74FCT646ATQCT
ACTIVE
SSOP
DBQ
24
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FCT646A
CY74FCT646ATSOC
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT646A
CY74FCT646ATSOCT
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT646A
CY74FCT646ATSOCTE4
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT646A
CY74FCT646CTSOC
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT646C
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Aug-2014
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CY74FCT646CTSOCT
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT646C
CY74FCT646CTSOCTE4
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT646C
CY74FCT646TSOC
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT646
CY74FCT646TSOCT
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT646
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CY74FCT646ATQCT
SSOP
DBQ
24
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CY74FCT646ATSOCT
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
CY74FCT646CTSOCT
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
CY74FCT646TSOCT
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CY74FCT646ATQCT
SSOP
DBQ
24
2500
367.0
367.0
38.0
CY74FCT646ATSOCT
SOIC
DW
24
2000
367.0
367.0
45.0
CY74FCT646CTSOCT
SOIC
DW
24
2000
367.0
367.0
45.0
CY74FCT646TSOCT
SOIC
DW
24
2000
367.0
367.0
45.0
Pack Materials-Page 2
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