Allegro A1365LKTTN-5-T Low-noise, high-precision, programmable linear hall-effect sensor ic Datasheet

A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
FEATURES AND BENEFITS
• Proprietary segmented linear temperature compensation
(TC) technology provides a typical accuracy of 1% over
the full operating temperature range
• 120 kHz nominal bandwidth achieved via proprietary
packaging and chopper stabilization techniques
• Over Field Fault signal with 6-bit programmable trigger
levels, 2-bit programmable hysteresis, and latching or
non-latching behavior
• Over Field Fault response time < 4.5 μs (typ)
• Extremely low noise and high resolution achieved via
proprietary Hall element and low-noise amplifier circuits
• Customer-programmable, high-resolution offset and
sensitivity trim
• Available in a 1-mm-thick SIP through-hole package
• Factory-programmed sensitivity and quiescent
output voltage TC with extremely stable temperature
performance
Continued on the next page…
PACKAGE:
DESCRIPTION
The A1365 linear output Hall-effect sensor IC is specifically
designed to provide a highly accurate output with improved
resolution at high bandwidth for use in current-sensing
applications. This device employs a segmented, linearly
interpolated temperature compensation technology, which
provides greater accuracy in sensitivity and offset voltage
trimming and hence virtually zero temperature drift. This
improvement greatly reduces the total error of the device across
the operating temperature range.
The highly programmable Over Field Fault signal (FAULT
pin) can be used to detect a high magnetic field condition.
Broken ground wire detection, undervoltage lockout for VCC
below specification, and user-selectable output voltage clamps
are also included, which are important for high reliability in
automotive applications. The sensor accuracy and diagnostic
capability make it ideally suited for automotive sockets such
as HEV inverter and DC-to-DC converter applications.
The A1365 Hall-effect sensor IC is extremely sensitive, fast,
and temperature-stable. The accuracy and flexibility of this
device is enhanced by user programmability, performed via
the VCC supply and the output pins, which allows the device
to be optimized in the application.
4-Pin SIP (suffix KT)
This ratiometric Hall-effect sensor IC provides a voltage output
that is proportional to the applied magnetic field. The quiescent
output voltage is user-adjustable around 50% (bidirectional) of
Continued on the next page…
Not to scale
V+
VCC (Programming)
Programming
Control
Temperature
Sensor
CBYPASS
EEPROM and
Control Logic
Sensitivity Control
6-Bit Programmable Window Comparator
6 bits
VREF(High)
–
COMP_IN
+
0.88 × VCC to 0.72 × VCC
VREF(Low)
Offset Control
–
Internal
Pull-Up
FAULT
+
Dynamic Offset
Cancellation
0.12 × VCC to 0.28 × VCC
Signal Recovery
GND
Functional Block Diagram
A1365-GS-DS
VOUT
(Programming)
A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
FEATURES AND BENEFITS (CONTINUED)
• Selectable sensitivity range between 0.6 and 14 mV/G through
use of coarse sensitivity program bits
• Ratiometric sensitivity, quiescent voltage output, and
clamps enable simple interface with application A-to-D
converter (ADC)
• Output voltage clamps provide short-circuit diagnostic
capabilities
• Open-circuit detection on ground pin (broken wire)
• Undervoltage lockout for VCC below specification
• Wide ambient temperature range: –40°C to 150°C
DESCRIPTION (CONTINUED)
the supply voltage, VCC . The device sensitivity is adjustable within
the range of 0.6 to 14 mV/G.
The A1365 incorporates a highly sensitive Hall element with a
BiCMOS interface integrated circuit that employs temperaturecompensation circuitry to reduce the intrinsic sensitivity and offset
drift of the Hall element. The IC also includes a small-signal high-gain
amplifier, a clamped low-impedance output stage, and a proprietary
high-bandwidth dynamic offset cancellation technique.
Device specifications apply across an extended ambient temperature
range: –40°C to 150°C. The A1365 sensor IC is provided in an
extremely thin case (1 mm thick), 4-pin SIP (single inline package,
suffix KT) that is lead (Pb) free, with 100% matte-tin leadframe
plating. The thin package allows for better magnetic coupling because
the smaller the air gap in the core is, the higher the coupling from
current to magnetic field will be.
Selection Guide
Part Number
Package
Packing1
A1365LKTTN-1-T
A1365LKTTN-2-T
A1365LKTTN-5-T
A1365LKTTN-10-T
4-pin SIP
4-pin SIP
4-pin SIP
4-pin SIP
4000 pieces per 13-in. reel
4000 pieces per 13-in. reel
4000 pieces per 13-in. reel
4000 pieces per 13-in. reel
Sensitivity Range2
(mV/G)
0.6 to 1.3
1.3 to 2.9
2.9 to 6.4
6.4 to 14
1 Contact Allegro
for additional packing options.
recommends against changing Coarse Sensitivity settings when programming devices that will be used in production.
Each A1365 has been factory temperature compensated at a specific sensitivity range, and changing the coarse bits setting could
cause sensitivity drift through temperature range (ΔSensTC ) to exceed specified limits.
2 Allegro
Specifications
Absolute Maximum Ratings
Thermal Characteristics
Pinout Diagram and Terminal List Table
Operating Characteristics
Characteristic Performance Data
Characteristic Definitions
Functional Description
Programming Sensitivity and Quiescent
Voltage Output
Coarse Sensitivity
Memory-Locking Mechanisms
Power-On Reset (POR) and Undervoltage
Lockout (UVLO) Operation
Detecting Broken Ground Wire
Over Magnet Field Fault
3
3
3
4
5
9
13
19
19
19
19
20
21
22
Table of Contents
Programming Serial Interface
24
Package Outline Drawing
31
Transaction Types
Writing the Access Code
Writing to Volatile Memory
Writing to EEPROM
Reading from EEPROM or Volatile Memory
Error Checking
Serial Interface Reference
Serial Interface Message Structure
VCC Levels During Manchester Communication
Shadow Mode
EEPROM Margining
EEPROM Cell Organization
EEPROM Error Checking and Correction (ECC)
Detecting ECC Error
24
24
24
25
25
25
26
27
27
28
29
30
30
30
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
SPECIFICATIONS
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Unit
Forward Supply Voltage
VCC
6
V
Reverse Supply Voltage
VRCC
–0.1
V
Forward Output Voltage
VOUT
25
V
Reverse Output Voltage
VROUT
–0.1
V
Forward Fault Voltage
V F̄¯Ā¯Ū¯L̄¯T̄¯
6
V
Reverse Fault Voltage
VR F̄¯Ā¯Ū¯L̄¯T̄¯
–0.1
V
Output Source Current
IOUT(source)
VOUT to GND
2.8
mA
IOUT(sink)
VCC to VOUT
10
mA
100
cycles
–40 to 150
ºC
Tstg
–65 to 165
ºC
TJ(max)
165
ºC
Output Sink Current
Maximum Number of EEPROM Write
Cycles
EEPROMw(max)
Operating Ambient Temperature
TA
Storage Temperature
Maximum Junction Temperature
L temperature range
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Symbol
Package Thermal Resistance
RθJA
Test Conditions*
On 1-layer PCB with exposed copper limited to solder pads
Value
Unit
174
ºC/W
*Additional thermal information available on the Allegro website
Power Dissipation versus Ambient Temperature
900
800
Power Dissipation, PD (mW)
700
600
(R
500
qJ
A
=
17
4
400
ºC
/W
)
300
200
100
0
20
40
60
80
100
120
Temperature, TA (°C)
140
160
180
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
A1365
Pinout Diagram and Terminal List Table
Terminal List Table
1
Number
Name
1
VCC
Function
Input Power Supply, use bypass capacitor to connect to ground;
also used for programming
2
VOUT
Output Signal, also used for programming
3
F̄¯Ā¯Ū¯L̄¯T̄¯
Over Field Fault Detection Flag
4
GND
Ground
2 3 4
KT Package Pinout Diagram
(Ejector pin mark on opposite side)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
OPERATING CHARACTERISTICS: valid through the full operating temperature range TA, CBYPASS = 0.1 µF, and VCC = 5 V,
unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit1
Electrical Characteristics
Supply Voltage
VCC
4.5
5
5.5
V
–
10
15
mA
Supply Current
ICC
No load on VOUT, F̄¯Ā¯Ū¯L̄¯T̄¯ pin in highimpedance state, connected through a 10 kΩ
resistor to VCC
Power-On Time2
tPO
TA = 25°C, CBYPASS = open, CL = 1 nF
–
100
–
µs
Temperature Compensation
Power-On Time2
tTC
TA = 25°C, CBYPASS = open, CL = 1 nF
–
90
–
µs
VUVLOH
VCC rising and device function enabled
–
4
4.3
V
VUVLOL
VCC falling and device function disabled
3.05
3.2
–
V
tUVLOE
TA = 25°C, CBYPASS = open, CL = 1 nF,
VCC fall time (5 V to 3 V) = 1.5 μs
–
67
–
µs
tUVLOD
TA = 25°C, CBYPASS = open, CL = 1 nF,
VCC recover time (3 V to 5 V) = 1.5 μs
–
6
–
µs
VPORH
TA = 25°C, VCC rising
–
2.9
–
V
VPORL
TA = 25°C, VCC falling
–
2.5
–
V
tPORR
TA = 25°C, VCC rising
Undervoltage Lockout (UVLO)
Threshold2
UVLO Enable/Disable Delay Time2
Power-On Reset Voltage2
Power-On Reset Release
Time2
Supply Zener Clamp Voltage
Internal Bandwidth
Vz
BWi
TA = 25°C, ICC = 30 mA
–
85
–
µs
6.5
7.5
–
V
Small signal –3 dB, CL = 1 nF, TA = 25°C
–
120
–
kHz
fC
TA = 25°C
–
500
–
kHz
Propagation Delay Time2
tpd
TA = 25°C, step magnetic field of 400 G,
CL = 1 nF, Sens = 2 mV/G
–
2.2
–
µs
Rise Time2
tr
TA = 25°C, step magnetic field of 400 G,
CL = 1 nF, Sens = 2 mV/G
–
3.6
–
µs
Response Time2
tRESPONSE
TA = 25°C, step magnetic field of 400 G,
CL = 1 nF, Sens = 2 mV/G
–
3.7
–
µs
Delay to Clamp2,4
tCLP
TA = 25°C, step magnetic field from 160 to
240 G, CL = 1 nF, Sens = 10 mV/G
–
10
–
µs
Chopping Frequency3
VOUT Characteristics
Output Voltage Clamp5
Output Saturation Voltage2
Broken Wire Voltage2
Noise6
VCLP(HIGH)
TA = 25°C, RL(PULLDWN) = 10 kΩ to GND
4.55
–
4.85
V
VCLP(LOW)
TA = 25°C, RL(PULLUP) = 10 kΩ to VCC
0.15
–
0.45
V
VSAT(HIGH)
TA = 25°C, RL(PULLDWN) = 10 kΩ to GND
4.8
–
–
V
VSAT(LOW)
TA = 25°C, RL(PULLDWN) = 10 kΩ to VCC
–
–
300
mV
VBRK(HIGH)
TA = 25°C, RL(PULLUP) = 10 kΩ to VCC
–
VCC
–
V
VBRK(LOW)
TA = 25°C, RL(PULLDWN) = 10 kΩ to GND
–
200
–
mV
TA = 25°C, CL = 1 nF
–
1.1
–
mG/√(Hz)
TA = 25°C, CL = 1 nF, Sens = 2 mV/G,
bandwidth = BWi
–
6.3
–
mVp-p
TA = 25°C, CL = 1 nF, Sens = 2 mV/G,
bandwidth = BWi
–
1
–
mVRMS
VN
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
OPERATING CHARACTERISTICS (continued): valid through the full operating temperature range TA, CBYPASS = 0.1 µF,
and VCC = 5 V, unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit1
VOUT Characteristics (continued)
DC Output Resistance
Output Load Resistance
ROUT
–
< 10
–
Ω
RL(PULLUP)
TA = 25°C
VOUT to VCC
4.7
–
–
kΩ
RL(PULLDWN)
VOUT to GND
4.7
–
–
kΩ
Output Load Capacitance7
CL
VOUT to GND
–
1
10
nF
Output Slew Rate8
SR
Sens = 2 mV/G, CL = 1 nF, TA = 25°C;
step magnetic field of 400 G
–
230
–
V/ms
–
6
–
bit
Over Field Fault Characteristics
Fault Switchpoint Programming Bits
FAULT_
THRESH
Positive Field Fault Switchpoint
Range9
VFPSP
TA = 25°C, programmable using FAULT_
THRESH bits
0.72 × VCC
–
0.88 × VCC
V
Negative Field Fault Switchpoint
Range9
VFNSP
TA = 25°C, programmable using FAULT_
THRESH bits
0.12 × VCC
–
0.28 × VCC
V
–
16
–
mV
–
2
–
bit
TA = 25°C, FAULT_HYST = 0 (decimal),
FAULT_THRESH = 0, no hysteresis
–
0
–
mV
TA = 25°C, FAULT_HYST = 1 (decimal),
FAULT_THRESH = 0, VCC = 5 V
–
30
–
mV
TA = 25°C, FAULT_HYST = 2 (decimal),
FAULT_THRESH = 0, VCC = 5 V
–
60
–
mV
TA = 25°C, FAULT_HYST = 3 (decimal),
FAULT_THRESH = 0, maximum hysteresis
value, VCC = 5 V
–
120
–
mV
–
1
–
bit
Fault Switchpoint Step Size
Fault Hysteresis Programming Bits
Fault Hysteresis Level Range9
Enable Latched Fault Bit
StepFAULT
TA = 25°C, Average Fault Switchpoint step
size, VCC = 5 V
FAULT_HYST
VFHYST
FAULT_
LATCH
DC Fault Switchpoint Error
ErrDFS
FAULT_THRESH = 0 (decimal), RF(PULLUP) =
10 kΩ from F̄¯Ā¯Ū¯L̄¯T̄¯ to VCC; measured under
DC conditions, VFHYST = 60 mV
–
±40
–
mV
DC Fault Switchpoint Symmetry Error
ErrDFSS
FAULT_THRESH = 0 (decimal), RF(PULLUP) =
10 kΩ from F̄¯Ā¯Ū¯L̄¯T̄¯ to VCC; measured under
DC conditions, VFHYST = 60 mV
–
±60
–
mV
¯Ā¯Ū¯L̄¯T̄¯ Pin Low Output Voltage
F̄
V F̄¯Ā¯Ū¯L̄¯T̄¯L
RF(PULLUP) = 10 kΩ from F̄¯Ā¯Ū¯L̄¯T̄¯ to VCC
–
–
0.3
V
tTFR
RF(PULLUP) = 10 kΩ from F̄¯Ā¯Ū¯L̄¯T̄¯ to VCC,
CF = Open, FAULT_THRESH = 0, VOUT
step from VOUT(Q) to VOUT = 1.3 × (VFPSP VOUT(Q)) + VOUT(Q)
–
4.5
–
µs
tTFRL
RF(PULLUP) = 10 kΩ from F̄¯Ā¯Ū¯L̄¯T̄¯ to VCC,
CF = Open, FAULT_THRESH = 0, VFHYST =
0 mV, VOUT step from VOUT = 1.1 × (VFPSP
- VOUT(Q)) + VOUT(Q)
–
2.5
–
µs
Transient Fault Response Time10
Transient Fault Release Time
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
OPERATING CHARACTERISTICS (continued): valid through the full operating temperature range, TA, CBYPASS = 0.1 µF,
and VCC = 5 V, unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit1
Fault Characteristics (continued)
Fault Delay Due to Load Capacitance
tFDC
RF(PULLUP) = 10 kΩ from F̄¯Ā¯Ū¯L̄¯T̄¯ to VCC
–
0.5
–
µs / nF
External Pull-Up Supply Voltage
VF(PULLUP)
1.65
VCC
VCC
V
¯Ā¯Ū¯L̄¯T̄¯ Pull-Up Resistor
External F̄
RF(PULLUP)
4.7
–
–
kΩ
CF
–
–
10
nF
¯Ā¯Ū¯L̄¯T̄¯ Pull-Up Resistor
Internal F̄
RIF(PULLUP)
–
10
–
kΩ
¯Ā¯Ū¯L̄¯T̄¯ Pull-Up Current
Internal F̄
IIF(PULLUP)
–
40
–
µA
¯Ā¯Ū¯L̄¯T̄¯ Capacitance
External F̄
Quiescent Voltage Output
(VOUT(Q))2
Initial Unprogrammed Quiescent
Voltage Output2,11
VOUT(Q)init
TA = 25°C
2.4
2.5
2.6
V
Quiescent Voltage Output
Programming Range2,5,12
VOUT(Q)PR
TA = 25°C
2.3
–
2.7
V
Quiescent Voltage Output
Programming Bits13
QVO
–
9
–
bit
1.9
2.3
2.8
mV
–
±0.5 ×
StepVOUT(Q)
–
mV
Average Quiescent Voltage Output
Programming Step Size2,14,15
StepVOUT(Q)
Quiescent Voltage Output
Programming Resolution2,16
ErrPGVOUT(Q) TA = 25°C
TA = 25°C
Sensitivity (Sens)2
Initial Unprogrammed Sensitivity11
Sensitivity Programming Range5,12
Coarse Sensitivity Programming
Bits17
Fine Sensitivity Programming Bits13
Average Fine Sensitivity and
Temperature Compensation
Programming Step Size2,14,15
Sensitivity Programming
Resolution2,16
Sensinit
SENS_COARSE = 00, TA = 25°C
–
1
–
mV/G
SENS_COARSE = 01, TA = 25°C
–
2.2
–
mV/G
SENS_COARSE = 10, TA = 25°C
–
4.7
–
mV/G
SENS_COARSE = 11, TA = 25°C
–
9.6
–
mV/G
SENS_COARSE = 00, TA = 25°C
0.6
–
1.3
mV/G
SENS_COARSE = 01, TA = 25°C
1.3
–
2.9
mV/G
SENS_COARSE = 10, TA = 25°C
2.9
–
6.4
mV/G
SENS_COARSE = 11, TA = 25°C
6.4
–
14
mV/G
SENS_
COARSE
–
2
–
bit
SENS_FINE
–
9
–
bit
SENS_COARSE = 00, TA = 25°C
2.4
3.2
4.1
µV/G
SENS_COARSE = 01, TA = 25°C
5
6.6
8.5
µV/G
SensPR
StepSENS
ErrPGSENS
SENS_COARSE = 10, TA = 25°C
11
14.2
18
µV/G
SENS_COARSE = 11, TA = 25°C
22
29
38
µV/G
TA = 25°C
–
±0.5 ×
StepSENS
–
µV/G
–
0
–
%/°C
Factory-Programmed Sensitivity Temperature Coefficient
Sensitivity Temperature Coefficient2
TCSENS
Sensitivity Drift Through Temperature
Range2,12,18,23
ΔSensTC
TA=150°C, TA= –40°C, calculated relative to
25°C
TA = 25°C to 150°C
–2.5
–
2.5
%
TA = –40°C to 25°C
–3
–
3
%
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
A1365
OPERATING CHARACTERISTICS (continued): valid through the full operating temperature range, TA, CBYPASS = 0.1 µF,
and VCC = 5 V, unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit1
–
0
–
mV/°C
–10
–
10
mV
Factory-Programmed Quiescent Voltage Output Temperature Coefficient
Quiescent Voltage Output
Temperature Coefficient2
Quiescent Voltage Output Drift
Through Temperature Range2,12,18
Average Quiescent Voltage
Output Temperature Compensation
Step Size
TCQVO
ΔVOUT(Q)TC
TA = 150°C, TA = –40°C, calculated relative
to 25°C
SENS_COARSE = 00, SENS_COARSE = 01,
or SENS_COARSE = 10, TA = 25°C to 150°C
SENS_COARSE = 11, TA = 25°C to 150°C
–15
–
15
mV
TA = –40°C to 25°C
–30
–
30
mV
StepQVOTC
–
2.3
–
mV
EELOCK
–
1
–
bit
LinERR
–1
< ±0.25
1
%
SymERR
–0.5
< ±0.25
0.5
%
–0.3
0
0.3
%
< ±0.5
1
%
Lock Bit Programming
EEPROM Lock Bit
Error Components
Linearity Sensitivity Error2,19
Symmetry Sensitivity
Error2
Ratiometry Quiescent Voltage Output
Error2,20
Ratiometry Sensitivity Error2,20
Ratiometry Clamp
Error2,21
RatERRVOUT(Q) Relative to VCC = 5 V ±5%
RatERRSens
Relative to VCC = 5 V ±5%
–1
RatERRCLP
TA = 25ºC, Relative to VCC = 5 V ±5%
–
< ±1
–
%
Sensitivity Drift Due to Package
Hysteresis2
ΔSensPKG
TA = 25°C, after temperature cycling, 25°C to
150°C and back to 25°C
–
-1.25
±1.25
–
%
Sensitivity Drift Over Lifetime22
ΔSensLIFE
TA = 25°C, shift after AEC Q100 grade 0
qualification testing
–
±1%
–
%
11
G (gauss) = 0.1 mT (millitesla).
Characteristic Definitions section.
2 See
3 f varies up to approximately ±5% over the full operating ambient
C
4 If the programmed Fault Switchpoint exceeds the clamp voltage,
temperature range, TA.
Fault operation will have priority over clamp operation.
VOUT(Q) , VCLP(LOW) , and VCLP(HIGH) scale with VCC due to ratiometry.
6 Noise, measured in mV
PP and in mVRMS , is dependent on the sensitivity of the device.
7 Output stability is maintained for capacitive loads as large as 10 nF.
8 High-to-low transition of output voltage is a function of external load components and device sensitivity.
9 Fault Switchpoint and Fault Hysteresis are ratiometric.
10 Refer to Fault Characteristics section for the impact of load circuit and different Fault switchpoint settings on Transient Fault
Response Time.
11 Raw device characteristic values before any programming.
12 Exceeding the specified ranges will cause sensitivity and Quiescent Voltage Output drift through the temperature range to deteriorate beyond the specified values.
13 Refer to Functional Description section.
14 Step size is larger than required, in order to provide for manufacturing spread. See Characteristic Definitions section.
15 Non-ideal behavior in the programming DAC can cause the step size at each significant bit rollover code to be greater than twice the maximum specified value of
StepVOUT(Q) or StepSENS.
16 Overall programming value accuracy. See Characteristic Definitions section.
17 Each A1365 part number is factory-programmed and temperature compensated at a different coarse sensitivity setting. Changing coarse bits setting could cause sensitivity drift through temperature range ,ΔSensTC , to exceed specified limits.
18 Allegro will be testing and temperature compensating each device at 150°C. Allegro will not be testing devices at –40°C. Temperature compensation codes will be applied
based on characterization data.
19 Linearity applies to output voltage ranges of ±2 V from the quiescent output for bidirectional devices.
20 Percent change from actual value at V
CC = 5 V, for a given temperature, through the supply voltage operating range.
21 Percent change from actual value at V
CC = 5 V, TA = 25°C, through the supply voltage operating range.
22 Based on characterization data obtained during standardized stress test for Qualification of Integrated Circuits. Cannot be guaranteed. Drift is a function of customer application conditions. Contact Allegro MicroSystems for further information.
23 Includes sensitivity drift due to package hysteresis after exposing the sensor to a temperature of 150ºC for 60 seconds during test.
5 Sens,
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
CHARACTERISTIC PERFORMANCE DATA
Response Time (tRESPONSE)
400 G Excitation Signal with 10% - 90% rise time = 1 µs
Sensitivity = 2 mV/G, CBYPASS = 0.1 µF, CL = 1 nF
Input = 400 G Excitation Signal
80% of Input
Output (VOUT, mV)
80% of Output
tRESPONSE = 3.64 µs
C1
FLT DC1M C1
FLT DC1M
1.00 V/div
-3.0100 V
3.0681 V
3.8212 V
200 mV/div
-3.10600 V
2.49230 V
3.13220 V
Timebase -6.96 µs Trigger C1 DC
2.00 µs/div Stop
830 mV
50.0 ks
2.5 GS/s Edge
Positive
X1 =
467.6 ns X =
3.6444 µs
X2 = 4.1120 µs 1/X = 274.390 kHz
11/6/2013 10:23:51 AM
Propagation Delay (tPD)
400 G Excitation Signal with 10% - 90% rise time = 1 µs
Sensitivity = 2 mV/G, CBYPASS = 0.1 µF, CL = 1 nF
Input = 400 G Excitation Signal
Output (VOUT, mV)
tPD = 2.1 µs
20% of Output
20% of Input
C1
FLT DC1M C2
FLT DC1M
1.00 V/div
-3.0100 V
767.5 V
3.7877 V
200 mV/div
-3.10600 V
2.50227 V
2.65287 V
Timebase -6.96 µs Trigger C1 DC
2.00 µs/div Stop
830 mV
50.0 ks
2.5 GS/s Edge
Positive
X =
X1 =
-33.2 ns
2.0216 µs
X2 = 1.9884 µs 1/X = 494.66 kHz
11/6/2013 10:22:47 AM
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
Rise Time (tr)
400 G Excitation Signal with 10% - 90% rise time = 1 µs
Sensitivity = 2 mV/G, CBYPASS = 0.1 µF, CL = 1 nF
Output (VOUT, mV)
Input = 400 G Excitation Signal
90% of Output
tR = 3.15 µs
10% of Input
C1
FLT DC1M C2
FLT DC1M
1.00 V/div
-3.0100 V
3.7602 V
3.8268 V
200 mV/div
-3.10600 V
2.57280 V
3.21215 V
Timebase -6.96 µs Trigger C1 DC
2.00 µs/div Stop
830 mV
50.0 ks
2.5 GS/s Edge
Positive
X =
X1 = 1.6316 µs
3.1448 µs
X2 = 4.7764 µs 1/X = 317.99 kHz
11/6/2013 10:21:02 AM
Power-On Time (tPO)
400 G Constant Excitation Signal with VCC 10% - 90% rise time = 1 µs
Sensitivity = 2 mV/G, CBYPASS = Open, CL = 1 nF
Supply (VCC, V)
VCC(min)
Output (VOUT, V)
90% of Output
tPO = 97 µs
C1 F BwL DC1M C2 F BwL DC1M
1.00 V/div
1.00 V/div
-3.0000 V
-3.0000 V
63.4 mV
4.5241 V
3.0335 V
4.9957 V
2.9701 V
471.6 mV y
y
Timebase -120 µs Trigger C1 DC
3.13 V
50.0 µs/div Stop
Positive
10.0 ks
20 MS/s Edge
X1 =
1.05 µs X =
96.75 µs
X2 = 97.80 µs 1/X = 10.336 kHz
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
Temperature Compensation Power-On Time (tTC)
400G Constant Excitation Signal, with VCC 10%-90% rise time = 1.5 μs
Sensitivity = 2mV/G, CBYPASS = Open, CL = 1 nF
Supply (VCC, V)
Output (VOUT, V)
90% of Temperature
Compensated Output
90% of Output
tTC = 89 µs
Timebase -120 µs Trigger C1 DC
3.13 V
50.0 µs/div Stop
Positive
10.0 ks
20 MS/s Edge
X1 = 97.80 µs X =
88.45 µs
X2 = 186.25 µs 1/X = 11.306 kHz
C1 F BwL DC1M C2 F BwL DC1M
1.00 V/div
1.00 V/div
-3.0000 V
-3.0000 V
3.0335 V
4.9957 V
3.4127 V
5.0019 V
379.2 mV
6.2 mV y
y
UVLO Enable Time (tUVLOE)
VCC 5 V - 3 V fall time = 1.5 µs
Sensitivity = 2 mV/G, CBYPASS = Open, CL = 1 nF
Supply (VCC, V)
tUVLOE = 67 µs
VUVLOL
Output (VOUT, V)
Output = 0 V
C1 F BwL DC1M C2 F BwL DC1M
1.00 V/div
1.00 V/div
-3.0000 V
-3.0000 V
3.5134 V
2.6689 V
3.0227 V
12.7 mV
-490.6 mV y
-2.6561 V
y
-2.5628 ms Trigger C1 DC
3.54 V
20.0 µs/div Stop
Positive
10.0 ks
50 MS/s Edge
X
=
X1 = 2.50062 ms
66.66 µs
X2 = 2.56728 ms 1/X = 15.002 kHz
Tbase
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
UVLO Disable Time (tUVLOD)
VCC 3.2 V - 5 V Recovery Time = 1.5 µs
Sensitivity = 2 mV/G, CBYPASS = Open, CL = 1 nF
Supply (VCC, V)
VCC(min)
tUVLOD = 6 µs
Output (VOUT, V)
90% of Output
C1 A F B DC1M C2 A F B DC1M
1.00 V/div
1.00 V/div
-3.0000 V
-3.0000 V
539 #
539 #
92.6 mV
4.5048 V
2.2821 V
5.0297 V
y
2.1895 V
524.9 mV y
Timebase
-6.4 µs Trigger C1 DC
3.54 V
5.00 µs/div Stop
Positive
10.0 ks 200 MS/s Edge
X = 6.000 µs
X1 = -2.285 µs
X2 = 3.715 µs
1/X = 166.7 kHz
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
CHARACTERISTIC DEFINITIONS
Power-On Time (tPO)
When the supply is ramped to its operating voltage, the device
requires a finite time to power its internal components before
responding to an input magnetic field.
Power-On Time (tPO ) is defined as: the time it takes for the
output voltage to settle within ±10% of its steady-state value
under an applied magnetic field, after the power supply has
reached its minimum specified operating voltage (VCC(min)) as
shown in Figure 1.
V
VCC
VCC(typ)
VOUT
90% VOUT
VCC(min)
t1
t2= time at which output voltage settles
within ±10% of its steady-state value
under an applied magnetic field
After Power-On Time (tPO ) elapses, tTC is also required before a
valid temperature compensated output.
0
Propagation Delay (tpd)
(%)
90
The time interval between a) when the sensor IC reaches 10% of
its final value, and b) when it reaches 90% of its final value (see
Figure 2). Both tr and tRESPONSE are detrimentally affected by
eddy current losses observed in the conductive IC ground plane.
A large magnetic input step may cause the clamp to overshoot
its steady-state value. The Delay to Clamp (tCLP ) is defined
as: the time it takes for the output voltage to settle within
steady-state clamp voltage ±1% of Clamp Voltage Dynamic
Range, after initially passing through its steady-state voltage, as
shown in Figure 4. Clamp Voltage Dynamic Range is defined as
VCLP(HIGH) (min) – VCLP(LOW) (max).
Applied Magnetic Field
Transducer Output
Rise Time, tr
20
10
0
Response Time (tRESPONSE)
Delay to Clamp (tCLP )
+t
Figure 1: Power-On Time Definition
Rise Time (tr)
The time interval between a) when the applied magnetic field
reaches 80% of its final value, and b) when the sensor reaches
80% of its output corresponding to the applied magnetic field
(see Figure 3).
tPO
t1= time at which power supply reaches
minimum specified operating voltage
Temperature Compensation Power-On Time
(tTC )
The time interval between a) when the applied magnetic field
reaches 20% of its final value, and b) when the output reaches
20% of its final value (see Figure 2).
t2
Propagation Delay, tpd
t
Figure 2: Propagation Delay and Rise Time Definitions
(%)
80
Applied Magnetic Field
Transducer Output
Response Time, tRESPONSE
0
t
Figure 3: Response Time Definition
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
A1365
Quiescent Voltage Output (VOUT(Q))
In the quiescent state (no significant magnetic field: B = 0 G),
the output (VOUT(Q) ) has a constant ratio to the supply voltage
(VCC ) throughout the entire operating ranges of VCC and ambient
temperature (TA) .
Initial Unprogrammed Quiescent Voltage
Output ( VOUT(Q)init )
Before any programming, the Quiescent Voltage Output
(VOUT(Q)) has a nominal value of VCC / 2, as shown in Figure 5.
Quiescent Voltage Output Programming
Range ( VOUT(Q)PR )
The Quiescent Voltage Output (VOUT(Q) ) can be programmed
within the Quiescent Voltage Output Range limits: VOUT(Q)PR(min)
and VOUT(Q)PR(max). Exceeding the specified Quiescent Voltage
Output Range will cause Quiescent Voltage Output Drift Through
Temperature Range ΔVOUT(Q)TC to deteriorate beyond the specified values, as shown in Figure 5.
Average Quiescent Voltage Output Programming Step Size (StepVOUT(Q))
The Average Quiescent Voltage Output Progamming Step Size
(StepVOUT(Q) ) is determined using the following calculation:
StepVOUT(Q) =
VOUT(Q)maxcode – VOUT(Q)mincode
2n – 1
,
where n is the number of available programming bits in the trim range,
9 bits, VOUT(Q)maxcode is at decimal code 255, and VOUT(Q)mincode is at
decimal code 256.
Quiescent Voltage Output Programming
Resolution (ErrPGVOUT(Q) )
The programming resolution for any device is half of its programming step size. Therefore, the typical programming resolution will be:
ErrPGVOUT(Q)(typ) = 0.5 × StepVOUT(Q)(typ)
Device VOUT(Q) changes as temperature changes, with respect to
its programmed Quiescent Voltage Output Temperature Coefficient, TCQVO . TCQVO is programmed at 150°C and is calculated
relative to the nominal VOUT(Q) programming temperature of
25°C. TCQVO (mV/°C) is defined as:
VOUT
tCLP
t1
VOUT(Q)EXPECTED(TA) = VOUT(Q)T1 + TCQVO(TA – T1)
t2
t1= time at which output voltage initially
reaches steady-state clamp voltage
t2= time at which output voltage settles to
steady-state clamp voltage ±1% of the
clamp voltage dynamic range, where
clamp voltage dynamic range =
VCLP(HIGH)(min) – VCLP(LOW)(max)
Note: Times apply to both high clamp
(shown) and low clamp.
0
Figure 4: Delay to Clamp Definition
(3)
where T1 is the nominal VOUT(Q) programming temperature of
25°C, and T2 is the TCQVO programming temperature of 150°C.
The expected VOUT(Q) through the full ambient temperature range
(VOUT(Q)EXPECTED(TA) ) is defined as:
Magnetic Input
VCLP(HIGH)
(2)
Quiescent Voltage Output Temperature Coefficient (TCQVO)
TCQVO = [VOUT(Q)T2 – VOUT(Q)T1][1/(T2 – T1)]
V
(1)
t
VOUT(Q)PR(min)
value
Distribution of values
resulting from minimum
programming code
(QVO programming bits
set to decimal code 256)
VOUT(Q)
Programming range
(specified limits)
Typical initial value before
customer programming
VOUT(Q)init
(QVO programming
bits set to code 0)
(4)
VOUT(Q)PR(max)
value
Distribution of values
resulting from maximum
programming code
(QVO programming bits
set to decimal code 255)
Figure 5: Quiescent Voltage Output Range Definition
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115 Northeast Cutoff
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14
A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
VOUT(Q)EXPECTED(TA) should be calculated using the actual
measured values of VOUT(Q)T1 and TCQVO rather than programming target values.
Quiescent Voltage Output Drift Through Temperature Range (ΔVOUT(Q)TC)
Due to internal component tolerances and thermal considerations,
the Quiescent Voltage Output (VOUT(Q)) may drift from its
nominal value through the operating ambient temperature (TA ).
The Quiescent Voltage Output Drift Through Temperature Range
(ΔVOUT(Q)TC) is defined as:
DVOUT(Q)TC = VOUT(Q)(TA) – VOUT(Q)EXPECTED(TA)
(5)
∆VOUT(Q)TC should be calculated using the actual measured
values of ∆VOUT(Q)(TA) and ∆VOUT(Q)EXPECTED(TA) rather than
programming target values.
Sensitivity (Sens)
The presence of a south polarity magnetic field, perpendicular
to the branded surface of the package face, increases the output
voltage from its quiescent value toward the supply voltage rail.
The amount of the output voltage increase is proportional to the
magnitude of the magnetic field applied.
Conversely, the application of a north polarity field decreases the
output voltage from its quiescent value. This proportionality is
specified as the magnetic sensitivity, Sens (mv/G), of the device,
and it is defined as:
Sens =
VOUT(BPOS) – VOUT(BNEG)
BPOS – BNEG
,
(6)
where BPOS and BNEG are two magnetic fields with opposite
polarities.
Branded
Face
Mold Ejector
Pin Indent
Initial Unprogrammed Sensitivity ( Sensinit )
Before any programming, Sensitivity has a nominal value that
depends on the SENS_COARSE bits setting. Each A1365 variant
has a different SENS_COARSE setting.
Sensitivity Programming Range (SensPR)
The magnetic sensitivity (Sens) can be programmed around its
initial value within the sensitivity range limits: SensPR(min) and
SensPR(max). Exceeding the specified Sensitivity Range will
cause Sensitivity Drift Through Temperature Range ΔSensTC to
deteriorate beyond the specified values. Refer to the Quiescent
Voltage Output Range section for a conceptual explanation of
how value distributions and ranges are related.
Average Fine Sensitivity Programming Step
Size (StepSENS)
Refer to the Average Quiescent Voltage Output Programming
Step Size section for a conceptual explanation.
Sensitivity Programming Resolution ( ErrPGSENS)
Refer to the Quiescent Voltage Output Programming Resolution
section for a conceptual explanation.
Sensitivity Temperature Coefficient (TCSENS)
Device sensitivity changes as temperature changes, with respect
to its programmed sensitivity temperature coefficient, TCSENS .
TCSENS is programmed at 150°C, and calculated relative to the
nominal sensitivity programming temperature of 25°C. TCSENS
(%/°C) is defined as:
TCSENS =
SensT2 – SensT1
1
× 100% T2–T1
SensT1
(7)
where T1 is the nominal Sens programming temperature of 25°C,
and T2 is the TCSENS programming temperature of 150°C. The
expected value of Sens over the full ambient temperature range,
SensEXPECTED(TA), is defined as:
SensEXPECTED(TA) = SensT1 × 100% +
Magnetic Flux
Direction Causing the
Output to Increase
,
TCSENS (TA –T1)
100
(8)
SensEXPECTED(TA) should be calculated using the actual measured
values of SensT1 rather than programming target values.
Figure 6: Magnetic Flux Polarity
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115 Northeast Cutoff
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15
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
A1365
Sensitivity Drift Through Temperature Range
(ΔSensTC )
Second-order-sensitivity temperature-coefficient effects cause the
magnetic sensitivity, Sens, to drift from its expected value over
the operating ambient temperature range (TA). The Sensitivity
Drift Through Temperature Range (∆SensTC ) is defined as:
∆SensTC =
SensTA – SensEXPECTED(TA)
SensEXPECTED(TA)
× 100% .
(9)
Sensitivity Drift Due to Package Hysteresis
(ΔSensPKG )
Package stress and relaxation can cause the device sensitivity at
TA = 25°C to change during and after temperature cycling. The
sensitivity drift due to package hysteresis (∆SensPKG ) is defined
as:
∆SensPKG =
Sens(25°C)2 – Sens(25°C)1
× 100%
Sens(25°C)1
,
(10)
where Sens(25°C)1 is the programmed value of sensitivity at TA = 25°C,
and Sens(25°C)2 is the value of sensitivity at TA = 25°C, after temperature cycling TA up to 150°C and back to 25°C.
Linearity Sensitivity Error (LinERR )
The A1365 is designed to provide a linear output in response to
a ramping applied magnetic field. Consider two magnetic fields,
B1 and B2. Ideally, the sensitivity of a device is the same for both
fields, for a given supply voltage and temperature. Linearity error
is present when there is a difference between the sensitivities
measured at B1 and B2.
Linearity Error
Linearity error is calculated separately for the positive
(LinERRPOS ) and negative (LinERRNEG ) applied magnetic fields.
Linearity Error (%) is measured and defined as:
 SensBPOS2 
 × 100%
LinERRPOS = 1–
 SensBPOS1 
,
 SensBNEG2
 × 100%
LinERRNEG = 1–
 SensBNEG1
,
|VOUT(Bx) – VOUT(Q)|
Bx
,
Then:
LinERR = max( LinERRPOS , LinERRNEG )
.
(13)
Symmetry Sensitivity Error (SymERR )
The magnetic sensitivity of an A1365 device is constant for any
two applied magnetic fields of equal magnitude and opposite
polarities. Symmetry Error, SymERR (%), is measured and
defined as:
 SensBPOS
SymERR = 1–
 SensBNEG

 × 100%

,
(14)
where SensBx is as defined in equation 12, and BPOSx and
BNEGx are positive and negative magnetic fields such that
|BPOSx| = |BNEGx|.
Ratiometry Error (RatERR )
The A1365 device features ratiometric output. This means that
the Quiescent Voltage Output (VOUT(Q) ) magnetic sensitivity,
Sens, and Output Voltage Clamp (VCLP(HIGH) and VCLP(LOW) ) are
proportional to the Supply Voltage (VCC). In other words, when
the supply voltage increases or decreases by a certain percentage, each characteristic also increases or decreases by the same
percentage. Error is the difference between the measured change
in the supply voltage relative to 5 V, and the measured change in
each characteristic.
The ratiometric error in Quiescent Voltage Output,
RatERRVOUT(Q) (%), for a given supply voltage (VCC) is defined
as:
 VOUT(Q)(VCC) / VOUT(Q)(5V) 
 × 100% . (15)
RatERRVOUT(Q) = 1–
VCC / 5 V


The ratiometric error in magnetic sensitivity, RatERRSens (%), for
a given Supply Voltage (VCC ) is defined as:
(11)
where:
SensBx =
and BPOSx and BNEGx are positive and negative magnetic
fields, with respect to the quiescent voltage output such that
|BPOS2| = 2 × |BPOS1| and |BNEG2| = 2 × |BNEG1|.
(12)
 Sens(VCC) / Sens(5V) 
 × 100% .
RatERRSens = 1–
VCC / 5 V


(16)
The ratiometric error in the clamp voltages, RatERRCLP (%), for a
given supply voltage (VCC) is defined as:
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16
A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
 VCLP(VCC) / VCLP(5V) 
 × 100% ,
RatERRCLP = 1–
VCC / 5 V


(17)
where VCLP is either VCLP(HIGH) or VCLP(LOW).
Power-On Reset Voltage (VPOR )
On power-up, to initialize to a known state and avoid current
spikes, the A1365 is held in Reset state. The Reset signal is
disabled when VCC reaches VUVLOH and time tPORR has elapsed,
allowing the output voltage to go from a high-impedance state
into normal operation. During power-down, the Reset signal is
enabled when VCC reaches VPORL , causing the output voltage to
go into a high-impedance state. (Note that a detailed description
of POR and UVLO operation can be found in the Functional
Description section).
Power-On Reset Release Time (tPORR)
When VCC rises to VPORH , the Power-On Reset Counter starts.
The A1365 output voltage will transition from a high-impedance
state to normal operation only when the Power-On Reset Counter
has reached tPORR and VCC has exceeded VUVLOH .
Undervoltage Lockout Threshold (VUVLO )
If VCC drops below VUVLOL, the output voltage will be pulled to
GND. If VCC starts rising, the A1365 will come out of this lock
state when VCC reaches VUVLOH .
or to VBRK(LOW) if a load resistor is connected to GND.
DC Fault Switchpoint Error (ErrDFS)
The Over Field Fault Switchpoint is user-programmable with a
step size of StepFAULT. DC Fault Switchpoint Error is a deviation
from the user-programmed value that occurs over the operating
temperature range.
DC Fault Switchpoint Symmetry Error
(ErrDFSS)
Writing FLT_THRESH bits sets the DC Fault Switchpoint for
positive and negative magnetic fields as follows:
Positive Field Fault Switchpoint (VFPSP) = Xpos × VCC and
Negative Field Fault Switchpoint (VFNSP) = Xneg × VCC where
Xpos + Xneg = 1. For example, programming VFPSP = 0.8 × VCC
should automatically set VFNSP = 0.2 × VCC. For a measured
VFPSP ,the DC Fault Switchpoint Symmetry error is the delta
between the expected VFNSP and the measured one.
Transient Fault Response Time (tTFR)
The time interval between a) when the input crosses the DC Fault
Switchpoint and b) when the FAULT pin reaches 20% of its final
value.
DC Fault
Switchpoint
(%)
VFAULT
Applied magnetic Field
UVLO Enable/Disable Delay Time (tUVLO )
When a falling VCC reaches VUVLOL , time tUVLOE is required to
engage the Undervoltage Lockout state. When VCC rises above
VUVLOH , time tUVLOD is required to disable UVLO and to have a
valid output voltage.
Output Saturation Voltage (VSAT )
When output voltage clamps are disabled, the output voltage
can swing to a maximum of VSAT(HIGH) and to a minimum of
VSAT(LOW) .
Broken Wire Voltage (VBRK )
If the GND pin is disconnected (broken wire event), output voltage will go to VBRK(HIGH) if a load resistor is connected to VCC,
Transducer Output
20
t
Transient Fault
Response Time
(tTFR)
Figure 7: Transient Fault Response Time (tTFR)
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115 Northeast Cutoff
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17
A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
Transient Fault Release Time (tTFRL)
As the Over Field Fault condition goes away, tTFRL is the time
interval between a) when the recovering input crosses the DC
Fault Switchpoint and when the FAULT pin reaches 80% of its
final value. Note that the DC Fault Switchpoint will be impacted
by the programmed Fault Hysteresis Level (VFHSYT).
(%)
80
VFAULT
DC Fault
Switchpoint
Transducer Output
Applied
Magnetic
Field
t
Transient Fault
Release Time
(tTFRL)
Figure 8: Transient Fault Release Time (tTFRL)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
18
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
A1365
FUNCTIONAL DESCRIPTION
Programming Sensitivity and Quiescent Voltage Output
Memory-Locking Mechanisms
Sensitivity and VOUT(Q) can be adjusted by programming
SENS_FINE and QVO bits, as illustrated in Figures 7 and 8.
The A1365 is equipped with two distinct memory-locking
mechanisms:
Users should not program sensitivity or VOUT(Q) beyond the
maximum or minimum programming ranges specified in the
Operating Characteristics table. Exceeding the specified limits
will cause the sensitivity and VOUT(Q) drift over the temperature
range (ΔSensTC and ΔVOUT(Q)TC ) to deteriorate beyond the
specified values.
Programming sensitivity might cause a small drift in VOUT(Q) . As
a result, Allegro recommends programming sensitivity first, then
VOUT(Q) .
Coarse Sensitivity
Each A1365 variant is programmed to a different coarse sensitivity setting. Devices are tested, and temperature compensation is
factory-programmed under that specific coarse sensitivity setting.
If the coarse sensitivity setting is changed, by programming
SENS_COARSE bits, Allegro cannot guarantee the specified
sensitivity drift through temperature range limits (ΔSensTC ).
• Default Lock At power-up, all registers of the A1365 are
locked by default. EEPROM and volatile memory cannot be
read or written. To disable Default Lock, a specific 30-bit
customer access code has to be written to address 0x24 within
Access Code Timeout (tACC = 8 ms) from power-up. After
doing so, registers can be accessed. If VCC is power-cycled,
the Default Lock will automatically be re-enabled. This
ensures that during normal operation, memory content will not
be altered due to unwanted glitches on VCC or the output pin.
• Lock Bit After EEPROM has been programmed by the user,
the EELOCK bit can be set high and VCC power-cycled to
permanently disable the ability to read or write any register.
This will prevent the ability to disable Default Lock using the
method described above. Note that after the EELOCK bit is
set high and the VCC pin is power-cycled, you will not have
the ability to clear the EELOCK bit or read/write any register.
Quiescent Voltage Output,
VOUT(Q) (mV)
Sensitivity, Sens (mV/G)
Max Specified
VOUT(Q)PR
Max Specified
SensPR
Specified Sensitivity
Programming Range
Mid Range
Specified VOUT(Q)
Programming Range
Mid Range
Min Specified
VOUT(Q)PR
Min Specified
SensPR
0
255 256
511
SENS_FINE Code
Figure 9: Device Sensitivity versus SENS_FINE
Programmed Value
0
255 256
511
QVO Code
Figure 10: Device VOUT(Q) versus QVO
Programmed Value
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
19
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
A1365
Power-On Reset (POR) and Undervoltage
Lockout (UVLO) Operation
go to VCC / 2 after tUVLOD [4].
• VCC drops below VCC(min)= 4.5 V If VCC drops below
VUVLOL [4', 5], the UVLO Enable Counter starts counting. If
VCC is still below VUVLOL when the counter reaches tUVLOE,
the UVLO function will be enabled and the ouput will be
pulled near GND [6]. If VCC exceeds VUVLOL before the
UVLO Enable Counter reaches 64 µs [5'] , the output will
continue to be VCC / 2.
The descriptions in this section assume: TA = 25°C, no output
load (RL, CL ) , and no significant magnetic field is present.
• Power-Up At power-up, as VCC ramps up, the output is in a
high-impedance state. When VCC crosses VPORH (location
[1] in Figure 11 and [1'] in Figure 12), the POR Release
counter starts counting for tPORR. At this point, if VCC exceeds
VUVLOH [2'], the output will go to VCC / 2 after tUVLOD [3']. If
VCC does not exceed VUVLOH [2], the output will stay in the
high-impedance state until VCC reaches VUVLOH [3] and then
• Coming out of UVLO While UVLO is enabled [6] , if VCC
exceeds VUVLOH [7] , UVLO will be disabled after tUVLOD ,
and the output will be VCC / 2 [8].
• Power-Down As VCC ramps down below VUVLOL [6’, 9], the
VCC
1
2
3
6
5
9
7
10 11
8
4
5.0
VUVLOH
VUVLOL
VPORH
VPORL
tUVLOE
tUVLOE
GND
Time
VOUT
Slope =
VCC / 2
2.5
tPORR
tUVLOD
tUVLOD
GND
High Impedance
High Impedance
Time
Figure 11: POR and UVLO Operation – Slow Rise Time Case
VCC
5.0
VUVLOH
1’
2’
4’ 5’
6’ 7’
3’
VUVLOL
VPORH
VPORL
< tUVLOE
GND
Time
VOUT
tPORR
Slope =
VCC / 2
< 64 µs
Slope =
VCC / 2
2.5
tUVLOD
GND
High Impedance
Time
High Impedance
Figure 12: POR and UVLO Operation – Fast Rise Time Case
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
20
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
A1365
UVLO Enable Counter will start counting. If VCC is higher
than VPORL when the counter reaches tUVLOE , the UVLO
function will be enabled and the ouput will be pulled near
GND [10]. The output will enter a high-impedance state as
VCC goes below VPORL [11]. If VCC falls below VPORL before
the UVLO Enable Couner reaches tUVLOE, the output will
transition directly into a high-impedance state [7'].
A1365
VCC
VOUT
VF(PULLUP)
GND FAULT
V+
RF(PULLUP)
CF
CL
Detecting Broken Ground Wire
(Optional)
If the GND pin is disconnected, node A becoming open (see
Figure 12), the VOUT pin will go to a high-impedance state.
The output voltage will go to VBRK(HIGH) if a load resistor
RL(PULLUP) is connected to VCC or to VBRK(LOW) if a load resistor
RL(PULLDWN) is connected to GND. The device will not respond
to any applied magnetic field.
CBYPASS
Figure 13: Typical Application Drawing
If the ground wire is reconnected, the A1365 will resume normal
operation.
VCC
VCC
VCC
RL(PULLUP)
VOUT
VCC
VOUT
VCC
VF(PULLUP)
VF(PULLUP)
A1365
RF(PULLUP)
A1365
GND
GND
A
A
Connecting VOUT to RL(PULLUP)
RF(PULLUP)
FAULT
FAULT
RL(PULLDWN)
Connecting VOUT to RL(PULLDWN)
Figure 14: Connections for Detecting Broken Ground Wire
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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21
A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
Over Magnetic Field Fault
The A1365 offers a 6-bit programmable Ratiometric Fault as well
as a 2-bit programmable Ratiometric Fault Hysteresis.
¯ pin is in a high-impedance
During normal operation, the F̄¯Ā¯Ū¯L̄¯T̄
state. The combination of an internal pull-up resistance with an
¯Ā¯Ū¯L̄¯T̄¯ pin to be pulled high.
internal current source enables the F̄
After the F̄¯Ā¯Ū¯L̄¯T̄¯ pin reaches VSAT(HIGH) , the current source is
shut down.
Figure 17 illustrates the impact of programming 60 mV of Fault
Hysteresis on the Fault Switchpoint:
¯L̄¯T̄¯
The user could install an external pull-up resistor on the F̄¯Ā¯Ū
¯
¯
¯
¯
¯
pin to reduce the amount of time required by the F̄ĀŪL̄T̄ pin to
reach VSAT(HIGH) after a fault event passes. An external pull-up
resistor can be connected to a voltage (VF(PULLUP)) different
from VCC as long as it remains within the VF(PULLUP) limits. If
VF(PULLUP) is less than VCC, the current provided by the internal
current source, IIF(PULLUP), will flow through the external pull-up
resistance causing a small voltage drop.
• FAULT_THRESH = 0, setting Positive and Negative Field
Fault Switchpoint (VFPSP, VFNSP) to the middle of their
programmable range.
• FAULT_HYST = 2, setting Fault Hysteresis Level to 60 mV.
The Fault Switchpoint is not affected by the selected Fault
Hysteresis Level.
The speed and accuracy with which a fault is triggered are
characterized by the Transient Fault Response Time (tTFR), the
DC Fault Switchpoint Error ( errDFS), and the Fault Delay Due to
Load Capacitance (tFDC).
Fault
Switchpoint (V)
VFAULT (V)
Max Specified
Switchpoint
5.0
VFHYST
Specified Fault
Switchpoint Range
Mid Range
VFPSP
0.1
3940
Min Specified
Switchpoint
0
31 32
63
4000
VOUT (mV)
FLT_THRESH
Figure 17: Fault Hysteresis Behavior at FAULT_
THRESH = 0, FAULT_HYST = 2
Figure 16: Fault Switchpoint Programming Profile
A1365
VCC
IIF(PULLUP)
RIF(PULLUP)
VCC
VOUT
V+
CL
(Optional)
GND
VF(PULLUP)
FAULT
RF(PULLUP)
CF
CBYPASS
Figure 18: Fault Functional Circuit
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
22
A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
A Fault Overstep is defined as the amount by which the output
voltage exceeds the delta between VOUT(Q) and the DC Fault
Switchpoint (VFPSP and VFNSP ). The larger the overstep caused
by an input magnetic field is, the faster tTFR will be. When VFPSP
and VFNSP are programmed near their limits, the maximum Fault
Overstep will be limited because VOUT will be reaching saturation levels (see Figure 19).
0.75
Faults can be latched by setting the FAULT_LATCH bit high.
¯L̄¯T̄¯ pin will be held low. To reset the
After a fault occurs, the F̄¯Ā¯Ū
¯Ū¯L̄¯T̄¯ pin, the A1365 must be powered down.
F̄¯Ā
Over Magnetic Field Fault can be disabled by setting the
FLT_DIS bit.
5.5
Transient Fault Response Time, tTFR (µs)
11
Worst Process Corner
when VFNSP = 0.1 × VCC
9
Worst Process Corner
when VFPSP = 0.9 × VCC
7
Worst Process Corner
when VFNSP > 0.17 × VCC
and VFPSP < 0.87 × VCC
5
Typical Process Corner
when VFNSP > 0.2 × VCC
and VFPSP < 0.8 × VCC
2
0
5
10
15
20
VFault Overstep (%)
Figure 19: Transient Fault Response Time versus Fault Overstep Voltage at VCC = 5 V, CF = 0 F, RL = Open.
Allegro MicroSystems, LLC
115 Northeast Cutoff
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23
A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
PROGRAMMING SERIAL INTERFACE
The A1365 incorporates a serial interface that allows an external
controller to read and write registers in the EEPROM and volatile
memory. The A1365 uses a point-to-point communication protocol, based on Manchester encoding per G. E. Thomas (a rising
edge indicates 0 and a falling edge indicates 1), with address and
data transmitted MSB first.
Transaction Types
Each transaction is initiated by a command from the controller;
the A1365 does not initiate any transactions. Three commands
are recognized by the A1365: Write Access Code, Write, and
Read. One response frame type is generated by the A1365, Read
Acknowledge. If the command is Read, the A1365 responds by
transmitting the requested data in a Read Acknowledge frame. If
the command is any other type, the A1365 does not acknowledge.
As shown in Figure 20, the A1365 receives all commands via the
VCC pin. It responds to Read commands via the VOUT pin. This
implementation of Manchester encoding requires the communication pulses be within a high (VMAN(H)) and low (VMAN(L)) range
of voltages for the VCC line and the VOUT line. The Write
command to EEPROM is supported by two high-voltage pulses
on the VOUT line.
Writing the Access Code
In order for the external controller to write or read from the
A1365 memory during the current session, it must establish serial
communication with the A1365 by sending a Write command
including the Access Code within Access Code Timeout (tACC )
from power-up. If this deadline is missed, all write and read
access is disabled until the next power-up.
Writing to Volatile Memory
In order for the external controller to write to volatile memory,
a Write command must be transmitted on the VCC pin. Successive Write commands to volatile memory must be separated by
tWRITE . The required sequence is shown in Figure 21.
VCC
Previous
Command
Write
to Register R#
tWRITE
Next
Command
tWRITE
t
Figure 21: Writing to Volatile Memory
Write/Read Command
– Manchester Code
Controller
VCC
RF(PULLUP)
High Voltage pulses to
activate EEPROM cells
VCC
A1365
FAULT
VOUT
GND
Read Acknowledge
– Manchester Code
Figure 20: Top-Level Programming Interface
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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24
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
A1365
Writing to EEPROM
In order for the external controller to write to non-volatile
EEPROM, a Write command must be transmitted on the VCC
pin. The controller must also send two Programming pulses,
long high-voltage strobes, via the VOUT pin. These strobes are
detected internally, allowing the A1365 to boost the voltage on
the EEPROM gates. The required sequence is shown in figures
22 and 23.
To ensure EEPROM integrity over lifetime, EEPROM should not
be exposed to more than 100 Write cycles.
Reading from EEPROM or Volatile Memory
In order for the external controller to read from EEPROM or
volatile memory, a Read command must be transmitted on
the VCC line. Within time tstart_read , the VOUT line will stop
VCC
VOUT
Write
to Register R#
Normal Operation
EEPROM
Programming
Pulses
High
Impedance
responding to the magnetic field and the Read Acknowledge
frame will be transmitted on the VOUT line. The Read Acknowledge frame contains Read data.
After the Read Acknowledge frame has been received from the
A1365, the VOUT line resumes normal operation after time
tREAD . The required sequence is shown in Figure 24.
Error Checking
The serial interface uses a cyclic redundancy check (CRC) for
data-bit error checking (synchronization bits are ignored during
the check). The CRC algorithm is based on the polynomial g(x)
= x3 + x + 1, and the calculation is represented graphically in
Figure 25. The trailing 3 bits of a message frame comprise the
CRC token. The CRC is initialized at 111. If the serial interface
receives a command with a CRC error, the command is ignored.
VOUT
Normal Operation
t
t
tsPULSE(E)
tWRITE(E)
Figure 22: Writing to EEPROM
VCC
Figure 23: EEPROM Programming Pulses
Read from
Register R#
C0
VOUT
Normal Operation
Read Acknowledge
R#
Input Data
C2
Normal Operation
t
tstart_read
C1
1x 0
1x 1
0x 2
1x 3
= x3 + x + 1
tREAD
Figure 24: Reading from EEPROM or Volatile Memory
Figure 25: CRC Calculation
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
25
A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
Serial Interface Reference
Required timing parameters for successful serial communication with A1365 device are given in table below.
Required Serial Interface Timing Parameters
Characteristics
Symbol
Note
Min.
Typ.
Max.
Unit
Input/Output Signal Timing
Access Code Timeout
tACC
Customer Access Code should be fully entered
in less than tACC , measured from when VCC
crosses VUVLOH .
–
–
8
ms
Bit Rate
tBITR
Defined by the input message bit rate sent from
the external controller
32
–
80
kbps
tBIT
Bit Time
Data bit pulse width at 70 kbps
13.6
14.3
15
µs
Bit Time Error
errTBIT
Deviation in tBIT during one command frame
–11
–
+ 11
%
Volatile Memory Write Delay
tWRITE
Required delay from the trailing edge of certain
Write command frames to the leading edge of a
following command frame
2 × tBIT
–
–
µs
Required delay from the trailing edge of the
second EEPROM Programming pulse to the
leading edge of a following command frame
2 × tBIT
–
–
µs
tREAD
Required delay from the trailing edge of a Read
Acknowledge frame to the leading edge of a
following command frame
2 × tBIT
–
–
µs
tstart_read
Delay from the trailing edge of a Read
command frame to the leading edge of the Read
Acknowledge frame
25 μs –
0.25 ×
tBIT
50 μs
–0.25 ×
tBIT
150 μs
– 0.25 ×
tBIT
µs
tsPULSE(E)
Delay from last edge of write command to start
of EEPROM programming pulse
40
–
–
μs
Non-Volatile Memory Write Delay
Read Acknowledge Delay
Read Delay
tWRITE(E)
EEPROM Programming Pulse
EEPROM Programming Pulse
Setup Time
Input/Output Signal Voltage
Applied to VCC line
Manchester Code High Voltage
VMAN(H)
Manchester Code Low Voltage
VMAN(L)
Manchester Level to VCC Delay
tMAN_VCC
5.1
–
–
V
VCC –
0.2 V
–
–
V
Applied to VCC line
–
–
3.9
V
Read from VOUT line
–
–
0.2
V
–
–
15
µs
Read from VOUT line
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
26
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
A1365
Serial Interface Message Structure
Read/Write
The general format of a command message frame is shown in
Figure 26. Note that, in the Manchester coding used, a bit value
of one is indicated by a falling edge within the bit boundary, and
a bit value of zero is indicated by a rising edge within the bit
boundary.
Memory Address
Synchronize
0
0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
MSB
VCC Levels During Manchester Communication
For all devices with UVLO functionality, after power-up, it
is important that the VCC pin be held at VCC until the first
Synchronization pulse of a read/write transaction is sent (see
Figure 27). During the transaction, the VCC pin varies between
VMAN(H) and VMAN(L) , but after the last CRC bit has been sent,
the controller must bring the VCC pin back to the VCC level in
less than tMAN_VCC . This is important in order to avoid triggering
the UVLO functionality during EEPROM read/write.
Data
...
CRC
0/1 0/1 0/1 0/1
MSB
0 0 1 1 0
Manchester Code per G. E. Thomas
Bit boundaries
Figure 26: General Format for Serial Interface
Commands
Read/Write
Memory Address
Synchronize
0
0 0/1
0
0
Data
CRC
0/1
VMAN(H)
VCC(V)
VMAN(L)
0V
1
0
tMAN_VCC
Bit boundaries
Figure 27: VCC Levels During Manchester Communication
Serial Interface Command General Format
Quantity
of Bits
Parameter Name
Values
2
Synchronization
00
Used to identify the beginning of a serial interface command
0
[As required] Write operation
1
[As required] Read operation
Description
1
Read/Write
6
Address
0/1
[Read/Write] Register address (volatile memory or EEPROM)
30
Data
0/1
24 data bits and 6 ECC bits
3
CRC
0/1
Incorrect value indicates errors
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
27
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
A1365
Read (Controller to A1365)
Read/Write
The fields for the Read command are:
Memory Address
Synchronize
• Sync (2 zero bits)
0
• Read/Write (1 bit, must be 1 for read)
0
0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 . . .
MSB
• Address (6 bits) (ADDR[5] is 0 for EEPROM, 1 for register)
• CRC (3 bits)
Figure 28 shows the sequence for a Read command.
Read/Write
0
CRC
1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
MSB
Figure 30: Write Sequence
Write Access Code (Controller to A1365)
The fields for the Access Code command are:
• Address (6 bits) (Address 0X24 for Customer Access)
Read/Write
• Sync (2 zero bits)
• Data (30 bits: [29:26] Don’t Care, [25:24] ECC Pass/Fail,
[23:0] Data)
• CRC (3 bits)
Figure 29 shows the sequence for a Read Acknowledge. Refer to
the Detecting ECC Error section for instructions on how to detect
and ECC failure.
Data
(30 bits maximum)
• Read/Write (1 bit, must be 0 for write)
Figure 31 shows the sequence for an Access Code command.
The fields for the data return frame are:
0
MSB
• CRC (3 bits)
Read Acknowledge (A1365 to Controller)
0
0/1 0/1 0/1 0/1
• Data (30 bits) (0x2781_1F77 for Customer Access)
Figure 28: Read Sequence
Synchronize
CRC
• Sync (2 zero bits)
Memory Address
Synchronize
0
Data
(30 bits maximum)
CRC
0/1 0/1 0/1 0/1 . . . 0/1 0/1 0/1 0/1 0/1
MSB
0
0
0
1
• Read/Write (1 bit, must be 0 for write)
• Address (6 bits) (ADDR[5] is 0 for EEPROM, 1 for register;
refer to the address map)
• Data (30 bits: [29:24] Don’t Care, [23:0] Data)
• CRC (3 bits)
Figure 30 shows the sequence for a Write command. Bits [29:24]
are Don’t Care because the A1365 automatically generates 6 ECC
bits based on the content of bits [23:0]. These ECC bits will be
stored in EEPROM at locations [29:24].
0
1
0
0 0/1 0/1 0/1 . . .
CRC
0/1 0/1 0/1 0/1
MSB
Figure 31: Access Code Write Sequence
The controller must open the serial communication with the
A1365 device by sending an Access Code. It must be sent within
Access Code Timeout (tACC ) from power-up or the device will
be disabled for read and write access.
Access Codes Information
Name
Write (Controller to A1365)
• Sync (2 zero bits)
0
MSB
Figure 29: Read Acknowledge Sequence
The fields for the Write command are:
Data
(30 bits)
Memory Address
Synchronize
Customer
Serial Interface Format
Register Address
(Hex)
Data (Hex)
0x24
0x2781_1F77
Shadow Mode
For faster programming, Shadow Mode puts the sensor in a try
mode where one can write to the EEPROM registers as if they
are volatile registers. This is especially useful when searching
for Sensitivity, QVO, and Over Field Fault codes. Once the
desired codes are identified, the user should exit Shadow Mode
and execute an EEPROM Write. If a power-cycle is executed
during Shadow Mode, the registers will reset to their initial state.
SHADOW_ENABLE bit should be set to enter Shadow Mode.
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
28
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
A1365
EEPROM Margining
Allegro factory-tests the capacity of each EEPROM bit to retain
a “0” or a “1” state. After the user has completed EEPROM
programming, the two VREAD bits could be set to “01” to
change the EEPROM margin setting. EEPROM registers that
were written by the user should be read and compared to the
user-programmed value. The procedure should be repeated using
VREAD = “10”. It is not mandatory for the user to execute
EEPROM Margining.
Memory Address Map
Register Name
Address
FAC_LOT_NUM
WAFER_NUM
Customer ReadOnly EEPROM
0x00*
Bits
r/w
16
Location
15:0
Factory Wafer (stores up to 64 wafers)
r/w
6
21:16
SCRATCH
Factory use only
r/w
2
23:22
8 bits X die location (accommodates up to 256 die in X)
r/w
8
7:0
8 bits Y die location (accommodates up to 256 die in Y)
r/w
8
15:8
SCRATCH
Factory use only
r/w
8
23:16
SENS_FINE
Sensitivity
r/w
9
8:0
0x01*
SENS_COARSE
Coarse Sensitivity
r/w
2
10:9
QVO
Quiescent Output Voltage
r/w
9
19:11
FACTORY_RES1
0x02
POL
Factory use only
r/w
1
20
Reverses output polarity
r/w
1
21
r/w
1
22
w
1
23
CLAMP_EN
Clamp Enable
EELOCK
EEPROM LOCK
FLT_THRESH
Sets the DC Fault Switchpoint, two’s complement
DAC profile
r/w
6
5:0
FLT_HYST
Fault Hysteresis Adjust, [00] = 0 V, [01] = 30 mV,
[10] = 60 mV, [11] = 120 mV
r/w
2
7:6
Enables Fault Latch
r/w
1
8
FLT_LATCH
0x03
FLT_DIS
Disables Fault
r/w
1
9
Misc(x)
Reserved for factory use; do not change default state
r/w
11
20:10
MISC3_1
Factory-reserved (unused)
r/w
3
23:21
Customer-reserved
r/w
24
23:0
Disable Analog Output
Sets the output pin to a high-impedance state
r/w
1
0
SHADOW_ENABLE
Enables register shadowing to bypass shadowed
EEPROM registers
r/w
1
1
r
1
2
r/w
2
4:3
r
1
5
CUSTOMER_RES
Volatile Memory
Customer Debug
Register
Description
X_DIE_LOC
Y_DIE_LOC
Customer R/W
EEPROM
r/w
Factory Lot (uses 3rd to 7th digits of the lot number)
0x04*
CUSTOMER_ACCESS
Customer write access enabled
Factory Reserved
Reserved for factory use. Do not change default
state.
OVERF_FLT
0x10
0 = No Over Field Fault
1 = Over Field Fault occurred, clears on read
Factory Reserved
Reserved for factory use; do not change default state.
r/w
2
8:7
VREAD
Change EEPROM read voltage for margining;
[00] = 1.2 V (default), [01] = 0 V, [10] = 4.3 V,
[11] = undefined
r/w
2
10:9
Reserved for factory use (unused)
n/a
13
23:11
30
29:0
–
ACCESS_CODE
0x24
Customer code (not addressable)
*EEPROM registers or bits that are not shadowed.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
29
A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
EEPROM Cell Organization
Programming coefficients are stored in non-volatile EEPROM,
which is separate from the digital subsystem, and accessed by the
digital subsystem EEPROM Controller module. The EEPROM
is organized as 30-bit-wide words, each word is made up of 24
data bits and 6 ECC (Error Checking and Correction) check bits,
stored as shown in figure below.
EEPROM Bit
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Contents
C5
C4
C3
C2
C1
C0
D23
D22
D21
D20
D19
D18
D17
D16
D15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
External EEPROM Word Bit Sequence; C# – Check Bit, D# – Data Bit
EEPROM Error Checking and Correction
(ECC)
Detecting ECC Error
If an uncorrectable error has occurred, bits 25:24 are set to 10, the
VOUT pin will go to a high-impedance state, and the device will
not respond to the applied magnetic field. Output voltage will go
to VBRK(HIGH) if a load resistor RL(PULLUP) is connected to VCC
or to VBRK(LOW) if a load resistor RL(PULLDWN) is connected to
GND.
Hamming code methodology is implemented for EEPROM
checking and correction. The device has ECC enabled after
power-up.
The device always returns 30 bits.
The message received from controller is analyzed by the device
EEPROM driver and ECC bits are added. The first 6 received bits
from device to controller are dedicated to ECC.
EEPROM ECC Errors
Bits
Name
Description
29:26
–
No meaning
00 = No error
25:24
ECC
01 = Error detected and message corrected
10 = Uncorrectable error
11 = No meaning
23:0
D[23:0]
EEPROM data
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
30
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
A1365
PACKAGE OUTLINE DRAWING
For Reference Only - Not for Tooling Use
(Reference DWG-9202)
Dimensions in millimeters - NOT TO SCALE
Dimensions exclusive of mold flash, gate burs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
B
10°
5.21
+0.08
–0.05
1.00
+0.08
–0.05
E
2.60 F
1.00 F
Mold Ejector
Pin Indent
+0.08
3.43
–0.05
F
0.89 MAX
1
2
3
Branded
Face
4
A
0.54 REF
NNNN
YYWW
0.41
+0.08
0.20
–0.05
+0.08
–0.05
D
12.14 ±0.05
1.27 NOM
N = Device part number
Y = Last two digits of year of manufacture
W = Week of manufacture
0.54 REF
0.89 MAX
1.50
+0.08
–0.05
D
+0.08
5.21
–0.05
Standard Branding Reference View
A
Dambar removal protrusion (16X)
B
Gate and tie burr area
C
Branding scale and appearance at supplier discretion
D
Thermoplastic Molded Lead Bar for alignment during shipment
E
Active Area Depth, 0.37 mm REF
F
Hall element, not to scale
+0.08
1.00
–0.05
Figure 32: Package KT, 4-Pin SIP
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
31
A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
Revision History
Revision
Current
Revision Date
–
January 7, 2016
Description of Revision
Initial release
Copyright ©2016, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
32