RF Agile Transceiver AD9363 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM RX1B_P, RX1B_N AD9363 RX1A_P, RX1A_N ADC RX1C_P, RX1C_N RX2A_P, RX2A_N DATA INTERFACE RX2B_P, RX2B_N ADC RX2C_P, RX2C_N RX LO TX_MON1 TX LO TX1A_P, TX1A_N DAC P0_D11/ TX_D5_x TO P0_D0/ TX_D0_x P1_D11/ RX_D5_x TO P1_D0/ RX_D0_x TX1B_P, TX1B_N TX_MON2 TX2A_P, TX2A_N DAC CTRL AUXADC AUXDACx GPO RADIO SWITCHING PLLs CLK_OUT XTALN NOTES 1. SPI, CTRL, P0_D11/TX_D5_x TO P0_D0/TX_D0_x, P1_D11/ RX_D5_x TO P1_D0/RX_D0_x, AND RADIO SWITCHING CONTAIN MULTIPLE PINS. APPLICATIONS 3G enterprise femtocell base stations 4G femtocell base stations Wireless video transmission 10558-001 SPI CTRL DAC DAC TX2B_P, TX2B_N ADC Radio frequency (RF) 2 × 2 transceiver with integrated 12-bit DACs and ADCs Wide bandwidth: 325 MHz to 3.8 GHz Supports time division duplex (TDD) and frequency division duplex (FDD) operation Tunable channel bandwidth (BW): up to 20 MHz Receivers: 6 differential or 12 single-ended inputs Superior receiver sensitivity with a noise figure: 3 dB Receive (Rx) gain control Real-time monitor and control signals for manual gain Independent automatic gain control (AGC) Dual transmitters: 4 differential outputs Highly linear broadband transmitter Transmit (Tx) error vector magnitude (EVM): −34 dB Tx noise: ≤−157 dBm/Hz noise floor Tx monitor: 66 dB dynamic range with 1 dB accuracy Integrated fractional N synthesizers 2.4 Hz local oscillator (LO) step size CMOS/LVDS digital interface Figure 1. GENERAL DESCRIPTION The AD9363 is a high performance, highly integrated RF agile transceiver designed for use in 3G and 4G femtocell applications. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. The device combines an RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor. The AD9363 operates in the 325 MHz to 3.8 GHz range, covering most licensed and unlicensed bands. Channel bandwidths from less than 200 kHz to 20 MHz are supported. The two independent direct conversion receivers have state-ofthe-art noise figure and linearity. Each Rx subsystem includes independent automatic gain control (AGC), dc offset correction, quadrature correction, and digital filtering, thereby eliminating the need for these functions in the digital baseband. The AD9363 also has flexible manual gain modes that can be externally controlled. Two high dynamic range ADCs per channel digitize the received I and Q signals and pass them through configurable decimation filters and 128-tap finite impulse response (FIR) filters to produce a 12-bit output signal at the appropriate Rev. D sample rate. The transmitters use a direct conversion architecture that achieves high modulation accuracy with ultralow noise. This transmitter design produces a best-in-class Tx EVM of −34 dB, allowing significant system margin for the external power amplifier (PA) selection. The on-board Tx power monitor can be used as a power detector, enabling highly accurate Tx power measurements. The fully integrated phase-locked loops (PLLs) provide low power fractional N frequency synthesis for all receive and transmit channels. Channel isolation, demanded by FDD systems, is integrated into the design. All voltage controlled oscillators (VCOs) and loop filter components are integrated. The core of the AD9363 can be powered directly from a 1.3 V regulator. The IC is controlled via a standard 4-wire serial port and four real-time I/O control pins. Comprehensive power-down modes are included to minimize power consumption during normal use. The AD9363 is packaged in a 10 mm × 10 mm, 144-ball chip scale package ball grid array (CSP_BGA). Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9363 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 2.4 GHz Frequency Band .......................................................... 24 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 28 Functional Block Diagram .............................................................. 1 General......................................................................................... 28 General Description ......................................................................... 1 Receiver........................................................................................ 28 Revision History ............................................................................... 2 Transmitter .................................................................................. 28 Specifications..................................................................................... 3 Clock Input Options .................................................................. 28 Current Consumption—VDD_INTERFACE........................... 8 Synthesizers ................................................................................. 28 Current Consumption—VDDD1P3_DIG and VDDAx (Combination of All 1.3 V Supplies) ....................................... 11 Digital Data Interface................................................................. 29 Absolute Maximum Ratings ..................................................... 15 SPI Interface ................................................................................ 30 Reflow Profile .............................................................................. 15 Control Pins ................................................................................ 30 Thermal Resistance .................................................................... 15 GPO Pins (GPO_3 to GPO_0) ................................................. 30 ESD Caution ................................................................................ 15 Auxiliary Converters.................................................................. 30 Pin Configuration and Function Descriptions ........................... 16 Packaging and Ordering Information ......................................... 32 Typical Performance Characteristics ........................................... 20 Outline Dimensions ................................................................... 32 800 MHz Frequency Band......................................................... 20 Ordering Guide .......................................................................... 32 Enable State Machine ................................................................. 29 REVISION HISTORY 11/2016—Revision D: Initial Version Rev. D | Page 2 of 32 Data Sheet AD9363 SPECIFICATIONS Electrical characteristics at VDD_GPO = 3.3 V, VDD_INTERFACE = 1.8 V, and all other VDDx pins (VDDA1P3_TX_LO, VDDA1P3_ TX_VCO_LDO, VDDA1P3_RX_LO, VDDA1P3_RX_VCO_LDO, VDDA1P3_RX_RF, VDDA1P3_RX_TX, VDDA1P3_TX_LO_BUFFER, VDDA1P3_TX_SYNTH, VDDA1P3_RX_SYNTH, VDDD1P3_DIG, and VDDA1P3_BB) = 1.3 V, TA = 25°C, unless otherwise noted. Table 1. Parameter1 RECEIVERS, GENERAL Center Frequency Rx Bandwidth Gain Minimum Maximum Gain Step Received Signal Strength Indicator Range Accuracy RECEIVERS, 800 MHz Noise Figure Third-Order Input Intermodulation Intercept Point Second-Order Input Intermodulation Intercept Point Local Oscillator (LO) Leakage Quadrature Gain Error Phase Error Modulation Accuracy (EVM) Input Return Loss RX1x_x to RX2x_x Isolation RX1A_x to RX2A_x, RX1C_x to RX2C_x RX1B_x to RX2B_x RX2_x to RX1_x Isolation RX2A_x to RX1A_x, RX2C_x to RX1C_x RX2B_x to RX1B_x RECEIVERS, 2.4 GHz Noise Figure Third-Order Input Intermodulation Intercept Point Second-Order Input Intermodulation Intercept Point Local Oscillator (LO) Leakage Quadrature Gain Error Phase Error Modulation Accuracy (EVM) Input Return Loss RX1x_x to RX2x_x Isolation RX1A_x to RX2A_x, RX1C_x to RX2C_x RX1B_x to RX2B_x Symbol Min Typ 325 Max Unit 3800 20 MHz MHz Test Conditions/Comments 0 74.5 73.0 72.0 1 dB dB dB dB dB 100 ±2 dB dB NF IIP3 2.5 −18 dB dBm Maximum Rx gain Maximum Rx gain IIP2 40 dBm Maximum Rx gain −122 dBm At Rx front-end input 0.2 0.2 −34 −10 % Degrees dB dB 70 55 dB dB 70 55 dB dB NF IIP3 3 −14 dB dBm Maximum Rx gain Maximum Rx gain IIP2 45 dBm Maximum Rx gain −110 dBm At Rx front-end input 0.2 0.2 −34 −10 % Degrees dB dB 65 50 dB dB At 800 MHz At 2300 MHz (RX1A_x, RX2A_x) At 2300 MHz (RX1B_x, RX1C_x, RX2B_x, RX2C_x) RSSI S11 S11 Rev. D | Page 3 of 32 19.2 MHz reference clock 40 MHz reference clock AD9363 Parameter1 RX2x_x to RX1x_x Isolation RX2A_x to RX1A_x, RX2C_x to RX1C_x RX2B_x to RX1B_x RECEIVERS, 3.5 GHz Noise Figure Third-Order Input Intermodulation Intercept Point Second-Order Input Intermodulation Intercept Point Local Oscillator (LO) Leakage Quadrature Gain Error Phase Error Modulation Accuracy (EVM) Input Return Loss RX1x_x to RX2x_x Isolation RX1A_x to RX2A_x, RX1C_x to RX2C_x RX1B_x to RX2B_x RX2x_x to RX1x_x Isolation RX2A_x to RX1A_x, RX2C_x to RX1C_x RX2B_x to RX1B_x TRANSMITTERS, GENERAL Center Frequency Tx Bandwidth Power Control Range Power Control Resolution TRANSMITTERS, 800 MHz Output Return Loss Maximum Output Power Modulation Accuracy (EVM) Third-Order Output Intermodulation Intercept Point Carrier Leakage Noise Floor Isolation TX1x_x to TX2x_x TX2x_x to TX1x_x TRANSMITTERS, 2.4 GHz Output Return Loss Maximum Output Power Modulation Accuracy (EVM) Third-Order Output Intermodulation Intercept Point Carrier Leakage Noise Floor Isolation TX1x_x to TX2x_x TX2x_x to TX1x_x TRANSMITTERS, 3.5 GHz Output Return Loss Maximum Output Power Modulation Accuracy (EVM) Data Sheet Symbol Min Typ Max Unit Test Conditions/Comments 65 50 dB dB NF IIP3 3.3 −15 dB dBm Maximum Rx gain Maximum Rx gain IIP2 44 dBm Maximum Rx gain −100 dBm At Rx front-end input 0.2 0.2 −34 −10 % Degrees dB dB 60 48 dB dB 60 48 dB dB S11 325 S22 OIP3 S22 OIP3 S22 3800 20 40 MHz reference clock 90 0.25 MHz MHz dB dB −10 8 −34 23 dB dBm dB dBm 1 MHz tone into 50 Ω load 19.2 MHz reference clock −50 −32 −157 dBc dBc dBm/Hz 0 dB attenuation 40 dB attenuation 90 MHz offset 50 50 dB dB −10 7.5 −34 19 dB dBm dB dBm 1 MHz tone into 50 Ω load 40 MHz reference clock −50 −32 −156 dBc dBc dBm/Hz 0 dB attenuation 40 dB attenuation 90 MHz offset 50 50 dB dB −10 7.0 −34 dB dBm dB Rev. D | Page 4 of 32 1 MHz tone into 50 Ω load 40 MHz reference clock Data Sheet AD9363 Parameter1 Third-Order Output Intermodulation Intercept Point Carrier Leakage Symbol OIP3 Min Noise Floor Isolation TX1 to TX2 TX2 to TX1 1 Typ 18 Max Unit dBm Test Conditions/Comments −50 −31 −154 dBc dBc dBm/Hz 0 dB attenuation 40 dB attenuation 90 MHz offset 50 50 dB dB When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section. Table 2. Parameter1 TX MONITOR INPUTS (TX_MON1, TX_MON2) Maximum Input Level Dynamic Range Accuracy LO SYNTHESIZER LO Frequency Step Integrated Phase Noise REFERENCE CLOCK (REF_CLK) Input Frequency Range Input Signal Level AUXILIARY ADC Resolution Input Voltage Minimum Maximum AUXILIARY DAC Resolution Output Voltage Minimum Maximum Output Current DIGITAL SPECIFICATIONS (CMOS) Logic Inputs Input Voltage High Input Voltage Low Input Current High Input Current Low Logic Outputs Output Voltage High Output Voltage Low DIGITAL SPECIFICATIONS (LVDS) Logic Inputs Input Voltage Range Input Differential Voltage Threshold Symbol Min Typ Max Unit 4 66 1 dBm dB dB 2.4 0.3 Hz °rms 10 1.3 80 MHz V p-p 12 Bits 0.05 VDDA1P3_BB − 0.05 V V 10 Bits 0.5 VDD_GPO − 0.3 10 V V mA VDD_INTERFACE × 0.8 0 VDD_INTERFACE V VDD_INTERFACE × 0.2 +10 +10 V VDD_INTERFACE × 0.8 0 VDD_INTERFACE V VDD_INTERFACE × 0.2 V 825 1575 mV −100 +100 mV −10 −10 Rev. D | Page 5 of 32 Test Conditions/Comments 2.4 GHz, 40 MHz reference clock 100 Hz to 100 MHz REF_CLK is the input to the XTALN pin External oscillator AC-coupled external oscillator μA μA Each differential input in the pair AD9363 Parameter1 Receiver Differential Input Impedance Logic Outputs Output Voltage High Output Voltage Low Output Differential Voltage Output Offset Voltage GENERAL-PURPOSE OUTPUTS Output Voltage High Output Voltage Low Output Current SPI TIMING SPI_CLK Period Pulse Width SPI_EN Setup to First SPI_CLK Rising Edge Last SPI_CLK Falling Edge to SPI_ENB Hold SPI_DI Data Input Setup to SPI_CLK Data Input Hold to SPI_CLK SPI_CLK Rising Edge to Output Data Delay 4-Wire Mode 3-Wire Mode Bus Turnaround Time, Read (Master) Bus Turnaround Time, Read (Slave) DIGITAL DATA TIMING (CMOS), VDD_INTERFACE = 1.8 V DATA_CLK_x Clock Period DATA_CLK_x and FB_CLK_x Pulse Width Tx Data Data Sheet Symbol Min Typ 100 Max Unit Ω 1375 mV mV mV 1025 150 1200 VDD_GPO × 0.8 0 Test Conditions/Comments Programmable in 75 mV steps mV VDD_GPO VDD_GPO × 0.2 10 V V mA VDD_INTERFACE = 1.8 V tCP tMP tSC 20 9 1 ns ns ns tHC 0 ns tS 2 ns tH 1 ns tCO tCO tHZM 3 3 tH 8 8 tCO (MAX) ns ns ns tHZS 0 tCO (MAX) ns tCP tMP 16.276 45% of tCP 55% of tCP ns ns After baseband processors (BBP) drives the last address bit After AD9363 drives the last data bit 61.44 MHz TX_FRAME_x, P0_Dx, and P1_Dx Setup to FB_CLK_x Hold to FB_CLK_x DATA_CLK_x to Data Bus Output Delay DATA_CLK_x to RX_FRAME_x Delay Pulse Width ENABLE TXNRX tSTX tHTX tDDRX 1 0 0 1.5 ns ns ns tDDDV 0 1.0 ns tENPW tTXNRXPW tCP tCP ns ns TXNRX Setup to ENABLE Bus Turnaround Time Before Rx After Rx Capacitive Load Capacitive Input tTXNRXSU 0 ns tRPRE tRPST 2 × tCP 2 × tCP ns ns pF pF 3 3 Rev. D | Page 6 of 32 FDD independent enable state machine (ENSM) mode TDD ENSM mode TDD mode Data Sheet Parameter1 DIGITAL DATA TIMING (CMOS), VDD_INTERFACE = 2.5 V DATA_CLK_x Clock Period DATA_CLK_x and FB_CLK_x Pulse Width Tx Data Setup to FB_CLK_x Hold to FB_CLK_x DATA_CLK_x to Data Bus Output Delay DATA_CLK_x to RX_FRAME_x Delay Pulse Width ENABLE TXNRX TXNRX Setup to ENABLE Bus Turnaround Time Before Rx After Rx Capacitive Load Capacitive Input DIGITAL DATA TIMING (LVDS) DATA_CLK_x Clock Period DATA_CLK_x and FB_CLK_x Pulse Width Tx Data Setup to FB_CLK_x Hold to FB_CLK_x DATA_CLK_x to Data Bus Output Delay DATA_CLK_x to RX_FRAME_x Delay Pulse Width ENABLE TXNRX TXNRX Setup to ENABLE Bus Turnaround Time Before Rx After Rx Capacitive Load Capacitive Input SUPPLY CHARACTERISTICS 1.3 V Main Supply VDD_INTERFACE Supply CMOS LVDS VDD_GPO Supply Current Consumption VDDx, Sleep Mode VDD_GPO 1 AD9363 Symbol Min tCP tMP 16.276 45% of tCP tSTX tHTX tDDRX Typ Max Unit Test Conditions/Comments ns ns 61.44 MHz 55% of tCP 1 0 0.25 1.25 ns ns ns tDDDV 0.25 1.25 ns tENPW tTXNRXPW tTXNRXSU tCP tCP 0 ns ns ns tRPRE tRPST 2 × tCP 2 × tCP ns ns pF pF TX_FRAME_x, P0_Dx, and P1_Dx 3 3 tCP tMP 4.069 45% of tCP 55% of tCP ns ns tSTX tHTX tDDRX 1 0 0 1.5 ns ns ns tDDDV 0 1.0 ns tENPW tTXNRXPW tTXNRXSU tCP tCP 0 ns ns ns tRPRE tRPST 2 × tCP 2 × tCP ns ns pF pF FDD independent ENSM mode TDD ENSM mode TDD mode 245.76 MHz TX_FRAME_x and TX_Dx 3 3 1.267 1.2 1.8 1.3 1.3 1.33 V 3.3 2.5 2.5 3.465 V V V 180 50 µA μA FDD independent ENSM mode TDD ENSM mode When unused, must be set to 1.3 V Sum of all input currents No load When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section. Rev. D | Page 7 of 32 AD9363 Data Sheet CURRENT CONSUMPTION—VDD_INTERFACE Table 3. VDD_INTERFACE = 1.2 V Parameter SLEEP MODE ONE Rx CHANNEL, ONE Tx CHANNEL, DOUBLE DATA RATE (DDR) LTE10 Single Port Dual Port LTE20 Dual Port TWO Rx CHANNELS, TWO Tx CHANNELS, DDR LTE3 Dual Port LTE10 Single Port Dual Port LTE20 Dual Port GSM Dual Port WiMAX 8.75 MHz Dual Port WiMAX 10 MHz Single Port TDD Rx TDD Tx FDD WiMAX 20 MHz Dual Port FDD Min Typ 45 Max Unit μA Test Conditions/Comments Power applied, device disabled 2.9 2.7 mA mA 30.72 MHz data clock, CMOS 15.36 MHz data clock, CMOS 5.2 mA 30.72 MHz data clock, CMOS 1.3 mA 7.68 MHz data clock, CMOS 4.6 5.0 mA mA 61.44 MHz data clock, CMOS 30.72 MHz data clock, CMOS 8.2 mA 61.44 MHz data clock, CMOS 0.2 mA 1.08 MHz data clock, CMOS 3.3 mA 20 MHz data clock, CMOS 0.5 3.6 3.8 mA mA mA 22.4 MHz data clock, CMOS 22.4 MHz data clock, CMOS 44.8 MHz data clock, CMOS 6.7 mA 44.8 MHz data clock, CMOS Rev. D | Page 8 of 32 Data Sheet AD9363 Table 4. VDD_INTERFACE = 1.8 V Parameter SLEEP MODE ONE Rx CHANNEL, ONE Tx CHANNEL, DDR LTE10 Single Port Dual Port LTE20 Dual Port TWO Rx CHANNELS, TWO Tx CHANNELS, DDR LTE3 Dual Port LTE10 Single Port Dual Port LTE20 Dual Port GSM Dual Port WiMAX 8.75 MHz Dual Port WiMAX 10 MHz Single Port TDD Rx TDD Tx FDD WiMAX 20 MHz Dual Port FDD Min Typ 84 Max Unit μA Test Conditions/Comments Power applied, device disabled 4.5 4.1 mA mA 30.72 MHz data clock, CMOS 15.36 MHz data clock, CMOS 8.0 mA 30.72 MHz data clock, CMOS 2.0 mA 7.68 MHz data clock, CMOS 8.0 7.5 mA mA 61.44 MHz data clock, CMOS 30.72 MHz data clock, CMOS 14.0 mA 61.44 MHz data clock, CMOS 0.3 mA 1.08 MHz data clock, CMOS 5.0 mA 20 MHz data clock, CMOS 0.7 5.6 6.0 mA mA mA 22.4 MHz data clock, CMOS 22.4 MHz data clock, CMOS 44.8 MHz data clock, CMOS 10.7 mA 44.8 MHz data clock, CMOS Rev. D | Page 9 of 32 AD9363 Data Sheet Table 5. VDD_INTERFACE = 2.5 V Parameter SLEEP MODE ONE Rx CHANNEL, ONE Tx CHANNEL, DDR LTE10 Single Port Dual Port LTE20 Dual Port TWO Rx CHANNELS, TWO Tx CHANNELS, DDR LTE3 Dual Port LTE10 Single Port Dual Port LTE20 Dual Port GSM Dual Port WiMAX 8.75 MHz Dual Port WiMAX 10 MHz Single Port TDD Rx TDD Tx FDD WiMAX 20 MHz Dual Port FDD Min Typ 150 Max Unit μA Test Conditions/Comments Power applied, device disabled 6.5 6.0 mA mA 30.72 MHz data clock, CMOS 15.36 MHz data clock, CMOS 11.5 mA 30.72 MHz data clock, CMOS 3.0 mA 7.68 MHz data clock, CMOS 11.5 10.0 mA mA 61.44 MHz data clock, CMOS 30.72 MHz data clock, CMOS 20.0 mA 61.44 MHz data clock, CMOS 0.5 mA 1.08 MHz data clock, CMOS 7.3 mA 20 MHz data clock, CMOS 1.3 8.0 8.7 mA mA mA 22.4 MHz data clock, CMOS 22.4 MHz data clock, CMOS 44.8 MHz data clock, CMOS 15.3 mA 44.8 MHz data clock, CMOS Rev. D | Page 10 of 32 Data Sheet AD9363 CURRENT CONSUMPTION—VDDx (COMBINATION OF ALL 1.3 V SUPPLIES) Table 6. TDD Mode, 800 MHz Parameter ONE Rx CHANNEL 5 MHz BW 10 MHz BW 20 MHz BW TWO Rx CHANNELS 5 MHz BW 10 MHz BW 20 MHz BW ONE Tx CHANNEL 5 MHz BW 7 dBm −27 dBm 10 MHz BW 7 dBm −27 dBm 20 MHz BW 7 dBm −27 dBm TWO Tx CHANNELS 5 MHz BW 7 dBm −27 dBm 10 MHz BW 7 dBm −27 dBm 20 MHz BW 7 dBm −27 dBm Min Typ Max Unit 180 210 260 mA mA mA 265 315 405 mA mA mA Test Conditions/Comments Continuous Rx Continuous Rx Continuous Tx 340 190 mA mA 360 220 mA mA 400 250 mA mA Continuous Tx 550 260 mA mA 600 310 mA mA 660 370 mA mA Rev. D | Page 11 of 32 AD9363 Data Sheet Table 7. TDD Mode, 2.4 GHz Parameter ONE Rx CHANNEL 5 MHz BW 10 MHz BW 20 MHz BW TWO Rx CHANNELS 5 MHz BW 10 MHz BW 20 MHz BW ONE Tx CHANNEL 5 MHz BW 7 dBm −27 dBm 10 MHz BW 7 dBm −27 dBm 20 MHz BW 7 dBm −27 dBm TWO Tx CHANNELS 5 MHz BW 7 dBm −27 dBm 10 MHz BW 7 dBm −27 dBm 20 MHz BW 7 dBm −27 dBm Min Typ Max Unit 175 200 240 mA mA mA 260 305 390 mA mA mA Test Conditions/Comments Continuous Rx Continuous Rx Continuous Tx 350 160 mA mA 380 220 mA mA 410 260 mA mA Continuous Tx 580 280 mA mA 635 330 mA mA 690 390 mA mA Rev. D | Page 12 of 32 Data Sheet AD9363 Table 8. FDD Mode, 800 MHz Parameter ONE Rx CHANNEL, ONE Tx CHANNEL 5 MHz BW 7 dBm −27 dBm 10 MHz BW 7 dBm −27 dBm 20 MHz BW 7 dBm −27 dBm TWO Rx CHANNELS, ONE Tx CHANNEL 5 MHz BW 7 dBm −27 dBm 10 MHz BW 7 dBm −27 dBm 20 MHz BW 7 dBm −27 dBm ONE Rx CHANNEL, TWO Tx CHANNELS 5 MHz BW 7 dBm −27 dBm 10 MHz BW 7 dBm −27 dBm 20 MHz BW 7 dBm −27 dBm TWO Rx CHANNELS, TWO Tx CHANNELS 5 MHz BW 7 dBm −27 dBm 10 MHz BW 7 dBm −27 dBm 20 MHz BW 7 dBm −27 dBm Min Typ Max Unit 490 345 mA mA 540 395 mA mA 615 470 mA mA Test Conditions/Comments Continuous Rx and Tx Continuous Rx and Tx 555 410 mA mA 625 480 mA mA 740 600 mA mA Continuous Rx and Tx 685 395 mA mA 755 465 mA mA 850 570 mA mA 790 495 mA mA 885 590 mA mA 1020 730 mA mA Rev. D | Page 13 of 32 AD9363 Data Sheet Table 9. FDD Mode, 2.4 GHz Parameter ONE Rx CHANNEL, ONE Tx CHANNEL 5 MHz BW 7 dBm −27 dBm 10 MHz BW 7 dBm −27 dBm 20 MHz BW 7 dBm −27 dBm TWO Rx CHANNELS, ONE Tx CHANNEL 5 MHz BW 7 dBm −27 dBm 10 MHz BW 7 dBm −27 dBm 20 MHz BW 7 dBm −27 dBm ONE Rx CHANNEL, TWO Tx CHANNELS 5 MHz BW 7 dBm −27 dBm 10 MHz BW 7 dBm −27 dBm 20 MHz BW 7 dBm −27 dBm TWO Rx CHANNELS, TWO Tx CHANNELS 5 MHz BW 7 dBm −27 dBm 10 MHz BW 7 dBm −27 dBm 20 MHz BW 7 dBm −27 dBm Min Typ Max Unit 500 350 mA mA 540 390 mA mA 620 475 mA mA Test Conditions/Comments Continuous Rx and Tx Continuous Rx and Tx 590 435 mA mA 660 510 mA mA 770 620 mA mA Continuous Rx and Tx 730 425 mA mA 800 500 mA mA 900 600 mA mA Continuous Rx and Tx 820 515 mA mA 900 595 mA mA 1050 740 mA mA Rev. D | Page 14 of 32 Data Sheet AD9363 ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE Table 10. The AD9363 reflow profile is in accordance with the JEDEC JESD20 criteria for Pb-free devices. The maximum reflow temperature is 260°C. Parameter VDDx to VSSx VDD_INTERFACE to VSSx VDD_GPO to VSSx Logic Inputs and Outputs to VSSx Input Current to Any Pin Except Supplies RF Inputs (Peak Power) Tx Monitor Input Power (Peak Power) Package Power Dissipation Maximum Junction Temperature (TJMAX) Temperature Range Operating Storage Reflow Rating −0.3 V to +1.4 V −0.3 V to +3.0 V −0.3 V to +3.9 V −0.3 V to VDD_INTERFACE + 0.3 V ±10 mA THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. θJA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. 2.5 dBm 9 dBm (TJMAX − TA)/θJA 110°C θJC is the junction to case thermal resistance. Table 11. Thermal Resistance Package Type BC-144-71 −40°C to +85°C −65°C to +150°C 260°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Airflow Velocity (m/sec) 0 1.0 2.5 1 θJA2 32.3 29.6 27.8 θJC3 9.6 N/A4 N/A4 Per JEDEC JESD51-7, plus JEDEC JESD51-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). Per MIL-STD-883, Method 1012.1. 4 N/A means not applicable. 2 3 ESD CAUTION Rev. D | Page 15 of 32 Unit °C/W °C/W °C/W AD9363 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A 1 2 3 4 5 6 7 8 9 RX2A_N RX2A_P DNC VSSA TX_MON2 VSSA TX2A_N TX2A_P TX2B_N 10 11 12 TX2B_P VDDA1P1_ TX_VCO VSSA TX_VCO_ LDO_OUT VSSA B VSSA VSSA AUXDAC1 GPO_3 GPO_2 GPO_1 GPO_0 VDD_GPO VDDA1P3_ TX_LO VDDA1P3_ TX_VCO_ LDO C RX2C_P VSSA AUXDAC2 TEST/ ENABLE CTRL_IN0 CTRL_IN1 VSSA VSSA VSSA VSSA VSSA VSSA D RX2C_N VDDA1P3_ RX_RF VDDA1P3_ CTRL_OUT0 RX_TX CTRL_IN3 CTRL_IN2 P0_D9/ TX_D4_P P0_D7/ TX_D3_P P0_D5/ TX_D2_P P0_D3/ TX_D1_P P0_D1/ TX_D0_P VSSD VDDA1P3_ TX_LO_ CTRL_OUT1 CTRL_OUT2 CTRL_OUT3 BUFFER P0_D11/ TX_D5_P P0_D8/ TX_D4_N P0_D6/ TX_D3_N P0_D4/ TX_D2_N P0_D2/ TX_D1_N P0_D0/ TX_D0_N VSSD P0_D10/ TX_D5_N VSSD FB_CLK_P VSSD VDDD1P3_ DIG E RX2B_P VDDA1P3_ RX_LO F RX2B_N VDDA1P3_ RX_VCO_ LDO VSSA G VSSA RX_VCO_ LDO_OUT VDDA1P1_ RX_VCO CTRL_OUT7 EN_AGC ENABLE RX_ FRAME_N RX_ FRAME_P TX_ FRAME_P FB_CLK_N DATA_ CLK_P VSSD H RX1B_P VSSA VSSA TXNRX VSSA VSSA VSSD P1_D11/ RX_D5_P TX_ FRAME_N VSSD DATA_ CLK_N VDD_ INTERFACE J RX1B_N VSSA VDDA1P3_ RX_SYNTH SPI_DI SPI_CLK CLK_OUT P1_D10/ RX_D5_N P1_D9/ RX_D4_P P1_D7/ RX_D3_P P1_D5/ RX_D2_P P1_D3/ RX_D1_P P1_D1/ RX_D0_P K RX1C_P VSSA VDDA1P3_ TX_SYNTH VDDA1P3_ BB RESET SPI_EN P1_D8/ RX_D4_N P1_D6/ RX_D3_N P1_D4/ RX_D2_N P1_D2/ RX_D1_N P1_D0/ RX_D0_N VSSD L RX1C_N VSSA VSSA RBIAS AUXADC SPI_DO VSSA VSSA VSSA VSSA VSSA VSSA M RX1A_P RX1A_N DNC VSSA TX_MON1 VSSA TX1A_P TX1A_N TX1B_P TX1B_N DNC XTALN DC POWER GROUND 10558-002 ANALOG I/O DIGITAL I/O DO NOT CONNECT CTRL_OUT6 CTRL_OUT5 CTRL_OUT4 Figure 2. Pin Configuration, Top View Table 12. Pin Function Descriptions Pin No. A1, A2 Type1 I Mnemonic RX2A_N, RX2A_P A3, M3, M11 A4, A6, A12, B1, B2, B12, C2, C7 to C12, F3, G1, H2, H3, H5, H6, J2, K2, L2, L3, L7 to L12, M4, M6 A5 A7, A8 A9, A10 A11 B3 NC GND DNC VSSA I O O P O TX_MON2 TX2A_N, TX2A_P TX2B_N, TX2B_P VDDA1P1_TX_VCO AUXDAC1 B4 to B7 B8 O I GPO_3 to GPO_0 VDD_GPO B9 B10 B11 I I O VDDA1P3_TX_LO VDDA1P3_TX_VCO_LDO TX_VCO_LDO_OUT C1, D1 I RX2C_P, RX2C_N C3 O AUXDAC2 C4 C5, C6, D5, D6 I I TEST/ENABLE CTRL_IN0 to CTRL_IN3 Description Receive Channel 2 Differential A Inputs. Alternatively, each pin can be used as a single-ended input. Unused pins must be tied to ground. Do Not Connect. Do not connect to these pins. Analog Ground. Tie these pins directly to the VSSD digital ground on the PCB (one ground plane). Transmit Channel 2 Power Monitor Input. If this pin is unused, tie it to ground. Transmit Channel 2 Differential A Outputs. Unused pins must be tied to 1.3 V. Transmit Channel 2 Differential B Outputs. Unused pins must be tied to 1.3 V. Transmit VCO Supply Input. Connect to B11. Auxiliary DAC 1 Output. If using the auxiliary DAC, connect a 0.1 µF capacitor from this pin to ground. 3.3 V Capable General-Purpose Outputs. 2.5 V to 3.3 V Supply for the AUXDAC and General-Purpose Output Pins. If the VDD_GPO supply is not used, this supply must be set to 1.3 V. Transmit Local Oscillator (LO) 1.3 V Supply Input. Transmit VCO LDO 1.3 V Supply Input. Connect to B9. Transmit VCO LDO Output. Connect to A11 and to a 1 μF bypass capacitor in series with a 1 Ω resistor to ground. Receive Channel 2 Differential C Inputs. Alternatively, use each pin as a single-ended input. Unused pins must be tied to ground. Auxiliary DAC 2 Output. If using the auxiliary DAC, connect a 0.1 µF capacitor from this pin to ground. Test Input. Ground this pin for normal operation. Control Inputs. Use these pins for manual Rx gain and Tx attenuation control. Rev. D | Page 16 of 32 Data Sheet AD9363 Pin No. D2 D3 D4, E4 to E6, F4 to F6, G4 Type1 I I O D7 I/O Mnemonic VDDA1P3_RX_RF VDDA1P3_RX_TX CTRL_OUT0, CTRL_OUT1 to CTRL_OUT3, CTRL_OUT6 to CTRL_OUT4, CTRL_OUT7 P0_D9/TX_D4_P D8 I/O P0_D7/TX_D3_P D9 I/O P0_D5/TX_D2_P D10 I/O P0_D3/TX_D1_P D11 I/O P0_D1/TX_D0_P D12, F7, F9, F11, G12, H7, H10, K12 E1, F1 GND VSSD I RX2B_P, RX2B_N E2 E3 E7 I I I/O VDDA1P3_RX_LO VDDA1P3_TX_LO_BUFFER P0_D11/TX_D5_P E8 I/O P0_D8/TX_D4_N E9 I/O P0_D6/TX_D3_N E10 I/O P0_D4/TX_D2_N E11 I/O P0_D2/TX_D1_N E12 I/O P0_D0/TX_D0_N F2 I VDDA1P3_RX_VCO_LDO Description Receiver 1.3 V Supply Input. Connect to D3. Receiver and Transmitter 1.3 V Supply Input. Control Outputs. These pins are multipurpose outputs that have programmable functionality. Digital Data Port 0, Data Bit 9/Transmit Differential Input Bus, Data Bit 4. This is a dual function pin. As P0_D9, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, as TX_D4_P, it functions as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Digital Data Port 0, Data Bit 7/Transmit Differential Input Bus, Data Bit 3. This is a dual function pin. As P0_D7, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, as TX_D3_P, it functions as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Digital Data Port 0, Data Bit 5/Transmit Differential Input Bus, Data Bit 2. This is a dual function pin. As P0_D5, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, as TX_D2_P, it functions as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Digital Data Port 0, Data Bit 3/Transmit Differential Input Bus, Data Bit 1. This is a dual function pin. As P0_D3, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, as TX_D1_P, it functions as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Digital Data Port 0, Data Bit 1/Transmit Differential Input Bus, Data Bit 0. This is a dual function pin. As P0_D1, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, as TX_D0_P, it functions as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Digital Ground. Tie these pins directly to the VSSA analog ground on the PCB (one ground plane). Receive Channel 2 Differential B Inputs. Alternatively, each pin can be used as a single-ended input. Unused pins must be tied to ground. Receive LO 1.3 V Supply Input. Transmitter LO Buffer 1.3 V Supply Input. Digital Data Port 0, Data Bit 11/Transmit Differential Input Bus, Data Bit 5. This is a dual function pin. As P0_D11, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, as TX_D5_P, it functions as part of the LVDS 6bit Tx differential input bus with internal LVDS termination. Digital Data Port 0, Data Bit 8/Transmit Differential Input Bus, Data Bit 4. This is a dual function pin. As P0_D8, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, as TX_D4_N, it functions as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Digital Data Port 0, Data Bit 6/Transmit Differential Input Bus, Data Bit 3. This is a dual function pin. As P0_D6, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, as TX_D3_N, it functions as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Digital Data Port 0, Data Bit 4/Transmit Differential Input Bus, Data Bit 2. This is a dual function pin. As P0_D4, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, as TX_D2_N, it functions as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Digital Data Port 0, Data Bit 2/Transmit Differential Input Bus, Data Bit 1. This is a dual function pin. As P0_D2, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, as TX_D1_N, it functions as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Digital Data Port 0, Data Bit 0/Transmit Differential Input Bus, Data Bit 0. This is a dual function pin. As P0_D0, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, as TX_D0_N, it functions as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Receive VCO LDO 1.3 V Supply Input. Connect to E2. Rev. D | Page 17 of 32 AD9363 Data Sheet Pin No. F8 Type1 I/O Mnemonic P0_D10/TX_D5_N F10, G10 I FB_CLK_P, FB_CLK_N F12 G2 I O VDDD1P3_DIG RX_VCO_LDO_OUT G3 G5 G6 G7, G8 I I I O VDDA1P1_RX_VCO EN_AGC ENABLE RX_FRAME_N, RX_FRAME_P G9, H9 I TX_FRAME_P, TX_FRAME_N G11, H11 O DATA_CLK_P, DATA_CLK_N H1, J1 I RX1B_P, RX1B_N H4 I TXNRX H8 I/O P1_D11/RX_D5_P H12 J3 J4 J5 J6 I I I I O VDD_INTERFACE VDDA1P3_RX_SYNTH SPI_DI SPI_CLK CLK_OUT J7 I/O P1_D10/RX_D5_N J8 I/O P1_D9/RX_D4_P J9 I/O P1_D7/RX_D3_P J10 I/O P1_D5/RX_D2_P J11 I/O P1_D3/RX_D1_P Description Digital Data Port 0, Data Bit 10/Transmit Differential Input Bus, Data Bit 5. This is a dual function pin. As P0_D10, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, as TX_D5_N, it functions as part of the LVDS 6bit Tx differential input bus with internal LVDS termination. Feedback Clock Inputs. These pins receive the FB_CLK signal that clocks in Tx data. In CMOS mode, use FB_CLK_P as the input and tie FB_CLK_N to ground. 1.3 V Digital Supply Input. Receive VCO LDO Output. Connect to G3 and to a 1 μF bypass capacitor in series with a 1 Ω resistor to ground. Receive VCO Supply Input. Connect to G2. Manual Control Input for Automatic Gain Control (AGC). Control Input. This pin moves the device through various operational states. Receive Digital Data Framing Outputs. These pins transmit the RX_FRAME signal that indicates whether the Rx output data is valid. In CMOS mode, use RX_FRAME_P as the output and leave RX_FRAME_N unconnected. Transmit Digital Data Framing Inputs. These pins receive the TX_FRAME signal that indicates when Tx data is valid. In CMOS mode, use TX_FRAME_P as the input and tie TX_FRAME_N to ground. Receive Data Clock Outputs. These pins transmit the DATA_CLK signal that the BBP uses to clock the Rx data. In CMOS mode, use DATA_CLK_P as the output and leave DATA_CLK_N unconnected. Receive Channel 1 Differential B Inputs. Alternatively, use each pin as a single-ended input. Unused pins must be tied to ground. Enable State Machine Control Signal. This pin controls the data port bus direction. A logic low selects the Rx direction; a logic high selects the Tx direction. Digital Data Port P1, Data Bit 11/Receive Differential Output Bus, Data Bit 5. This is a dual function pin. As P1_D11, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, as RX_D5_P, it functions as part of the LVDS 6bit Rx differential output bus with internal LVDS termination. 1.2 V to 2.5 V Supply for Digital I/O Pins (1.8 V to 2.5 V in LVDS Mode). Receiver Synthesizer 1.3 V Supply Input. SPI Serial Data Input. SPI Clock Input. Output Clock. This pin can be configured to output either a buffered version of the external input clock (the digital controlled crystal oscillator (DCXO)) or a divideddown version of the internal ADC sample clock (ADC_CLK). Digital Data Port 1, Data Bit 10/Receive Differential Output Bus, Data Bit 5. This is a dual function pin. As P1_D10, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, as RX_D5_N, it functions as part of the LVDS 6bit Rx differential output bus with internal LVDS termination. Digital Data Port 1, Data Bit 9/Receive Differential Output Bus, Data Bit 4. This is a dual function pin. As P1_D9, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, as RX_D4_P, it functions as part of the LVDS 6bit Rx differential output bus with internal LVDS termination. Digital Data Port 1, Data Bit 7/Receive Differential Output Bus, Data Bit 3. This is a dual function pin. As P1_D7, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, as RX_D3_P, it functions as part of the LVDS 6bit Rx differential output bus with internal LVDS termination. Digital Data Port 1, Data Bit 5/Receive Differential Output Bus, Data Bit 2. This is a dual function pin. As P1_D5, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, as RX_D2_P, it functions as part of the LVDS 6bit Rx differential output bus with internal LVDS termination. Digital Data Port 1, Data Bit 3/Receive Differential Output Bus, Data Bit 1. This is a dual function pin. As P1_D3, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, as RX_D1_P, it functions as part of the LVDS 6bit Rx differential output bus with internal LVDS termination. Rev. D | Page 18 of 32 Data Sheet AD9363 Pin No. J12 Type1 I/O Mnemonic P1_D1/RX_D0_P K1, L1 I RX1C_P, RX1C_N K3 I VDDA1P3_TX_SYNTH K4 I VDDA1P3_BB K5 K6 K7 I I I/O RESET SPI_EN P1_D8/RX_D4_N K8 I/O P1_D6/RX_D3_N K9 I/O P1_D4/RX_D2_N K10 I/O P1_D2/RX_D1_N K11 I/O P1_D0/RX_D0_N L4 I RBIAS L5 L6 M1, M2 I O I AUXADC SPI_DO RX1A_P, RX1A_N M5 M7, M8 M9, M10 M12 I O O I TX_MON1 TX1A_P, TX1A_N TX1B_P, TX1B_N XTALN 1 Description Digital Data Port 1, Data Bit 1/Receive Differential Output Bus, Data Bit 0. This is a dual function pin. As P1_D1, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, as RX_D0_P, it functions as part of the LVDS 6bit Rx differential output bus with internal LVDS termination. Receive Channel 1 Differential C Inputs. Alternatively, use each pin as a single-ended input. Tie unused pins to ground. Transmitter Synthesizer 1.3 V Supply Input. Connect this pin to a 1.3 V regulator through a separate trace to a common supply point. Baseband 1.3 V Supply Input. Connect this pin to a 1.3 V regulator through a separate trace to a common supply point. Asynchronous Reset Input. A logic low resets the device. SPI Enable. Set this pin to logic low to enable the SPI bus. Digital Data Port 1, Data Bit 8/Receive Differential Output Bus, Data Bit 4. This is a dual function pin. As P1_D8, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, as RX_D4_N, it functions as part of the LVDS 6bit Rx differential output bus with internal LVDS termination. Digital Data Port 1, Data Bit 6/Receive Differential Output Bus, Data Bit 3. This is a dual function pin. As P1_D6, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, as RX_D3_N, it functions as part of the LVDS 6bit Rx differential output bus with internal LVDS termination. Digital Data Port 1, Data Bit 4/Receive Differential Output Bus, Data Bit 2. This is a dual function pin. As P1_D4, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, as RX_D2_N, it functions as part of the LVDS 6bit Rx differential output bus with internal LVDS termination. Digital Data Port 1, Data Bit 2/Receive Differential Output Bus, Data Bit 1. This is a dual function pin. As P1_D2, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, as RX_D1_N, it functions as part of the LVDS 6bit Rx differential output bus with internal LVDS termination. Digital Data Port 1, Data Bit 0/Receive Differential Output Bus, Data Bit 0. This is a dual function pin. As P1_D0, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, as RX_D0_N, it functions as part of the LVDS 6bit Rx differential output bus with internal LVDS termination. Bias Input Reference. Connect this pin through a 14.3 kΩ (1% tolerance) resistor to ground. Auxiliary ADC Input. If this pin is unused, tie it to ground. SPI Serial Data Output in 4-Wire Mode, High-Z in 3-Wire Mode. Receive Channel 1 Differential A Inputs. Alternatively, use each pin as a single-ended input. Tie unused pins to ground. Transmit Channel 1 Power Monitor Input. If this pin is unused, tie it to ground. Transmit Channel 1 Differential A Outputs. Tie unused pins to 1.3 V. Transmit Channel 1 Differential B Outputs. Tie unused pins to 1.3 V. Reference Frequency Connection. Connect the external clock source to XTALN. I is input, NC is not connected, GND is ground, O is output, P is power, and I/O is input/output. Rev. D | Page 19 of 32 AD9363 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS ATTEN is the attenuation setting. fLO_RX and fLO_TX are the receive and transmit local oscillator frequencies, respectively. 800 MHZ FREQUENCY BAND 0 4.0 –4 3.0 2.5 Rx EVM (dB) Rx NOISE FIGURE (dB) –40°C +25°C +85°C –40°C +25°C +85°C 3.5 2.0 1.5 –8 –12 1.0 750 800 850 900 RF FREQUENCY (MHz) Figure 3. Rx Noise Figure vs. RF Frequency 5 –16 –56 10558-003 0 700 –52 –50 –48 –46 –44 –42 –40 –38 –36 INTERFERER POWER LEVEL (dBm) Figure 6. Rx EVM vs. Interferer Power Level, LTE 10 MHz Signal of Interest with PIN = −90 dBm, 5 MHz OFDM Blocker at 17.5 MHz Offset 14 –40°C +25°C +85°C 4 –54 10558-007 0.5 12 –40°C +25°C +85°C Rx NOISE FIGURE (dB) 2 1 0 –1 –80 –70 –60 –50 –40 –30 –20 –10 6 4 0 –47 10558-004 –90 Rx INPUT POWER (dBm) Figure 4. RSSI Error vs. Rx Input Power, LTE 10 MHz Modulation (Referenced to −50 dBm Input Power at 800 MHz) 0 8 2 –2 –3 –100 10 –43 –39 –35 –31 –27 –23 INTERFERER POWER LEVEL (dBm) 10558-008 RSSI ERROR (dB) 3 Figure 7. Rx Noise Figure vs. Interferer Power Level, Enhanced Data Rates for GSM Evolution (EDGE) Signal of Interest with PIN = −90 dBm, Continuous Wave (CW) Blocker at 3 MHz Offset, Gain Index = 64 80 –40°C +25°C +85°C –40°C +25°C +85°C 78 –5 76 Rx GAIN (dB) Rx EVM (dB) –10 –15 74 72 –20 70 –25 –64 –60 –56 –52 –48 –44 –40 INTERFERER POWER LEVEL (dBm) –36 –32 66 700 Figure 5. Rx EVM vs. Interferer Power Level, LTE 10 MHz Signal of Interest with PIN = −82 dBm, 5 MHz Orthogonal Frequency Division Multiplexing (OFDM) Blocker at 7.5 MHz Offset 750 800 Rx LO FREQUENCY (MHz) 850 900 10558-009 –68 10558-006 –30 –72 68 Figure 8. Rx Gain vs. Rx LO Frequency, Gain Index = 76 (Maximum Setting) Rev. D | Page 20 of 32 Data Sheet AD9363 0 15 10 IIP3 (dBm) 5 0 –5 –40°C +25°C +85°C –10 –15 –25 20 28 36 44 52 Rx GAIN INDEX 60 68 76 Figure 9. Third-Order Input Intercept Point (IIP3) vs. Rx Gain Index, f1 = 1.45 MHz, f2 = 2.89 MHz, GSM Mode –40 –60 –80 –100 –120 10558-010 –20 –20 0 2000 6000 4000 10000 8000 12000 FREQUENCY (MHz) 10558-013 Rx EMISSION AT LNA INPUT (dBm/750kHz) 20 Figure 12. Rx Emission at LNA Input vs. Frequency, DC to 12 GHz, fLO_RX = 800 MHz, LTE 10 MHz, fLO_TX = 860 MHz 10.0 100 90 –40°C +25°C +85°C 9.5 Tx OUTPUT POWER (dBm) 80 IIP2 (dBm) 70 60 50 40 30 9.0 8.5 8.0 7.5 7.0 20 44 52 60 68 76 Rx GAIN INDEX Figure 10. Second-Order Input Intercept Point (IIP2) vs. Rx Gain Index, f1 = 2.00 MHz, f2 = 2.01 MHz, GSM Mode –100 –40°C +25°C +85°C –110 –115 –120 –125 750 800 850 Rx LO FREQUENCY (MHz) Figure 11. Rx LO Leakage vs. Rx LO Frequency 900 10558-012 Rx LO LEAKAGE (dBm) –105 –130 700 6.0 700 750 800 850 900 Tx LO FREQUENCY (MHz) 10558-014 36 Figure 13. Tx Output Power vs. Tx LO Frequency, Attenuation Setting = 0 dB, Single-Tone Output 0.5 –40°C +25°C +85°C 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 10 20 30 ATTENUATION SETTING (dB) 40 50 10558-015 28 Tx POWER CONTROL STEP LINEARITY ERROR (dB) 0 20 6.5 –40°C +25°C +85°C 10558-011 10 Figure 14. Tx Power Control Step Linearity Error vs. Attenuation Setting Rev. D | Page 21 of 32 Data Sheet –20 –30 –40 –50 –60 –70 –80 –100 –15 –10 –5 0 5 10 15 FREQUENCY OFFSET FROM CARRIER FREQUENCY (MHz) 10558-016 –90 –40°C +25°C +85°C 0.4 0.3 0.2 0.1 0 700 750 800 850 900 FREQUENCY (MHz) –70 –75 –80 700 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C 800 750 850 900 Figure 18. Tx Second-Order Harmonic Distortion (HD2) vs. Frequency –20 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C –25 ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –30 –35 –40 –45 –50 –55 –60 700 750 800 850 900 FREQUENCY (MHz) Figure 19. Tx Third-Order Harmonic Distortion (HD3) vs. Frequency 30 ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –40°C +25°C +85°C 25 Tx OIP3 (dBm) –40 –45 –50 –55 20 15 10 –60 5 –65 –70 700 750 800 850 FREQUENCY (MHz) Figure 17. Tx Carrier Rejection vs. Frequency 900 0 10558-020 Tx CARRIER REJECTION (dBc) –35 –65 FREQUENCY (MHz) Figure 16. Integrated Tx LO Phase Noise vs. Frequency, 19.2 MHz REF_CLK –30 ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –60 10558-019 INTEGRATED Tx LO PHASE NOISE (°rms) 0.5 ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C –55 Tx THIRD-ORDER HARMONIC DISTORTION (dBc) Figure 15. Tx Output Power vs. Frequency Offset from Carrier Frequency, fLO_TX = 800 MHz, LTE 10 MHz Downlink (Digital Attenuation Variations Shown) ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C 0 4 8 12 Tx ATTENUATION SETTING (dB) 16 20 10558-023 Tx OUTPUT POWER (dBm/100kHz) –10 –50 10558-021 ATT 0dB ATT 3dB ATT 6dB 10558-022 0 Tx SECOND-ORDER HARMONIC DISTORTION (dBc) AD9363 Figure 20. Tx Third-Order Output Intercept Point (OIP3) vs. Tx Attenuation Setting Rev. D | Page 22 of 32 Data Sheet –30 Tx SINGLE SIDEBAND REJECTION (dBc) –40°C +25°C +85°C Tx SNR (dB/Hz) 165 160 155 150 140 0 3 6 9 Tx ATTENUATION SETTING (dB) 12 15 10558-024 145 Figure 21. Tx Signal-to-Noise Ratio (SNR) vs. Tx Attenuation Setting, LTE 10 MHz Signal of Interest with Noise Measured at 90 MHz Offset Rev. D | Page 23 of 32 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C –35 ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –40 –45 –50 –55 –60 –65 –70 700 750 800 850 FREQUENCY (MHz) Figure 22. Tx Single Sideband Rejection vs. Frequency, 1.5375 MHz Offset 900 10558-026 170 AD9363 AD9363 Data Sheet 2.4 GHZ FREQUENCY BAND 0 4.0 3.5 –40°C +25°C +85°C –10 2.5 RX EVM (dB) Rx NOISE FIGURE (dB) –5 3.0 2.0 1.5 –15 –20 1.0 1900 2000 2100 2200 2300 2400 2500 2600 2700 RF FREQUENCY (MHz) Figure 23. Rx Noise Figure vs. RF Frequency 5 4 –30 –60 10558-027 0 1800 –40°C +25°C +85°C –55 –50 –45 –40 –35 –30 –25 10558-043 –25 0.5 –20 INTERFERER POWER LEVEL (dBm) Figure 26. Rx EVM vs. Interferer Power Level, LTE 20 MHz Signal of Interest with PIN = −75 dBm, LTE 20 MHz Blocker at 40 MHz Offset 80 –40°C +25°C +85°C 78 –40°C +25°C +85°C 3 Rx GAIN (dB) 1 0 74 72 70 –1 68 –2 –90 –80 –70 –60 –50 –40 –30 –20 –10 INPUT POWER (dBm) Figure 24. RSSI Error vs. Input Power (Referenced to −50 dBm Input Power at 2.4 GHz) 0 66 1800 10558-028 –3 –100 1900 2000 2100 2200 2300 2400 2500 2600 10558-029 RSSI ERROR (dB) 76 2 2700 Rx LO FREQUENCY (MHz) Figure 27. Rx Gain vs. Rx LO Frequency, Gain Index = 76 (Maximum Setting) 20 –40°C +25°C +85°C 15 –40°C +25°C +85°C –5 10 5 IIP3 (dBm) RX EVM (dB) –10 –15 0 –5 –10 –20 –15 –25 –68 –64 –60 –56 –52 –48 –44 –40 INTERFERER POWER LEVEL (dBm) –36 –32 –28 Figure 25. Rx EVM vs. Interferer Power Level, LTE 20 MHz Signal of Interest with PIN = −75 dBm, LTE 20 MHz Blocker at 20 MHz Offset Rev. D | Page 24 of 32 –25 20 28 36 44 52 Rx GAIN INDEX 60 68 76 10558-030 –30 –72 10558-042 –20 Figure 28. Third-Order Input Intercept Point (IIP3) vs. Rx Gain Index, f1 = 30 MHz, f2 = 61 MHz Data Sheet AD9363 80 10.0 –40°C +25°C +85°C –40°C +25°C +85°C 9.5 Tx OUTPUT POWER (dBm) 70 IIP2 (dBm) 60 50 40 9.0 8.5 8.0 7.5 7.0 30 52 60 68 76 Rx GAIN INDEX Figure 29. Second-Order Input Intercept Point (IIP2) vs. Rx Gain Index, f1 = 60 MHz, f2 = 61 MHz –100 –40°C +25°C +85°C Rx LO LEAKAGE (dBm) –105 –110 –115 –120 1900 2000 2100 2200 2300 2400 2500 2600 2700 Rx LO FREQUENCY (MHz) 10558-032 –125 –130 1800 Figure 30. Rx Local Oscillator (LO) Leakage vs. Rx LO Frequency 0.5 –80 –100 10000 12000 FREQUENCY (MHz) Figure 31. Rx Emission at LNA Input vs. Frequency, DC to 12 GHz, fLO_RX = 2.4 GHz, LTE 20 MHz, fLO_TX = 2.46 GHz 2500 2600 2700 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 10 20 30 40 50 ATTENUATION SETTING (dB) Tx OUTPUT POWER (dBm/100kHz) –60 8000 2400 Figure 33. Tx Power Control Step Linearity Error vs. Attenuation Setting –40 6000 2300 0.2 –20 4000 2200 0.3 –20 2000 2100 –40°C +25°C +85°C 0.4 0 0 2000 Figure 32. Tx Output Power vs. Tx LO Frequency, Attenuation Setting = 0 dB, Single-Tone Output 0 –120 1900 Tx LO FREQUENCY (MHz) ATT 0dB ATT 3dB ATT6dB –40 –60 –80 –100 –120 –25 10558-044 Rx EMISSION AT LNA INPUT (dBm/750kHz) 6.0 1800 10558-034 44 –20 –15 –10 –5 0 5 10 15 20 FREQUENCY OFFSET FROM CARRIER FREQUENCY (MHz) 25 10558-045 36 Tx POWER CONTROL STEP LINEARITY ERROR (dB) 28 10558-031 20 20 10558-033 6.5 Figure 34. Tx Output Power vs. Frequency Offset from Carrier Frequency, fLO_TX = 2.3 GHz, LTE 20 MHz Downlink (Digital Attenuation Variations Shown) Rev. D | Page 25 of 32 0.3 0.2 0.1 0 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 FREQUENCY (MHz) Figure 35. Integrated Tx LO Phase Noise vs. Frequency, 40 MHz REF_CLK ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –40 –45 –50 –55 –60 –65 –70 1800 1900 2000 2100 2200 2300 2400 2500 2600 FREQUENCY (MHz) 2700 –55 –60 –65 –70 –75 –80 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 Figure 37. Tx Second-Order Harmonic Distortion (HD2) vs. Frequency 10558-036 Tx CARRIER REJECTION (dBc) –35 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C FREQUENCY (MHz) Tx THIRD-ORDER HARMONIC DISTORTION (dBc) –30 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C 10558-037 0.4 –50 Figure 36. Tx Carrier Rejection vs. Frequency –20 –25 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C –30 –35 –40 –45 –50 –55 –60 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 FREQUENCY (MHz) Figure 38. Tx Third-Order Harmonic Distortion (HD3) vs. Frequency Rev. D | Page 26 of 32 10558-038 –40°C +25°C +85°C 10558-035 INTEGRATED Tx LO PHASE NOISE (°rms) 0.5 Data Sheet Tx SECOND-ORDER HARMONIC DISTORTION (dBc) AD9363 Data Sheet –30 Tx SINGLE SIDEBAND REJECTION (dBc) –40°C +25°C +85°C Tx OIP3 (dBm) 25 20 15 10 0 0 4 8 12 16 20 Tx ATTENUATION SETTING (dB) 10558-039 5 Figure 39. Tx Third-Order Output Intercept Point (OIP3) vs. Tx Attenuation Setting 160 –40°C +25°C +85°C 158 156 Tx SNR (dB/Hz) 154 152 150 148 146 144 140 0 3 6 9 Tx ATTENUATION SETTING (dB) 12 15 10558-040 142 Figure 40. Tx Signal-to-Noise Ratio (SNR) vs. Tx Attenuation Setting, LTE 20 MHz Signal of Interest with Noise Measured at 90 MHz Offset Rev. D | Page 27 of 32 ATT 0, –40°C ATT 25, –40°C ATT 50, –40°C –35 ATT 0, +25°C ATT 25, +25°C ATT 50, +25°C ATT 0, +85°C ATT 25, +85°C ATT 50, +85°C –40 –45 –50 –55 –60 –65 –70 1800 1900 2000 2100 2200 2300 2400 2500 2600 FREQUENCY (MHz) Figure 41. Tx Single Sideband Rejection vs. Frequency, 3.075 MHz Offset 2700 10558-041 30 AD9363 AD9363 Data Sheet THEORY OF OPERATION GENERAL TRANSMITTER The AD9363 is a highly integrated radio frequency (RF) transceiver capable of being configured for a wide range of applications. The device integrates all RF, mixed-signal, and digital blocks necessary to provide all transceiver functions in a single device. Programmability allows this broadband transceiver to be adapted for use with multiple communication standards, including FDD and TDD systems. This programmability also allows the device to interface to various BBPs using a single 12bit parallel data port, dual 12-bit parallel data ports, or a 12-bit low voltage differential signaling (LVDS) interface. The transmitter section consists of two identical and independently controlled channels that provide all digital processing, mixed-signal, and RF blocks necessary to implement a direct conversion system while sharing a common frequency synthesizer. The digital data received from the BBP passes through a fully programmable 128-tap FIR filter with interpolation options. The FIR output is sent to a series of interpolation filters that provide additional filtering and data rate interpolation prior to reaching the DAC. Each 12-bit DAC has an adjustable sampling rate. Both the I and Q channels are fed to the RF block for upconversion. The AD9363 also provides self calibration and AGC systems to maintain a high performance level under varying temperatures and input signal conditions. In addition, the device includes several test modes that allow system designers to insert test tones and create internal loopback modes to debug their designs during prototyping and optimize their radio configuration for a specific application. RECEIVER The receiver section contains all blocks necessary to receive RF signals and convert them to digital data that is usable by a BBP. Two independently controlled channels can receive signals from different sources, allowing the device to be used in multiple input, multiple output (MIMO) systems while sharing a common frequency synthesizer. Each channel has three inputs that can be multiplexed to the signal chain, making the AD9363 suitable for use in diversity systems with multiple antenna inputs. The receiver is a direct conversion system that contains a low noise amplifier (LNA) followed by matched in-phase (I) and quadrature (Q) amplifiers, mixers, and band shaping filters that downconvert received signals to baseband for digitization. External LNAs can also be interfaced to the device, allowing designers the flexibility to customize the receiver front end for their specific application. Gain control is achieved by following a preprogrammed gain index map that distributes gain among the blocks for optimal performance at each level. This gain control can be achieved by enabling the internal AGC in either fast or slow mode or by using manual gain control, allowing the BBP to make the gain adjustments as needed. Additionally, each channel contains independent RSSI measurement capability, dc offset tracking, and all circuitry necessary for self calibration. The receivers include 12-bit, sigma-delta (Σ-Δ) ADCs and adjustable sample rates that produce data streams from the received signals. The digitized signals can be conditioned further by a series of decimation filters and a fully programmable 128-tap FIR filter with additional decimation settings. The sample rate of each digital filter block can also be adjusted by changing the decimation factors to produce the desired output data rate. After being converted to baseband analog signals, the I and Q signals are filtered to remove sampling artifacts and provide band shaping, and then they are passed to the upconversion mixers. At this point, the I and Q signals are recombined and modulated on the carrier frequency for transmission to the output stage. The output stage provides attenuation control that provides a range of output levels while keeping the output impedance at 50 Ω. A wide range of attenuation adjustment with fine granularity is included to help designers optimize SNR. Self calibration circuitry is included in the transmit channel to provide internal adjustment capability. The transmitter also provides a Tx monitor block that receives the transmitter output and routes it back through an unused receiver channel to the BBP for signal monitoring. The Tx monitor blocks are available only in TDD mode operation while the receiver is idle. CLOCK INPUT OPTIONS The AD9363 uses a reference clock provided by an external oscillator or clock distribution device (such as the AD9548) connected to the XTALN pin. The frequency of this reference clock can vary from 10 MHz to 80 MHz. This reference clock supplies the synthesizer blocks that generate all data clocks, sample clocks, and local oscillators inside the device. SYNTHESIZERS RF PLLs The AD9363 contains two identical synthesizers to generate the required LO signals for the RF signal paths—one for the receiver and one for the transmitter. PLL synthesizers are fractional N designs that incorporate completely integrated VCOs and loop filters. In TDD mode, the synthesizers turn on and off as appropriate for the Rx and Tx frames. In FDD mode, the Tx PLL and the Rx PLL can be activated at the same time. These PLLs require no external components. Rev. D | Page 28 of 32 Data Sheet AD9363 BB PLL ENABLE STATE MACHINE The AD9363 also contains a baseband PLL (BB PLL) synthesizer that generates all baseband related clock signals. These signals include the ADC and DAC sampling clocks, the DATA_CLK signal (see the Digital Data Interface section), and all data framing signals. The BB PLL is programmed from 700 MHz to 1400 MHz based on the data rate and sample rate requirements of the system. The AD9363 transceiver includes an ENSM that allows realtime control over the current state of the device. The device can be placed in several different states during normal operation, including DIGITAL DATA INTERFACE The AD9363 data interface uses parallel data ports (P0 and P1) to transfer data between the device and the BBP. The data ports can be configured in either single-ended CMOS format or differential LVDS format. Both formats can be configured in multiple arrangements to match system requirements for data ordering and data port connections. These arrangements include single port data bus, dual port data bus, single data rate, double data rate, and various combinations of data ordering to transmit data from different channels across the bus at appropriate times. Bus transfers are controlled using simple hardware handshake signaling. The two ports can be operated in either bidirectional (TDD) mode or in full duplex (FDD) mode, where half the bits are used for transmitting data and half are used for receiving data. The interface can also be configured to use only one of the data ports for applications that do not require high data rates and require fewer interface pins. DATA_CLK Signal The AD9363 outputs the DATA_CLK signal that the BBP uses to sample receiver data. The signal is synchronized with the receiver data such that data transitions occur out of phase with DATA_CLK. The DATA_CLK can be set to a rate that provides single data rate (SDR) timing, where data is sampled on each rising clock edge, or it can be set to provide double data rate (DDR) timing, where data is captured on both rising and falling clock edges. SDR or DDR timing applies to operation using either a single port or both ports. FB_CLK Signal For transmit data, the interface uses the FB_CLK signal as the timing reference. The FB_CLK signal allows source synchronous timing with rising edge capture for burst control signals and either rising edge capture (SDR mode) or both edge capture (DDR mode) for transmit signal bursts. The FB_CLK signal must have the same frequency and duty cycle as DATA_CLK. RX_FRAME and TX_FRAME Signals The device generates an RX_FRAME output signal whenever the receiver outputs valid data. This signal has two modes: level mode (the RX_FRAME signal stays high as long as the data is valid) and pulse mode (the RX_FRAME signal pulses with a 50% duty cycle). Similarly, the BBP must provide a TX_FRAME signal that indicates the beginning of a valid data transmission with a rising edge. Like the RX_FRAME signal, the TX_FRAME signal stays high throughout the burst or it pulses with a 50% duty cycle. • • • • • • Wait—power save, synthesizers disabled Sleep—wait with all clocks and the BB PLL disabled Tx—Tx signal chain enabled Rx—Rx signal chain enabled FDD—Tx and Rx signal chains enabled Alert—synthesizers enabled The ENSM has two control modes: SPI control and pin control. SPI Control Mode In SPI control mode, the ENSM is controlled asynchronously by writing to SPI registers to advance the current state to the next state. SPI control is considered asynchronous to the DATA_CLK signal because the SPI clock can be derived from a different clock reference and can still function properly. The SPI control ENSM mode is recommended when real-time control of the synthesizers is not necessary. SPI control can be used for realtime control as long as the BBP can perform timed SPI writes accurately. Pin Control Mode In pin control mode, the enable functions of the ENABLE pin and the TXNRX pin allow real-time control of the current state. The ENSM allows TDD or FDD operation, depending on the configuration of the corresponding SPI register. The ENABLE and TXNRX pin control mode is recommended if the BBP has extra control outputs that can be controlled in real time, allowing a simple 2-wire interface to control the state of the device. To advance the current state of the ENSM to the next state, drive the enable function of the ENABLE pin by either a pulse (edge detected internally) or a level. When a pulse is used, it must have a minimum pulse width of one cycle of the FB_CLK signal. In level mode, the ENABLE and TXNRX pins are also edge detected by the AD9363 and must meet the same minimum pulse width requirement of one cycle of the FB_CLK signal. In FDD mode, the ENABLE and TXNRX pins can be remapped to serve as real-time Rx and Tx data transfer control signals. In this mode, the ENABLE pin assumes the receive on (RXON) function (controls when the Rx path is enabled and disabled), and the TXNRX pin assumes the transmit on (TXON) function (controls when the Tx path is enabled and disabled). The ENSM must be controlled by SPI writes in this mode while the ENABLE and TXNRX pins control all data flow. For more information about RXON and TXON, see the AD9363 reference manual, available from Integrated Wideband RF Transceiver Design Resources. Rev. D | Page 29 of 32 AD9363 Data Sheet SPI INTERFACE AUXILIARY CONVERTERS The AD9363 uses a serial peripheral interface (SPI) to communicate with the BBP. The SPI can be configured as a 4-wire interface with dedicated receive and transmit ports, or it can be configured as a 3-wire interface with a bidirectional data communication port. This bus allows the BBP to set all device control parameters using a simple address data serial bus protocol. AUXADC CONTROL PINS Control Outputs (CTRL_OUT7 to CTRL_OUT0) The AD9363 provides eight simultaneous real-time output signals for use as interrupts to the BBP. These outputs can be configured to output a number of internal settings and measurements that the BBP uses when monitoring trans-ceiver performance in different situations. The control output pointer register selects the information that is output to these pins, and the control output enable register determines which signals are activated for monitoring by the BBP. Signals used for manual gain mode, calibration flags, state machine states, and the ADC output are among the outputs that can be monitored on these pins. Control Inputs (CTRL_IN3 to CTRL_IN0) The AD9363 provides four edge detected control input pins. In manual gain mode, the BBP uses these pins to change the gain table index in real time. The AD9363 contains two identical auxiliary DACs that can provide power amplifier (PA) bias or other system functionality. The auxiliary DACs are 10 bits wide, have an output voltage range of 0.5 V to VDD_GPO − 0.3 V and a current drive of 10 mA, and can be directly controlled by the internal ENSM. POWERING THE AD9363 The AD9363 must be powered by the following three supplies: the analog supply (VDDx = 1.3 V), the interface supply (VDD_ INTERFACE = 1.8 V), and the GPO supply (VDD_GPO = 3.3 V). For applications requiring optimal noise performance, split and source the 1.3 V analog supply from low noise, low dropout (LDO) regulators. Figure 42 shows the recommended method. 3.3V ADP2164 1.8V ADP1755 1.3V_A ADP1755 1.3V_B 10558-074 Read commands follow a similar format with the exception that the first 16 bits are transferred on the SPI_DI pin, and the final eight bits are read from the AD9363, either on the SPI_DO pin in 4-wire mode or on the SPI_DI pin in 3-wire mode. AUXDAC1 and AUXDAC2 Figure 42. Low Noise Power Solution for the AD9363 For applications where board space is at a premium, and optimal noise performance is not an absolute requirement, provide the 1.3 V analog rail directly from a switcher, and adopt a more integrated power management unit (PMU) approach. Figure 43 shows this approach. GPO PINS (GPO_3 TO GPO_0) ADP5040 The AD9363 provides four 3.3 V capable general-purpose logic output pins: GPO_3, GPO_2, GPO_1, and GPO_0. These pins control other peripheral devices such as regulators and switches via the AD9363 SPI bus, or they function as slaves for the internal AD9363 state machine. 1.2A BUCK ADP1755 1.3V LDO VDDx AD9363 300mA LDO 1.8V 300mA LDO 3.3V VDD_INTERFACE VDD_GPO Figure 43. Space Optimized Power Solution for the AD9363 Rev. D | Page 30 of 32 10558-075 Write commands follow a 24-bit format. The first six bits set the bus direction and number of bytes to transfer. The next 10 bits set the address where data is to be written. The final eight bits are the data to be transferred to the specified register address (MSB to LSB). The AD9363 also supports an LSB first format that allows the commands to be written in LSB to MSB format. In this mode, the register addresses are incremented for multibyte writes. The AD9363 contains an auxiliary ADC that monitors system functions such as temperature or power output. The converter is 12 bits wide and has an input range of 0.05 V to VDDA1P3_BB − 0.05 V. When enabled, the ADC is free running. SPI reads provide the last value latched at the ADC output. A multiplexer in front of the ADC allows the user to select between the AUXADC input pin and a built-in temperature sensor. Data Sheet AD9363 APPLICATIONS INFORMATION For additional information about how to program the AD9363 device, see the AD9363 reference manual, and for additional information about the AD9363 registers, see the AD9363 register map reference manual, both of which are available by registering at the Integrated Wideband RF Transceiver Design Resources web page and clicking Download the AD9363 Design File Package. The register map is provided as a convenient and informational resource about low level operation of the device; however, it is not recommended for creating user software. Analog Devices, Inc., provides complete drivers for the AD9363 for both bare metal/no operating system (no OS) and Linux operating systems. The AD9361, AD9363, and AD9364 share the same application program interface (API). For the AD9361 drivers, visit the following online locations: • • Linux wiki page No OS wiki page For support for these drivers, visit the following online locations: • • Rev. D | Page 31 of 32 Linux Engineer Zone® page No OS Engineer Zone page AD9363 Data Sheet PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS A1 BALL CORNER 10.10 10.00 SQ 9.90 A1 BALL CORNER 12 11 10 9 8 7 6 5 4 3 2 1 A B C D 8.80 SQ E F G H 0.80 J K L M 0.60 REF TOP VIEW BOTTOM VIEW DETAIL A 1.70 MAX DETAIL A 1.00 MIN 0.32 MIN 0.50 COPLANARITY 0.45 0.12 0.40 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-275-EEAB-1. 11-18-2011-A SEATING PLANE Figure 44. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-144-7) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9363ABCZ AD9363ABCZ-REEL ADRV9363-W/PCBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Evaluation Board, 325 MHz to 3800 MHz Matching Circuits Z = RoHS Compliant Part. ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10558-0-11/16(D) Rev. D | Page 32 of 32 Package Option BC-144-7 BC-144-7