DS28EC20
20Kb 1-Wire EEPROM
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS28EC20 is a 20480-bit, 1-Wire® EEPROM
organized as 80 memory pages of 256 bits each. An
additional page is set aside for control functions.
Data is written to a 32-byte scratchpad, verified, and
then copied to the EEPROM memory. As a special
feature, blocks of eight memory pages can be write
protected or put in EPROM-Emulation mode, where
bits can only be changed from a 1 to a 0 state. The
DS28EC20 communicates over the single-conductor
1-Wire bus. The communication follows the standard
1-Wire protocol. Each device has its own unalterable
and unique 64-bit ROM registration number that is
factory lasered into the chip. The registration number
is used to address the device in a multidrop 1-Wire
net environment.
APPLICATIONS
Device Authentication
IEEE 1451.4 Sensor TEDS
Ink/Toner Cartridges
Medical Sensors
PCB Identification
Wireless Base Stations
PIN CONFIGURATION
ORDERING INFORMATION
PART
PINPACKAGE
3 TO-92
3 TO-92, T&R
TEMP RANGE
DS28EC20+
-40°C to +85°C
DS28EC20+T
-40°C to +85°C
+ Denotes a lead-free package.
T = tape and reel
20480 Bits of Nonvolatile (NV) EEPROM
Partitioned into Eighty 256-Bit Pages
Individual 8-Page Groups of Memory Pages
(Blocks) can be Permanently Write Protected or
Put in OTP EPROM-Emulation Mode ("Write to
0")
Read and Write Access Highly BackwardCompatible to Legacy Devices (e.g., DS2433)
256-Bit Scratchpad with Strict Read/Write
Protocols Ensures Integrity of Data Transfer
200k Write/Erase Cycle Endurance at +25°C
Unique Factory-Programmed 64-Bit Registration
Number Ensures Error-Free Device Selection
and Absolute Part Identity
Switchpoint Hysteresis and Filtering to Optimize
Performance in the Presence of Noise
Communicates to Host at 15.4kbps or 125kbps
Using 1-Wire Protocol
Low-Cost TO-92 Package
Operating Range: 5V ±5%, -40°C to +85°C
IEC 1000-4-2 Level 4 ESD Protection (8kV
Contact, 15kV Air, Typical) for I/O Pin
DALLAS
28EC20
1 2 3
FOR TAPE-ANDREEL THE LEADS
ARE FORMED TO
100 MILS (2.54mm)
SPACING VERSUS
50 MILS (1.27mm)
FOR BULK.
1 2 3
BOTTOM VIEW
TYPICAL OPERATING CIRCUIT
VCC
RPUP (300Ω
to 2.2kΩ)
PX.Y
I/O
PIN 1 ---------- GND
PIN 2 ---------- I/O
PIN 3 ---------- N.C.
DS28EC20
µC
GND
Commands, bytes, and modes are capitalized for
clarity.
1-Wire is a registered trademark of Dallas Semiconductor Corp., a
wholly owned subsidiary of Maxim Integrated products, Inc.
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REV: 071007
DS28EC20: 20Kb 1-Wire EEPROM
ABSOLUTE MAXIMUM RATINGS
I/O Voltage to GND
I/O Sink Current
Operating Temperature Range
Junction Temperature
Storage Temperature Range
Soldering Temperature
-0.5V, +6V
20mA
-40°C to +85°C
+150°C
-55°C to +125°C
See IPC/JEDEC J-STD-020A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(TA = -40°C to +85°C, see Note 1.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.25
2.2
1000
55
VPUP 1.8
0.5
VPUP 1.1
1.30
0.20
V
I/O PIN GENERAL DATA
1-Wire Pullup Voltage
1-Wire Pullup Resistance
Input Capacitance
Input Load Current
High-to-Low Switching
Threshold
Input Low Voltage
Low-to-High Switching
Threshold
Switching Hysteresis
Output Low Voltage
VPUP
RPUP
CIO
IL
(Notes 2)
(Notes 2, 3)
4.75
0.3
(Notes 4, 5)
I/O pin at VPUP
0.05
VTL
(Notes 5, 6, 7)
1.6
VIL
(Notes 2, 8)
VTH
(Notes 5, 6, 9)
2.5
VHY
VOL
(Notes 5, 6, 10)
At 4mA (Note 11)
Standard speed
Overdrive speed
Overdrive speed, directly prior to reset
pulse
Standard speed
Overdrive speed
Standard speed
Overdrive speed
0.30
Recovery Time
(Notes 2, 12)
tREC
Rising-Edge Hold-off Time
(Notes 5, 13)
tREH
Timeslot Duration
(Note 2, 14)
tSLOT
6.7
5
2
kΩ
pF
µA
V
V
V
V
V
µs
5
0.5
5.0
Not applicable (0)
65
8
µs
µs
I/O PIN, 1-Wire RESET, PRESENCE DETECT CYCLE
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
480
48
15
2
60
8
60
6
640
80
60
6
240
24
75
10
Standard speed
Overdrive speed
Standard speed
Overdrive speed
60
6
1
1
120
15.5
15
2
tRL
Standard speed
Overdrive speed
5
1
tMSR
Standard speed
Overdrive speed
tRL + δ
tRL + δ
15 - δ
2-δ
15
2
Reset-Low Time (Note 2)
tRSTL
Presence-Detect High
Time
tPDH
Presence-Detect Low
Time
tPDL
Presence-Detect Sample
Time (Notes 2, 15)
tMSP
µs
µs
µs
µs
I/O PIN, 1-Wire WRITE
Write-0 Low Time
(Notes 2, 16, 17)
tW0L
Write-1 Low Time
(Notes 2, 17)
tW1L
µs
µs
I/O PIN, 1-Wire READ
Read-Low Time
(Notes 2, 18)
Read-Sample Time
(Notes 2, 18)
2 of 24
µs
µs
DS28EC20: 20Kb 1-Wire EEPROM
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.8
10
mA
ms
EEPROM
Programming Current
Programming Time
Write/Erase Cycles
(Endurance) (Notes 21,
22)
Data Retention
(Notes 23, 24, 25)
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
Note 19:
Note 20:
Note 21:
Note 22:
Note 23:
Note 24:
Note 25:
IPROG
tPROG
NCY
tDR
(Note 19)
(Note 20)
At +25°C
200k
At +85°C (worst case)
50k
At +85°C (worst case)
40
⎯
years
Specifications at TA = -40°C are guaranteed by design only and not production-tested.
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system, 1-Wire recovery times, and
current requirements during EEPROM programming. The specified value here applies to systems with only one device and with
the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00,
DS2480B, or DS2490 may be required.
Maximum value represents the internal parasite capacitance when VPUP is first applied. If a 2.2kΩ resistor is used to pull up the
data line, 2.5µs after VPUP has been applied the parasite capacitance does not affect normal communications.
Guaranteed by design, characterization and/or simulation only. Not production tested.
VTL, VTH, and VHY are a function of the internal supply voltage which is itself a function of VPUP, RPUP, 1-Wire timing, and
capacitive loading on I/O. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH,
and VHY.
Voltage below which, during a falling edge on I/O, a logic 0 is detected.
The voltage on I/O needs to be less or equal to VILMAX at all times the master is driving I/O to a logic 0 level.
Voltage above which, during a rising edge on I/O, a logic 1 is detected.
After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by at least VHY to be detected as logic 0.
The I-V characteristic is approximately linear for voltages less than 1V.
Applies to a single device attached to a 1-Wire line.
The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge.
Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN).
Interval after tRSTL during which a bus master is guaranteed to sample a logic 0 on I/O if there is a DS28EC20 present. Minimum
limit is tPDHMAX; maximum limit is tPDHMIN + tPDLMIN.
Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below.
ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to VTH. The actual
maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to the input high threshold
of the bus master. The actual maximum duration for the master to pull the line low is tRLmax + tF.
Current drawn from I/O during the EEPROM programming interval. During a programming cycle the voltage at I/O drops by IPROG
× RPUP below VPUP. If VPUP and RPUP are within their EC table limits, the residual I/O voltage meets the guaranteed-by-design
minimum voltage requirements for programming.
The tPROG interval begins tREHMAX after the leading negative edge on I/O for the last time slot of the E/S byte for a valid copy
scratchpad sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn
by the device has returned from IPROG to IL.
Write-cycle endurance is degraded as TA increases.
Not 100% production-tested; guaranteed by reliability monitor sampling.
Data retention is degraded as TA increases.
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet
limit at operating temperature range is established by reliability testing.
EEPROM writes may become nonfunctional after the data retention time is exceeded. Long-time storage at elevated
temperatures is not recommended; the device may lose its write capability after 10 years at +125°C or 40 years at +85°C.
PARAMETER
tSLOT (incl. tREC)
tRSTL
tPDH
tPDL
tW0L
LEGACY VALUES
STANDARD SPEED
OVERDRIVE SPEED
MIN
MAX
MIN
MAX
61µs
(undefined)
7µs
(undefined)
480µs
(undefined)
48µs
80µs
15µs
60µs
2µs
6µs
60µs
240µs
8µs
24µs
60µs
120µs
6µs
16µs
DS28EC20 VALUES
STANDARD SPEED
OVERDRIVE SPEED
MIN
MAX
MIN
MAX
65µs*
(undefined)
8µs*
(undefined)
480µs
640µs
48µs
80µs
15µs
60µs
2µs
6µs
60µs
240µs
8µs
24µs
60µs
120µs
6µs
15.5µs
* Intentional change, longer recovery time requirement due to modified 1-Wire front-end.
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DS28EC20: 20Kb 1-Wire EEPROM
PIN DESCRIPTION
NAME
I/O
GND
N.C.
FUNCTION
1-Wire Bus Interface. Open drain, requires external pullup resistor.
Ground Reference
Not Connected
DESCRIPTION
The DS28EC20 combines 20Kb of data EEPROM with a fully featured 1-Wire interface in a single chip. The
memory is organized as 80 pages of 256 bits each. In addition, the device has one page for control functions such
as permanent write protection and EPROM-Emulation mode for individual 2048-bit (8-page) memory blocks. A
volatile 256-bit memory page called the scratchpad acts as a buffer when writing data to the EEPROM to ensure
data integrity. Data is first written to the scratchpad, from which it can be read back for verification before
transferring it to the EEPROM. The operation of the DS28EC20 is controlled over the single-conductor 1-Wire bus.
Device communication follows the standard 1-Wire protocol. The energy required to read and write the DS28EC20
is derived entirely from the 1-Wire communication line. Each DS28EC20 has its own unalterable and unique 64-bit
registration number. The registration number guarantees unique identification and is used to address the device in
a multidrop 1-Wire net environment. Multiple DS28EC20 devices can reside on a common 1-Wire bus and be
operated independently of each other. Applications of the DS28EC20 include device authentication, analog-sensor
calibration such as IEEE-P1451.4 Smart Sensors TEDS, ink and toner print cartridge identification, medical-sensor
calibration data storage, PC board identification, and data for self-configuration of central office switches, wireless
base stations, PBXs, or other modular-based rack systems. The DS28EC20 provides a high degree of backward
compatibility with the DS2433. Besides the different family codes, the only protocol change that is required on an
existing DS2433 implementation is a lengthening of the programming duration (tPROG) from 5ms to 10ms.
Figure 1. Block Diagram
Parasite Power
DS28EC20
I/O
1-Wire
Function Control
64-Bit
Registration #
Memory
Function
Control Unit
CRC16
Generator
32-Byte
Scratchpad
Data Memory
80 Pages of
32 Bytes each
Special Function
Registers
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DS28EC20: 20Kb 1-Wire EEPROM
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of the
DS28EC20. The DS28EC20 has four main data components: 1) 64-bit registration number, 2) 32-byte scratchpad,
3) eighty 32-byte pages of EEPROM, and 4) special function registers. The hierarchical structure of the 1-Wire
protocol is shown in Figure 2. The bus master must first provide one of the seven ROM (network) function
commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume, 6) Overdrive Skip ROM, or
7) Overdrive Match ROM. Upon completion of an Overdrive ROM command byte executed at standard speed, the
device enters Overdrive mode where all subsequent communication occurs at a higher speed. The protocol
required for these ROM function commands is described in Figure 9. After a ROM function command is
successfully executed, the memory functions become accessible and the master may provide any one of the five
memory function commands. The protocol for these commands is described in Figure 7. All data is read and written
least significant bit first.
Figure 2. Hierarchical Structure for 1-Wire Protocol
Available
Commands:
Data Field
Affected:
1-Wire ROM Function
Commands (see Figure 9)
Read ROM
Match ROM
Search ROM
Skip ROM
Resume
Overdrive Skip
Overdrive Match
64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
RC-Flag
RC-Flag
RC-Flag, OD-Flag
64-bit Reg. #, RC-Flag, OD-Flag
DS28EC20-Specific
Memory Function
Commands (see Figure 7)
Write Scratchpad
Read Scratchpad
Copy Scratchpad
Read Memory
Extended Read Mem.
32-byte Scratchpad, Flags
32-byte Scratchpad
Data Memory, Register Page
Data Memory, Register Page
Data Memory, Register Page
DS28EC20 Command Level:
64-BIT LASERED ROM
Each DS28EC20 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The
next 48 bits are a unique serial number. The last 8 bits are a cyclic redundancy check (CRC) of the first 56 bits.
See Figure 3 for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register
and XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the 1-Wire
CRC is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with Dallas
Semiconductor iButton® Products (www.maxim-ic.com/AN27).
The shift register bits are initialized to 0. Then, starting with the least significant bit of the family code, one bit at a
time is shifted in. After the 8th bit of the family code has been entered, the serial number is entered. After the last
bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of the
CRC returns the shift register to all 0s.
Figure 3. 64-Bit Lasered ROM
MSB
LSB
8-Bit
CRC Code
MSB
LSB
8-Bit Family
Code (43h)
48-Bit Serial Number
MSB
LSB
MSB
LSB
iButton is a registered trademark of Dallas Semiconductor Corp., a wholly owned subsidiary of Maxim Integrated products, Inc.
5 of 24
DS28EC20: 20Kb 1-Wire EEPROM
Figure 4. 1-Wire CRC Generator
8
5
4
Polynomial = X + X + X + 1
st
nd
1
STAGE
X
0
rd
2
STAGE
X
1
th
3
STAGE
X
2
th
4
STAGE
X
3
th
5
STAGE
X
4
th
6
STAGE
X
5
th
7
STAGE
X
6
8
STAGE
X
7
X
8
INPUT DATA
MEMORY
Data memory and special function registers are located in a linear address space, as shown in Figure 5. The data
memory and the registers have unrestricted read access. The data memory consists of 80 pages of 32 bytes each.
Eight adjacent pages form one 2Kb block. Each block can be individually set to open (default), write protected, or
EPROM mode by setting the associated protection byte in the register page, which starts at address 0A00h.
Besides the 10 block protection control bytes (one for each 2Kb data memory block) the register page contains 20
bytes of user EEPROM plus a memory block lock byte and a register page lock byte. Starting at address 0A20h,
the DS28EC20 has a read-only memory page that stores a factory byte and a 2-byte field reserved for a factoryadministered service to program manufacturer identification. All other bytes of that page are reserved. The
manufacturer ID can be a customer-supplied identification code that assists the application software in identifying
the product the DS28EC20 is associated with. Contact the factory to set up and register a custom manufacturer ID.
In addition to the EEPROM, the device has a 32-byte volatile scratchpad. Writes to the EEPROM array are a twostep process. First, data is written to the scratchpad, and then copied into the main array. The user can verify the
data in the scratchpad prior to copying.
The protection control registers, along with the Memory Block Lock byte, determine whether write protection,
EPROM mode, or copy protection is enabled for each of the 10 data memory blocks. A value of 55h sets write
protection for the associated memory block. A value of AAh sets EPROM mode. The Memory Block Lock byte, if
programmed to either 55h or AAh, sets copy protection for all write-protected data memory blocks. Blocks in
EPROM mode are not affected. Programming the Register Page Lock byte to either 55h or AAh copy protects the
entire register page. The protection control registers and the Lock bytes write protect themselves if set to 55h or
AAh. Any other setting leaves them open for unrestricted write access. See the Copy Protection section for
explanation of copy protect vs. write protect.
Write Protection: Write protection prevents data from being changed, but does not block the copy-scratchpad
function; this allows the memory to be reprogrammed with the same data. In EEPROM devices digital information
is stored as electrical charge (electrons) on floating gates. Quantum mechanical effects allow electrons to be
transported in large numbers to and from the floating gate for programming and erasing memory cells. Electrons
leave the floating gate at a temperature-dependent rate. The higher the temperature, the faster is the rate at which
electrons escape. This rate is expressed as Data Retention in the EC table. Reprogramming the memory returns
the charge to the original value for a full data retention time. This is particularly useful in applications where data
retention is a concern, e.g., at high temperatures.
Copy Protection: Copy protection blocks the execution of the copy-scratchpad function. This feature achieves a
higher level of security, and should only be used after all write-protected locations and their associated protection
control bytes are set to their final values. Copy protection does not prevent copying data from one device to
another.
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DS28EC20: 20Kb 1-Wire EEPROM
Figure 5. Memory Map
ADDRESS RANGE
TYPE
DESCRIPTION
PROTECTION CODES (NOTES)
0000h to 00FFh
R/(W)
Data Memory
Pages 0 to 7 (Block 0)
(Protection controlled by address 0A00h)
0100h to 01FFh
R/(W)
Data Memory
Pages 8 to 15 (Block 1)
(Protection controlled by address 0A01h)
0200h to 02FFh
R/(W)
Data Memory
Pages 16 to 23 (Block 2)
(Protection controlled by address 0A02h)
0300h to 03FFh
R/(W)
Data Memory
Pages 24 to 31 (Block 3)
(Protection controlled by address 0A03h)
0400h to 04FFh
R/(W)
Data Memory
Pages 32 to 39 (Block 4)
(Protection controlled by address 0A04h)
0500h to 05FFh
R/(W)
Data Memory
Pages 40 to 47 (Block 5)
(Protection controlled by address 0A05h)
0600h to 06FFh
R/(W)
Data Memory
Pages 48 to 55 (Block 6)
(Protection controlled by address 0A06h)
0700h to 07FFh
R/(W)
Data Memory
Pages 56 to 63 (Block 7)
(Protection controlled by address 0A07h)
0800h to 08FFh
R/(W)
Data Memory
Pages 64 to 71 (Block 8)
(Protection controlled by address 0A08h)
0900h to 09FFh
R/(W)
Data Memory
Pages 72 to 79 (Block 9)
(Protection controlled by address 0A09h)
0A00h* to 0A09h*
R/(W)
Protection Control
Blocks 0 to 9
55h: Write protected; AAh: EPROM mode.
Address 0A00h is associated with Block 0,
address 0A01h with Block 1, etc.
0A0Ah to 0A1Dh
R/(W)
User EEPROM
(Protection controlled by address 0A1Fh)
0A1Eh*
R/(W)
Memory Block Lock
(See text)
0A1Fh*
R/(W)
Register Page Lock
(See text)
0A20h
R
Factory Byte
(55h Î no valid manufacturer ID, AAh Î
0A23h to 0A24h are a valid Manufacturer ID)
0A21h to 0A22h
R
Factory Trim Bytes
(Unspecified value)
0A23h to 0A24h
R
Manufacturer ID
Validity depends on factory byte
0A25h to 0A3Fh
R
Reserved
(Unspecified value)
* Once programmed to AAh or 55h this address becomes read-only. All other codes can be stored but neither write-protect the address nor
activate any function.
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DS28EC20: 20Kb 1-Wire EEPROM
ADDRESS REGISTERS AND TRANSFER STATUS
The DS28EC20 employs three address registers: TA1, TA2, and E/S (Figure 6). Registers TA1 and TA2 must be
loaded with the target address to which the data is written or from which data is read. Register E/S is a read-only
transfer status register used to verify data integrity with write commands. ES bits E[4:0] are loaded with the
incoming T[4:0] on a Write Scratchpad command and increment on each subsequent data byte. This is, in effect, a
byte-ending offset counter within the 32-byte scratchpad. Bit 5 of the E/S register, called PF, is set if the number of
data bits sent by the master is not an integer multiple of 8 or if the data in the scratchpad is not valid due to a loss
of power. A valid write to the scratchpad clears the PF bit. Bit 6 has no function; it always reads 0. The highest
valued bit of the E/S register, called authorization accepted (AA), is valid only if the PF flag reads 0. If PF is 0 and
AA is 1, the data stored in the scratchpad has already been copied to the target memory address. Writing data to
the scratchpad clears this flag.
Figure 6. Address Registers
Bit #
7
6
5
4
3
2
1
0
Target Address (TA1)
T7
T6
T5
T4
T3
T2
T1
T0
Target Address (TA2)
T15
T14
T13
T12
T11
T10
T9
T8
Ending Address with
Data Status (E/S)
(Read Only)
AA
0
PF
E4
E3
E2
E1
E0
WRITING WITH VERIFICATION
To write data to the DS28EC20, the scratchpad must be used as intermediate storage. First, the master issues the
Write Scratchpad command to specify the desired target address, followed by the data to be written to the
scratchpad. Under certain conditions (see the Write Scratchpad Command section) the master receives an inverted
CRC16 of the command, address (actual address sent), and data at the end of the Write Scratchpad command
sequence. Knowing this CRC value, the master can compare it to the value it has calculated itself to decide if the
communication was successful and precede to the Copy Scratchpad command. If the master could not receive the
CRC16, it should send the Read Scratchpad command to verify data integrity. As a preamble to the scratchpad
data, the DS28EC20 repeats the target address TA1 and TA2 and sends the contents of the E/S register. If the PF
flag is set, data did not arrive correctly in the scratchpad or there was a loss of power since data was last written to
the scratchpad. The master does not need to continue reading; it can start a new trial to write data to the
scratchpad. Similarly, a set AA flag together with a cleared PF flag indicates that the device did not recognize the
Write command. If everything went correctly, both flags are cleared and the ending offset indicates the address of
the last byte written to the scratchpad. Now the master can continue reading and verifying every data byte. After
the master has verified the data, it can send the Copy Scratchpad command, for example. This command must be
followed exactly by the data of the three address registers TA1, TA2, and E/S. The master should obtain the
contents of these registers by reading the scratchpad. As soon as the DS28EC20 has received these bytes
correctly, it starts copying the scratchpad data to the requested location, provided that the target memory is not
copy protected, the PF flag is cleared, and there was no Read Memory or Extended Read Memory command
issued between Write Scratchpad and Copy Scratchpad.
8 of 24
DS28EC20: 20Kb 1-Wire EEPROM
MEMORY FUNCTION COMMANDS
The Memory Function Flow Chart (Figure 7) describes the protocols necessary for accessing the memory of the
DS28EC20. The target address registers TA1 and TA2 are used for both read and write. To prevent accidental
changes to the data memory or control registers the device employs a BS-flag indicating a “bad sequence”. The
communication between master and DS28EC20 takes place either at standard speed (default, OD = 0) or at
overdrive speed (OD = 1). If not explicitly set into the Overdrive mode, the DS28EC20 assumes standard speed.
WRITE SCRATCHPAD COMMAND [0Fh]
The Write Scratchpad command applies to the data memory and the writable addresses in the register page. After
issuing the Write Scratchpad command, the master must first provide the 2-byte target address, followed by the
data to be written to the scratchpad. The data is written to the scratchpad starting at the byte offset of T[4:0]. The
ES bits E[4:0] are loaded with the starting byte offset, and increment with each subsequent byte. Effectively, E[4:0]
is the byte offset of the last full byte written to the scratchpad. Only full bytes are accepted. If the last byte is
incomplete its content is ignored and the partial byte flag PF is set. The PF flag is also set if the master ends the
command before a complete target address is transmitted. The PF and BS flags are both cleared when a complete
target address is received.
When executing the Write Scratchpad command, the CRC generator inside the DS28EC20 (Figure 13) calculates a
16-bit CRC of the entire data stream, starting at the command code and ending at the last data byte as sent by the
master. This CRC is generated using the CRC16 polynomial (x16 + x15 + x2 + 1) by first clearing the CRC generator
and then shifting in the command code (0Fh) of the Write Scratchpad command, the target addresses TA1 and
TA2 as supplied by the master, and all the data bytes. The master can end the Write Scratchpad command at any
time. However, if the end of the scratchpad is reached (E[4:0] = 11111b), the master can send 16 read-time slots to
receive the CRC generated by the DS28EC20.
If a Write Scratchpad is attempted to a write-protected location, the scratchpad is loaded with the data already in
memory, rather than the data transmitted. Similarly, if the target address page is in EPROM mode, the scratchpad
is loaded with the bitwise logical AND of the transmitted data and the data already in memory.
The DS28EC20’s memory address range is 0000h to 0A3Fh. If the bus master sends a target address higher than
this, the DS28EC20’s internal circuitry sets the four most significant address bits to zero as they are shifted into the
internal address register. The Read Scratchpad command reveals the modified target address. The master
identifies such address modifications by comparing the target address read back to the target address transmitted.
If the master does not read the scratchpad, a subsequent Copy Scratchpad command does not work since the
most significant bits of the target address the master sends do not match the value the DS28EC20 expects.
READ SCRATCHPAD COMMAND [AAh]
The Read Scratchpad command allows verifying the target address and the integrity of the scratchpad data. After
issuing the command code, the master begins reading. The first two bytes are the target address. The next byte is
the Ending Offset/Data Status byte (E/S) followed by the scratchpad data beginning at the byte offset (T[4:0]). The
scratchpad data can be different from what the master originally sent. This is of particular importance if the target
address is within the register page or a page in either Write Protection or EPROM modes. See the Write
Scratchpad Command section for details. The master should read through the end of the scratchpad, after which it
receives an inverted CRC16, based on data as it was sent by the DS28EC20. If the master continues reading after
the CRC, all data are logic 1s.
9 of 24
DS28EC20: 20Kb 1-Wire EEPROM
Figure 7-1. Memory Function Flow Chart
From ROM Functions
Flow Chart (Figure 9)
Bus Master TX Memory
Function Command
0Fh
Write Scratchpad ?
To Figure 7,
nd
2 Part
N
Y
Note: The PF Flag is set upon poweron reset. It is cleared only if a complete 16-bit target address is transmitted. Sending less than 16 bits for
the target address sets the PF flag.
Bus Master TX EEPROM
Array Target Address
TA1 (T[7:0]), TA2 (T[15:8])
DS28EC20 sets Scratchpad Offset = (T[4:0]),
Clears PF, AA, BS
If the memory is write-protected, the
DS28EC20 copies the data byte from
the target address into the scratchpad.
Master TX Data Byte
To Scratchpad Offset
DS28EC20 sets (E[4:0]) =
Scratchpad Offset
DS28EC20
Increments
Scratchpad
Offset
If the memory is in EPROM mode, the
DS28EC20 stores the bitwise logical
AND of the transmitted byte and the
data byte from the targeted address
into the scratchpad.
Y
Master
TX Reset ?
Partial
Byte ?
N
N
N
Y
Scrpad. Offset
= 11111b?
PF = 1
Y
DS28EC20 TX CRC16
of Command, Address,
Data Bytes as they were
sent by the bus master
Bus Master
RX “1”s
N
Master
TX Reset?
Y
To ROM Functions
Flow Chart (Figure 9)
10 of 24
From Figure 7,
nd
2 Part
DS28EC20: 20Kb 1-Wire EEPROM
Figure 7-2. Memory Function Flow Chart (continued)
From Figure 7,
st
1 Part
AAh
Read ScratchPad ?
N
To Figure 7,
rd
3 Part
Y
Bus Master RX
TA1 (T[7:0]), TA2 (T[15:8])
and E/S Byte
DS28EC20 sets Scratchpad Offset = (T[4:0])
Bus Master RX Data Byte
from Scratchpad Offset
DS28EC20
Increments
Scratchpad
Offset
Master
TX Reset ?
See note in Write
Scratchpad flow chart
for additional details.
Y
N
N
Scrpad. Offset
= 11111b ?
Y
Bus Master RX CRC16 of
Command, Address, E/S
Byte, Data Bytes as sent
by the DS28EC20
Bus Master
RX “1”s
N
Master
TX Reset ?
Y
To Figure 7,
st
1 Part
From Figure 7,
rd
3 Part
11 of 24
DS28EC20: 20Kb 1-Wire EEPROM
Figure 7-3. Memory Function Flow Chart (continued)
From Figure 7,
nd
2 Part
55h
Copy ScratchPad ?
To Figure 7,
th
4 Part
N
Y
Bus Master TX
TA1 (T[7:0]), TA2 (T[15:8])
and E/S Byte
Y
Auth. Code
Match ?
N
N
PF = 0?
Y
N
BS = 0?
Y
Y
CopyProtected ?
N
AA = 1
DS28EC20 copies Scratchpad Data to Address
DS28EC20 TX “0”
Y
Bus Master
RX “1”s
Master
TX Reset ?
N
Master
TX Reset ?
N
DS28EC20 TX “1”
Y
Master
TX Reset ?
N
Y
To Figure 7,
nd
2 Part
* 1-Wire idle high for tPROG for power
12 of 24
From Figure 7,
th
4 Part
*
DS28EC20: 20Kb 1-Wire EEPROM
Figure 7-4. Memory Function Flow Chart (continued)
From Figure 7,
rd
3 Part
F0h
Read Memory ?
A5h
Extended Read
Memory?
N
Y
Y
Bus Master TX
TA1 (T[7:0]),
TA2 (T[15:8])
Decision
made by
DS28EC20
N
Bus Master TX
TA1 (T[7:0]),
TA2 (T[15:8])
Decision
made by
Master
Bus Master
RX “1”s
BS = 1
N
BS = 1
DS28EC20 sets Memory
Address = (T[15:0])
Y
DS28EC20 sets Memory
Address = (T[15:0])
N
Address
<0A40h
Y
Bus Master RX
Data Byte from
Memory Address
Master RX
FFh Byte
DS28EC20
Increments
Address
Counter
Master RX Byte from
Memory Address
Y
Master
TX Reset?
Address
< 0A3Fh?
N
Bus Master
RX “1”s
N
DS28EC20
Increments
Address
Counter
Master TX
Reset?
N
Y
N
End of
Page?
N
Y
Master
TX Reset ?
Y
Master RX CRC16 of
Command, Address, Data
st
(1 Pass); CRC16 of Data
(Subsequent Passes)
Y
CRC OK?
Master
TX Reset?
N
Y
Master TX
Reset
To Figure 7,
rd
3 Part
13 of 24
DS28EC20: 20Kb 1-Wire EEPROM
COPY SCRATCHPAD [55h]
The Copy Scratchpad command is used to copy data from the scratchpad to the data memory and the writable
sections of the register page. After issuing the Copy Scratchpad command, the master must provide a 3-byte
authorization pattern, which should have been obtained by an immediately preceding Read Scratchpad command.
This 3-byte pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that
order). If the pattern matches, the target address is valid, the PF and BS flag are not set, and the target memory is
not copy protected, the AA flag is set and the copy begins. The data to be copied is determined by the three
address registers. The scratchpad data from the beginning offset through the ending offset is copied to memory,
starting at the target address. Anywhere from 1 to 32 bytes can be copied with this command. The duration of the
device’s internal data transfer is tPROG during which the 1-Wire bus must be idle or actively pulled high. Active
pullup is optional for this device. A pattern of alternating 0s and 1s are transmitted after the data has been copied
until the master issues a reset pulse. If the PF flag or BS flag is set or the target memory is copy protected, the
copy does not begin and the AA flag is not set. The BS flag ensures that Copy Scratchpad is not executed
(blocked) if there was a Read Memory or Extended Read Memory between Write Scratchpad and Copy
Scratchpad.
READ MEMORY [F0h]
The Read Memory command is the general function to read from the DS28EC20. After issuing the command, the
master must provide a 2-byte target address, which should be in the range of 0000h to 0A3Fh. If the target address
is higher than 0A3Fh, the DS28EC20 changes the upper four address bits to 0. After the address is transmitted, the
master reads data starting at the (modified) target address and can continue until address 0A3Fh. If the master
continues reading, the result is FFh. The Read Memory command sequence can be ended at any point by issuing
a reset pulse. Note that the target address provided with the Read Memory flow overwrites the target address that
was specified with a previously issued Write Scratchpad command. Since the command also sets the BS flag, a
subsequent Copy Scratchpad command fails even if the authorization pattern matches.
EXTENDED READ MEMORY [A5h]
This command works essentially the same way as Read Memory, except for the 16-bit CRC that the DS28EC20
generates and transmits following the last data byte of a memory page. The CRC generated by this command uses
the same polynomial as the Write Scratchpad command. After issuing the command, the master must provide a 2byte target address, which should be in the range of 0000h to 0A3Fh. If the target address is higher than 0A3Fh,
the DS28EC20 changes the upper four address bits to 0. After the address is transmitted, the master reads data
starting at the (modified) target address and continuing until the end of a 32-byte page is reached. At that point the
bus master receives an inverted 16-bit CRC. If the master continues reading it receives data starting at the beginning of the next page, followed again by the inverted CRC for that page. Reading beyond the end of the memory is
permissible, but the result is FFh. The Extended Read Memory command sequence can be ended at any point by
issuing a reset pulse. Note that the target address provided with the Extended Read Memory flow overwrites the
target address that was specified with a previously issued Write Scratchpad command. Since the command also
sets the BS flag, a subsequent Copy Scratchpad command fails even if the authorization pattern matches.
1-Wire BUS SYSTEM
The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS28EC20 is
a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into
three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). The
1-Wire protocol defines bus transactions in terms of the bus state during specific time slots, which are initiated on
the falling edge of sync pulses from the bus master.
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at
the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open-drain or tri-state
outputs. The 1-Wire port of the DS28EC20 is open drain with an internal circuit equivalent to that shown in
Figure 8.
14 of 24
DS28EC20: 20Kb 1-Wire EEPROM
A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The DS28EC20 supports both a standard
and overdrive communication speed of 15.4kbps (max) and 125kbps (max), respectively. Note that legacy 1-Wire
products support a standard communication speed of 16.3kbps and overdrive of 142kbps. The slightly reduced
rates for the DS28EC20 are a result of additional recovery times, which in turn were driven by a 1-Wire physical
interface enhancement to improve noise immunity. The value of the pullup resistor primarily depends on the
network size and load conditions. The DS28EC20 requires a pullup resistor of 2.2kΩ (max) at any speed.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be
left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16µs
(overdrive speed) or more than 120µs (standard speed), one or more devices on the bus can be reset.
Figure 8. Hardware Configuration
BUS MASTER
VPUP
DS28EC20 1-Wire PORT
RPUP
RX
DATA
RX
TX
IL
TX
RX = RECEIVE
Open-Drain
Port Pin
TX = TRANSMIT
100Ω
MOSFET
TRANSACTION SEQUENCE
The protocol for accessing the DS28EC20 through the 1-Wire port is as follows:
Initialization
ROM Function Command
Memory Function Command
Transaction/Data
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a
reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence
pulse lets the bus master know that the DS28EC20 is on the bus and is ready to operate. For more details, see the
1-Wire Signaling section.
1-Wire ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the seven ROM function commands that the
DS28EC20 supports. All ROM function commands are 8 bits long. See Figure 9 for list of these commands.
READ ROM [33h]
This command allows the bus master to read the DS28EC20’s 8-bit family code, unique 48-bit serial number, and
8-bit CRC. This command can only be used if there is a single slave on the bus. If more than one slave is present
on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wiredAND result). The resultant family code and 48-bit serial number result in a mismatch of the CRC.
15 of 24
DS28EC20: 20Kb 1-Wire EEPROM
MATCH ROM [55h]
The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific
DS28EC20 on a multidrop bus. Only the DS28EC20 that exactly matches the 64-bit ROM sequence responds to
the following memory function command. All other slaves wait for a reset pulse. This command can be used with a
single or multiple devices on the bus.
SEARCH ROM [F0h]
When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or
their registration numbers. By taking advantage of the bus’s wired-AND property, the master can use a process of
elimination to identify the registration numbers of all slave devices. For each bit of the registration number, starting
with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device
participating in the search outputs the true value of its registration number bit. On the second slot, each slave
device participating in the search outputs the complemented value of its registration number bit. On the third slot,
the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the
master stop participating in the search. If both of the read bits are zero, the master knows that slave devices exist
with both states of the bit. By choosing which state to write, the bus master branches in the ROM code tree. After
one complete pass, the bus master knows the registration number of a single device. Additional passes identify the
registration numbers of the remaining devices. Refer to Application Note 187: 1-Wire Search Algorithm
(www.maxim-ic.com/AN187) for a detailed discussion, including an example.
SKIP ROM [CCh]
This command can save time in a single-drop bus system by allowing the bus master to access the memory
functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a
Read command is issued following the Skip ROM command, data collision occurs on the bus as multiple slaves
transmit simultaneously (open-drain pulldowns produce a wired-AND result).
RESUME [A5h]
To maximize the data throughput in a multidrop environment, the Resume function is available. This function
checks the status of the RC bit and, if it is set, directly transfers control to the memory functions, similar to a Skip
ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM, or
Overdrive Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the
Resume command function. Accessing another device on the bus clears the RC bit, preventing two or more
devices from simultaneously responding to the Resume command function.
OVERDRIVE SKIP ROM [3Ch]
On a single-drop bus this command can save time by allowing the bus master to access the memory functions
without providing the 64-bit ROM code. Unlike the normal Skip ROM command, the Overdrive Skip ROM sets the
DS28EC20 in the Overdrive mode (OD = 1). All communication following this command must occur at overdrive
speed until a reset pulse of minimum 480µs duration resets all devices on the bus to standard speed (OD = 0).
When issued on a multidrop bus, this command sets all overdrive-supporting devices into Overdrive mode. To
subsequently address a specific overdrive-supporting device, a reset pulse at overdrive speed must be issued
followed by a Match ROM or Search ROM command sequence. This speeds up the time for the search process. If
more than one slave supporting overdrive is present on the bus and the Overdrive Skip ROM command is followed
by a Read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain
pulldowns produce a wired-AND result).
OVERDRIVE MATCH ROM [69h]
The Overdrive Match ROM command followed by a 64-bit ROM sequence transmitted at overdrive speed allows
the bus master to address a specific DS28EC20 on a multidrop bus and to simultaneously set it in Overdrive mode.
Only the DS28EC20 that exactly matches the 64-bit ROM sequence responds to the subsequent memory function
command. Slaves already in Overdrive mode from a previous Overdrive Skip or successful Overdrive Match
command remain in Overdrive mode. All overdrive-capable slaves return to standard speed at the next Reset Pulse
of minimum 480µs duration. The Overdrive Match ROM command can be used with a single or multiple devices on
the bus.
16 of 24
DS28EC20: 20Kb 1-Wire EEPROM
Figure 9-1. ROM Functions Flow Chart
Bus Master TX
Reset Pulse
From Figure 9, 2
From Memory Functions
Flow Chart (Figure 7)
OD
Reset Pulse?
nd
Part
N
OD = 0
Y
Bus Master TX ROM
Function Command
33h
Read ROM
Command?
Y
DS28EC20 TX
Presence Pulse
N
55h
Match ROM
Command?
F0h
Search ROM
Command?
N
Y
Y
RC = 0
RC = 0
DS28EC20 TX
Family Code
(1 Byte)
Master TX Bit 0
DS28EC20 TX Bit 0
DS28EC20 TX Bit 0
Master TX Bit 0
N
N
Y
DS28EC20 TX Bit 1
DS28EC20 TX Bit 1
Master TX Bit 1
Master TX Bit 1
N
Bit 1
Match?
N
Bit 1
Match?
Y
DS28EC20 TX
CRC Byte
RC = 0
Bit 0
Match?
Y
DS28EC20 TX
Serial Number
(6 Bytes)
CCh
Skip ROM
Command?
Y
RC = 0
Bit 0
Match?
N
To Figure 9,
nd
2 Part
N
Y
DS28EC20 TX Bit 63
DS28EC20 TX Bit 63
Master TX Bit 63
Master TX Bit 63
N
Bit 63
Match?
N
Bit 63
Match?
Y
Y
RC = 1
RC = 1
To Memory Functions
Flow Chart (Figure 7)
17 of 24
To Figure 9,
nd
2 Part
From Figure 9,
nd
2 Part
DS28EC20: 20Kb 1-Wire EEPROM
Figure 9-2. ROM Functions Flow Chart (continued)
st
To Figure 9, 1 Part
From Figure 9,
st
1 Part
A5h
Resume
Command?
3Ch
Overdrive
Skip ROM?
N
Y
N
Y
69h
N
Overdrive Match
ROM?
Y
RC = 0 ; OD = 1
RC = 0 ; OD = 1
N
RC = 1 ?
Master TX Bit 0
Y
Master
TX Reset ?
Y
N
Bit 0
Match?
1)
OD = 0
Y
N
Master TX Bit 1
Master
TX Reset ?
Y
N
Bit 1
Match?
1)
OD = 0
Y
N
Master TX Bit 63
N
Bit 63
Match?
1)
OD = 0
Y
From Figure 9,
st
1 Part
To Figure 9,
st
1 Part
RC = 1
1) The OD flag remains at 1 if the device was already at overdrive
speed before the Overdrive Match ROM command was issued.
18 of 24
DS28EC20: 20Kb 1-Wire EEPROM
1-Wire SIGNALING
The DS28EC20 requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on
one line: reset sequence with reset pulse and presence pulse, write-zero, write-one, and read-data. Except for the
presence pulse, the bus master initiates all falling edges. The DS28EC20 can communicate at two different
speeds: standard speed and overdrive speed. If not explicitly set into the Overdrive mode, the DS28EC20
communicates at standard speed. While in Overdrive mode the fast timing applies to all waveforms.
To get from idle to active, the voltage on the 1-Wire line needs to fall from VPUP below the threshold VTL. To get
from active to idle, the voltage needs to rise from VILMAX past the threshold VTH. The time it takes for the voltage to
make this rise is seen in Figure 10 as ε, and its duration depends on the pullup resistor (RPUP) used and the
capacitance of the 1-Wire network attached. The voltage VILMAX is relevant for the DS28EC20 when determining a
logical level, not triggering any events.
Figure 10 shows the initialization sequence required to begin any communication with the DS28EC20. A reset
pulse followed by a presence pulse indicates that the DS28EC20 is ready to receive data, given the correct ROM
and memory function command. If the bus master uses slew-rate control on the falling edge, it must pull down the
line for tRSTL + tF to compensate for the edge. A tRSTL duration of 480µs or longer exits the Overdrive mode,
returning the device to standard speed. If the DS28EC20 is in Overdrive mode and tRSTL is no longer than 80µs, the
device remains in Overdrive mode. If the device is in Overdrive mode and tRSTL is between 80µs and 480µs, the
device resets, but the communication speed is undetermined.
Figure 10. Initialization Procedure: Reset and Presence Pulse
MASTER TX “RESET PULSE” MASTER RX “PRESENCE PULSE”
tMSP
ε
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
tRSTL
tF
RESISTOR
tPDH
MASTER
tPDL
tRSTH
tREC
DS28EC20
After the bus master has released the line it goes into Receive mode. Now the 1-Wire bus is pulled to VPUP through
the pullup resistor, or in case of a DS2482-x00 or DS2480B driver, by active circuitry. When the threshold VTH is
crossed, the DS28EC20 waits for tPDH and then transmits a presence pulse by pulling the line low for tPDL. To detect
a presence pulse, the master must test the logical state of the 1-Wire line at tMSP.
The tRSTH window must be at least the sum of tPDHMAX, tPDLMAX, and tRECMIN. Immediately after tRSTH is expired, the
DS28EC20 is ready for data communication. In a mixed population network, tRSTH should be extended to minimum
480µs at standard speed and 48µs at overdrive speed to accommodate other 1-Wire devices.
Read-/Write-Time Slots
Data communication with the DS28EC20 takes place in time slots, which carry a single bit each. Write-time slots
transport data from bus master to slave. Read-time slots transfer data from slave to master. Figure 11 illustrates
the definitions of the write- and read-time slots.
All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below the
threshold VTL, the DS28EC20 starts its internal timing generator that determines when the data line is sampled
during a write-time slot and how long data is valid during a read-time slot.
19 of 24
DS28EC20: 20Kb 1-Wire EEPROM
Master-to-Slave
For a write-one time slot, the voltage on the data line must have crossed the VTH threshold before the write-one low
time tW1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay below the VTH threshold
until the write-zero low time tW0LMIN is expired. For the most reliable communication, the voltage on the data line
should not exceed VILMAX during the entire tW0L or tW1L window. After the VTH threshold has been crossed, the
DS28EC20 needs a recovery time tREC before it is ready for the next time slot.
Figure 11. Read/Write Timing Diagram
Write-One Time Slot
tW1L
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
ε
tF
tSLOT
RESISTOR
MASTER
Write-Zero Time Slot
tW0L
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
ε
tF
tSLOT
RESISTOR
tREC
MASTER
Read-Data Time Slot
tMSR
tRL
VPUP
VIHMASTER
VTH
Master
Sampling
Window
VTL
VILMAX
0V
δ
tF
tREC
tSLOT
RESISTOR
MASTER
20 of 24
DS28EC20
DS28EC20: 20Kb 1-Wire EEPROM
Slave-to-Master
A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below VTL until the
read low time tRL is expired. During the tRL window, when responding with a 0, the DS28EC20 starts pulling the data
line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When
responding with a 1, the DS28EC20 does not hold the data line low at all, and the voltage starts rising as soon as
tRL is over.
The sum of tRL + δ (rise time) on one side and the internal timing generator of the DS28EC20 on the other side
define the master sampling window (tMSRMIN to tMSRMAX) in which the master must perform a read from the data line.
For the most reliable communication, tRL should be as short as permissible, and the master should read close to
but no later than tMSRMAX. After reading from the data line, the master must wait until tSLOT is expired. This
guarantees sufficient recovery time tREC for the DS28EC20 to get ready for the next time slot. Note that tREC
specified herein applies only to a single DS28EC20 attached to a 1-Wire line. For multidevice configurations, tREC
needs to be extended to accommodate the additional 1-Wire device input capacitance. Alternatively, an interface
that performs active pullup during the 1-Wire recovery time such as the DS2482-x00 or DS2480B 1-Wire line
drivers can be used.
IMPROVED NETWORK BEHAVIOR (SWITCHPOINT HYSTERESIS)
In a 1-Wire environment, line termination is possible only during transients controlled by the bus master (1-Wire
driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the physical size and
topology of the network, reflections from end points and branch points can add up or cancel each other to some
extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. Noise coupled onto the
1-Wire line from external sources can also result in signal glitching. A glitch during the rising edge of a time slot can
cause a slave device to lose synchronization with the master and, consequently, result in a Search ROM command
coming to a dead end or cause a device-specific function command to abort. For better performance in network
applications, the DS28EC20 uses a new 1-Wire front-end, which makes it less sensitive to noise.
The 1-Wire front-end of the DS28EC20 differs from traditional slave devices in three characteristics:
1) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a time slot.
This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at overdrive speed.
2) There is a hysteresis at the low-to-high switching threshold VTH. If a negative glitch crosses VTH but does not go
below VTH - VHY, it is not recognized (Figure 12, Case A). The hysteresis is effective at any 1-Wire speed.
3) There is a time window specified by the rising edge hold-off time tREH during which glitches are ignored, even if
they extend below VTH - VHY threshold (Figure 12, Case B, tGL < tREH). Deep voltage droops or glitches that
appear late after crossing the VTH threshold and extend beyond the tREH window cannot be filtered out and are
taken as the beginning of a new time slot (Figure 12, Case C, tGL ≥ tREH).
Devices that have the parameters VHY and tREH specified in their electrical characteristics use the improved 1-Wire
front-end.
Figure 12. Noise Suppression Scheme
tREH
VPUP
tREH
VTH
VHY
Case A
Case B
Case C
0V
tGL
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tGL
DS28EC20: 20Kb 1-Wire EEPROM
CRC GENERATION
The DS28EC20 uses two different types of CRCs. One CRC is an 8-bit type and is stored in the most significant
byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and
compare it to the value stored within the DS28EC20 to determine if the ROM data has been received error-free.
The equivalent polynomial function of this CRC is X8 + X5 + X4 + 1. This 8-bit CRC is received in the true
(noninverted) form. It is computed at the factory and lasered into the ROM.
The other CRC is a 16-bit type, generated according to the standardized CRC16 polynomial function
x16 + x15 + x2 + 1. This CRC is used for fast verification of a data transfer when writing to or reading from the
scratchpad and with the Extended Read Memory command. In contrast to the 8-bit CRC, the 16-bit CRC is always
communicated in the inverted form. A CRC generator inside the DS28EC20 (Figure 13) calculates a new 16-bit
CRC, as shown in the command flow chart (Figure 7). The bus master compares the CRC value read from the
device to the one it calculates from the data, and decides whether to continue with an operation or to reread the
portion of the data with the CRC error.
With the Write Scratchpad command, the CRC is generated by first clearing the CRC generator and then shifting in
the command code, the target addresses TA1 and TA2, and all the data bytes as they were sent by the bus
master. The DS28EC20 transmits this CRC only if the data bytes written to the scratchpad include scratchpad
ending offset 11111b. The data can start at any location within the scratchpad.
With the Read Scratchpad command, the CRC is generated by first clearing the CRC generator and then shifting in
the command code, the target addresses TA1 and TA2, the E/S byte, and the scratchpad data as they were sent
by the DS28EC20 starting at the target address. The DS28EC20 transmits this CRC only if the reading continues
through the end of the scratchpad, regardless of the actual ending offset.
With the initial pass through the extended read memory flow, the 16-bit CRC value is the result of shifting the
command byte into the cleared CRC generator, followed by the two address bytes and the data bytes. Subsequent
passes through the extended read memory flow generate a 16-bit CRC that is the result of clearing the CRC
generator and then shifting in the data bytes. For more information on generating CRC values refer to Application
Note 27: Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor iButton Products
(www.maxim-ic.com/AN27).
Figure 13. CRC-16 Hardware Description and Polynomial
16
Polynomial = X
st
nd
1
STAGE
0
X
th
8
X
th
9
STAGE
10
STAGE
9
X
X
th
3
STAGE
1
X
X
rd
2
STAGE
th
3
11
X
4
12
X
5
13
th
7
STAGE
6
X
8
STAGE
7
X
th
14
STAGE
X
th
6
STAGE
X
th
13
STAGE
th
5
STAGE
X
th
12
STAGE
2
+X +1
th
4
STAGE
X
th
11
STAGE
10
2
15
+X
th
15
STAGE
14
X
16
STAGE
15
X
INPUT DATA
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16
X
CRC
OUTPUT
DS28EC20: 20Kb 1-Wire EEPROM
COMMAND-SPECIFIC 1-Wire COMMUNICATION PROTOCOL—LEGEND
SYMBOL
RST
PD
Select
WS
RS
CPS
RM
ERM
TA
TA-E/S
<data to EOS>
<data to EOM>
<data to EOP>
CRC16\
FF loop
AA loop
Programming
DESCRIPTION
1-Wire reset pulse generated by master.
1-Wire presence pulse generated by slave.
Command and data to satisfy the ROM function protocol.
Command "Write Scratchpad".
Command "Read Scratchpad".
Command "Copy Scratchpad".
Command "Read Memory".
Command "Extended Read Memory".
Target address TA1, TA2.
Target address TA1, TA2 with E/S byte.
Transfer of as many bytes as needed to reach the end of the scratchpad for a given
target address.
Transfer of as many data bytes as are needed to reach the end of the memory.
Transfer of as many data bytes as are needed to reach the end of the page for a given
target address.
Transfer of an inverted CRC16.
Indefinite loop where the master reads FF bytes.
Indefinite loop where the master reads AA bytes.
Data transfer to EEPROM; no activity on the 1-Wire bus permitted during this time.
COMMAND-SPECIFIC 1-Wire COMMUNICATION PROTOCOL—COLOR CODES
Master to Slave
Slave to Master
Programming
WRITE SCRATCHPAD (CANNOT FAIL)
RST
PD
Select
WS
TA
<Data to EOS>
CRC16\
FF Loop
READ SCRATCHPAD
RST
PD
Select
RS
TA-E/S
<Data to EOS>
CRC16\
FF Loop
COPY SCRATCHPAD (SUCCESS)
RST
PD
Select
CPS
TA-E/S
Programming
AA Loop
COPY SCRATCHPAD (BS = 1 OR PF = 1 OR COPY PROTECTED)
RST
PD
Select
CPS
TA-E/S
FF Loop
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DS28EC20: 20Kb 1-Wire EEPROM
READ MEMORY (CANNOT FAIL)
RST
PD
Select
RM
TA
<Data to EOM>
FF Loop
EXTENDED READ MEMORY (CANNOT FAIL)
RST
PD
Select
ERM
TA
<Data to EOP>
CRC16\
<32 Bytes>
CRC16\
Loop
PACKAGE INFORMATION
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor
product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any
time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor.
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